Age | Commit message (Expand) | Author |
2017-08-11 | [ARM] Assembler support for the ARMv8.2a dot product instructions | Sjoerd Meijer |
2017-06-28 | [ARM] Improve if-conversion for M-class CPUs without branch predictors | John Brawn |
2017-06-02 | [ARM] Cortex-A57 scheduling model for ARM backend (AArch32) | Javed Absar |
2017-05-24 | [ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCI | Javed Absar |
2017-02-22 | [ARM] Classification Improvements to ARM Sched-Models. NFCI. | Javed Absar |
2017-02-02 | [ARM] Classification Improvements to ARM Sched-Model. NFCI. | Javed Absar |
2017-01-23 | [ARM] Classification Improvements to ARM Sched-Models. NFCI. | Javed Absar |
2016-11-15 | [ARM] Add machine scheduler for Cortex-R52 | Javed Absar |
2016-02-23 | CodeGen: TII: Take MachineInstr& in predicate API, NFC | Duncan P. N. Exon Smith |
2016-01-25 | [ARM] Add ARMv8.2-A FP16 scalar instructions | Oliver Stannard |
2015-12-16 | Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions" | Reid Kleckner |
2015-12-16 | [ARM] Add ARMv8.2-A FP16 scalar instructions | Oliver Stannard |
2013-06-06 | ARM sched model: Add integer VFP/SIMD instructions on Swift | Arnold Schwaighofer |
2013-06-05 | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer |
2013-06-04 | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer |
2013-06-04 | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer |
2013-04-05 | ARM scheduler model: Add scheduler info to more instructions and resource | Arnold Schwaighofer |
2013-04-05 | ARM scheduler model: Swift has varying latencies, uops for simple ALU ops | Arnold Schwaighofer |
2013-04-01 | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer |
2013-03-26 | Revert ARM Scheduler Model: Add resources instructions, map resources | Arnold Schwaighofer |
2013-03-26 | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer |
2013-03-26 | ARM Scheduler Model: Partial implementation of the new machine scheduler model | Arnold Schwaighofer |
2012-09-29 | Add LLVM support for Swift. | Bob Wilson |
2012-07-02 | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
2012-06-29 | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick |
2012-06-29 | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick |
2012-06-22 | Use "NoItineraries" for processors with no itineraries. | Andrew Trick |
2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
2012-01-22 | Add fused multiple+add instructions from VFPv4. | Anton Korobeynikov |
2011-01-20 | Sorry, several patches in one. | Evan Cheng |
2010-11-30 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
2010-11-29 | Add support for NEON VLD3-dup instructions. | Bob Wilson |
2010-11-28 | Add support for NEON VLD2-dup instructions. | Bob Wilson |
2010-11-27 | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson |
2010-11-13 | Conditional moves are slightly more expensive than moves. | Evan Cheng |
2010-11-03 | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng |
2010-11-02 | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
2010-11-01 | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson |
2010-10-11 | More ARM scheduling itinerary fixes. | Evan Cheng |
2010-10-11 | Proper VST scheduling itineraries. | Evan Cheng |
2010-10-09 | Add VLD4 scheduling itineraries. | Evan Cheng |
2010-10-09 | Finish vld3 and vld4. | Evan Cheng |
2010-10-09 | Correct some load / store instruction itinerary mistakes: | Evan Cheng |
2010-10-07 | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng |
2010-10-06 | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng |
2010-10-01 | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng |
2010-09-30 | ARM instruction itinerary fixes: | Evan Cheng |
2010-09-29 | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng |
2010-09-29 | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng |
2010-09-29 | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng |