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path: root/lib/Target/ARM/ARMSchedule.td
AgeCommit message (Expand)Author
2017-08-11[ARM] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer
2017-06-28[ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn
2017-06-02[ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar
2017-05-24[ARM] Add VLDx/VSTx sched defs for machine-schedulers. NFCIJaved Absar
2017-02-22[ARM] Classification Improvements to ARM Sched-Models. NFCI.Javed Absar
2017-02-02[ARM] Classification Improvements to ARM Sched-Model. NFCI.Javed Absar
2017-01-23[ARM] Classification Improvements to ARM Sched-Models. NFCI.Javed Absar
2016-11-15[ARM] Add machine scheduler for Cortex-R52 Javed Absar
2016-02-23CodeGen: TII: Take MachineInstr& in predicate API, NFCDuncan P. N. Exon Smith
2016-01-25[ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard
2015-12-16Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner
2015-12-16[ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard
2013-06-06ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer
2013-06-05ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer
2013-06-04Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer
2013-06-04ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer
2013-04-05ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer
2013-04-05ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer
2013-04-01ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
2013-03-26ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer
2013-03-26ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer
2012-09-29Add LLVM support for Swift.Bob Wilson
2012-07-02Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
2012-06-29Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick
2012-06-29Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick
2012-06-22Use "NoItineraries" for processors with no itineraries.Andrew Trick
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu
2012-01-22Add fused multiple+add instructions from VFPv4.Anton Korobeynikov
2011-01-20Sorry, several patches in one.Evan Cheng
2010-11-30Add support for NEON VLD3-dup instructions.Bob Wilson
2010-11-29Add support for NEON VLD3-dup instructions.Bob Wilson
2010-11-28Add support for NEON VLD2-dup instructions.Bob Wilson
2010-11-27Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson
2010-11-13Conditional moves are slightly more expensive than moves.Evan Cheng
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten...Evan Cheng
2010-11-02Add NEON VST1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-10-11More ARM scheduling itinerary fixes.Evan Cheng
2010-10-11Proper VST scheduling itineraries.Evan Cheng
2010-10-09Add VLD4 scheduling itineraries.Evan Cheng
2010-10-09Finish vld3 and vld4.Evan Cheng
2010-10-09Correct some load / store instruction itinerary mistakes:Evan Cheng
2010-10-07Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng
2010-10-06- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng
2010-10-01NEON scheduling info fix. vmov reg, reg are single cycle instructions.Evan Cheng
2010-09-30ARM instruction itinerary fixes:Evan Cheng
2010-09-29Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMPEvan Cheng
2010-09-29Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.Evan Cheng
2010-09-29Assign bitwise binary instructions different itinerary classes from ALU instr...Evan Cheng