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path: root/lib/Target/AMDGPU
AgeCommit message (Expand)Author
2018-04-10Merging r329588:Tom Stellard
2018-04-09Merging r326535:Tom Stellard
2018-02-19Merging r324353:Hans Wennborg
2018-02-13Merging r324746:Hans Wennborg
2018-02-02Merging r323908:Hans Wennborg
2018-02-02Merging r323909:Hans Wennborg
2018-01-30Merging r323706:Hans Wennborg
2018-01-03Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury
2017-12-29AMDGPU: Use unique PSVs for buffer resourcesMatt Arsenault
2017-12-29AMDGPU: Remove mayLoad/hasSideEffects from MIMG storesMatt Arsenault
2017-12-29AMDGPU: Implement getTgtMemIntrinsic for imagesMatt Arsenault
2017-12-29[AMDGPU][MC] Incorrect parsing of flat/global atomic modifiersDmitry Preobrazhensky
2017-12-22(Re-landing) Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
2017-12-22[AMDGPU][MC] Corrected handling of negative expressionsDmitry Preobrazhensky
2017-12-22[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32Dmitry Preobrazhensky
2017-12-22[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky
2017-12-21Revert "Expose a TargetMachine::getTargetTransformInfo function"Sanjoy Das
2017-12-21Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
2017-12-20[AMDGPU, AsmParser] Enable the mnemonic spell corrector.Matt Arsenault
2017-12-19[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for A...Mark Searles
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun
2017-12-15Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-14TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault
2017-12-14DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault
2017-12-14Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-13CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.valueYaxun Liu
2017-12-13AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault
2017-12-13[Targets] Don't automatically include the scheduler class enum from *GenInstr...Craig Topper
2017-12-13Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun
2017-12-11LSR: Check more intrinsic pointer operandsMatt Arsenault
2017-12-11[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky
2017-12-08AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov
2017-12-08AMDGPU: Set IntrReadMem on memtime intrinsicsMatt Arsenault
2017-12-08AMDGPU: image_getlod and image_getresinfo do not read memoryMatt Arsenault
2017-12-08AMDGPU: Preserve MMO in adjustWritemaskMatt Arsenault
2017-12-08AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is no...Konstantin Zhuravlyov
2017-12-08[AMDGPU] add labels to +DumpCode outputTim Renouf
2017-12-07[AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr c...Mark Searles
2017-12-07[AMDGPU] Add options for waitcnt pass debugging; add instr count in debug out...Mark Searles
2017-12-07[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecogn...Mark Searles
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-05AMDGPU: Fix SDWA crash on inline asmMatt Arsenault
2017-12-05AMDGPU: Fix infinite loop with dbg_valueMatt Arsenault
2017-12-05AMDGPU: Fix missing subtarget feature initializerMatt Arsenault
2017-12-05AMDGPU: Fix crash when scheduling DBG_VALUEMatt Arsenault
2017-12-04AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instructionJan Vesely
2017-12-04AMDGPU: Disable fp64 support on pre GCN asicsJan Vesely
2017-12-04AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault
2017-12-04AMDGPU: Use return value of MorphNodeToMatt Arsenault
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
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