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path: root/lib/Target/AMDGPU/VOP1Instructions.td
AgeCommit message (Expand)Author
2018-06-27[AMDGPU] Convert rcp to rcp_iflagStanislav Mekhanoshin
2018-04-11[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32Dmitry Preobrazhensky
2018-04-02[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16Dmitry Preobrazhensky
2018-03-30[AMDGPU] Fixed some instructions latenciesStanislav Mekhanoshin
2018-03-26AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen base classesNicolai Haehnle
2018-01-15[AMDGPU] Copy impdefs from pseudo to real instructionsStanislav Mekhanoshin
2017-10-03AMDGPU: Remove global isGCN predicatesMatt Arsenault
2017-08-16[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky
2017-08-08[AMDGPU] Add llvm.amdgpu.update.dpp intrinsicConnor Abbott
2017-08-07[AMDGPU] Add pseudo "old" source to all DPP instructionsConnor Abbott
2017-06-21[AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton
2017-05-23[AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton
2017-04-12[AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)Dmitry Preobrazhensky
2017-03-27[AMDGPU][MC] Fix for Bug 28207 + LIT testsDmitry Preobrazhensky
2017-03-15AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault
2017-03-03[AMDGPU][MC] Fix for Bug 30829 + LIT testsDmitry Preobrazhensky
2017-02-28AMDGPU: Add definition for v_swap_b32Matt Arsenault
2017-02-27AMDGPU: Add VOP3P instruction formatMatt Arsenault
2017-02-23AMDGPU/SI: Fix trunc i16 patternJan Vesely
2017-02-10AMDGPU: Fix trailing whitespaceMatt Arsenault
2017-02-02AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault
2017-01-11[AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate...Sam Kolton
2016-12-22[AMDGPU] Add pseudo SDWA instructionsSam Kolton
2016-12-22[AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwaSam Kolton
2016-11-19Check that emitted instructions meet their predicates on all targets except A...Daniel Sanders
2016-11-18[AMDGPU] Change frexp.exp intrinsic to return i16 for f16 inputKonstantin Zhuravlyov
2016-11-13[AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov
2016-11-10AMDGPU: Add VI i16 supportTom Stellard
2016-11-04Revert "AMDGPU: Add VI i16 support"Tom Stellard
2016-11-03AMDGPU: Add VI i16 supportTom Stellard
2016-10-24AMDGPU: Fix Two Address problems with v_movreldNicolai Haehnle
2016-10-12AMDGPU: Initial implementation of VGPR indexing modeMatt Arsenault
2016-10-12AMDGPU: Add instruction definitions for VGPR indexingMatt Arsenault
2016-09-23[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin
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