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path: root/lib/Target/AMDGPU/SIRegisterInfo.td
AgeCommit message (Expand)Author
2018-06-15AMDGPU: Make v4i16/v4f16 legalMatt Arsenault
2018-06-07AMDGPU: Fix not including v2f64 in SReg_128Matt Arsenault
2018-01-10[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky
2017-12-22[AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky
2017-12-11[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky
2017-09-29AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle
2017-08-01AMDGPU: Initial implementation of callsMatt Arsenault
2017-07-24AMDGPU: Fix allocating pseudo-registersMatt Arsenault
2017-07-21AMDGPU: Add instruction definitions for some scratch_* instructionsMatt Arsenault
2017-07-18AMDGPU: Figure out private memory regs after loweringMatt Arsenault
2017-07-18[AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8Dmitry Preobrazhensky
2017-03-21AMDGPU: Fix not including v2i16/v2f16 in register classMatt Arsenault
2017-02-27AMDGPU: Add VOP3P instruction formatMatt Arsenault
2017-02-21AMDGPU: Don't use stack space for SGPR->VGPR spillsMatt Arsenault
2017-02-18AMDGPU: Merge initial gfx9 supportMatt Arsenault
2016-12-14AMDGPU: Make AllocationPriority of SGPRs higher than VGPRsMatt Arsenault
2016-12-10AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault
2016-12-09AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructionsMatt Arsenault
2016-12-05AMDGPU: Assembler support for expMatt Arsenault
2016-12-05AMDGPU: Change how exp is printedMatt Arsenault
2016-11-29AMDGPU: Disallow exec as SMEM instruction operandMatt Arsenault
2016-11-25AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak
2016-11-25Revert "AMDGPU: Make m0 unallocatable"Marek Olsak
2016-11-24AMDGPU: Make m0 unallocatableMatt Arsenault
2016-11-13[AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov
2016-11-10AMDGPU: Add VI i16 supportTom Stellard
2016-11-04Revert "AMDGPU: Add VI i16 support"Tom Stellard
2016-11-03AMDGPU: Add VI i16 supportTom Stellard
2016-11-01AMDGPU: Whitespace fixesMatt Arsenault
2016-09-09AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.Wei Ding
2016-09-09AMDGPU] Assembler: better support for immediate literals in assembler.Sam Kolton
2016-09-07Remove unnecessary call to getAllocatableRegClassMatt Arsenault
2016-09-03AMDGPU: Set sizes of spill pseudosMatt Arsenault
2016-07-21[AMDGPU] Some code cleaning in SIRegisterInfo.tdSam Kolton
2016-07-19AMDGPU: Expand register indexing pseudos in custom inserterMatt Arsenault
2016-05-21AMDGPU: Define priorities for register classesMatt Arsenault
2016-05-21AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0Matt Arsenault
2016-04-29Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rewor...Artem Tamazov
2016-04-27Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ...Chad Rosier
2016-04-27[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov
2016-04-20AMDGPU/SI: Assembler: improvements to support trap handlers.Nikolay Haustov
2016-04-13[AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov
2016-02-12AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard
2016-01-26AMDGPU: Make v32i8/v64i8 illegal typesMatt Arsenault
2015-12-21AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VITom Stellard
2015-12-21AMDGPU/SI: Change assembly name for flat scratch registers to flat_scratchTom Stellard
2015-11-25AMDGPU: Make v2i64/v2f64 legal types.Matt Arsenault
2015-11-12Revert "Remove unnecessary call to getAllocatableRegClass"Tom Stellard
2015-11-11AMDGPU: Set isAllocatable = 0 on VS_32/VS_64Matt Arsenault
2015-11-06AMDGPU: Fix hardcoded alignment of spill.Matt Arsenault
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