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path: root/lib/Target/AMDGPU/SIInstrInfo.td
AgeCommit message (Expand)Author
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-06-28AMDGPU: Separate R600 and GCN TableGen filesTom Stellard
2018-06-22AMDGPU: Add patterns for i32/i64 local atomic load/storeMatt Arsenault
2018-06-21AMDGPU: Remove old-style image intrinsicsNicolai Haehnle
2018-06-21AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle
2018-06-21AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle
2018-06-04AMDGPU: Make various NamedOperands upper caseNicolai Haehnle
2018-05-24AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard
2018-04-30AMDGPU: Add Vega12 and Vega20Matt Arsenault
2018-04-04AMDGPU: Dimension-aware image intrinsicsNicolai Haehnle
2018-03-16[AMDGPU] Supported ds_write_b128 generation.Farhana Aleen
2018-03-16[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP o...Dmitry Preobrazhensky
2018-03-09[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local a...Farhana Aleen
2018-02-21[AMDGPU][MC] Added lds support for MUBUF instructionsDmitry Preobrazhensky
2018-01-29[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16Dmitry Preobrazhensky
2018-01-26[AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky
2018-01-18AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang
2018-01-17[AMDGPU] add LDS f32 intrinsicsDaniil Fukalov
2018-01-17[AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky
2018-01-12AMDGPU/SI: Add d16 support for buffer intrinsics.Changpeng Fang
2017-12-04AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault
2017-11-29AMDGPU: Select DS insts without m0 initializationMatt Arsenault
2017-11-13AMDGPU: Select d16 loads into low component of registerMatt Arsenault
2017-11-09AMDGPU: Lower buffer store and atomic intrinsics manuallyMarek Olsak
2017-10-24AMDGPU: Add new intrinsic llvm.amdgcn.kill(i1)Marek Olsak
2017-10-23AMDGPU: Cleanup local atomic node namesMatt Arsenault
2017-10-10AMDGPU: Fix failure to select branch with optnoneMatt Arsenault
2017-09-29AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle
2017-09-20AMDGPU: Cleanup load/store PatFragsMatt Arsenault
2017-09-11[AMDGPU] exp should not be in WQM modeTim Renouf
2017-09-07AMDGPU: Start selecting v_mad_mix_f32Matt Arsenault
2017-08-31AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault
2017-08-30AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault
2017-08-16[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky
2017-08-09[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky
2017-08-07[AMDGPU] Add pseudo "old" source to all DPP instructionsConnor Abbott
2017-08-07[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VIDmitry Preobrazhensky
2017-07-22AMDGPU: Remove leftover td fileMatt Arsenault
2017-07-21[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky
2017-07-18[AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if om...Sam Kolton
2017-07-18Revert r308179 which causes tablegen to spam stderr on every build.Chandler Carruth
2017-07-17[AMDGPU] CodeGen: check dst operand type to determine if omod is supported fo...Sam Kolton
2017-07-07[AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX*Dmitry Preobrazhensky
2017-06-28[AMDGPU] Add pattern for v_alignbit_b32 with immediateStanislav Mekhanoshin
2017-06-22[AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard
2017-06-21[AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton
2017-06-20AMDGPU: Start adding global_* instructionsMatt Arsenault
2017-06-12AMDGPU: Start adding offset fields to flat instructionsMatt Arsenault
2017-05-31[AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky
2017-05-26[AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton
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