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path: root/lib/Target/AMDGPU/SIInstrFormats.td
AgeCommit message (Expand)Author
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-07-05[AMDGPU] Add VALU to V_INTERP InstructionsRyan Taylor
2018-06-28AMDGPU: Separate R600 and GCN TableGen filesTom Stellard
2018-06-21AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle
2018-06-21AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle
2018-02-23[MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry
2018-01-30[AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry
2018-01-18AMDGPU/SI: Add d16 support for image intrinsics.Changpeng Fang
2017-11-20[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky
2017-11-17[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky
2017-10-03AMDGPU: Remove global isGCN predicatesMatt Arsenault
2017-08-31AMDGPU: Fold clamp modifier for packed instructionsMatt Arsenault
2017-08-16[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodesDmitry Preobrazhensky
2017-08-09[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodesDmitry Preobrazhensky
2017-07-21AMDGPU: Introduce maybeAtomic instruction flagKonstantin Zhuravlyov
2017-07-21[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifierDmitry Preobrazhensky
2017-05-19[AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky
2017-03-24AMDGPU: Unify divergent function exits.Matt Arsenault
2017-02-27AMDGPU: Add VOP3P instruction formatMatt Arsenault
2017-02-22AMDGPU: Fold FP clamp as modifier bitMatt Arsenault
2016-12-10AMDGPU: Fix vintrp disassemblyMatt Arsenault
2016-12-09AMDGPU: Clean up instruction bitsMatt Arsenault
2016-12-09AMDGPU/SI: Don't mark VINTRP instructions as mayLoadTom Stellard
2016-12-05AMDGPU: Refactor exp instructionsMatt Arsenault
2016-11-15[AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>Sam Kolton
2016-11-01AMDGPU: Workaround for instruction size with literalsMatt Arsenault
2016-10-28AMDGPU: Add definitions for scalar store instructionsMatt Arsenault
2016-09-23[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitionsValery Pykhtin
2016-09-19[AMDGPU] Refactor VOPC instruction TD definitionsValery Pykhtin
2016-09-16AMDGPU: Allow some control flow intrinsics to be CSEdMatt Arsenault
2016-09-16AMDGPU: Use SOPK compare instructionsMatt Arsenault
2016-09-14Revert "AMDGPU: Use SOPK compare instructions"Matt Arsenault
2016-09-14AMDGPU: Use SOPK compare instructionsMatt Arsenault
2016-09-10[AMDGPU] Refactor MUBUF/MTBUF instructionsValery Pykhtin
2016-09-10AMDGPU: Implement is{LoadFrom|StoreTo}FrameIndexMatt Arsenault
2016-09-09[AMDGPU] Assembler: match e32 VOP instructions before e64.Sam Kolton
2016-09-05[AMDGPU] Refactor FLAT TD instructionsValery Pykhtin
2016-09-01[AMDGPU] Scalar Memory instructions TD refactoringValery Pykhtin
2016-08-30[AMDGPU] Refactor SOP instructions TD files.Valery Pykhtin
2016-08-27AMDGPU: Remove unneeded implicit exec uses/defsMatt Arsenault
2016-08-02AMDGPU: Stay in WQM for non-intrinsic storesNicolai Haehnle
2016-08-01[AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin
2016-07-12AMDGPU: Cleanup pseudoinstructionsMatt Arsenault
2016-07-11AMDGPU: Treat texture gather instructions more like other MIMG instructionsNicolai Haehnle
2016-06-22AMDGPU: Fix verifier errors in SILowerControlFlowMatt Arsenault
2016-05-06[TableGen] AsmMatcher: support for default values for optional operandsSam Kolton
2016-04-26[AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton
2016-04-01[AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin
2016-03-11[AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin
2016-03-10[AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin
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