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path: root/lib/Target/AMDGPU/SIISelLowering.h
AgeCommit message (Expand)Author
2017-12-14TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault
2017-12-04AMDGPU: Fix creating invalid copy when adjusting dmaskMatt Arsenault
2017-11-15AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault
2017-11-13AMDGPU: Fix multi-use shl/add combineMatt Arsenault
2017-10-13AMDGPU: Implement hasBitPreservingFPLogicMatt Arsenault
2017-09-20AMDGPU: Start selecting v_mad_mixhi_f16Matt Arsenault
2017-08-11AMDGPU: Start adding tail call supportMatt Arsenault
2017-08-03AMDGPU: Pass special input registers to functionsMatt Arsenault
2017-08-01AMDGPU: Initial implementation of callsMatt Arsenault
2017-07-29AMDGPU: Teach isLegalAddressingMode about global_* instructionsMatt Arsenault
2017-07-28AMDGPU: Annotate implicitarg.ptr usageMatt Arsenault
2017-07-26TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<in...Zvi Rackover
2017-07-21[SystemZ, LoopStrengthReduce]Jonas Paulsson
2017-07-18AMDGPU: Figure out private memory regs after loweringMatt Arsenault
2017-07-10Add DAG argument to canMergeStoresTo NFC.Nirav Dave
2017-06-21[AMDGPU] Combine add and adde, sub and subeStanislav Mekhanoshin
2017-06-21[AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin
2017-06-19AMDGPU: Cleanup CreateLiveInRegisterMatt Arsenault
2017-05-24[AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI.Nirav Dave
2017-05-17AMDGPU: Start defining a calling conventionMatt Arsenault
2017-05-11AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault
2017-04-12AMDGPU: Fix invalid copies when copying i1 to phys regMatt Arsenault
2017-04-11AMDGPU: Refactor argument loweringMatt Arsenault
2017-04-06AMDGPU/GFX9: Fix shared and private aperture queriesKonstantin Zhuravlyov
2017-03-31AMDGPU: Remove unnecessary ands when f16 is legalMatt Arsenault
2017-03-17AMDGPU: Cleanup control flow intrinsicsMatt Arsenault
2017-03-15AMDGPU: Allow sinking of addressing modes for atomic_inc/decMatt Arsenault
2017-02-27AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault
2017-02-22AMDGPU: Add cvt.pkrtz intrinsicMatt Arsenault
2017-02-21AMDGPU: Redefine clamp node as clamp 0.0-1.0Matt Arsenault
2017-01-23AMDGPU: Custom lower more vector operationsMatt Arsenault
2017-01-09AMDGPU: Add Assert[SZ]Ext during argument load creationMatt Arsenault
2016-12-22AMDGPU: Check fast math flags in fadd/fsub combinesMatt Arsenault
2016-12-22AMDGPU: Form more FMAs if fusion is allowedMatt Arsenault
2016-12-22AMDGPU: Move combines into separate functionsMatt Arsenault
2016-12-22AMDGPU: Custom lower f16 fdivMatt Arsenault
2016-12-08AMDGPU: Make f16 ConstantFP legalMatt Arsenault
2016-12-08[AMDGPU] Scalarization of global uniform loads.Alexander Timofeev
2016-12-02AMDGPU: Implement isCheapAddrSpaceCastMatt Arsenault
2016-11-17[AMDGPU] Custom lower f16 = fp_round f64Konstantin Zhuravlyov
2016-11-17[AMDGPU] Promote f16/i16 conversions to f32/i32Konstantin Zhuravlyov
2016-11-13[AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov
2016-10-20[AMDGPU] Emit constant address space data in .rodata section and use relocati...Konstantin Zhuravlyov
2016-09-17AMDGPU: Fix broken FrameIndex handlingMatt Arsenault
2016-09-14AMDGPU: Improve splitting 64-bit bit ops by constantsMatt Arsenault
2016-07-28AMDGPU: Remove analyzeImmediateMatt Arsenault
2016-07-19AMDGPU: Change fdiv lowering based on !fpmath metadataMatt Arsenault
2016-07-12AMDGPU: Follow up to r275203Matt Arsenault
2016-06-30CodeGen: Use MachineInstr& in TargetLowering, NFCDuncan P. N. Exon Smith
2016-06-25[AMDGPU] Emit debugger prologue and emit the rest of the debugger fields in t...Konstantin Zhuravlyov
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