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path: root/lib/Target/AMDGPU/SIISelLowering.cpp
AgeCommit message (Expand)Author
2018-08-01[AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor
2018-08-01AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov
2018-07-31AMDGPU: Break 64-bit arguments into 32-bit piecesMatt Arsenault
2018-07-31AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on callsMatt Arsenault
2018-07-31AMDGPU: Scalarize vector argument types to callsMatt Arsenault
2018-07-31AMDGPU: Don't handle FP16_TO_FP in isCanonicalizedMatt Arsenault
2018-07-31AMDGPU: Fold undef fcanonicalize to qNaNMatt Arsenault
2018-07-28AMDGPU: Stop wasting argument registers with v3i32/v3f32Matt Arsenault
2018-07-20Reapply "AMDGPU: Fix handling of alignment padding in DAG argument lowering"Matt Arsenault
2018-07-16[AMDGPU] [AMDGPU] Support a fdot2 pattern.Farhana Aleen
2018-07-14Revert "AMDGPU: Fix handling of alignment padding in DAG argument lowering"Evgeniy Stepanov
2018-07-13AMDGPU: Properly handle shader inputs with split argumentsMatt Arsenault
2018-07-13AMDGPU: Fix handling of alignment padding in DAG argument loweringMatt Arsenault
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-06-28AMDGPU: Separate R600 and GCN TableGen filesTom Stellard
2018-06-28AMDGPU: Remove MFI::ABIArgOffsetMatt Arsenault
2018-06-28AMDGPU: Error on calls from graphics shadersMatt Arsenault
2018-06-27[AMDGPU] Convert rcp to rcp_iflagStanislav Mekhanoshin
2018-06-26[AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsicStanislav Mekhanoshin
2018-06-25AMDGPU: Remove commented out codeMatt Arsenault
2018-06-21AMDGPU: Remove old-style image intrinsicsNicolai Haehnle
2018-06-21AMDGPU: Select MIMG instructions manually in SITargetLoweringNicolai Haehnle
2018-06-21AMDGPU: Refactor MIMG instruction TableGen using generic tablesNicolai Haehnle
2018-06-21AMDGPU: Use generic tables instead of SearchableTableNicolai Haehnle
2018-06-21AMDGPU: Turn D16 for MIMG instructions into a regular operandNicolai Haehnle
2018-06-16[AMDGPU] setcc (select cc, CT, CF), CF, eq | ne -> xor cc, -1 | ccStanislav Mekhanoshin
2018-06-15AMDGPU: Add combine for short vector extract_vector_eltsMatt Arsenault
2018-06-15AMDGPU: Make v4i16/v4f16 legalMatt Arsenault
2018-06-13AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLoweringTom Stellard
2018-06-12[AMDGPU] DAG combine to produce V_PERM_B32Stanislav Mekhanoshin
2018-06-08[AMDGPU] Inline asm - added i16, half and i128 types supportDaniil Fukalov
2018-06-07AMDGPU: Try a lot harder to emit scalar loadsMatt Arsenault
2018-06-06AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16Matt Arsenault
2018-06-05AMDGPU: Use more custom insert/extract_vector_elt loweringMatt Arsenault
2018-06-01Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet
2018-05-31[AMDGPU] Track occupancy in MFIStanislav Mekhanoshin
2018-05-30AMDGPU: Use better alignment for kernarg loweringMatt Arsenault
2018-05-29AMDGPU: Pass function directly instead of MachineFunctionMatt Arsenault
2018-05-29AMDGPU: Add nuw to add off of kernarg ptrMatt Arsenault
2018-05-29[AMDGPU] Fixed build warningTim Renouf
2018-05-24AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMPTom Stellard
2018-05-22AMDGPU: Move AMDGPUTargetLowering::isFPExtFoldable() into SITargetLoweringTom Stellard
2018-05-22AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault
2018-05-22AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard
2018-05-16[AMDGPU] Change llvm.debugtrap to be a debug breakpoint that can resume execu...Tony Tye
2018-05-16AMDGPU: Custom lower v4i16/v4f16 vector operationsMatt Arsenault
2018-05-15[AMDGPU] Fix handling of void types in isLegalAddressingModeStanislav Mekhanoshin
2018-05-13AMDGPU: Make undef legal for v2i16/v2f16Matt Arsenault
2018-05-09[AMDGPU] Support horizontal vectorization of min/max.Farhana Aleen
2018-05-09AMDGPU: Stop special casing constant indexes of extract_vector_eltMatt Arsenault
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