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path: root/lib/Target/AMDGPU/EvergreenInstructions.td
AgeCommit message (Expand)Author
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-06-28AMDGPU: Separate R600 and GCN TableGen filesTom Stellard
2018-02-07AMDGPU: Select BFI patterns with 64-bit intsMatt Arsenault
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-10-23AMDGPU: Cleanup local atomic node namesMatt Arsenault
2017-10-12Implement custom lowering for ISD::CTTZ_ZERO_UNDEF and ISD::CTTZ.Wei Ding
2017-10-03AMDGPU: Remove global isGCN predicatesMatt Arsenault
2017-09-20AMDGPU: Cleanup load/store PatFragsMatt Arsenault
2017-03-15AMDGPU: Fix unnecessary ands when packing f16 vectorsMatt Arsenault
2017-02-23AMDGPU: Add another BFE patternMatt Arsenault
2017-01-16ADMGPU/EG,CM: Implement _noret global atomicsJan Vesely
2017-01-11AMDGPU/EG,CM: Add fp16 conversion instructionsJan Vesely
2016-08-27AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault
2016-08-15AMDGPU/R600: Convert buffer id to VTX_READ inputJan Vesely
2016-07-18AMDGPU/R600: Replace barrier intrinsicsMatt Arsenault
2016-07-10AMDGPU/R600: Add implicitarg.ptr intrinsicJan Vesely
2016-07-05AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loadsTom Stellard
2016-05-13AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)Jan Vesely
2016-01-29AMDGPU: Remove 24-bit intrinsicsMatt Arsenault
2016-01-22AMDGPU: Remove random TGSI intrinsicMatt Arsenault
2016-01-11AMDGPU: Pattern match ffbh pattern to instruction.Matt Arsenault
2015-10-01AMDGPU: Add MEM_RAT STORE_TYPED.Tom Stellard
2015-06-13R600 -> AMDGPU renameTom Stellard
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