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path: root/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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2018-04-10Merging r329588:Tom Stellard
------------------------------------------------------------------------ r329588 | tstellar | 2018-04-09 09:09:13 -0700 (Mon, 09 Apr 2018) | 11 lines AMDGPU: Initialize GlobalISel passes Summary: This fixes AMDGPU GlobalISel test failures when enabling the AMDGPU target without any other targets that use GlobalISel. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D45353 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329662 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-22(Re-landing) Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
Re-land r321234. It had to be reverted because it broke the shared library build. The shared library build broke because there was a missing LLVMBuild dependency from lib/Passes (which calls TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can tell, this problem was always there but was somehow masked before (perhaps because TargetMachine::getTargetIRAnalysis was a virtual function). Original commit message: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target. See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this. Reviewers: echristo, MatzeB, hfinkel Reviewed By: hfinkel Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D41464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321375 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21Revert "Expose a TargetMachine::getTargetTransformInfo function"Sanjoy Das
This reverts commit r321234. It breaks the -DBUILD_SHARED_LIBS=ON build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-21Expose a TargetMachine::getTargetTransformInfo functionSanjoy Das
Summary: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target. See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this. Reviewers: echristo, MatzeB, hfinkel Reviewed By: hfinkel Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D41464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321234 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-20AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG ↵Valery Pykhtin
(experimental) Differential revision: https://reviews.llvm.org/D39897 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-06[AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environmentYaxun Liu
Differential Revision: https://reviews.llvm.org/D39657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-31[AMDGPU] Clean up symbols in the global namespace.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317051 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-12Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine"Matthias Braun
Reverting to investigate layering effects of MCJIT not linking libCodeGen but using TargetMachine::getNameWithPrefix() breaking the lldb bots. This reverts commit r315633. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-12TargetMachine: Merge TargetMachine and LLVMTargetMachineMatthias Braun
Merge LLVMTargetMachine into TargetMachine. - There is no in-tree target anymore that just implements TargetMachine but not LLVMTargetMachine. - It should still be possible to stub out all the various functions in case a target does not want to use lib/CodeGen - This simplifies the code and avoids methods ending up in the wrong interface. Differential Revision: https://reviews.llvm.org/D38489 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315633 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-10AMDGPU: Fix incorrect selection of pseudo-branchesMatt Arsenault
These should only be used if the machine structurizer is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315357 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-10[AMDGPU] Lower enqueued blocks and generate runtime metadataYaxun Liu
This patch adds a post-linking pass which replaces the function pointer of enqueued block kernel with a global variable (runtime handle) and adds runtime-handle attribute to the enqueued block kernel. In LLVM CodeGen the runtime-handle metadata will be translated to RuntimeHandle metadata in code object. Runtime allocates a global buffer for each kernel with RuntimeHandel metadata and saves the kernel address required for the AQL packet into the buffer. __enqueue_kernel function in device library knows that the invoke function pointer in the block literal is actually runtime handle and loads the kernel address from it and puts it into AQL packet for dispatching. This cannot be done in FE since FE cannot create a unique global variable with external linkage across LLVM modules. The global variable with internal linkage does not work since optimization passes will try to replace loads of the global variable with its initialization value. Differential Revision: https://reviews.llvm.org/D38610 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315352 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-29[AMDGPU] Set fast-math flags on functions given the optionsStanislav Mekhanoshin
We have a single library build without relaxation options. When inlined library functions remove fast math attributes from the functions they are integrated into. This patch sets relaxation attributes on the functions after linking provided corresponding relaxation options are given. Math instructions inside the inlined functions remain to have no fast flags, but inlining does not prevent fast math transformations of a surrounding caller code anymore. Differential Revision: https://reviews.llvm.org/D38325 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[AMDGPU] Fixed memory leak with inliner replacedStanislav Mekhanoshin
Delete inliner before replacing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313723 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[AMDGPU] Fix regression in test clang/test/CodeGen/backend-unsupported-error.llStanislav Mekhanoshin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313718 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-20[AMDGPU] Port of HSAIL inlinerStanislav Mekhanoshin
Differential Revision: https://reviews.llvm.org/D36849 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313714 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-19AMDGPU: Run internalize symbols at -O0Matt Arsenault
The relocations used for externally visible functions aren't supported, so the direct call emitted ends up hitting a linker error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313616 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-11[AMDGPU] Ported and adopted AMDLibCalls passStanislav Mekhanoshin
The pass does simplifications of well known AMD library calls. If given -amdgpu-prelink option it works in a pre-link mode which allows to reference new library functions which will be linked in later. In addition it also used to process traditional AMD option -fuse-native which allows to replace some of the functions with their fast native implementations from the library. The necessary glue to pass the prelink option and translate -fuse-native is to be added to the driver. Differential Revision: https://reviews.llvm.org/D36436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310731 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-08AMDGPU: Move R600 parts of AMDGPUISelDAGToDAG into their own classTom Stellard
Summary: This refactoring is required in order to split the R600 and GCN tablegen files. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D36286 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310336 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-07AMDGPU: Remove redundant opt level checkMatt Arsenault
addOptimizedRegAlloc isn't used for -O0 already. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-07AMDGPU: Remove FixControlFlowLiveIntervals passMatt Arsenault
This hasn't done anything in a long time. This was running after the the control flow pseudos were expanded, so this would never find them. The control flow pseudo expansion was moved to solve the problem this pass was supposed to solve in the first place, except handling it earlier also fixes it for fast regalloc which doesn't use LiveIntervals. Noticed by checking LCOV reports. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310274 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-07AMDGPU: Cleanup subtarget featuresMatt Arsenault
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-04[AMDGPU] Add support for Whole Wavefront ModeConnor Abbott
Summary: Whole Wavefront Wode (WWM) is similar to WQM, except that all of the lanes are always enabled, regardless of control flow. This is required for implementing wavefront reductions in non-uniform control flow, where we need to use the inactive lanes to propagate intermediate results, so they need to be enabled. We need to propagate WWM to uses (unless they're explicitly marked as exact) so that they also propagate intermediate results correctly. We do the analysis and exec mask munging during the WQM pass, since there are interactions with WQM for things that require both WQM and WWM. For simplicity, WWM is entirely block-local -- blocks are never WWM on entry or exit of a block, and WWM is not propagated to the block level. This means that computations involving WWM cannot involve control flow, but we only ever plan to use WWM for a few limited purposes (none of which involve control flow) anyways. Shaders can ask for WWM using the @llvm.amdgcn.wwm intrinsic. There isn't yet a way to turn WWM off -- that will be added in a future change. Finally, it turns out that turning on inactive lanes causes a number of problems with register allocation. While the best long-term solution seems like teaching LLVM's register allocator about predication, for now we need to add some hacks to prevent ourselves from getting into trouble due to constraints that aren't currently expressed in LLVM. For the gory details, see the comments at the top of SIFixWWMLiveness.cpp. Reviewers: arsenm, nhaehnle, tpr Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D35524 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310087 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03AMDGPU: Remove error on calls for amdgcnMatt Arsenault
Repurpose the -amdgpu-function-calls flag. Rather than require it to emit a call, only use it to run the always inline path or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310003 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03AMDGPU: Add analysis pass for function argument infoMatt Arsenault
This will allow only adding necessary inputs to callee functions that need special inputs forwarded from the kernel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309996 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03[GlobalISel] Make GlobalISel a non-optional library.Quentin Colombet
With this change, the GlobalISel library gets always built. In particular, this is not possible to opt GlobalISel out of the build using the LLVM_BUILD_GLOBAL_ISEL variable any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-03Delete Default and JITDefault code modelsRafael Espindola
IMHO it is an antipattern to have a enum value that is Default. At any given piece of code it is not clear if we have to handle Default or if has already been mapped to a concrete value. In this case in particular, only the target can do the mapping and it is nice to make sure it is always done. This deletes the two default enum values of CodeModel and uses an explicit Optional<CodeModel> when it is possible that it is unspecified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-02AMDGPU/R600: Initialize more passesTom Stellard
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36128 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309893 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-02AMDGPU: Analyze callee resource usage in AsmPrinterMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309781 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-01[AMDGPU] Collapse adjacent SI_END_CFStanislav Mekhanoshin
Add a pass to remove redundant S_OR_B64 instructions enabling lanes in the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any vector instructions between them we can only keep outer SI_END_CF, given that CFG is structured and exec bits of the outer end statement are always not less than exec bit of the inner one. This needs to be done before the RA to eliminate saved exec bits registers but after register coalescer to have no vector registers copies in between of different end cf statements. Differential Revision: https://reviews.llvm.org/D35967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309762 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-01AMDGPU: Initial implementation of callsMatt Arsenault
Includes a hack to fix the type selected for the GlobalAddress of the function, which will be fixed by changing the default datalayout to use generic pointers for 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309732 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-28AMDGPU: Add pass to replace out argumentsMatt Arsenault
It is better to return arguments directly in registers if we are making a call rather than introducing expensive stack usage. In one of sample compile from one of Blender's many kernel variants, this fires on about ~20 different functions. Future improvements may be to recognize simple cases where the pointer is indexing a small array. This also fails when the store to the out argument is in a separate block from the return, which happens in a few of the Blender functions. This should also probably be using MemorySSA which might help with that. I'm not sure this is correct as a FunctionPass, but MemoryDependenceAnalysis seems to not work with a ModulePass. I'm also not sure where it should run.I think it should run before DeadArgumentElimination, so maybe either EP_CGSCCOptimizerLate or EP_ScalarOptimizerLate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309416 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-21AMDGPU: Implement memory modelKonstantin Zhuravlyov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308781 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06AMDGPU: Add macro fusion schedule DAG mutationMatt Arsenault
Try to increase opportunities to shrink vcc uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05[AMDGPU] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet
NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307186 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-04[AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev
Differential revision: https://reviews.llvm.org/D34407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307097 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-04Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi
It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307054 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-03[AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev
Differential revision: https://reviews.llvm.org/D34407 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307026 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-28AMDGPU: Remove SITypeRewriterMatt Arsenault
This was an old workaround for using v16i8 in some old intrinsics for resource descriptors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306603 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-19[AMDGPU] Add infer address spaces pass before SROAStanislav Mekhanoshin
It adds it for the target after inlining but before SROA where we can get most out of it. Differential Revision: https://reviews.llvm.org/D34366 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305759 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-03[AMDGPU] Untangle SDWA pass from SIShrinkInstructionsStanislav Mekhanoshin
Remove dependency of SDWA pass on SIShrinkInstructions. The goal is to move SDWA even higher in the stack to avoid second run of MachineLICM, MachineCSE and SIFoldOperands. Also added handling to preserve original src modifiers. Differential Revision: https://reviews.llvm.org/D33860 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02AMDGPU: Register AMDGPUAlwaysInlineMatt Arsenault
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02[AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.Mark Searles
-enable-si-insert-waitcnts=1 becomes the default -enable-si-insert-waitcnts=0 to use old pass Differential Revision: https://reviews.llvm.org/D33730 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun
TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTargetMachine instead of just to a TargetMachine. While at it, also change the constructor to take a reference instead of a pointer as the TM must not be nullptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304247 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30[AMDGPU] Allow SDWA in instructions with immediates and SGPRsStanislav Mekhanoshin
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304219 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18[LegacyPassManager] Remove TargetMachine constructorsFrancis Visoiu Mistrih
This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-15Re-submit AMDGPUMachineCFGStructurizer.Jan Sjodin
Differential Revision: https://reviews.llvm.org/D23209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-15Revert 303091.Jan Sjodin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303098 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-15Add AMDGPUMachineCFGStructurizer.Jan Sjodin
Differential Revision: https://reviews.llvm.org/D23209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303091 91177308-0d34-0410-b5e6-96231b3b80d8