| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-02-12 | [AArch64] Improve v8.1-A code-gen for atomic load-and | Oliver Stannard |
| 2017-11-30 | [globalisel][tablegen] Add support for relative AtomicOrderings | Daniel Sanders |
| 2017-08-05 | [AArch64] LSE Atomics reorg - part 1 | Joel Jones |
| 2017-07-28 | [AArch64] Standardize suffixes for LSE Atomics mnemonics (NFCI) | Joel Jones |
| 2017-07-13 | [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomics | Matthew Simpson |
| 2017-06-21 | [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics. | Christof Douma |
| 2017-04-20 | AArch64: lower "fence singlethread" to a pure compiler barrier. | Tim Northover |
| 2016-08-02 | AArch64: properly calculate cmpxchg status in FastISel. | Tim Northover |
| 2016-04-14 | AArch64: expand cmpxchg after regalloc at -O0. | Tim Northover |
| 2016-04-06 | NFC: make AtomicOrdering an enum class | JF Bastien |
| 2014-08-18 | Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends | Robin Morisset |
| 2014-05-24 | AArch64/ARM64: move ARM64 into AArch64's place | Tim Northover |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |