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2018-06-15Added XGene modelMartin Elshuber
2017-12-18AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover
For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare circumstances. Work around the issue conservatively by avoiding the instruction entirely. This patch changes CodeGen so that problematic instructions are never generated, and the AsmParser so that an equivalent instruction is used (with a warning). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320965 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14[AArch64] Test patchEvandro Menezes
Fix formatting by adding a missing blank line to test new network setup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320760 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-17AArch64: Enable AES instruction fusion on Cyclone.Matthias Braun
Note that cyclone itself doesn't fuse, but newer apple chips do and we are using cyclone as the default when targeting apple OSes. The current code also does not capture all fusion patterns of apple CPUs yet; I am still looking for ways to refactor the code nicely to extend it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316036 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-25[AArch64] Add basic support for Qualcomm's Saphira CPU.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314105 91177308-0d34-0410-b5e6-96231b3b80d8
2017-09-18[AArch64] Add V8_2aOps feature to Cortex-A55 and 75Sam Parker
Add the missing hardware features the ProcA55 and ProcA75 feature. These are already enabled via the target parser, but I had missed them in the backend. Differential Revision: https://reviews.llvm.org/D37974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-28[AArch64][Falkor] Avoid generating STRQro* instructionsGeoff Berry
Summary: STRQro* instructions are slower than the alternative ADD/STRQui expanded instructions on Falkor, so avoid generating them unless we're optimizing for code size. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37020 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311931 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-21[ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker
This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311316 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-10[AArch64] Assembler support for v8.3 RCpcSam Parker
Added assembler and disassembler support for the new Release Consistent processor consistent instructions, introduced with ARM v8.3-A for AArch64. Differential Revision: https://reviews.llvm.org/D36522 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310575 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-10[ARM][AArch64] ARMv8.3-A enablementSam Parker
The beta ARMv8.3 ISA specifications have been released for AArch64 and AArch32, these can be found at: https://developer.arm.com/products/architecture/a-profile/exploration-tools An introduction to this architecture update can be found at: https://community.arm.com/processors/b/blog/posts/armv8-a-architecture-2016-additions This patch is the first in a series which will add ARM v8.3-A support in LLVM and Clang. It adds the necessary changes that create targets for both the ARM and AArch64 backends. Differential Revision: https://reviews.llvm.org/D36514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310561 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-09[AArch64] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer
Dot product is an optional ARMv8.2a extension, see also the public architecture specification here: https://developer.arm.com/products/architecture/a-profile/exploration-tools. This patch adds AArch64 assembler support for these dot product instructions. Differential Revision: https://reviews.llvm.org/D36515 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310480 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-18[AArch64] Adjust the feature set for Exynos M2Evandro Menezes
Add fusion of AES operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308388 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-13[AArch64] Add an SVE target feature to the backend and TargetParser.Amara Emerson
The feature will be used properly once assembler/disassembler support begins to land. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307917 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-15[AArch64] Enable FeatureFuseAES for the generic processor model.Florian Hahn
Summary: Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back gives a double digit speedup on benchmarks using those instructions on Cortex-A processors. In GCC, this optimization is part of the generic processor model as well. This change should not have a major performance impact on processors that do not optimize AES instruction pairs, although I only had access to Cortex-A processors for benchmarking. Reviewers: rengolin, kristof.beyls, javed.absar, evandro, silviu.baranga, MatzeB, mcrosier, joelkevinjones, joel_k_jones, bmakam, t.p.northover Reviewed By: evandro Subscribers: sbaranga, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D33836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305457 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-31[AArch64] Enable FeatureFuseAES on Cortex-A53.Florian Hahn
It improves performance on Cortex-A53. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304307 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-31[AArch64] Enable FeatureFuseAES on Cortex-A73.Florian Hahn
It improves performance on Cortex-A73. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304304 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-15[AArch64] Enable FeatureFuseAES on Cortex-A72.Florian Hahn
This patch enables fusing dependent AESE/AESMC and AESD/AESIMC instruction pairs on Cortex-A72, as recommended in the Software Optimization Guide, section 4.10. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303073 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-03[AArch64] armv8-A doesn't have CRC.Ahmed Bougacha
That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302077 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05[AArch64] Crypto requires FP.James Molloy
So if FP is disabled, crypto should also be disabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-31[AArch64] Add new subtarget feature to fold LSL into address mode.Balaram Makam
Summary: This feature enables folding of logical shift operations of up to 3 places into addressing mode on Kryo and Falkor that have a fastpath LSL. Reviewers: mcrosier, rengolin, t.p.northover Subscribers: junbuml, gberry, llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D31113 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299240 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-28[AArch64] [Assembler] option to disable negative immediate conversionsSanne Wouda
Summary: Similar to the ARM target in https://reviews.llvm.org/rL298380, this patch adds identical infrastructure for disabling negative immediate conversions, and converts the existing aliases to the new infrastucture. Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker Reviewed By: samparker Subscribers: samparker, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D31243 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298908 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-07[AArch64] Vulcan is now ThunderXT99Joel Jones
Broadcom Vulcan is now Cavium ThunderX2T99. LLVM Bugzilla: http://bugs.llvm.org/show_bug.cgi?id=32113 Minor fixes for the alignments of loops and functions for ThunderX T81/T83/T88 (better performance). Patch was tested with SpecCPU2006. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D30510 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297190 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-17[AArch64] Add Cavium ThunderX supportJoel Jones
This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295475 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01[AArch64] Add new target feature to fuse literal generationEvandro Menezes
This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, sections 4.14 and 4.15. Differential revision: https://reviews.llvm.org/D28698 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-01[AArch64] Add new subtarget feature to fuse AES crypto operationsEvandro Menezes
This feature enables the fusion of such operations on Cortex A57, as recommended in its Software Optimisation Guide, section 4.13, and on Exynos M1. Differential revision: https://reviews.llvm.org/D28491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293738 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24[AArch64] Fix typo. NFC.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292959 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24[AArch64] Rename 'no-quad-ldst-pairs' to 'slow-paired-128'Evandro Menezes
In order to follow the pattern of the existing 'slow-misaligned-128store' option, rename the option 'no-quad-ldst-pairs' to 'slow-paired-128'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292954 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-19Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292478 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18Re-revert: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders
More missing guards. My build didn't notice it due to a stale file left over from a Global ISel build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292369 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since last commit: The new tablegen pass is now correctly guarded by LLVM_BUILD_GLOBAL_ISEL and this should fix the buildbots however it may not be the whole fix. The previous buildbot failures suggest there may be a memory bug lurking that I'm unable to reproduce (including when using asan) or spot in the source. If they re-occur on this commit then I'll need assistance from the bot owners to track it down. Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292367 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16[AArch64] Falkor supports Rounding Double Multiply Add/Subtract instructions.Chad Rosier
Falkor only partially implements the ARMv8.1a extensions, so this patch refactors the support for the SQRDML[A|S]H instruction into a separate feature. Differential Revision: https://reviews.llvm.org/D28681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292142 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16Revert r292132: [globalisel] Tablegen-erate current Register Bank ↵Daniel Sanders
Information'... Several buildbots encountered a crash in tablegen when building this commit. Reverting while I investigate the cause. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292136 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-16[globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders
Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292132 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-04[AArch64] Update the feature set for Qualcomm's Falkor CPU.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291010 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-16[AArch64] Add FeatureSlowMisaligned128Store to Exynos M1 and M2Evandro Menezes
This feature now gates such stores after r289845. Thus the Exynos processors now need this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289898 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-13Add support for Samsung Exynos M3 (NFC)Evandro Menezes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289613 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-30[AArch64] Refactor LSE support as feature separate from V8.1a support.Joel Jones
Summary: This is preparation for ThunderX processors that have Large System Extension (LSE) atomic instructions, but not the other instructions introduced by V8.1a. This will mimic changes to GCC as described here: https://gcc.gnu.org/ml/gcc-patches/2015-06/msg00388.html LSE instructions are: LD/ST<op>, CAS*, SWP Reviewers: t.p.northover, echristo, jmolloy, rengolin Subscribers: aemerson, mehdi_amini Differential Revision: https://reviews.llvm.org/D26621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288279 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-29[AArch64] Add a basic SchedMachineModel for Falkor.Chad Rosier
Differential Revision: https://reviews.llvm.org/D26972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288194 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-15[AArch64] Add support for Qualcomm's Falkor CPU.Chad Rosier
Differential Revision: https://reviews.llvm.org/D26673 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287036 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-11[AArch64] Enable merging of adjacent zero stores for all subtargets.Chad Rosier
This optimization merges adjacent zero stores into a wider store. e.g., strh wzr, [x0] strh wzr, [x0, #2] ; becomes str wzr, [x0] e.g., str wzr, [x0] str wzr, [x0, #4] ; becomes str xzr, [x0] Previously, this was only enabled for Kryo and Cortex-A57. Differential Revision: https://reviews.llvm.org/D26396 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286592 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-07[AArch64] Removed the narrow load merging code in the ld/st optimizer.Chad Rosier
This feature has been disabled for some time now, so remove cruft. Differential Revision: https://reviews.llvm.org/D26248 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286110 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-26[AArch64] Create feature set for Samsung Exynos-M2Evandro Menezes
Since Exynos-M2 improved the FP square root unit a bit over the one in Exynos-M1, it does not benefit from using the Newton series for such operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285246 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-24[AArch64] Optionally use the Newton series for reciprocal estimationEvandro Menezes
Add support for estimating the square root or its reciprocal and division or reciprocal using the combiner generic Newton series. Differential revision: https://reviews.llvm.org/D25291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284986 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-04AArch64: Macrofusion: Split features, add missing combinations.Matthias Braun
AArch64InstrInfo::shouldScheduleAdjacent() determines whether two instruction can benefit from macroop fusion on apple CPUs. The list turned out to be incomplete: - the "rr" variants of the instructions were missing - even the "rs" variants can have shift value == 0 and behave like the "rr" variants This also splits the MacropFusion target feature into ArithmeticBccFusion and ArithmeticCbzFusion. Differential Revision: https://reviews.llvm.org/D25142 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283243 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20Revert part of "AArch64: Do not test for CPUs, use SubtargetFeatures"Evandro Menezes
This reverts part of commit 119e358d9635c8d1f3e7aee67e3ea3b8a62f8db6 by removing FeatureUseRSqrt et al per request by Eric Christopher <echristo@gmail.com> (v. http://bit.ly/2cmz6kW). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282001 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24[AArch64] Adjust the feature set for Exynos M1.Evandro Menezes
Enable zero cycle zeroing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279648 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01[AArch64] Add support for Samsung Exynos M2 (NFC).Evandro Menezes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277364 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-19[AArch64] PredictableSelectIsExpensive for Vulcan.Pankaj Gode
Adding PredictableSelectIsExpensive for Vulcan Differential Revision: https://reviews.llvm.org/D22448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275978 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-14[AArch64] Adjust the scheduling model for Exynos-M1.Evandro Menezes
Enable use-postra-scheduler. (NFC) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275457 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-12[Kryo] Enable ZCZeroing featureHaicheng Wu
This feature uses immediate #0 to zero a register. Differential Revision: http://reviews.llvm.org/D19985 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275143 91177308-0d34-0410-b5e6-96231b3b80d8
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