Age | Commit message (Expand) | Author |
2017-12-11 | [PowerPC] Sign-extend negative constant stores | Nemanja Ivanovic |
2017-12-11 | [DAGCombiner] Add combined indexed load to the work list | Nemanja Ivanovic |
2017-12-11 | [ARM GlobalISel] Add test for a MOVTi16 pattern. NFC | Diana Picus |
2017-12-11 | [X86] Add fsgsbase schedule tests. | Simon Pilgrim |
2017-12-11 | [RISCV] Add custom CC_RISCV calling convention and improved call support | Alex Bradbury |
2017-12-11 | [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore | Alex Bradbury |
2017-12-11 | [RISCV] Implement prolog and epilog insertion | Alex Bradbury |
2017-12-11 | [X86] Regenerate fsgsbase intrinsic tests. NFCI. | Simon Pilgrim |
2017-12-11 | [ARM] Use ADDCARRY / SUBCARRY | Roger Ferrer Ibanez |
2017-12-11 | [RISCV] Support lowering FrameIndex | Alex Bradbury |
2017-12-11 | [ARM GlobalISel] Add tests for PKHBT and PKHTB | Diana Picus |
2017-12-11 | [mips] Removal of microMIPS64R6 | Aleksandar Beserminji |
2017-12-11 | [AVR] Implement some missing code paths | Dylan McKay |
2017-12-11 | [AVR] Fix incorrectly-calculated AVRMCExpr evaluations | Dylan McKay |
2017-12-11 | [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors. | Craig Topper |
2017-12-11 | [DAGCombiner] Reuse existing SDLoc variable instead of creating a new one. NFC | Craig Topper |
2017-12-11 | [X86] Regenerate test with update_llc_test_checks.py | Craig Topper |
2017-12-11 | [X86] Add a test case for masked scatter where the index needs to be legalize... | Craig Topper |
2017-12-10 | [X86] Add ROL/ROR schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add DIV/MUL/NEG/NOP/NOT/PAUSE schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add DEC/INC schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add INS/OUTS schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add CMPS/MOVS/SCAS/STOS schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add CMOV schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add BT/BTC/BTR/BTS schedule tests | Simon Pilgrim |
2017-12-10 | [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake... | Craig Topper |
2017-12-10 | [X86] Rename some instructions that start with Int_ to have the _Int at the end. | Craig Topper |
2017-12-10 | [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns | Simon Pilgrim |
2017-12-10 | [X86][X87] Add missing x87 scheduler tests | Simon Pilgrim |
2017-12-10 | [X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix... | Craig Topper |
2017-12-10 | [X86] Add VCVTQQ2PS to the skylake server scheduler models. | Craig Topper |
2017-12-10 | [X86] Add VPMULLWZ256 to the skylake server scheduler model | Craig Topper |
2017-12-10 | [X86] Add 256/512-bit EVEX VPSADBW instructions to skylake server scheduler m... | Craig Topper |
2017-12-10 | [X86] Fix a few instructions that were named Z512 instead of just Z. | Craig Topper |
2017-12-10 | [X86] Add VPSRLWZrr to skylake server scheduler model. | Craig Topper |
2017-12-10 | [X86] Add VPUNPCKLWDZrr to skylake server scheduler model. | Craig Topper |
2017-12-10 | [X86] Adjust tablegen includes so we can use Instructions in scheduler models... | Craig Topper |
2017-12-10 | [SimplifyLibCalls] propagate FMF when folding pow(x, -1.0) call | Sanjay Patel |
2017-12-10 | [InstCombine] add test for pow(x, -1.0) with FMF; NFC | Sanjay Patel |
2017-12-10 | [SimplifyLibCalls] propagate FMF when folding pow(x, 2.0) call (PR35601) | Sanjay Patel |
2017-12-10 | [InstCombine] add test for pow(x, 2.0) with FMF; NFC | Sanjay Patel |
2017-12-10 | [X86] Flag BroadWell scheduler model as complete | Simon Pilgrim |
2017-12-10 | Regenerate some AVX2+ scheduling tests that got missed | Simon Pilgrim |
2017-12-10 | Strip trailing whitespace. NFCI. | Simon Pilgrim |
2017-12-10 | Regenerate some scheduling tests that got missed | Simon Pilgrim |
2017-12-10 | [X86] Flag ZNVER1 scheduler model as complete | Simon Pilgrim |
2017-12-10 | [X86] Flag SLM scheduler model as complete | Simon Pilgrim |
2017-12-10 | [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classes | Simon Pilgrim |
2017-12-10 | [X86] Tag SSE4A instructions as SSE INTALU scheduler classes | Simon Pilgrim |
2017-12-10 | [X86] Flag BTVER2 scheduler model as complete | Simon Pilgrim |