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2018-01-23Add external project LDC to release notes.Kai Nacke
LDC, the LLVM-based D compiler, is already ready for LLVM 6.0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323186 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-22Merging r323034:Hans Wennborg
------------------------------------------------------------------------ r323034 | dmgreen | 2018-01-20 11:29:37 +0100 (Sat, 20 Jan 2018) | 9 lines [Dominators] Fix some edge cases for PostDomTree updating These fix some odd cfg cases where batch-updating the post dom tree fails. Usually around infinite loops and roots ending up being different. Differential Revision: https://reviews.llvm.org/D42247 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323121 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-22Merging r322993:Hans Wennborg
------------------------------------------------------------------------ r322993 | kuhar | 2018-01-19 22:27:24 +0100 (Fri, 19 Jan 2018) | 16 lines [Dominators] Visit affected node candidates found at different root levels Summary: This patch attempts to fix the DomTree incremental insertion bug found here [[ https://bugs.llvm.org/show_bug.cgi?id=35969 | PR35969 ]] . When performing an insertion into a piece of unreachable CFG, we may find the same not at different levels. When this happens, the node can turn out to be affected when we find it starting from a node with a lower level in the tree. The level at which we start visitation affects if we consider a node affected or not. This patch tracks the lowest level at which each node was visited during insertion and allows it to be visited multiple times, if it can cause it to be considered affected. Reviewers: brzycki, davide, dberlin, grosser Reviewed By: brzycki Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42231 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323110 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-22Merging r322973:Hans Wennborg
------------------------------------------------------------------------ r322973 | mgorny | 2018-01-19 18:47:03 +0100 (Fri, 19 Jan 2018) | 7 lines [cmake] Include LLVM_LIBXML2_ENABLED in LLVMConfig.cmake, PR36006 Include the LLVM_LIBXML2_ENABLED cache variable in LLVMConfig.cmake in order to make it available for other LLVM packages to query. This is necessary to fix stand-alone testing of LLD. Differential Revision: https://reviews.llvm.org/D42252 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323107 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-22Merging r322878:Hans Wennborg
------------------------------------------------------------------------ r322878 | aemerson | 2018-01-18 20:21:27 +0100 (Thu, 18 Jan 2018) | 5 lines [AArch64][GlobalISel] Add isel support for global values in the large code model. Fixes PR35958. Differential Revision: https://reviews.llvm.org/D42175 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323103 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-20Merging r322875:Dimitry Andric
------------------------------------------------------------------------ r322875 | dim | 2018-01-18 19:39:13 +0100 (Thu, 18 Jan 2018) | 9 lines Add a -no-libcxxabi option to the test-release.sh script. On FreeBSD, it is currently not possible to build libcxxabi and link against it, so we have been building releases with -no-libs for quite some time. However, libcxx and libunwind should build without problems, so provide an option to skip just libcxxabi. ------------------------------------------------------------------------ Merging r322879: ------------------------------------------------------------------------ r322879 | dim | 2018-01-18 20:30:30 +0100 (Thu, 18 Jan 2018) | 2 lines Follow-up to rL322875 by initializing the do_libcxxabi variable properly. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323038 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-19Merging r322053:Hans Wennborg
------------------------------------------------------------------------ r322053 | echristo | 2018-01-09 03:38:17 +0100 (Tue, 09 Jan 2018) | 1 line Remove unused function HvxSelector::zerous. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322953 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-18Merging r322644:Hans Wennborg
------------------------------------------------------------------------ r322644 | d0k | 2018-01-17 05:01:06 -0800 (Wed, 17 Jan 2018) | 7 lines [X86] Don't mutate shuffle arguments after early-out for AVX512 The match* functions have the annoying behavior of modifying its inputs. Save and restore the inputs, just in case the early out for AVX512 is hit. This is still not great and its only a matter of time this kind of bug happens again, but I couldn't come up with a better pattern without rewriting significant chunks of this code. Fixes PR35977. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322840 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-18Merging r322724:Hans Wennborg
------------------------------------------------------------------------ r322724 | ctopper | 2018-01-17 10:46:01 -0800 (Wed, 17 Jan 2018) | 7 lines [X86] When legalizing (v64i1 select i8, v64i1, v64i1) make sure not to introduce bitcasts to i64 in 32-bit mode We legalize selects of masks with scalar conditions using a bitcast to an integer type. But if we are in 32-bit mode we can't convert v64i1 to i64. So instead split the v64i1 to v32i1 and concat it back together. Each half will then be legalized by bitcasting to i32 which is fine. The test case is a little indirect. If we have the v64i1 select in IR it will get legalized by legalize vector ops which has a run of type legalization after it. That type legalization run is able to fix this i64 bitcast. So in order to avoid that we need a build_vector of a splat which legalize vector ops will ignore. Legalize DAG will then turn that into a select via LowerBUILD_VECTORvXi1. And the select will get legalized. In this case there is no type legalizer run to cleanup the bitcast. This fixes pr35972. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322835 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322003:Hans Wennborg
------------------------------------------------------------------------ r322003 | niravd | 2018-01-08 08:21:35 -0800 (Mon, 08 Jan 2018) | 11 lines [DAG] Teach BaseIndexOffset to correctly handle with indexed operations BaseIndexOffset address analysis incorrectly ignores offsets folded into indexed memory operations causing potential errors in alias analysis of pre-indexed operations. Reviewers: efriedma, RKSimon, hfinkel, jyknight Subscribers: hiraditya, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D41701 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322693 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r321751, r321806, and r321878:Hans Wennborg
------------------------------------------------------------------------ r321751 | arsenm | 2018-01-03 10:45:37 -0800 (Wed, 03 Jan 2018) | 25 lines StructurizeCFG: Fix broken backedge detection The work order was changed in r228186 from SCC order to RPO with an arbitrary sorting function. The sorting function attempted to move inner loop nodes earlier. This was was apparently relying on an assumption that every block in a given loop / the same loop depth would be seen before visiting another loop. In the broken testcase, a block outside of the loop was encountered before moving onto another block in the same loop. The testcase would then structurize such that one blocks unconditional successor could never be reached. Revert to plain RPO for the analysis phase. This fixes detecting edges as backedges that aren't really. The processing phase does use another visited set, and I'm unclear on whether the order there is as important. An arbitrary order doesn't work, and triggers some infinite loops. The reversed RPO list seems to work and is closer to the order that was used before, minus the arbitary custom sorting. A few of the changed tests now produce smaller code, and a few are slightly worse looking. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321806 | arsenm | 2018-01-04 09:23:24 -0800 (Thu, 04 Jan 2018) | 4 lines StructurizeCFG: xfail one of the testcases from r321751 It fails with -verify-region-info. This seems to be a issue with RegionInfo itself which existed before. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321878 | arsenm | 2018-01-05 09:51:36 -0800 (Fri, 05 Jan 2018) | 4 lines RegionInfo: Use report_fatal_error instead of llvm_unreachable Otherwise when using -verify-region-info in a release build the error won't be emitted. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322686 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322313:Hans Wennborg
------------------------------------------------------------------------ r322313 | matze | 2018-01-11 13:57:03 -0800 (Thu, 11 Jan 2018) | 18 lines PeepholeOptimizer: Do not form PHI with subreg arguments When replacing a PHI the PeepholeOptimizer currently takes the register class of the register at the first operand. This however is not correct if this argument has a subregister index. As there is currently no API to query the register class resulting from applying a subregister index to all registers in a class, we can only abort in these cases and not perform the transformation. This changes findNextSource() to require the end of all copy chains to not use a subregister if there is any PHI in the chain. I had to rewrite the overly complicated inner loop there to have a good place to insert the new check. This fixes https://llvm.org/PR33071 (aka rdar://32262041) Differential Revision: https://reviews.llvm.org/D40758 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322684 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322223:Hans Wennborg
------------------------------------------------------------------------ r322223 | matze | 2018-01-10 12:49:57 -0800 (Wed, 10 Jan 2018) | 5 lines TargetLoweringBase: The ios simulator has no bzero function. Make sure I really get back to the beahvior before my rewrite in r321035 which turned out not to be completely NFC as I changed the behavior for the ios simulator environment. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322681 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322106:Hans Wennborg
------------------------------------------------------------------------ r322106 | abataev | 2018-01-09 11:08:22 -0800 (Tue, 09 Jan 2018) | 11 lines [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86. Summary: If the vector type is transformed to non-vector single type, the compile may crash trying to get vector information about non-vector type. Reviewers: RKSimon, spatel, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41862 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322680 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322272:Hans Wennborg
------------------------------------------------------------------------ r322272 | zvi | 2018-01-11 04:26:52 -0800 (Thu, 11 Jan 2018) | 15 lines X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is smaller than Indices Summary: As RKSimon suggested in pr35820, in the case that Src is smaller in bit-size than Indices, need to widen Src to avoid type mismatch. Fixes pr35820 Reviewers: RKSimon, craig.topper Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41865 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322679 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r321870, r321872, and r321994:Hans Wennborg
------------------------------------------------------------------------ r321870 | abataev | 2018-01-05 07:20:40 -0800 (Fri, 05 Jan 2018) | 1 line [SLP] Update test checks, NFC. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321872 | abataev | 2018-01-05 08:15:17 -0800 (Fri, 05 Jan 2018) | 1 line [SLP] Update more test checks, NFC. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321994 | abataev | 2018-01-08 06:43:06 -0800 (Mon, 08 Jan 2018) | 13 lines [SLP] Fix PR35777: Incorrect handling of aggregate values. Summary: Fixes the bug with incorrect handling of InsertValue|InsertElement instrucions in SLP vectorizer. Currently, we may use incorrect ExtractElement instructions as the operands of the original InsertValue|InsertElement instructions. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41767 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322675 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322473:Hans Wennborg
------------------------------------------------------------------------ r322473 | a.elovikov | 2018-01-15 02:56:07 -0800 (Mon, 15 Jan 2018) | 23 lines [LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV from a trunc. Summary: This method is supposed to be called for IVs that have casts in their use-def chains that are completely ignored after vectorization under PSE. However, for truncates of such IVs the same InductionDescriptor is used during creation/widening of both original IV based on PHINode and new IV based on TruncInst. This leads to unintended second call to recordVectorLoopValueForInductionCast with a VectorLoopVal set to the newly created IV for a trunc and causes an assert due to attempt to store new information for already existing entry in the map. This is wrong and should not be done. Fixes PR35773. Reviewers: dorit, Ayal, mssimpso Reviewed By: dorit Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41913 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322673 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r321791 and r321862:Hans Wennborg
------------------------------------------------------------------------ r321791 | sam_parker | 2018-01-04 01:42:27 -0800 (Thu, 04 Jan 2018) | 4 lines [X86] Codegen test for PR37563 Adding test to ease review of D41628. ------------------------------------------------------------------------ ------------------------------------------------------------------------ r321862 | sam_parker | 2018-01-05 00:47:23 -0800 (Fri, 05 Jan 2018) | 10 lines [DAGCombine] Fix for PR37563 While searching for loads to be narrowed, equal sized loads were not added to the list, resulting in anyext loads not being converted to zext loads. https://bugs.llvm.org/show_bug.cgi?id=35763 Differential Revision: https://reviews.llvm.org/D41628 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322671 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r321991:Hans Wennborg
------------------------------------------------------------------------ r321991 | sam_parker | 2018-01-08 05:21:24 -0800 (Mon, 08 Jan 2018) | 9 lines [DAGCombine] Fix for PR35761 I had falsely assumed that constant operands would be operand(1) of the bin ops that may need their constant operand to be masked. Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35761 Differential Revision: https://reviews.llvm.org/D41667 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322670 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r321993:Hans Wennborg
------------------------------------------------------------------------ r321993 | abataev | 2018-01-08 06:33:11 -0800 (Mon, 08 Jan 2018) | 11 lines [SLP] Fix PR35628: Count external uses on extra reduction arguments. Summary: If the vectorized value is marked as extra reduction argument, its users are not considered as external users. Patch fixes this. Reviewers: mkuper, hfinkel, RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41786 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322669 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322623:Hans Wennborg
------------------------------------------------------------------------ r322623 | avt77 | 2018-01-17 02:12:06 -0800 (Wed, 17 Jan 2018) | 3 lines Allow usage of X86-prefixes as separate instrs. Differential Revision: https://reviews.llvm.org/D42102 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322654 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-17Merging r322056:Hans Wennborg
------------------------------------------------------------------------ r322056 | skatkov | 2018-01-08 20:37:06 -0800 (Mon, 08 Jan 2018) | 13 lines [CGP] Fix Complex addressing mode for offset If the offset is differ in two addressing mode we can continue only if ScaleReg is not set due to we will use it as merge of different offsets. It should fix PR35799 and PR35805. Reviewers: john.brawn, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41227 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322645 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-16ReleaseNotes: add Zig to External Open Source ProjectsHans Wennborg
Patch by Andrew Kelley! Differential revision: https://reviews.llvm.org/D41875 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322567 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-16Merging r321980:Hans Wennborg
------------------------------------------------------------------------ r321980 | phosek | 2018-01-07 18:23:10 -0800 (Sun, 07 Jan 2018) | 5 lines [llvm-readobj] Support -needed-libs option for Mach-O files This implements the -needed-libs option in Mach-O dumper. Differential Revision: https://reviews.llvm.org/D41527 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322561 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-16Merging r321789:Hans Wennborg
------------------------------------------------------------------------ r321789 | hiraditya | 2018-01-03 23:47:24 -0800 (Wed, 03 Jan 2018) | 8 lines [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases load in case of a loop Reviewers: dberlin sebpop eli.friedman Differential Revision: https://reviews.llvm.org/D41453 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322558 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-16Merging r322103:Hans Wennborg
------------------------------------------------------------------------ r322103 | tejohnson | 2018-01-09 10:32:53 -0800 (Tue, 09 Jan 2018) | 25 lines Fix crash when linking metadata with ODR type uniquing Summary: With DebugTypeODRUniquing enabled, during IR linking debug metadata in the destination module may be reached from the source module. This means that ConstantAsMetadata nodes (e.g. on DITemplateValueParameter) may contain a value the destination module. When trying to map such metadata nodes, we will attempt to map a GV already in the dest module. linkGlobalValueProto will end up with a source GV that is the same as the dest GV as well as the new GV. Trying to access the TypeMap for the source GV type, which is actually a dest GV type, hits an assertion since it appears that we have mapped into the source module (because the type is the value not a key into the map). Detect that we don't need to access the TypeMap in this case, since there is no need to create a bitcast from the new GV to the source GV type as they GV are the same. Fixes PR35722. Reviewers: mehdi_amini, pcc Subscribers: probinson, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D41624 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322545 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-11[docs] Add JFS as an external project built againt LLVM 6.0.Dan Liew
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322287 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-09[docs] Mention SjLj fixes in the release notesMartin Storsjo
Enabling SjLj on x86 on platforms where it isn't used by default was partially implemented before 6.0, but didn't actually fully work until now. Differential Revision: https://reviews.llvm.org/D41712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322059 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Drop 'svn' suffix from the version number.Hans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@321742 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Creating release_60 branch off revision 321711Hans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@321713 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Remove left-over debug printout from r321692Hans Wennborg
Besides the unsightly print-out, it was causing some buildbots to fail, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/9311 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321711 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[InstSimplify] Missed optimization in math expression: squashing exp(log), ↵Dmitry Venikov
log(exp) Summary: This patch enables folding following expressions under -ffast-math flag: exp(log(x)) -> x, exp2(log2(x)) -> x, log(exp(x)) -> x, log2(exp2(x)) -> x Reviewers: spatel, hfinkel, davide Reviewed By: spatel, hfinkel, davide Subscribers: scanon, llvm-commits Differential Revision: https://reviews.llvm.org/D41381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321710 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackendAlex Bradbury
After D41349, we can now directly access MCSubtargetInfo from createARM*AsmBackend. This patch makes use of this, avoiding the need to create a fresh MCSubtargetInfo (which was previously always done with a blank CPU and feature string). Given the total size of the change remains pretty tiny and we're removing the old explicit destructor, I changed the STI field to a reference rather than a pointer. Differential Revision: https://reviews.llvm.org/D41693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321707 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[InstCombine] Add test to remove VarArg casts (NFC)Florian Hahn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321706 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[TableGen] Add support of Intrinsics with multiple returnsHal Finkel
This change deals with intrinsics with multiple outputs, for example load instrinsic with address updated. DAG selection for Instrinsics could be done either through source code or tablegen. Handling all intrinsics in source code would introduce a huge chunk of repetitive code if we have a large number of intrinsic that return multiple values (see NVPTX as an example). While intrinsic class in tablegen supports multiple outputs, tablegen only supports Intrinsics with zero or one output on TreePattern. This appears to be a simple bug in tablegen that is fixed by this change. For Intrinsics defined as: def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>; Instruction will be defined as: def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>; Patch by Wenbo Sun, thanks! Differential Revision: https://reviews.llvm.org/D32888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321704 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.Sander de Smalen
Summary: Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15) Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE. Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41441 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321699 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Fix build of WebAssembly and AVR backends after r321692Alex Bradbury
As experimental backends, I didn't have them configured to build in my local build config. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321696 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Fix incorrect documentation comment left after r321692Alex Bradbury
TargetRegistryInfo::createMCAsmBackend no longer takes a TheTriple parameter. The majory of the TargetRegistryInfo::create* functions have no or very limitied per-parameter doc comments, and adding a comment for the MCSubtargetInfo, MCRegisterInfo and MCTargetOptions parameters seems like it would add no real value beyond reading the function signature. As such, I've just deleted the doc comment for TheTriple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321694 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03Thread MCSubtargetInfo through Target::createMCAsmBackendAlex Bradbury
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. D20830 threaded an MCSubtargetInfo reference through MCAsmBackend::relaxInstruction, but this isn't the only function that would benefit from access. This patch removes the Triple and CPUString arguments from createMCAsmBackend and replaces them with MCSubtargetInfo. This patch just changes the interface without making any intentional functional changes. Once in, several cleanups are possible: * Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend * Support 16-bit instructions when valid in MipsAsmBackend::writeNopData * Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl * Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221) This change initially exposed PR35686, which has since been resolved in r321026. Differential Revision: https://reviews.llvm.org/D41349 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321692 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-03[GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflowAmara Emerson
Previously the code for handling G_SMULO didn't properly check for the signed multiply overflow, instead treating it the same as the unsigned G_UMULO. Fixes PR35800. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321690 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[llvm-objcopy] Add support for visibilityJake Ehrlich
I have no clue how this was missed when symbol table support was added. This change ensures that the visibility of symbols is preserved by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321681 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02Handle the case of live 16-bit subregisters in X86FixupBWInstsAndrew Kaylor
Differential Revision: https://reviews.llvm.org/D40524 Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321674 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[AArch64] fix typos in comments; NFCSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321673 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[ValueTracking] recognize min/max of min/max patternsSanjay Patel
This is part of solving PR35717: https://bugs.llvm.org/show_bug.cgi?id=35717 The larger IR optimization is proposed in D41603, but we can show the improvement in ValueTracking using codegen tests because SelectionDAG creates min/max nodes based on ValueTracking. Any target with min/max ops should show wins here. I chose AArch64 vector ops because they're clean and uniform. Some Alive proofs for the tests (can't put more than 2 tests in 1 page currently because the web app says it's too long): https://rise4fun.com/Alive/WRN https://rise4fun.com/Alive/iPm https://rise4fun.com/Alive/HmY https://rise4fun.com/Alive/CNm https://rise4fun.com/Alive/LYf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321672 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[AArch64] add tests for min/max of min/max (PR35717); NFCSanjay Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321668 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[AArch64][GlobalISel] Fix assert fail with unknown intrinsic.Amara Emerson
A call may have an intrinsic name but not have a valid intrinsic ID, for example with llvm.invariant.group.barrier. If so, treat it as a normal call like FastISel does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321662 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[opt-viewer] Check for pygments.lexer.c_cppJonas Hahnfeld
Some systems still don't have this module which was introduced in version 2.0 (CentOS 7, sigh). Differential Revision: https://reviews.llvm.org/D41611 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321659 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons ↵Sanjay Patel
(PR33325) This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion for x86 to use 2 pairs of loads per block. The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern with oversized integer compares, so we want to transform these into x86-specific vector nodes before legalization splits things into scalar chunks. See PR33325 for more details: https://bugs.llvm.org/show_bug.cgi?id=33325 Differential Revision: https://reviews.llvm.org/D41618 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321656 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[AArch64][GlobalISel] Enable GlobalISel at -O0 by defaultAmara Emerson
Tests updated to explicitly use fast-isel at -O0 instead of implicitly. This change also allows an explicit -fast-isel option to override an implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0. Differential Revision: https://reviews.llvm.org/D41362 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321655 91177308-0d34-0410-b5e6-96231b3b80d8
2018-01-02[BasicBlockUtils] Check for unreachable preds before updating LI in ↵Anna Thomas
UpdateAnalysisInformation Summary: We are incorrectly updating the LI when loop-simplify generates dedicated exit blocks for a loop. The issue is that there's an implicit assumption that the Preds passed into UpdateAnalysisInformation are reachable. However, this is not true and breaks LI by incorrectly updating the header of a loop. One such case is when we generate dedicated exits when the exit block is a landing pad (through SplitLandingPadPredecessors). There maybe other cases as well, since we do not guarantee that Preds passed in are reachable basic blocks. The added test case shows how loop-simplify breaks LI for the outer loop (and DT in turn) after we try to generate the LoopSimplifyForm. Reviewers: davide, chandlerc, sanjoy Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321653 91177308-0d34-0410-b5e6-96231b3b80d8
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