diff options
Diffstat (limited to 'test')
-rw-r--r-- | test/MC/ARM/diagnostics.s | 6 | ||||
-rw-r--r-- | test/MC/ARM/invalid-fp-armv8.s | 24 | ||||
-rw-r--r-- | test/MC/ARM/invalid-neon-v8.s | 14 | ||||
-rw-r--r-- | test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s | 8 | ||||
-rw-r--r-- | test/MC/ARM/ldrd-strd-gnu-bad-inst.s | 8 | ||||
-rw-r--r-- | test/MC/ARM/ldrd-strd-gnu-sp.s | 8 | ||||
-rw-r--r-- | test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s | 4 | ||||
-rw-r--r-- | test/MC/ARM/thumb-mov.s | 6 | ||||
-rw-r--r-- | test/MC/ARM/thumb2-diagnostics.s | 11 | ||||
-rw-r--r-- | test/MC/ARM/vfp4.s | 12 |
10 files changed, 49 insertions, 52 deletions
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 51616af818e..42e8b6a6128 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -1,4 +1,4 @@ - RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t +@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s @ RUN: not llvm-mc -triple=armv8 < %s 2> %t @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s @@ -164,7 +164,7 @@ @ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] -@ CHECK-ERRORS-V8: error: invalid operands for instruction +@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS: operand must be an immediate in the range [0,15] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15] @@ -208,7 +208,7 @@ @ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] -@ CHECK-ERRORS-V8: error: invalid operands for instruction +@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS: operand must be an immediate in the range [0,15] diff --git a/test/MC/ARM/invalid-fp-armv8.s b/test/MC/ARM/invalid-fp-armv8.s index 8cb2ab34289..dca0e448d11 100644 --- a/test/MC/ARM/invalid-fp-armv8.s +++ b/test/MC/ARM/invalid-fp-armv8.s @@ -35,38 +35,38 @@ @ V8: error: invalid instruction vseleq.f32 s0, d2, d1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vselgt.f64 s3, s2, s1 @ V8: error: invalid operand for instruction vselgt.f32 s0, q3, q1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vselgt.f64 q0, s3, q1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vmaxnm.f32 s0, d2, d1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vminnm.f64 s3, s2, s1 @ V8: error: invalid operand for instruction vmaxnm.f32 s0, q3, q1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vmaxnm.f64 q0, s3, q1 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vmaxnmgt.f64 q0, s3, q1 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified vcvta.s32.f64 d3, s2 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vcvtp.s32.f32 d3, s2 @ V8: error: operand must be a register in range [s0, s31] vcvtn.u32.f64 d3, s2 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vcvtm.u32.f32 d3, s2 @ V8: error: operand must be a register in range [s0, s31] vcvtnge.u32.f64 d3, s2 @ V8: error: instruction 'vcvtn' is not predicable, but condition code specified vcvtbgt.f64.f16 q0, d3 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vcvttlt.f64.f16 s0, s3 @ V8: error: invalid instruction, any one of the following would fix this: @ V8: note: operand must be a register in range [d0, d31] @@ -79,12 +79,12 @@ vcvtthi.f16.f64 q0, d3 @ V8: error: operand must be a register in range [s0, s31] vrintrlo.f32.f32 d3, q0 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vrintxcs.f32.f32 d3, d0 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vrinta.f64.f64 s3, q0 -@ V8: error: invalid operands for instruction +@ V8: error: invalid instruction vrintn.f32.f32 d3, d0 @ V8: error: instruction requires: NEON vrintp.f32 q3, q0 diff --git a/test/MC/ARM/invalid-neon-v8.s b/test/MC/ARM/invalid-neon-v8.s index 47cdab12ea7..cae1fb331cf 100644 --- a/test/MC/ARM/invalid-neon-v8.s +++ b/test/MC/ARM/invalid-neon-v8.s @@ -1,9 +1,9 @@ @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s vmaxnm.f32 s4, d5, q1 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction vmaxnm.f64.f64 s4, d5, q1 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction vmaxnmge.f64.f64 s4, d5, q1 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified @@ -12,12 +12,12 @@ vcvta.s32.f32 s1, s2 vcvtp.u32.f32 s1, d2 @ CHECK: error: operand must be a register in range [d0, d31] vcvtp.f32.u32 d1, q2 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction vcvtplo.f32.u32 s1, s2 @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified vrinta.f64.f64 s3, d12 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction vrintn.f32 d3, q12 @ CHECK: error: invalid instruction, any one of the following would fix this: @ CHECK: note: operand must be a register in range [d0, d31] @@ -50,7 +50,7 @@ sha1heq.32 q0, q1 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified sha1c.32 s0, d1, q2 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction sha1m.32 q0, s1, q2 @ CHECK: error: operand must be a register in range [q0, q15] sha1p.32 s0, q1, q2 @@ -62,12 +62,12 @@ sha256h.32 q0, s1, q2 sha256h2.32 q0, q1, s2 @ CHECK: error: operand must be a register in range [q0, q15] sha256su1.32 s0, d1, q2 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction sha256su1lt.32 q0, d1, q2 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified vmull.p64 q0, s1, s3 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction vmull.p64 s1, d2, d3 @ CHECK: error: operand must be a register in range [q0, q15] vmullge.p64 q0, d16, d17 diff --git a/test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s b/test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s index b5ed9b7346e..bb30bde49af 100644 --- a/test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s +++ b/test/MC/ARM/ldrd-strd-gnu-arm-bad-regs.s @@ -2,18 +2,18 @@ .text .arm -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: ldrd r12, [r0, #512] ldrd r12, [r0, #512] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: strd r12, [r0, #512] strd r12, [r0, #512] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: ldrd r1, [r0, #512] ldrd r1, [r0, #512] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: strd r1, [r0, #512] strd r1, [r0, #512] diff --git a/test/MC/ARM/ldrd-strd-gnu-bad-inst.s b/test/MC/ARM/ldrd-strd-gnu-bad-inst.s index d46dc514de8..e080538eeac 100644 --- a/test/MC/ARM/ldrd-strd-gnu-bad-inst.s +++ b/test/MC/ARM/ldrd-strd-gnu-bad-inst.s @@ -10,9 +10,9 @@ strd r0 @ CHECK: error: too few operands for instruction ldrd r0 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction strd s0, [r0] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction ldrd s0, [r0] .arm @ CHECK: error: too few operands for instruction @@ -23,7 +23,7 @@ strd r0 @ CHECK: error: too few operands for instruction ldrd r0 -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction strd s0, [r0] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction ldrd s0, [r0] diff --git a/test/MC/ARM/ldrd-strd-gnu-sp.s b/test/MC/ARM/ldrd-strd-gnu-sp.s index bf5cd8bfe1b..3d6db3bf422 100644 --- a/test/MC/ARM/ldrd-strd-gnu-sp.s +++ b/test/MC/ARM/ldrd-strd-gnu-sp.s @@ -8,20 +8,20 @@ .arm -// V7: error: invalid operands for instruction +// V7: error: invalid instruction // V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xc2,0xc0,0xe1] ldrd r12, [r0, #32] -// V7: error: invalid operands for instruction +// V7: error: invalid instruction // V8: strd r12, sp, [r0, #32] @ encoding: [0xf0,0xc2,0xc0,0xe1] strd r12, [r0, #32] .thumb -// V7: error: invalid operands for instruction +// V7: error: invalid instruction // V8: ldrd r12, sp, [r0, #32] @ encoding: [0xd0,0xe9,0x08,0xcd] ldrd r12, [r0, #32] -// V7: error: invalid operands for instruction +// V7: error: invalid instruction // V8: strd r12, sp, [r0, #32] @ encoding: [0xc0,0xe9,0x08,0xcd] strd r12, [r0, #32] diff --git a/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s b/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s index 732061589a2..93e2db1cb0c 100644 --- a/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s +++ b/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s @@ -2,10 +2,10 @@ .text .thumb -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: ldrd r12, [r0, #512] ldrd r12, [r0, #512] -@ CHECK: error: invalid operands for instruction +@ CHECK: error: invalid instruction @ CHECK: strd r12, [r0, #512] strd r12, [r0, #512] diff --git a/test/MC/ARM/thumb-mov.s b/test/MC/ARM/thumb-mov.s index 12d683695e0..5ceb0082ddd 100644 --- a/test/MC/ARM/thumb-mov.s +++ b/test/MC/ARM/thumb-mov.s @@ -19,7 +19,7 @@ // CHECK-NEXT: movs r0, pc // CHECK: note: invalid operand for instruction // CHECK-NEXT: movs r0, pc -// CHECK: error: invalid operands for instruction +// CHECK: error: invalid instruction // CHECK-NEXT: movs pc, pc // mov.w selects t2MOVr @@ -32,7 +32,7 @@ // CHECK-NEXT: mov.w r0, pc // CHECK: note: invalid operand for instruction // CHECK-NEXT: mov.w r0, pc -// CHECK: error: invalid operands for instruction +// CHECK: error: invalid instruction // CHECK-NEXT: mov.w pc, pc // movs.w selects t2MOVr @@ -45,7 +45,7 @@ // CHECK-NEXT: movs.w r0, pc // CHECK: note: invalid operand for instruction // CHECK-NEXT: movs.w r0, pc -// CHECK: error: invalid operands for instruction +// CHECK: error: invalid instruction // CHECK-NEXT: movs.w pc, pc diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s index 5ccbec44110..b784d79fa43 100644 --- a/test/MC/ARM/thumb2-diagnostics.s +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -43,7 +43,7 @@ @ CHECK-ERRORS: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7] -@ CHECK-ERRORS-V8: error: invalid operands for instruction +@ CHECK-ERRORS-V8: invalid instruction @ CHECK-ERRORS-V8: too many operands for instruction @ CHECK-ERRORS: operand must be an immediate in the range [0,15] @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15] @@ -91,11 +91,8 @@ foo2: and sp, r1, #80008000 and pc, r1, #80008000 -@ CHECK-ERRORS-V7: error: invalid operands for instruction -@ CHECK-ERRORS-V8: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS-V8: note: invalid operand for instruction -@ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14] -@ CHECK-ERRORS: error: invalid operands for instruction +@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: error: invalid instruction ssat r0, #1, r0, asr #32 usat r0, #1, r0, asr #32 @@ -132,7 +129,7 @@ foo2: @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: error: invalid operands for instruction +@ CHECK-ERRORS: error: invalid instruction @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: @ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS: note: instruction requires: arm-mode diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s index 986d07a7d88..be36abe15d3 100644 --- a/test/MC/ARM/vfp4.s +++ b/test/MC/ARM/vfp4.s @@ -6,7 +6,7 @@ @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17 vfma.f64 d16, d18, d17 @@ -17,7 +17,7 @@ vfma.f32 s2, s4, s0 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17 vfma.f32 d16, d18, d17 @@ -29,7 +29,7 @@ vfma.f32 q2, q4, q0 @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17 vfnma.f64 d16, d18, d17 @@ -40,7 +40,7 @@ vfnma.f32 s2, s4, s0 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17 vfms.f64 d16, d18, d17 @@ -51,7 +51,7 @@ vfms.f32 s2, s4, s0 @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] @ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17 vfms.f32 d16, d18, d17 @@ -63,7 +63,7 @@ vfms.f32 q2, q4, q0 @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid operands for instruction +@ THUMB_V7EM-ERRORS: error: invalid instruction @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17 vfnms.f64 d16, d18, d17 |