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-rw-r--r--test/CodeGen/RISCV/rem.ll8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/RISCV/rem.ll b/test/CodeGen/RISCV/rem.ll
index 253653c9fea..3f8f7ebea96 100644
--- a/test/CodeGen/RISCV/rem.ll
+++ b/test/CodeGen/RISCV/rem.ll
@@ -11,11 +11,11 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__umodsi3)
; RV32I-NEXT: addi a2, a2, %lo(__umodsi3)
-; RV32I-NEXT: jalr ra, a2, 0
+; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = urem i32 %a, %b
ret i32 %1
}
@@ -29,11 +29,11 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lui a2, %hi(__modsi3)
; RV32I-NEXT: addi a2, a2, %lo(__modsi3)
-; RV32I-NEXT: jalr ra, a2, 0
+; RV32I-NEXT: jalr a2
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = srem i32 %a, %b
ret i32 %1
}