diff options
Diffstat (limited to 'test/CodeGen/Mips')
28 files changed, 1151 insertions, 9 deletions
diff --git a/test/CodeGen/Mips/dins.ll b/test/CodeGen/Mips/dins.ll index 2aa824250d3..8a8b377861a 100644 --- a/test/CodeGen/Mips/dins.ll +++ b/test/CodeGen/Mips/dins.ll @@ -58,13 +58,13 @@ entry: ; CHECK-LABEL: f123: ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37 +; MIPS64R2: dinsm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4 ; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6 ; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14 +; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14 ; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50 -; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16 +; MIPS64R2: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16 ; MIPS32R2: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 2, 16 ; MIPS32R2-NOT: ins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 18, 46 ; MIPS16-NOT: ins{{[[:space:]].*}} diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll index e0229d14c52..9ec2b8e2425 100644 --- a/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -48,7 +48,7 @@ entry: ; 64: dmtc1 $[[OR]], $f0 ; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 -; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 ; 64R2: dmtc1 $[[INS]], $f0 %add = fadd double %d, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index ffc72a12f23..9be876f2a9b 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -28,8 +28,8 @@ entry: ; 64: dmtc1 $[[OR]], $f0 ; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 -; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 -; 64R2: dmtc1 $[[INS]], $f0 +; 64R2: dinsu $[[INS:[0-9]+]], $[[EXT]], 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 %call = tail call double @copysign(double %d0, double %d1) nounwind readnone ret double %call diff --git a/test/CodeGen/Mips/instverify/dext-pos.mir b/test/CodeGen/Mips/instverify/dext-pos.mir new file mode 100644 index 00000000000..5b57564df70 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dext-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: dext +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXT %0, 55, 10 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dext-size.mir b/test/CodeGen/Mips/instverify/dext-size.mir new file mode 100644 index 00000000000..d6436108cef --- /dev/null +++ b/test/CodeGen/Mips/instverify/dext-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: dext +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXT %0, 5, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/test/CodeGen/Mips/instverify/dextm-pos-size.mir new file mode 100644 index 00000000000..eec459fef42 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 32..64 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 3, 62 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-pos.mir b/test/CodeGen/Mips/instverify/dextm-pos.mir new file mode 100644 index 00000000000..782d3fb8b65 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextm-size.mir b/test/CodeGen/Mips/instverify/dextm-size.mir new file mode 100644 index 00000000000..771abef6517 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextm-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 32..64 +--- +name: dextm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTM %0, 31, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/test/CodeGen/Mips/instverify/dextu-pos-size.mir new file mode 100644 index 00000000000..5356cf5dfc1 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 32..64 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 43, 30 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-pos.mir b/test/CodeGen/Mips/instverify/dextu-pos.mir new file mode 100644 index 00000000000..11b94c3fd8d --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 32..63 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dextu-size.mir b/test/CodeGen/Mips/instverify/dextu-size.mir new file mode 100644 index 00000000000..4efdd966f7b --- /dev/null +++ b/test/CodeGen/Mips/instverify/dextu-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: dextu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DEXTU %0, 33, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-pos-size.mir b/test/CodeGen/Mips/instverify/dins-pos-size.mir new file mode 100644 index 00000000000..6276790edc5 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 0..32 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 17, 17 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-pos.mir b/test/CodeGen/Mips/instverify/dins-pos.mir new file mode 100644 index 00000000000..fe61deaebf0 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 55, 10 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dins-size.mir b/test/CodeGen/Mips/instverify/dins-size.mir new file mode 100644 index 00000000000..9fa0bc79a4b --- /dev/null +++ b/test/CodeGen/Mips/instverify/dins-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: dins +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINS %0, 5, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/test/CodeGen/Mips/instverify/dinsm-pos-size.mir new file mode 100644 index 00000000000..450aa6a5053 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 32..64 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 20, 50 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-pos.mir b/test/CodeGen/Mips/instverify/dinsm-pos.mir new file mode 100644 index 00000000000..75bf00edd96 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: dinsm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsm-size.mir b/test/CodeGen/Mips/instverify/dinsm-size.mir new file mode 100644 index 00000000000..9b501d44c47 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 2..64 +--- +name: dinsm +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSM %0, 31, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/test/CodeGen/Mips/instverify/dinsu-pos-size.mir new file mode 100644 index 00000000000..51a53041504 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 32..64 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 50, 20 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-pos.mir b/test/CodeGen/Mips/instverify/dinsu-pos.mir new file mode 100644 index 00000000000..cbfae688b0a --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 32..63 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 65, 5 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/dinsu-size.mir b/test/CodeGen/Mips/instverify/dinsu-size.mir new file mode 100644 index 00000000000..048a6f01c80 --- /dev/null +++ b/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: dinsu +alignment: 3 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64, preferred-register: '' } +liveins: + - { reg: '%a0_64', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0_64 + + %0 = COPY %a0_64 + %1 = DINSU %0, 33, 67 + %v0_64 = COPY %1 + RetRA implicit %v0_64 + +... diff --git a/test/CodeGen/Mips/instverify/ext-pos-size.mir b/test/CodeGen/Mips/instverify/ext-pos-size.mir new file mode 100644 index 00000000000..c230331e8ef --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 0..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 17, 17 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ext-pos.mir b/test/CodeGen/Mips/instverify/ext-pos.mir new file mode 100644 index 00000000000..ce472db2ef0 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-pos.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 44, 21 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ext-size.mir b/test/CodeGen/Mips/instverify/ext-size.mir new file mode 100644 index 00000000000..00f7182df4a --- /dev/null +++ b/test/CodeGen/Mips/instverify/ext-size.mir @@ -0,0 +1,49 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0 + + %0 = COPY %a0 + %1 = EXT %0, 0, 33 + %v0 = COPY %1 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-pos-size.mir b/test/CodeGen/Mips/instverify/ins-pos-size.mir new file mode 100644 index 00000000000..95872364e07 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position + Size is out of range! + +# Check that the machine verifier checks the pos + size is in range 0..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 17, 17, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-pos.mir b/test/CodeGen/Mips/instverify/ins-pos.mir new file mode 100644 index 00000000000..c8811ed3e20 --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-pos.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Position operand is out of range! + +# Check that the machine verifier checks the position operand is in range 0..31 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 32, 4, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/instverify/ins-size.mir b/test/CodeGen/Mips/instverify/ins-size.mir new file mode 100644 index 00000000000..fba25212e1a --- /dev/null +++ b/test/CodeGen/Mips/instverify/ins-size.mir @@ -0,0 +1,54 @@ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s + +# CHECK: Size operand is out of range! + +# Check that the machine verifier checks the size operand is in range 0..32 +--- +name: f +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gpr32, preferred-register: '' } + - { id: 1, class: gpr32, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } +liveins: + - { reg: '%a0', virtual-reg: '%0' } + - { reg: '%a1', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 4294967295 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + savePoint: '' + restorePoint: '' +fixedStack: +stack: +constants: +body: | + bb.0.entry: + liveins: %a0, %a1 + + %1 = COPY %a1 + %0 = COPY %a0 + %2 = ANDi %1, 15 + %3 = INS killed %2, 0, 40, %0 + %v0 = COPY %3 + RetRA implicit %v0 + +... diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index aa73c522eda..33a65070c7f 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -425,7 +425,7 @@ declare fp128 @llvm.powi.f128(fp128, i32) #3 ; NOT-R2R6-DAG: and $[[R4:[0-9]+]], $[[R1]], $[[R3]] ; ALL-DAG: ld $[[R5:[0-9]+]], %got_disp(gld0) ; ALL-DAG: ld $[[R6:[0-9]+]], 8($[[R5]]) -; R2R6: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1 +; R2R6: dinsu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 63, 1 ; NOT-R2R6-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1 ; NOT-R2R6-DAG: and $[[R8:[0-9]+]], $[[R6]], $[[R7]] ; NOT-R2R6-DAG: or $4, $[[R8]], $[[R4]] diff --git a/test/CodeGen/Mips/mips64extins.ll b/test/CodeGen/Mips/mips64extins.ll index 7876266fb85..f160603c250 100644 --- a/test/CodeGen/Mips/mips64extins.ll +++ b/test/CodeGen/Mips/mips64extins.ll @@ -41,7 +41,7 @@ entry: define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { entry: ; CHECK-LABEL: dinsm: -; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 +; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 %shl4 = shl i64 %j, 10 %and = and i64 %shl4, 8796093021184 %and5 = and i64 %i, -8796093021185 @@ -52,7 +52,7 @@ entry: define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { entry: ; CHECK-LABEL: dinsu: -; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 +; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 %shl4 = shl i64 %j, 40 %and = and i64 %shl4, 9006099743113216 %and5 = and i64 %i, -9006099743113217 |