diff options
Diffstat (limited to 'test/CodeGen/MIR/NVPTX')
3 files changed, 42 insertions, 50 deletions
diff --git a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir index 1a746ce802b..28fb2a2cf5c 100644 --- a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir +++ b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir @@ -14,13 +14,11 @@ name: test registers: - { id: 0, class: float32regs } - { id: 1, class: float32regs } -body: - - id: 0 - name: entry - instructions: - - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0' -# CHECK: [[@LINE+1]]:38: expected a floating point literal - - '%1 = FADD_rnf32ri %0, float 3' - - 'StoreRetvalF32 %1, 0' - - Return +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + ; CHECK: [[@LINE+1]]:33: expected a floating point literal + %1 = FADD_rnf32ri %0, float 3 + StoreRetvalF32 %1, 0 + Return ... diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir index 3b2ae0f99ee..18866d58a94 100644 --- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir +++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir @@ -38,22 +38,20 @@ registers: - { id: 5, class: float32regs } - { id: 6, class: float32regs } - { id: 7, class: float32regs } -body: - - id: 0 - name: entry - instructions: - - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0' - - '%1 = CVT_f64_f32 %0, 0' - - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1' -# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00 - - '%3 = FADD_rnf64ri %1, double 3.250000e+00' - - '%4 = CVT_f32_f64 %3, 5' - - '%5 = CVT_f32_s32 %2, 5' -# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00 - - '%6 = FADD_rnf32ri %5, float 6.250000e+00' - - '%7 = FMUL_rnf32rr %6, %4' - - 'StoreRetvalF32 %7, 0' - - Return +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + %1 = CVT_f64_f32 %0, 0 + %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1 + ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00 + %3 = FADD_rnf64ri %1, double 3.250000e+00 + %4 = CVT_f32_f64 %3, 5 + %5 = CVT_f32_s32 %2, 5 + ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00 + %6 = FADD_rnf32ri %5, float 6.250000e+00 + %7 = FMUL_rnf32rr %6, %4 + StoreRetvalF32 %7, 0 + Return ... --- name: test2 @@ -66,20 +64,18 @@ registers: - { id: 5, class: float32regs } - { id: 6, class: float32regs } - { id: 7, class: float32regs } -body: - - id: 0 - name: entry - instructions: - - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0' - - '%1 = CVT_f64_f32 %0, 0' - - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1' -# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 - - '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000' - - '%4 = CVT_f32_f64 %3, 5' - - '%5 = CVT_f32_s32 %2, 5' -# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 - - '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000' - - '%7 = FMUL_rnf32rr %6, %4' - - 'StoreRetvalF32 %7, 0' - - Return +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0 + %1 = CVT_f64_f32 %0, 0 + %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1 + ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 + %3 = FADD_rnf64ri %1, double 0x7FF8000000000000 + %4 = CVT_f32_f64 %3, 5 + %5 = CVT_f32_s32 %2, 5 + ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 + %6 = FADD_rnf32ri %5, float 0x7FF8000000000000 + %7 = FMUL_rnf32rr %6, %4 + StoreRetvalF32 %7, 0 + Return ... diff --git a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir index 810fa15bedd..e4080f80ee5 100644 --- a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir +++ b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir @@ -14,13 +14,11 @@ name: test registers: - { id: 0, class: float32regs } - { id: 1, class: float32regs } -body: - - id: 0 - name: entry - instructions: - - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0' -# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float' - - '%1 = FADD_rnf32ri %0, float 0xH3C00' - - 'StoreRetvalF32 %1, 0' - - Return +body: | + bb.0.entry: + %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0 + ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float' + %1 = FADD_rnf32ri %0, float 0xH3C00 + StoreRetvalF32 %1, 0 + Return ... |