diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/limit-coalesce.mir')
| -rw-r--r-- | test/CodeGen/AMDGPU/limit-coalesce.mir | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/AMDGPU/limit-coalesce.mir b/test/CodeGen/AMDGPU/limit-coalesce.mir index a0d2d6c097a..7d6d8a5891c 100644 --- a/test/CodeGen/AMDGPU/limit-coalesce.mir +++ b/test/CodeGen/AMDGPU/limit-coalesce.mir @@ -2,13 +2,13 @@ # Check that coalescer does not create wider register tuple than in source -# CHECK: - { id: 2, class: vreg_64 } -# CHECK: - { id: 3, class: vreg_64 } -# CHECK: - { id: 4, class: vreg_64 } -# CHECK: - { id: 5, class: vreg_96 } -# CHECK: - { id: 6, class: vreg_96 } -# CHECK: - { id: 7, class: vreg_128 } -# CHECK: - { id: 8, class: vreg_128 } +# CHECK: - { id: 2, class: vreg_64, preferred-register: '' } +# CHECK: - { id: 3, class: vreg_64, preferred-register: '' } +# CHECK: - { id: 4, class: vreg_64, preferred-register: '' } +# CHECK: - { id: 5, class: vreg_96, preferred-register: '' } +# CHECK: - { id: 6, class: vreg_96, preferred-register: '' } +# CHECK: - { id: 7, class: vreg_128, preferred-register: '' } +# CHECK: - { id: 8, class: vreg_128, preferred-register: '' } # No more registers shall be defined # CHECK-NEXT: liveins: # CHECK: FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %4, |