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-rw-r--r--test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll2
-rw-r--r--test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll2
-rw-r--r--test/CodeGen/AArch64/arm64-csldst-mmo.ll4
-rw-r--r--test/CodeGen/AArch64/arm64-dead-register-def-bug.ll2
-rw-r--r--test/CodeGen/AArch64/arm64-misched-memdep-bug.ll6
-rw-r--r--test/CodeGen/AArch64/arm64-misched-multimmo.ll4
-rw-r--r--test/CodeGen/AArch64/loh.mir82
-rw-r--r--test/CodeGen/AArch64/machine-copy-prop.ll10
-rw-r--r--test/CodeGen/AArch64/phi-dbg.ll2
-rw-r--r--test/CodeGen/AArch64/scheduledag-constreg.mir8
10 files changed, 61 insertions, 61 deletions
diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
index 29b71e04261..3ad9442b674 100644
--- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
+++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
@@ -296,7 +296,7 @@ declare double @hh(double) #1
; Check that we correctly deal with repeated operands.
; The following testcase creates:
-; %D1<def> = FADDDrr %D0<kill>, %D0
+; %d1<def> = FADDDrr %d0<kill>, %d0
; We'll get a crash if we naively look at the first operand, remove it
; from the substitution list then look at the second operand.
diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
index ef8d6f3b4ef..a21b6f2b0d9 100644
--- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
+++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm64-apple-ios -verify-machineinstrs | FileCheck %s
; LdStOpt bug created illegal instruction:
-; %D1<def>, %D2<def> = LDPSi %X0, 1
+; %d1<def>, %d2<def> = LDPSi %x0, 1
; rdar://11512047
%0 = type opaque
diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll
index 37cc5411aa3..b0059193d34 100644
--- a/test/CodeGen/AArch64/arm64-csldst-mmo.ll
+++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll
@@ -10,8 +10,8 @@
;
; CHECK: Before post-MI-sched:
; CHECK-LABEL: # Machine code for function test1:
-; CHECK: SU(2): STRWui %WZR
-; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP
+; CHECK: SU(2): STRWui %wzr
+; CHECK: SU(3): %x21<def>, %x20<def> = LDPXi %sp
; CHECK: Predecessors:
; CHECK-NEXT: SU(0): Out
; CHECK-NEXT: SU(0): Out
diff --git a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
index 1bbcf50ba73..03d05429308 100644
--- a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
+++ b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll
@@ -3,7 +3,7 @@
; Check that the dead register definition pass is considering implicit defs.
; When rematerializing through truncates, the coalescer may produce instructions
; with dead defs, but live implicit-defs of subregs:
-; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
+; E.g. %x1<def, dead> = MOVi64imm 2, %w1<imp-def>; %x1:GPR64, %w1:GPR32
; These instructions are live, and their definitions should not be rewritten.
;
; <rdar://problem/16492408>
diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
index 9cbf0cb3803..1b102e63569 100644
--- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -9,11 +9,11 @@
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2
; CHECK-NEXT: SU(4): Ord Latency=0
-; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3): STRWui %wzr, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
; CHECK: Successors:
; CHECK: SU(4): Ord Latency=0
-; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4): STRWui %wzr, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
+; CHECK: SU(5): %w0<def> = COPY %vreg2; GPR32:%vreg2
; CHECK: ** ScheduleDAGMI::schedule picking next node
define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
entry:
diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
index 75f45da0e48..9d92f96a208 100644
--- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll
+++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll
@@ -8,11 +8,11 @@
; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
;
; CHECK-LABEL: # Machine code for function foo:
-; CHECK: SU(2): %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi
+; CHECK: SU(2): %w{{[0-9]+}}<def>, %w{{[0-9]+}}<def> = LDPWi
; CHECK: Successors:
; CHECK-NOT: ch SU(4)
; CHECK: SU(3)
-; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}}
+; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}}
define i32 @foo() {
entry:
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
diff --git a/test/CodeGen/AArch64/loh.mir b/test/CodeGen/AArch64/loh.mir
index 6e4bb5cfaee..001e7755829 100644
--- a/test/CodeGen/AArch64/loh.mir
+++ b/test/CodeGen/AArch64/loh.mir
@@ -22,14 +22,14 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
- ; CHECK-NEXT: %X0<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X0<def> = ADRP <ga:@g1>
+ ; CHECK-NEXT: %x0<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x0<def> = ADRP <ga:@g1>
%x0 = ADRP target-flags(aarch64-page) @g0
%x0 = ADRP target-flags(aarch64-page) @g1
%x1 = ADRP target-flags(aarch64-page) @g2
@@ -38,11 +38,11 @@ body: |
bb.1:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X20<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X3<def> = ADDXri %X20, <ga:@g0>
+ ; CHECK-NEXT: %x20<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x3<def> = ADDXri %x20, <ga:@g0>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g0>
- ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g0>
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g0>
+ ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g0>
%x1 = ADRP target-flags(aarch64-page) @g0
%x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
@@ -73,11 +73,11 @@ body: |
bb.5:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %S6<def> = LDRSui %X5, <ga:@g2>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %s6<def> = LDRSui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
%x5 = ADRP target-flags(aarch64-page) @g2
@@ -85,11 +85,11 @@ body: |
bb.6:
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X6<def> = LDRXui %X5, <ga:@g2>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x6<def> = LDRXui %x5, <ga:@g2>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
- ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2>
- ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2>
+ ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2>
%x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
%x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
%x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
@@ -104,24 +104,24 @@ body: |
bb.8:
; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
- ; CHECK-NEXT: %X7<def> = ADRP <ga:@g3>[TF=1]
- ; CHECK-NEXT: %X8<def> = ADDXri %X7, <ga:@g3>
- ; CHECK-NEXT: %D1<def> = LDRDui %X8, 8
+ ; CHECK-NEXT: %x7<def> = ADRP <ga:@g3>[TF=1]
+ ; CHECK-NEXT: %x8<def> = ADDXri %x7, <ga:@g3>
+ ; CHECK-NEXT: %d1<def> = LDRDui %x8, 8
%x7 = ADRP target-flags(aarch64-page) @g3
%x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
%d1 = LDRDui %x8, 8
bb.9:
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X3<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X3<def> = ADDXri %X3, <ga:@g3>
+ ; CHECK-NEXT: %x3<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x3<def> = ADDXri %x3, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAdd:
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X2<def> = ADDXri %X5, <ga:@g3>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = ADDXri %x5, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g3>
- ; CHECK-NEXT: STRXui %XZR, %X1, 16
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g3>
+ ; CHECK-NEXT: STRXui %xzr, %x1, 16
%x1 = ADRP target-flags(aarch64-page) @g3
%x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
STRXui %xzr, %x1, 16
@@ -138,12 +138,12 @@ body: |
bb.10:
; CHECK-NEXT: Adding MCLOH_AdrpLdr:
- ; CHECK-NEXT: %X2<def> = ADRP <ga:@g3>
- ; CHECK-NEXT: %X2<def> = LDRXui %X2, <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = ADRP <ga:@g3>
+ ; CHECK-NEXT: %x2<def> = LDRXui %x2, <ga:@g3>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, 24
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, 24
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
%x1 = LDRXui %x1, 24
@@ -154,12 +154,12 @@ body: |
bb.11:
; CHECK-NEXT: Adding MCLOH_AdrpLdr
- ; CHECK-NEXT: %X5<def> = ADRP <ga:@g1>
- ; CHECK-NEXT: %X5<def> = LDRXui %X5, <ga:@g1>
+ ; CHECK-NEXT: %x5<def> = ADRP <ga:@g1>
+ ; CHECK-NEXT: %x5<def> = LDRXui %x5, <ga:@g1>
; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
- ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4>
- ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4>
- ; CHECK-NEXT: STRXui %XZR, %X1, 32
+ ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4>
+ ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4>
+ ; CHECK-NEXT: STRXui %xzr, %x1, 32
%x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
STRXui %xzr, %x1, 32
@@ -171,9 +171,9 @@ body: |
bb.12:
; CHECK-NOT: MCLOH_AdrpAdrp
; CHECK: Adding MCLOH_AdrpAddLdr
- ; %X9<def> = ADRP <ga:@g4>
- ; %X9<def> = ADDXri %X9, <ga:@g4>
- ; %X5<def> = LDRXui %X9, 0
+ ; %x9<def> = ADRP <ga:@g4>
+ ; %x9<def> = ADDXri %x9, <ga:@g4>
+ ; %x5<def> = LDRXui %x9, 0
%x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
%x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
%x5 = LDRXui %x9, 0
diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll
index 6bacf852907..ed0955ccf48 100644
--- a/test/CodeGen/AArch64/machine-copy-prop.ll
+++ b/test/CodeGen/AArch64/machine-copy-prop.ll
@@ -2,12 +2,12 @@
; This file check a bug in MachineCopyPropagation pass. The last COPY will be
; incorrectly removed if the machine instructions are as follows:
-; %Q5_Q6<def> = COPY %Q2_Q3
-; %D5<def> =
-; %D3<def> =
-; %D3<def> = COPY %D6
+; %q5_q6<def> = COPY %q2_q3
+; %d5<def> =
+; %d3<def> =
+; %d3<def> = COPY %d6
; This is caused by a bug in function SourceNoLongerAvailable(), which fails to
-; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3".
+; remove the relationship of D6 and "%q5_q6<def> = COPY %q2_q3".
@failed = internal unnamed_addr global i1 false
diff --git a/test/CodeGen/AArch64/phi-dbg.ll b/test/CodeGen/AArch64/phi-dbg.ll
index a1adf0f50d9..80bc885afa5 100644
--- a/test/CodeGen/AArch64/phi-dbg.ll
+++ b/test/CodeGen/AArch64/phi-dbg.ll
@@ -30,7 +30,7 @@ define i32 @func(i32) #0 !dbg !8 {
; CHECK: ldr w[[REG:[0-9]+]], [sp, #8]
; CHECK-NEXT: .Ltmp
call void @llvm.dbg.value(metadata i32 %.0, i64 0, metadata !15, metadata !13), !dbg !16
-; CHECK-NEXT: //DEBUG_VALUE: func:c <- %W[[REG]]
+; CHECK-NEXT: //DEBUG_VALUE: func:c <- %w[[REG]]
%5 = add nsw i32 %.0, %0, !dbg !22
call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !15, metadata !13), !dbg !16
ret i32 %5, !dbg !23
diff --git a/test/CodeGen/AArch64/scheduledag-constreg.mir b/test/CodeGen/AArch64/scheduledag-constreg.mir
index 6b83dc715e0..1f97fe1360c 100644
--- a/test/CodeGen/AArch64/scheduledag-constreg.mir
+++ b/test/CodeGen/AArch64/scheduledag-constreg.mir
@@ -7,16 +7,16 @@
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
# CHECK-LABEL: MI Scheduling
-# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(0): %wzr<def,dead> = SUBSWri %w1, 0, 0, %nzcv<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(1): %W2<def> = COPY %WZR
+# CHECK: SU(1): %w2<def> = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
+# CHECK: SU(2): %wzr<def,dead> = SUBSWri %w3, 0, 0, %nzcv<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
-# CHECK: SU(3): %W4<def> = COPY %WZR
+# CHECK: SU(3): %w4<def> = COPY %wzr
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
name: func
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 19:43:30 +0000