1 files changed, 0 insertions, 90 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
deleted file mode 100644
index fb5af0a8f10..00000000000
--- a/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
+++ /dev/null
@@ -1,90 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
-
-# PR36345
---- |
-  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-arm-none-eabi"
-
-  %struct.struct2 = type { [2 x half] }
-
-  @global_arg0 = common dso_local global %struct.struct2 zeroinitializer, align 2
-
-  ; Function Attrs: noinline nounwind optnone
-  define dso_local void @c_test([2 x half], [2 x half]* %addr) {
-  ; CHECK-LABEL: name: c_test
-  ; CHECK: bb.0 (%ir-block.1):
-  ; CHECK:   liveins: %h0, %h1, %x0
-  ; CHECK:   [[COPY:%[0-9]+]]:fpr16 = COPY %h0
-  ; CHECK:   [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
-  ; CHECK:   [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
-  ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
-  ; CHECK:   [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
-  ; CHECK:   [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
-  ; CHECK:   [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
-  ; CHECK:   [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
-  ; CHECK:   [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
-  ; CHECK:   [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
-  ; CHECK:   [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
-  ; CHECK:   [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
-  ; CHECK:   [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
-  ; CHECK:   STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
-  ; CHECK:   RET_ReallyLR
-    store [2 x half] %0, [2 x half]* %addr, align 2
-    ret void
-  }
-...
----
-name:            c_test
-alignment:       2
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: gpr }
-  - { id: 1, class: fpr }
-  - { id: 2, class: fpr }
-  - { id: 3, class: gpr }
-  - { id: 4, class: gpr }
-  - { id: 5, class: gpr }
-  - { id: 6, class: gpr }
-  - { id: 7, class: gpr }
-  - { id: 8, class: gpr }
-  - { id: 9, class: gpr }
-  - { id: 10, class: gpr }
-  - { id: 11, class: gpr }
-  - { id: 12, class: gpr }
-body:             |
-  bb.1 (%ir-block.1):
-    liveins: %h0, %h1, %x0
-
-    ; CHECK-LABEL: name: c_test
-    ; CHECK: liveins: %h0, %h1, %x0
-    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY %h1
-    ; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]]
-    ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.sub_32
-    ; CHECK: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 0, 15
-    ; CHECK: [[SUBREG_TO_REG2:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
-    ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG2]]
-    ; CHECK: [[SUBREG_TO_REG3:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY3]], %subreg.sub_32
-    ; CHECK: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[BFMXri]], [[SUBREG_TO_REG3]], 48, 15
-    ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[BFMXri1]]
-    ; CHECK: [[COPY5:%[0-9]+]]:gpr64sp = COPY %x0
-    ; CHECK: STRWui [[COPY4]], [[COPY5]], 0 :: (store 4 into %ir.addr, align 2)
-    ; CHECK: RET_ReallyLR
-    %1:fpr(s16) = COPY %h0
-    %2:fpr(s16) = COPY %h1
-    %3:gpr(s32) = G_IMPLICIT_DEF
-    %11:gpr(s16) = COPY %1(s16)
-    %4:gpr(s32) = G_INSERT %3, %11(s16), 0
-    %12:gpr(s16) = COPY %2(s16)
-    %5:gpr(s32) = G_INSERT %4, %12(s16), 16
-    %0:gpr(s32) = COPY %5(s32)
-    %6:gpr(p0) = COPY %x0
-    G_STORE %0(s32), %6(p0) :: (store 4 into %ir.addr, align 2)
-    RET_ReallyLR
-
-...