diff options
Diffstat (limited to 'lib')
46 files changed, 136 insertions, 138 deletions
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index ba11f9a7626..f0c603f0c8f 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -515,8 +515,8 @@ static void FixTail(MachineBasicBlock *CurMBB, MachineBasicBlock *SuccBB, if (I != MF->end() && !TII->analyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = &*I; if (TBB == NextBB && !Cond.empty() && !FBB) { - if (!TII->ReverseBranchCondition(Cond)) { - TII->RemoveBranch(*CurMBB); + if (!TII->reverseBranchCondition(Cond)) { + TII->removeBranch(*CurMBB); TII->insertBranch(*CurMBB, SuccBB, nullptr, Cond, dl); return; } @@ -1071,7 +1071,7 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) { // branch. SmallVector<MachineOperand, 4> NewCond(Cond); if (!Cond.empty() && TBB == IBB) { - if (TII->ReverseBranchCondition(NewCond)) + if (TII->reverseBranchCondition(NewCond)) continue; // This is the QBB case described above if (!FBB) { @@ -1107,7 +1107,7 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) { // Remove the unconditional branch at the end, if any. if (TBB && (Cond.empty() || FBB)) { DebugLoc dl; // FIXME: this is nowhere - TII->RemoveBranch(*PBB); + TII->removeBranch(*PBB); if (!Cond.empty()) // reinsert conditional branch only, for now TII->insertBranch(*PBB, (TBB == IBB) ? FBB : TBB, nullptr, @@ -1326,7 +1326,7 @@ ReoptimizeBlock: // a fall-through. if (PriorTBB && PriorTBB == PriorFBB) { DebugLoc dl = getBranchDebugLoc(PrevBB); - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); PriorCond.clear(); if (PriorTBB != MBB) TII->insertBranch(PrevBB, PriorTBB, nullptr, PriorCond, dl); @@ -1374,7 +1374,7 @@ ReoptimizeBlock: // If the previous branch *only* branches to *this* block (conditional or // not) remove the branch. if (PriorTBB == MBB && !PriorFBB) { - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); MadeChange = true; ++NumBranchOpts; goto ReoptimizeBlock; @@ -1384,7 +1384,7 @@ ReoptimizeBlock: // the condition is false, remove the uncond second branch. if (PriorFBB == MBB) { DebugLoc dl = getBranchDebugLoc(PrevBB); - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); TII->insertBranch(PrevBB, PriorTBB, nullptr, PriorCond, dl); MadeChange = true; ++NumBranchOpts; @@ -1396,9 +1396,9 @@ ReoptimizeBlock: // fall-through. if (PriorTBB == MBB) { SmallVector<MachineOperand, 4> NewPriorCond(PriorCond); - if (!TII->ReverseBranchCondition(NewPriorCond)) { + if (!TII->reverseBranchCondition(NewPriorCond)) { DebugLoc dl = getBranchDebugLoc(PrevBB); - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); TII->insertBranch(PrevBB, PriorFBB, nullptr, NewPriorCond, dl); MadeChange = true; ++NumBranchOpts; @@ -1431,12 +1431,12 @@ ReoptimizeBlock: if (DoTransform) { // Reverse the branch so we will fall through on the previous true cond. SmallVector<MachineOperand, 4> NewPriorCond(PriorCond); - if (!TII->ReverseBranchCondition(NewPriorCond)) { + if (!TII->reverseBranchCondition(NewPriorCond)) { DEBUG(dbgs() << "\nMoving MBB: " << *MBB << "To make fallthrough to: " << *PriorTBB << "\n"); DebugLoc dl = getBranchDebugLoc(PrevBB); - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); TII->insertBranch(PrevBB, MBB, nullptr, NewPriorCond, dl); // Move this block to the end of the function. @@ -1501,9 +1501,9 @@ ReoptimizeBlock: // Loop: xxx; jncc Loop; jmp Out if (CurTBB && CurFBB && CurFBB == MBB && CurTBB != MBB) { SmallVector<MachineOperand, 4> NewCond(CurCond); - if (!TII->ReverseBranchCondition(NewCond)) { + if (!TII->reverseBranchCondition(NewCond)) { DebugLoc dl = getBranchDebugLoc(*MBB); - TII->RemoveBranch(*MBB); + TII->removeBranch(*MBB); TII->insertBranch(*MBB, CurFBB, CurTBB, NewCond, dl); MadeChange = true; ++NumBranchOpts; @@ -1520,7 +1520,7 @@ ReoptimizeBlock: // This block may contain just an unconditional branch. Because there can // be 'non-branch terminators' in the block, try removing the branch and // then seeing if the block is empty. - TII->RemoveBranch(*MBB); + TII->removeBranch(*MBB); // If the only things remaining in the block are debug info, remove these // as well, so this will behave the same as an empty block in non-debug // mode. @@ -1551,7 +1551,7 @@ ReoptimizeBlock: PriorFBB = MBB; } DebugLoc pdl = getBranchDebugLoc(PrevBB); - TII->RemoveBranch(PrevBB); + TII->removeBranch(PrevBB); TII->insertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, pdl); } @@ -1577,7 +1577,7 @@ ReoptimizeBlock: *PMBB, NewCurTBB, NewCurFBB, NewCurCond, true); if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) { DebugLoc pdl = getBranchDebugLoc(*PMBB); - TII->RemoveBranch(*PMBB); + TII->removeBranch(*PMBB); NewCurCond.clear(); TII->insertBranch(*PMBB, NewCurTBB, nullptr, NewCurCond, pdl); MadeChange = true; diff --git a/lib/CodeGen/EarlyIfConversion.cpp b/lib/CodeGen/EarlyIfConversion.cpp index b1a31b1bef6..5f8141df4b9 100644 --- a/lib/CodeGen/EarlyIfConversion.cpp +++ b/lib/CodeGen/EarlyIfConversion.cpp @@ -547,7 +547,7 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) { // Fix up Head's terminators. // It should become a single branch or a fallthrough. DebugLoc HeadDL = Head->getFirstTerminator()->getDebugLoc(); - TII->RemoveBranch(*Head); + TII->removeBranch(*Head); // Erase the now empty conditional blocks. It is likely that Head can fall // through to Tail, and we can join the two blocks. diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index 61cf3130158..f5f752ac27e 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -207,7 +207,7 @@ namespace { } private: - bool ReverseBranchCondition(BBInfo &BBI) const; + bool reverseBranchCondition(BBInfo &BBI) const; bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups, BranchProbability Prediction) const; bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI, @@ -501,10 +501,10 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB, /// Reverse the condition of the end of the block branch. Swap block's 'true' /// and 'false' successors. -bool IfConverter::ReverseBranchCondition(BBInfo &BBI) const { +bool IfConverter::reverseBranchCondition(BBInfo &BBI) const { DebugLoc dl; // FIXME: this is nowhere - if (!TII->ReverseBranchCondition(BBI.BrCond)) { - TII->RemoveBranch(*BBI.BB); + if (!TII->reverseBranchCondition(BBI.BrCond)) { + TII->removeBranch(*BBI.BB); TII->insertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); std::swap(BBI.TrueBB, BBI.FalseBB); return true; @@ -857,11 +857,11 @@ bool IfConverter::ValidForkedDiamond( if (!FalseBBI.IsBrReversible) return false; FalseReversed = true; - ReverseBranchCondition(FalseBBI); + reverseBranchCondition(FalseBBI); } auto UnReverseOnExit = make_scope_exit([&]() { if (FalseReversed) - ReverseBranchCondition(FalseBBI); + reverseBranchCondition(FalseBBI); }); // Count duplicate instructions at the beginning of the true and false blocks. @@ -955,7 +955,7 @@ void IfConverter::AnalyzeBranches(BBInfo &BBI) { !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); BBI.IsBrReversible = (RevCond.size() == 0) || - !TII->ReverseBranchCondition(RevCond); + !TII->reverseBranchCondition(RevCond); BBI.HasFallThrough = BBI.IsBrAnalyzable && BBI.FalseBB == nullptr; if (BBI.BrCond.size()) { @@ -1113,10 +1113,10 @@ bool IfConverter::FeasibilityAnalysis(BBInfo &BBI, SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end()); SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end()); if (RevBranch) { - if (TII->ReverseBranchCondition(Cond)) + if (TII->reverseBranchCondition(Cond)) return false; } - if (TII->ReverseBranchCondition(RevPred) || + if (TII->reverseBranchCondition(RevPred) || !TII->SubsumesPredicate(Cond, RevPred)) return false; } @@ -1202,7 +1202,7 @@ void IfConverter::AnalyzeBlock( SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); - bool CanRevCond = !TII->ReverseBranchCondition(RevCond); + bool CanRevCond = !TII->reverseBranchCondition(RevCond); unsigned Dups = 0; unsigned Dups2 = 0; @@ -1502,7 +1502,7 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { return false; if (Kind == ICSimpleFalse) - if (TII->ReverseBranchCondition(Cond)) + if (TII->reverseBranchCondition(Cond)) llvm_unreachable("Unable to reverse branch condition!"); // Initialize liveins to the first BB. These are potentiall redefined by @@ -1517,7 +1517,7 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { DontKill.addLiveIns(NextMBB); if (CvtMBB.pred_size() > 1) { - BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + BBI.NonPredSize -= TII->removeBranch(*BBI.BB); // Copy instructions in the true block, predicate them, and add them to // the entry block. CopyAndPredicateBlock(BBI, *CvtBBI, Cond); @@ -1530,7 +1530,7 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { PredicateBlock(*CvtBBI, CvtMBB.end(), Cond); // Merge converted block into entry block. - BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + BBI.NonPredSize -= TII->removeBranch(*BBI.BB); MergeBlocks(BBI, *CvtBBI); } @@ -1590,11 +1590,11 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) { return false; if (Kind == ICTriangleFalse || Kind == ICTriangleFRev) - if (TII->ReverseBranchCondition(Cond)) + if (TII->reverseBranchCondition(Cond)) llvm_unreachable("Unable to reverse branch condition!"); if (Kind == ICTriangleRev || Kind == ICTriangleFRev) { - if (ReverseBranchCondition(*CvtBBI)) { + if (reverseBranchCondition(*CvtBBI)) { // BB has been changed, modify its predecessors (except for this // one) so they don't get ifcvt'ed based on bad intel. for (MachineBasicBlock *PBB : CvtMBB.predecessors()) { @@ -1629,7 +1629,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) { } if (CvtMBB.pred_size() > 1) { - BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + BBI.NonPredSize -= TII->removeBranch(*BBI.BB); // Copy instructions in the true block, predicate them, and add them to // the entry block. CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true); @@ -1639,11 +1639,11 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) { BBI.BB->removeSuccessor(&CvtMBB, true); } else { // Predicate the 'true' block after removing its branch. - CvtBBI->NonPredSize -= TII->RemoveBranch(CvtMBB); + CvtBBI->NonPredSize -= TII->removeBranch(CvtMBB); PredicateBlock(*CvtBBI, CvtMBB.end(), Cond); // Now merge the entry of the triangle with the true block. - BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + BBI.NonPredSize -= TII->removeBranch(*BBI.BB); MergeBlocks(BBI, *CvtBBI, false); } @@ -1651,7 +1651,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) { if (HasEarlyExit) { SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(), CvtBBI->BrCond.end()); - if (TII->ReverseBranchCondition(RevCond)) + if (TII->reverseBranchCondition(RevCond)) llvm_unreachable("Unable to reverse branch condition!"); // Update the edge probability for both CvtBBI->FalseBB and NextBBI. @@ -1744,7 +1744,7 @@ bool IfConverter::IfConvertDiamondCommon( BBInfo *BBI1 = &TrueBBI; BBInfo *BBI2 = &FalseBBI; SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end()); - if (TII->ReverseBranchCondition(RevCond)) + if (TII->reverseBranchCondition(RevCond)) llvm_unreachable("Unable to reverse branch condition!"); SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; SmallVector<MachineOperand, 4> *Cond2 = &RevCond; @@ -1764,7 +1764,7 @@ bool IfConverter::IfConvertDiamondCommon( } // Remove the conditional branch from entry to the blocks. - BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + BBI.NonPredSize -= TII->removeBranch(*BBI.BB); MachineBasicBlock &MBB1 = *BBI1->BB; MachineBasicBlock &MBB2 = *BBI2->BB; @@ -1819,7 +1819,7 @@ bool IfConverter::IfConvertDiamondCommon( if (!BBI1->IsBrAnalyzable) verifySameBranchInstructions(&MBB1, &MBB2); #endif - BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB); + BBI1->NonPredSize -= TII->removeBranch(*BBI1->BB); // Remove duplicated instructions. DI1 = MBB1.end(); for (unsigned i = 0; i != NumDups2; ) { @@ -1841,7 +1841,7 @@ bool IfConverter::IfConvertDiamondCommon( // The branches have been checked to match. Skip over the branch in the false // block so that we don't try to predicate it. if (RemoveBranch) - BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB); + BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB); else { do { assert(DI2 != MBB2.begin()); diff --git a/lib/CodeGen/ImplicitNullChecks.cpp b/lib/CodeGen/ImplicitNullChecks.cpp index 308d25d428a..7f5c9b712b2 100644 --- a/lib/CodeGen/ImplicitNullChecks.cpp +++ b/lib/CodeGen/ImplicitNullChecks.cpp @@ -518,7 +518,7 @@ void ImplicitNullChecks::rewriteNullChecks( for (auto &NC : NullCheckList) { // Remove the conditional branch dependent on the null check. - unsigned BranchesRemoved = TII->RemoveBranch(*NC.getCheckBlock()); + unsigned BranchesRemoved = TII->removeBranch(*NC.getCheckBlock()); (void)BranchesRemoved; assert(BranchesRemoved > 0 && "expected at least one branch!"); diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index 9ab4a1915fd..b43a253e2df 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -416,7 +416,7 @@ void MachineBasicBlock::updateTerminator() { // The block has an unconditional branch. If its successor is now its // layout successor, delete the branch. if (isLayoutSuccessor(TBB)) - TII->RemoveBranch(*this); + TII->removeBranch(*this); } else { // The block has an unconditional fallthrough. If its successor is not its // layout successor, insert a branch. First we have to locate the only @@ -446,12 +446,12 @@ void MachineBasicBlock::updateTerminator() { // successors is its layout successor, rewrite it to a fallthrough // conditional branch. if (isLayoutSuccessor(TBB)) { - if (TII->ReverseBranchCondition(Cond)) + if (TII->reverseBranchCondition(Cond)) return; - TII->RemoveBranch(*this); + TII->removeBranch(*this); TII->insertBranch(*this, FBB, nullptr, Cond, DL); } else if (isLayoutSuccessor(FBB)) { - TII->RemoveBranch(*this); + TII->removeBranch(*this); TII->insertBranch(*this, TBB, nullptr, Cond, DL); } return; @@ -474,7 +474,7 @@ void MachineBasicBlock::updateTerminator() { // Remove the conditional jump, leaving unconditional fallthrough. // FIXME: This does not seem like a reasonable pattern to support, but it // has been seen in the wild coming out of degenerate ARM test cases. - TII->RemoveBranch(*this); + TII->removeBranch(*this); // Finally update the unconditional successor to be reached via a branch if // it would not be reached by fallthrough. @@ -486,7 +486,7 @@ void MachineBasicBlock::updateTerminator() { // We enter here iff exactly one successor is TBB which cannot fallthrough // and the rest successors if any are EHPads. In this case, we need to // change the conditional branch into unconditional branch. - TII->RemoveBranch(*this); + TII->removeBranch(*this); Cond.clear(); TII->insertBranch(*this, TBB, nullptr, Cond, DL); return; @@ -494,16 +494,16 @@ void MachineBasicBlock::updateTerminator() { // The block has a fallthrough conditional branch. if (isLayoutSuccessor(TBB)) { - if (TII->ReverseBranchCondition(Cond)) { + if (TII->reverseBranchCondition(Cond)) { // We can't reverse the condition, add an unconditional branch. Cond.clear(); TII->insertBranch(*this, FallthroughBB, nullptr, Cond, DL); return; } - TII->RemoveBranch(*this); + TII->removeBranch(*this); TII->insertBranch(*this, FallthroughBB, nullptr, Cond, DL); } else if (!isLayoutSuccessor(FallthroughBB)) { - TII->RemoveBranch(*this); + TII->removeBranch(*this); TII->insertBranch(*this, TBB, FallthroughBB, Cond, DL); } } diff --git a/lib/CodeGen/MachineBlockPlacement.cpp b/lib/CodeGen/MachineBlockPlacement.cpp index de950585419..90a576a6621 100644 --- a/lib/CodeGen/MachineBlockPlacement.cpp +++ b/lib/CodeGen/MachineBlockPlacement.cpp @@ -1635,14 +1635,14 @@ void MachineBlockPlacement::optimizeBranches() { if (TBB && !Cond.empty() && FBB && MBPI->getEdgeProbability(ChainBB, FBB) > MBPI->getEdgeProbability(ChainBB, TBB) && - !TII->ReverseBranchCondition(Cond)) { + !TII->reverseBranchCondition(Cond)) { DEBUG(dbgs() << "Reverse order of the two branches: " << getBlockName(ChainBB) << "\n"); DEBUG(dbgs() << " Edge probability: " << MBPI->getEdgeProbability(ChainBB, FBB) << " vs " << MBPI->getEdgeProbability(ChainBB, TBB) << "\n"); DebugLoc dl; // FIXME: this is nowhere - TII->RemoveBranch(*ChainBB); + TII->removeBranch(*ChainBB); TII->insertBranch(*ChainBB, FBB, TBB, Cond, dl); ChainBB->updateTerminator(); } diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp index 886f1bd3dd2..516296c1cdd 100644 --- a/lib/CodeGen/MachinePipeliner.cpp +++ b/lib/CodeGen/MachinePipeliner.cpp @@ -2363,7 +2363,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage, // Check if we need to remove the branch from the preheader to the original // loop, and replace it with a branch to the new loop. - unsigned numBranches = TII->RemoveBranch(*PreheaderBB); + unsigned numBranches = TII->removeBranch(*PreheaderBB); if (numBranches) { SmallVector<MachineOperand, 0> Cond; TII->insertBranch(*PreheaderBB, PrologBBs[0], nullptr, Cond, DebugLoc()); @@ -2452,7 +2452,7 @@ void SwingSchedulerDAG::generateEpilog(SMSchedule &Schedule, unsigned LastStage, // Create a branch to the new epilog from the kernel. // Remove the original branch and add a new branch to the epilog. - TII->RemoveBranch(*KernelBB); + TII->removeBranch(*KernelBB); TII->insertBranch(*KernelBB, KernelBB, EpilogStart, Cond, DebugLoc()); // Add a branch to the loop exit. if (EpilogBBs.size() > 0) { diff --git a/lib/CodeGen/TailDuplicator.cpp b/lib/CodeGen/TailDuplicator.cpp index a8e294129ee..26b9b074ede 100644 --- a/lib/CodeGen/TailDuplicator.cpp +++ b/lib/CodeGen/TailDuplicator.cpp @@ -716,7 +716,7 @@ bool TailDuplicator::duplicateSimpleBB( if (PredTBB == NextBB && PredFBB == nullptr) PredTBB = nullptr; - TII->RemoveBranch(*PredBB); + TII->removeBranch(*PredBB); if (!PredBB->isSuccessor(NewTarget)) PredBB->replaceSuccessor(TailBB, NewTarget); @@ -784,7 +784,7 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB, TDBBs.push_back(PredBB); // Remove PredBB's unconditional branch. - TII->RemoveBranch(*PredBB); + TII->removeBranch(*PredBB); // Clone the contents of TailBB into PredBB. DenseMap<unsigned, RegSubRegPair> LocalVRMap; diff --git a/lib/Target/AArch64/AArch64BranchRelaxation.cpp b/lib/Target/AArch64/AArch64BranchRelaxation.cpp index e2e5511a1a2..9142f3ed9b2 100644 --- a/lib/Target/AArch64/AArch64BranchRelaxation.cpp +++ b/lib/Target/AArch64/AArch64BranchRelaxation.cpp @@ -300,9 +300,9 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { DEBUG(dbgs() << " Invert condition and swap " "its destination with " << MBB->back()); - TII->ReverseBranchCondition(Cond); + TII->reverseBranchCondition(Cond); int OldSize = 0, NewSize = 0; - TII->RemoveBranch(*MBB, &OldSize); + TII->removeBranch(*MBB, &OldSize); TII->insertBranch(*MBB, FBB, TBB, Cond, DL, &NewSize); BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize); @@ -340,8 +340,8 @@ bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) { // Insert a new conditional branch and a new unconditional branch. int RemovedSize = 0; - TII->ReverseBranchCondition(Cond); - TII->RemoveBranch(*MBB, &RemovedSize); + TII->reverseBranchCondition(Cond); + TII->removeBranch(*MBB, &RemovedSize); MBBSize -= RemovedSize; int AddedSize = 0; diff --git a/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/lib/Target/AArch64/AArch64ConditionalCompares.cpp index c4005fcb1fb..f2b5ce49e93 100644 --- a/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -568,7 +568,7 @@ void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) { CmpBB->removeSuccessor(Tail, true); Head->transferSuccessorsAndUpdatePHIs(CmpBB); DebugLoc TermDL = Head->getFirstTerminator()->getDebugLoc(); - TII->RemoveBranch(*Head); + TII->removeBranch(*Head); // If the Head terminator was one of the cbz / tbz branches with built-in // compare, we need to insert an explicit compare instruction in its place. diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index c81c2dadbe8..6907e061332 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -257,7 +257,7 @@ bool AArch64InstrInfo::analyzeBranch(MachineBasicBlock &MBB, return true; } -bool AArch64InstrInfo::ReverseBranchCondition( +bool AArch64InstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { if (Cond[0].getImm() != -1) { // Regular Bcc @@ -298,7 +298,7 @@ bool AArch64InstrInfo::ReverseBranchCondition( return false; } -unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) diff --git a/lib/Target/AArch64/AArch64InstrInfo.h b/lib/Target/AArch64/AArch64InstrInfo.h index 5c4afba5728..e03cfd77221 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.h +++ b/lib/Target/AArch64/AArch64InstrInfo.h @@ -183,14 +183,14 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, unsigned, unsigned, int &, int &, int &) const override; void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/lib/Target/AMDGPU/R600InstrInfo.cpp b/lib/Target/AMDGPU/R600InstrInfo.cpp index 7b1b4a544ba..e88bd076718 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -778,7 +778,7 @@ unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, } } -unsigned R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -910,7 +910,7 @@ R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, bool -R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { MachineOperand &MO = Cond[1]; switch (MO.getImm()) { case AMDGPU::PRED_SETE_INT: diff --git a/lib/Target/AMDGPU/R600InstrInfo.h b/lib/Target/AMDGPU/R600InstrInfo.h index 66d0d06df46..a280052dbd4 100644 --- a/lib/Target/AMDGPU/R600InstrInfo.h +++ b/lib/Target/AMDGPU/R600InstrInfo.h @@ -159,7 +159,7 @@ public: DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override; - bool ReverseBranchCondition( + bool reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -172,7 +172,7 @@ public: const DebugLoc &DL, int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed = nullptr) const override; bool isPredicated(const MachineInstr &MI) const override; diff --git a/lib/Target/AMDGPU/SIInstrInfo.cpp b/lib/Target/AMDGPU/SIInstrInfo.cpp index d933d807920..fcdd1fd6599 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1105,7 +1105,7 @@ bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, return true; } -unsigned SIInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { MachineBasicBlock::iterator I = MBB.getFirstTerminator(); @@ -1167,7 +1167,7 @@ unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB, return 2; } -bool SIInstrInfo::ReverseBranchCondition( +bool SIInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1); Cond[0].setImm(-Cond[0].getImm()); diff --git a/lib/Target/AMDGPU/SIInstrInfo.h b/lib/Target/AMDGPU/SIInstrInfo.h index aced35a852f..aeeee7d57e1 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.h +++ b/lib/Target/AMDGPU/SIInstrInfo.h @@ -163,7 +163,7 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, @@ -171,7 +171,7 @@ public: const DebugLoc &DL, int *BytesAdded = nullptr) const override; - bool ReverseBranchCondition( + bool reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const override; bool diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9c6f03d8730..6aa060ae0d9 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -382,7 +382,7 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } -unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -453,7 +453,7 @@ unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB, } bool ARMBaseInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); Cond[0].setImm(ARMCC::getOppositeCondition(CC)); return false; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 5608cc7ccfb..a42ed0c392f 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -124,7 +124,7 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, @@ -132,7 +132,7 @@ public: int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; // Predication support. bool isPredicated(const MachineInstr &MI) const override; diff --git a/lib/Target/AVR/AVRInstrInfo.cpp b/lib/Target/AVR/AVRInstrInfo.cpp index 462e21fadf1..634d83de148 100644 --- a/lib/Target/AVR/AVRInstrInfo.cpp +++ b/lib/Target/AVR/AVRInstrInfo.cpp @@ -407,7 +407,7 @@ unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB, return Count; } -unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -435,7 +435,7 @@ unsigned AVRInstrInfo::RemoveBranch(MachineBasicBlock &MBB, return Count; } -bool AVRInstrInfo::ReverseBranchCondition( +bool AVRInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1 && "Invalid AVR branch condition!"); diff --git a/lib/Target/AVR/AVRInstrInfo.h b/lib/Target/AVR/AVRInstrInfo.h index 03c76352433..c5105dafe5e 100644 --- a/lib/Target/AVR/AVRInstrInfo.h +++ b/lib/Target/AVR/AVRInstrInfo.h @@ -98,10 +98,10 @@ public: MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; private: const AVRRegisterInfo RI; diff --git a/lib/Target/BPF/BPFInstrInfo.cpp b/lib/Target/BPF/BPFInstrInfo.cpp index 13b7e748e0e..cbe4466164f 100644 --- a/lib/Target/BPF/BPFInstrInfo.cpp +++ b/lib/Target/BPF/BPFInstrInfo.cpp @@ -151,7 +151,7 @@ unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB, llvm_unreachable("Unexpected conditional branch"); } -unsigned BPFInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); diff --git a/lib/Target/BPF/BPFInstrInfo.h b/lib/Target/BPF/BPFInstrInfo.h index 4cfac0d185f..c7048ab979b 100644 --- a/lib/Target/BPF/BPFInstrInfo.h +++ b/lib/Target/BPF/BPFInstrInfo.h @@ -49,7 +49,7 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index c86a7c611cf..bcb8dce927f 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -963,7 +963,7 @@ void HexagonEarlyIfConversion::mergeBlocks(MachineBasicBlock *PredB, << PrintMB(SuccB) << "\n"); bool TermOk = hasUncondBranch(SuccB); eliminatePhis(SuccB); - HII->RemoveBranch(*PredB); + HII->removeBranch(*PredB); PredB->removeSuccessor(SuccB); PredB->splice(PredB->end(), SuccB, SuccB->begin(), SuccB->end()); MachineBasicBlock::succ_iterator I, E = SuccB->succ_end(); diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index b4fa29e692b..7681683540b 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -537,7 +537,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, } -unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -572,7 +572,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert(!BytesAdded && "code size not handled"); - // Check if ReverseBranchCondition has asked to reverse this branch + // Check if reverseBranchCondition has asked to reverse this branch // If we want to reverse the branch an odd number of times, we want // J2_jumpf. if (!Cond.empty() && Cond[0].isImm()) @@ -590,8 +590,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, if (Term != MBB.end() && isPredicated(*Term) && !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) && MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) { - ReverseBranchCondition(Cond); - RemoveBranch(MBB); + reverseBranchCondition(Cond); + removeBranch(MBB); return insertBranch(MBB, TBB, nullptr, Cond, DL); } BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); @@ -1360,7 +1360,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { // We indicate that we want to reverse the branch by // inserting the reversed branching opcode. -bool HexagonInstrInfo::ReverseBranchCondition( +bool HexagonInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { if (Cond.empty()) return true; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 4d1b847a2c1..2d184d1484e 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -73,7 +73,7 @@ public: /// condition. These operands can be passed to other TargetInstrInfo /// methods to create new branches. /// - /// Note that RemoveBranch and insertBranch must be implemented to support + /// Note that removeBranch and insertBranch must be implemented to support /// cases where this method returns success. /// /// If AllowModify is true, then this routine is allowed to modify the basic @@ -87,7 +87,7 @@ public: /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where AnalyzeBranch returns success. It /// returns the number of instructions that were removed. - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; /// Insert branch code into the end of the specified MachineBasicBlock. @@ -197,7 +197,7 @@ public: /// Reverses the branch condition of the specified condition list, /// returning false on success and true if it cannot be reversed. - bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) + bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; /// Insert a noop into the instruction stream at the specified point. diff --git a/lib/Target/Lanai/LanaiInstrInfo.cpp b/lib/Target/Lanai/LanaiInstrInfo.cpp index 2f3e64aa025..fcd5da876b1 100644 --- a/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -641,10 +641,10 @@ bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return false; } -// ReverseBranchCondition - Reverses the branch condition of the specified +// reverseBranchCondition - Reverses the branch condition of the specified // condition list, returning false on success and true if it cannot be // reversed. -bool LanaiInstrInfo::ReverseBranchCondition( +bool LanaiInstrInfo::reverseBranchCondition( SmallVectorImpl<llvm::MachineOperand> &Condition) const { assert((Condition.size() == 1) && "Lanai branch conditions should have one component."); @@ -690,7 +690,7 @@ unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB, return 2; } -unsigned LanaiInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); diff --git a/lib/Target/Lanai/LanaiInstrInfo.h b/lib/Target/Lanai/LanaiInstrInfo.h index f0f43275a95..4387fe1af3c 100644 --- a/lib/Target/Lanai/LanaiInstrInfo.h +++ b/lib/Target/Lanai/LanaiInstrInfo.h @@ -86,7 +86,7 @@ public: SmallVectorImpl<MachineOperand> &Condition, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; // For a comparison instruction, return the source registers in SrcReg and @@ -130,7 +130,7 @@ public: SmallPtrSetImpl<MachineInstr *> &SeenMIs, bool PreferFalse) const override; - bool ReverseBranchCondition( + bool reverseBranchCondition( SmallVectorImpl<MachineOperand> &Condition) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, diff --git a/lib/Target/MSP430/MSP430BranchSelector.cpp b/lib/Target/MSP430/MSP430BranchSelector.cpp index cb08042629e..13e6a4666ca 100644 --- a/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -154,7 +154,7 @@ bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) { Cond.push_back(I->getOperand(1)); // Jump over the uncond branch inst (i.e. $+6) on opposite condition. - TII->ReverseBranchCondition(Cond); + TII->reverseBranchCondition(Cond); BuildMI(MBB, I, dl, TII->get(MSP430::JCC)) .addImm(4).addOperand(Cond[0]); diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index f7200f8c0ca..6135ce08092 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -104,7 +104,7 @@ void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(KillSrc)); } -unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -130,7 +130,7 @@ unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB, } bool MSP430InstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1 && "Invalid Xbranch condition!"); MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); diff --git a/lib/Target/MSP430/MSP430InstrInfo.h b/lib/Target/MSP430/MSP430InstrInfo.h index b2107768b57..e3259bd6a7b 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.h +++ b/lib/Target/MSP430/MSP430InstrInfo.h @@ -72,14 +72,14 @@ public: // Branch folding goodness bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; bool isUnpredicatedTerminator(const MachineInstr &MI) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index ea583e7cf41..19af1914c81 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -147,7 +147,7 @@ unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, return 1; } -unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -174,9 +174,9 @@ unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB, return removed; } -/// ReverseBranchCondition - Return the inverse opcode of the +/// reverseBranchCondition - Return the inverse opcode of the /// specified Branch instruction. -bool MipsInstrInfo::ReverseBranchCondition( +bool MipsInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 1b268c080f6..347b9187d08 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -55,7 +55,7 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, @@ -64,7 +64,7 @@ public: int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/lib/Target/NVPTX/NVPTXInstrInfo.cpp index 3b48874b322..60f8c47b7e4 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -143,7 +143,7 @@ bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const { /// operands can be passed to other TargetInstrInfo methods to create new /// branches. /// -/// Note that RemoveBranch and insertBranch must be implemented to support +/// Note that removeBranch and insertBranch must be implemented to support /// cases where this method returns success. /// bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, @@ -205,7 +205,7 @@ bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return true; } -unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.end(); diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.h b/lib/Target/NVPTX/NVPTXInstrInfo.h index 13ae987068c..3d3ae3507d8 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -63,7 +63,7 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index d5ccc4dc723..8cbd71ec048 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -605,7 +605,7 @@ bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return true; } -unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -1204,7 +1204,7 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } bool PPCInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 8a206964675..b1988dee18f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -168,7 +168,7 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, @@ -200,7 +200,7 @@ public: const TargetRegisterInfo *TRI) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override; diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 061b9641805..ea8ed830baf 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -271,7 +271,7 @@ unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB, return 2; } -unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -295,7 +295,7 @@ unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB, return Count; } -bool SparcInstrInfo::ReverseBranchCondition( +bool SparcInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1); SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 91d86cb6453..c053cc4c475 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -70,7 +70,7 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, @@ -79,7 +79,7 @@ public: int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index c2b38116d93..bdc844d21af 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -363,7 +363,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return false; } -unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -389,7 +389,7 @@ unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB, } bool SystemZInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 2 && "Invalid condition"); Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm()); return false; diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index 5364bff09af..3982b280246 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -164,7 +164,7 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, @@ -214,7 +214,7 @@ public: MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS = nullptr) const override; bool expandPostRAPseudo(MachineInstr &MBBI) const override; - bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const + bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; // Return the SystemZRegisterInfo, which this class owns. diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp index c0987724424..91f53630701 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -142,7 +142,7 @@ bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, return false; } -unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -196,7 +196,7 @@ unsigned WebAssemblyInstrInfo::insertBranch(MachineBasicBlock &MBB, return 2; } -bool WebAssemblyInstrInfo::ReverseBranchCondition( +bool WebAssemblyInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 2 && "Expected a flag and a successor block"); Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm()); diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/lib/Target/WebAssembly/WebAssemblyInstrInfo.h index 8d2cf87075e..df6c937a364 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.h +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.h @@ -48,14 +48,14 @@ public: MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; }; } // end namespace llvm diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 891aad2b1a6..b40004f7c0e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -4441,7 +4441,7 @@ bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, return true; } -unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB, +unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); @@ -7276,7 +7276,7 @@ bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First, } bool X86InstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 1 && "Invalid X86 branch condition!"); X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); Cond[0].setImm(GetOppositeBranchCondition(CC)); diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 864594746b7..a891af566d8 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -335,7 +335,7 @@ public: TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify = false) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, @@ -445,7 +445,7 @@ public: void getNoopForMachoTarget(MCInst &NopInst) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine /// instruction that defines the specified register class. diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 1adcc19b9c7..7a9c6fc93f8 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -184,7 +184,7 @@ static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) /// operands can be passed to other TargetInstrInfo methods to create new /// branches. /// -/// Note that RemoveBranch and insertBranch must be implemented to support +/// Note that removeBranch and insertBranch must be implemented to support /// cases where this method returns success. /// bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB, @@ -304,7 +304,7 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB, } unsigned -XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { +XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); @@ -400,11 +400,9 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addMemOperand(MMO); } -/// ReverseBranchCondition - Return the inverse opcode of the -/// specified Branch instruction. bool XCoreInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { - assert((Cond.size() == 2) && +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { + assert((Cond.size() == 2) && "Invalid XCore branch condition!"); Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); return false; diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index ce8c14f3e0a..a377784caf4 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -60,7 +60,7 @@ public: const DebugLoc &DL, int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, @@ -79,7 +79,7 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - bool ReverseBranchCondition( + bool reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const override; // Emit code before MBBI to load immediate value into physical register Reg. |