aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Bitcode/Writer/BitcodeWriter.cpp2
-rw-r--r--lib/CodeGen/CodeGenPrepare.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp8
-rw-r--r--lib/DebugInfo/DWARF/DWARFContext.cpp2
-rw-r--r--lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp2
-rw-r--r--lib/IR/SafepointIRVerifier.cpp2
-rw-r--r--lib/ObjectYAML/DWARFEmitter.cpp6
-rw-r--r--lib/ObjectYAML/DWARFVisitor.cpp4
-rw-r--r--lib/Target/AArch64/AArch64CallLowering.cpp2
-rw-r--r--lib/Target/AMDGPU/AMDGPULibFunc.cpp5
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp3
-rw-r--r--lib/Target/X86/X86InstructionSelector.cpp9
-rw-r--r--lib/Transforms/Scalar/NewGVN.cpp2
-rw-r--r--lib/XRay/Trace.cpp4
15 files changed, 38 insertions, 17 deletions
diff --git a/lib/Bitcode/Writer/BitcodeWriter.cpp b/lib/Bitcode/Writer/BitcodeWriter.cpp
index c81e2006ad8..7fcec9c7a8d 100644
--- a/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -4031,6 +4031,7 @@ void llvm::WriteIndexToFile(
Out.write((char *)&Buffer.front(), Buffer.size());
}
+namespace {
/// Class to manage the bitcode writing for a thin link bitcode file.
class ThinLinkBitcodeWriter : public ModuleBitcodeWriterBase {
/// ModHash is for use in ThinLTO incremental build, generated while writing
@@ -4051,6 +4052,7 @@ public:
private:
void writeSimplifiedModuleInfo();
};
+} // namespace
// This function writes a simpilified module info for thin link bitcode file.
// It only contains the source file name along with the name(the offset and
diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp
index 6d0043ba9e0..03ef8985210 100644
--- a/lib/CodeGen/CodeGenPrepare.cpp
+++ b/lib/CodeGen/CodeGenPrepare.cpp
@@ -1656,6 +1656,7 @@ static bool despeculateCountZeros(IntrinsicInst *CountZeros,
return true;
}
+namespace {
// This class provides helper functions to expand a memcmp library call into an
// inline expansion.
class MemCmpExpansion {
@@ -1703,6 +1704,7 @@ public:
unsigned NumLoadsPerBlock, const DataLayout &DL);
Value *getMemCmpExpansion(uint64_t Size);
};
+} // namespace
MemCmpExpansion::ResultBlock::ResultBlock()
: BB(nullptr), PhiSrc1(nullptr), PhiSrc2(nullptr) {}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 083167ca62f..fc441b8d857 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7015,6 +7015,7 @@ static bool createVirtualRegs(SmallVector<unsigned, 4> &Regs, unsigned NumRegs,
return true;
}
+namespace {
class ExtraFlags {
unsigned Flags = 0;
@@ -7048,6 +7049,7 @@ public:
unsigned get() const { return Flags; }
};
+} // namespace
/// visitInlineAsm - Handle a call to an InlineAsm object.
///
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 0ac92b5efa2..4d43a3b41f8 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1287,10 +1287,10 @@ static void propagateSwiftErrorVRegs(FunctionLoweringInfo *FuncInfo) {
}
}
-void preassignSwiftErrorRegs(const TargetLowering *TLI,
- FunctionLoweringInfo *FuncInfo,
- BasicBlock::const_iterator Begin,
- BasicBlock::const_iterator End) {
+static void preassignSwiftErrorRegs(const TargetLowering *TLI,
+ FunctionLoweringInfo *FuncInfo,
+ BasicBlock::const_iterator Begin,
+ BasicBlock::const_iterator End) {
if (!TLI->supportSwiftError() || FuncInfo->SwiftErrorVals.empty())
return;
diff --git a/lib/DebugInfo/DWARF/DWARFContext.cpp b/lib/DebugInfo/DWARF/DWARFContext.cpp
index eaf26bfa295..0bd9c927b0a 100644
--- a/lib/DebugInfo/DWARF/DWARFContext.cpp
+++ b/lib/DebugInfo/DWARF/DWARFContext.cpp
@@ -927,7 +927,6 @@ namespace {
struct DWARFSectionMap final : public DWARFSection {
RelocAddrMap Relocs;
};
-} // namespace
class DWARFObjInMemory final : public DWARFObject {
bool IsLittleEndian;
@@ -1279,6 +1278,7 @@ public:
F(P.second);
}
};
+} // namespace
std::unique_ptr<DWARFContext>
DWARFContext::create(const object::ObjectFile &Obj, const LoadedObjectInfo *L,
diff --git a/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp b/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
index 7c88748da80..dd41202e346 100644
--- a/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
+++ b/lib/DebugInfo/PDB/Native/GSIStreamBuilder.cpp
@@ -169,7 +169,7 @@ Error GSIStreamBuilder::finalizeMsfLayout() {
return Error::success();
}
-bool comparePubSymByAddrAndName(const CVSymbol *LS, const CVSymbol *RS) {
+static bool comparePubSymByAddrAndName(const CVSymbol *LS, const CVSymbol *RS) {
assert(LS->kind() == SymbolKind::S_PUB32);
assert(RS->kind() == SymbolKind::S_PUB32);
diff --git a/lib/IR/SafepointIRVerifier.cpp b/lib/IR/SafepointIRVerifier.cpp
index 8b328c221da..02382afb8c4 100644
--- a/lib/IR/SafepointIRVerifier.cpp
+++ b/lib/IR/SafepointIRVerifier.cpp
@@ -60,6 +60,7 @@ static cl::opt<bool> PrintOnly("safepoint-ir-verifier-print-only",
static void Verify(const Function &F, const DominatorTree &DT);
+namespace {
struct SafepointIRVerifier : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
DominatorTree DT;
@@ -79,6 +80,7 @@ struct SafepointIRVerifier : public FunctionPass {
StringRef getPassName() const override { return "safepoint verifier"; }
};
+} // namespace
void llvm::verifySafepointIR(Function &F) {
SafepointIRVerifier pass;
diff --git a/lib/ObjectYAML/DWARFEmitter.cpp b/lib/ObjectYAML/DWARFEmitter.cpp
index 89fc652035c..c49c2249cdf 100644
--- a/lib/ObjectYAML/DWARFEmitter.cpp
+++ b/lib/ObjectYAML/DWARFEmitter.cpp
@@ -62,8 +62,8 @@ static void ZeroFillBytes(raw_ostream &OS, size_t Size) {
OS.write(reinterpret_cast<char *>(FillData.data()), Size);
}
-void writeInitialLength(const DWARFYAML::InitialLength &Length, raw_ostream &OS,
- bool IsLittleEndian) {
+static void writeInitialLength(const DWARFYAML::InitialLength &Length,
+ raw_ostream &OS, bool IsLittleEndian) {
writeInteger((uint32_t)Length.TotalLength, OS, IsLittleEndian);
if (Length.isDWARF64())
writeInteger((uint64_t)Length.TotalLength64, OS, IsLittleEndian);
@@ -131,6 +131,7 @@ void DWARFYAML::EmitPubSection(raw_ostream &OS,
}
}
+namespace {
/// \brief An extension of the DWARFYAML::ConstVisitor which writes compile
/// units and DIEs to a stream.
class DumpVisitor : public DWARFYAML::ConstVisitor {
@@ -195,6 +196,7 @@ public:
DumpVisitor(const DWARFYAML::Data &DI, raw_ostream &Out)
: DWARFYAML::ConstVisitor(DI), OS(Out) {}
};
+} // namespace
void DWARFYAML::EmitDebugInfo(raw_ostream &OS, const DWARFYAML::Data &DI) {
DumpVisitor Visitor(DI, OS);
diff --git a/lib/ObjectYAML/DWARFVisitor.cpp b/lib/ObjectYAML/DWARFVisitor.cpp
index 36a9f7638bd..e6114c85ac0 100644
--- a/lib/ObjectYAML/DWARFVisitor.cpp
+++ b/lib/ObjectYAML/DWARFVisitor.cpp
@@ -34,11 +34,11 @@ void DWARFYAML::VisitorImpl<T>::onVariableSizeValue(uint64_t U, unsigned Size) {
}
}
-unsigned getOffsetSize(const DWARFYAML::Unit &Unit) {
+static unsigned getOffsetSize(const DWARFYAML::Unit &Unit) {
return Unit.Length.isDWARF64() ? 8 : 4;
}
-unsigned getRefSize(const DWARFYAML::Unit &Unit) {
+static unsigned getRefSize(const DWARFYAML::Unit &Unit) {
if (Unit.Version == 2)
return Unit.AddrSize;
return getOffsetSize(Unit);
diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp
index fc09763ed38..a1cc0b53a43 100644
--- a/lib/Target/AArch64/AArch64CallLowering.cpp
+++ b/lib/Target/AArch64/AArch64CallLowering.cpp
@@ -50,6 +50,7 @@ using namespace llvm;
AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
: CallLowering(&TLI) {}
+namespace {
struct IncomingArgHandler : public CallLowering::ValueHandler {
IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn)
@@ -167,6 +168,7 @@ struct OutgoingArgHandler : public CallLowering::ValueHandler {
CCAssignFn *AssignFnVarArg;
uint64_t StackSize;
};
+} // namespace
void AArch64CallLowering::splitToValueTypes(
const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
diff --git a/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/lib/Target/AMDGPU/AMDGPULibFunc.cpp
index 1796989b6b8..96addc01eda 100644
--- a/lib/Target/AMDGPU/AMDGPULibFunc.cpp
+++ b/lib/Target/AMDGPU/AMDGPULibFunc.cpp
@@ -516,10 +516,12 @@ bool AMDGPULibFunc::parseName(const StringRef& fullName) {
///////////////////////////////////////////////////////////////////////////////
// Itanium Demangling
+namespace {
struct ItaniumParamParser {
AMDGPULibFunc::Param Prev;
bool parseItaniumParam(StringRef& param, AMDGPULibFunc::Param &res);
};
+} // namespace
bool ItaniumParamParser::parseItaniumParam(StringRef& param,
AMDGPULibFunc::Param &res) {
@@ -689,7 +691,7 @@ static const char *getItaniumTypeName(AMDGPULibFunc::EType T) {
return nullptr;
}
-
+namespace {
// Itanium mangling ABI says:
// "5.1.8. Compression
// ... Each non-terminal in the grammar for which <substitution> appears on the
@@ -784,6 +786,7 @@ public:
if (Ptr.ArgType) Str.push_back(Ptr);
}
};
+} // namespace
std::string AMDGPULibFunc::mangleNameItanium() const {
SmallString<128> Buf;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index bc701c2987b..8ecc035ec57 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -8782,7 +8782,8 @@ static bool matchVectorShuffleAsBlend(SDValue V1, SDValue V2,
return true;
}
-uint64_t scaleVectorShuffleBlendMask(uint64_t BlendMask, int Size, int Scale) {
+static uint64_t scaleVectorShuffleBlendMask(uint64_t BlendMask, int Size,
+ int Scale) {
uint64_t ScaledMask = 0;
for (int i = 0; i != Size; ++i)
if (BlendMask & (1ull << i))
diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp
index 028039d0b0c..e2f38c51198 100644
--- a/lib/Target/X86/X86InstructionSelector.cpp
+++ b/lib/Target/X86/X86InstructionSelector.cpp
@@ -167,7 +167,7 @@ X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg,
return getRegClass(Ty, RegBank);
}
-unsigned getSubRegIndex(const TargetRegisterClass *RC) {
+static unsigned getSubRegIndex(const TargetRegisterClass *RC) {
unsigned SubIdx = X86::NoSubRegister;
if (RC == &X86::GR32RegClass) {
SubIdx = X86::sub_32bit;
@@ -180,7 +180,7 @@ unsigned getSubRegIndex(const TargetRegisterClass *RC) {
return SubIdx;
}
-const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
+static const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
if (X86::GR64RegClass.contains(Reg))
return &X86::GR64RegClass;
@@ -403,8 +403,9 @@ unsigned X86InstructionSelector::getLoadStoreOp(LLT &Ty, const RegisterBank &RB,
}
// Fill in an address from the given instruction.
-void X86SelectAddress(const MachineInstr &I, const MachineRegisterInfo &MRI,
- X86AddressMode &AM) {
+static void X86SelectAddress(const MachineInstr &I,
+ const MachineRegisterInfo &MRI,
+ X86AddressMode &AM) {
assert(I.getOperand(0).isReg() && "unsupported opperand.");
assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
diff --git a/lib/Transforms/Scalar/NewGVN.cpp b/lib/Transforms/Scalar/NewGVN.cpp
index 1afbde991f8..e545163c96c 100644
--- a/lib/Transforms/Scalar/NewGVN.cpp
+++ b/lib/Transforms/Scalar/NewGVN.cpp
@@ -148,6 +148,7 @@ PHIExpression::~PHIExpression() = default;
}
}
+namespace {
// Tarjan's SCC finding algorithm with Nuutila's improvements
// SCCIterator is actually fairly complex for the simple thing we want.
// It also wants to hand us SCC's that are unrelated to the phi node we ask
@@ -380,6 +381,7 @@ private:
// This is used so we can detect store equivalence changes properly.
int StoreCount = 0;
};
+} // namespace
namespace llvm {
struct ExactEqualsExpression {
diff --git a/lib/XRay/Trace.cpp b/lib/XRay/Trace.cpp
index 89fd0b0748b..0c5a562cf30 100644
--- a/lib/XRay/Trace.cpp
+++ b/lib/XRay/Trace.cpp
@@ -21,6 +21,7 @@ using namespace llvm;
using namespace llvm::xray;
using llvm::yaml::Input;
+namespace {
using XRayRecordStorage =
std::aligned_storage<sizeof(XRayRecord), alignof(XRayRecord)>::type;
@@ -134,7 +135,7 @@ struct FDRState {
uint64_t CurrentBufferConsumed;
};
-Twine fdrStateToTwine(const FDRState::Token &state) {
+const char *fdrStateToTwine(const FDRState::Token &state) {
switch (state) {
case FDRState::Token::NEW_BUFFER_RECORD_OR_EOF:
return "NEW_BUFFER_RECORD_OR_EOF";
@@ -484,6 +485,7 @@ Error loadYAMLLog(StringRef Data, XRayFileHeader &FileHeader,
});
return Error::success();
}
+} // namespace
Expected<Trace> llvm::xray::loadTraceFile(StringRef Filename, bool Sort) {
int Fd;
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-04 10:26:20 +0000