diff options
358 files changed, 4046 insertions, 4044 deletions
diff --git a/include/llvm/CodeGen/LivePhysRegs.h b/include/llvm/CodeGen/LivePhysRegs.h index 6d54ebf1b78..eb935bb7c06 100644 --- a/include/llvm/CodeGen/LivePhysRegs.h +++ b/include/llvm/CodeGen/LivePhysRegs.h @@ -20,11 +20,11 @@ /// register. /// /// X86 Example: -/// %YMM0<def> = ... -/// %XMM0<def> = ... (Kills %XMM0, all %XMM0s sub-registers, and %YMM0) +/// %ymm0<def> = ... +/// %xmm0<def> = ... (Kills %xmm0, all %xmm0s sub-registers, and %ymm0) /// -/// %YMM0<def> = ... -/// %XMM0<def> = ..., %YMM0<imp-use> (%YMM0 and all its sub-registers are alive) +/// %ymm0<def> = ... +/// %xmm0<def> = ..., %ymm0<imp-use> (%ymm0 and all its sub-registers are alive) //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_LIVEPHYSREGS_H diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 6693ed22328..1f1dc5c6830 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -371,7 +371,7 @@ public: /// substPhysReg - Substitute the current register with the physical register /// Reg, taking any existing SubReg into account. For instance, - /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. + /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al. /// void substPhysReg(unsigned Reg, const TargetRegisterInfo&); diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h index 2641a1aea83..308216b7998 100644 --- a/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1140,7 +1140,7 @@ struct VirtReg2IndexFunctor { /// %noreg - NoRegister /// %vreg5 - a virtual register. /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). -/// %EAX - a physical register +/// %eax - a physical register /// %physreg17 - a physical register when no TRI instance given. /// /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; @@ -1151,8 +1151,8 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, /// /// Register units are named after their root registers: /// -/// AL - Single root. -/// FP0~ST7 - Dual roots. +/// al - Single root. +/// fp0~st7 - Dual roots. /// /// Usage: OS << printRegUnit(Unit, TRI) << '\n'; Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp index e527110872a..b8a006492d0 100644 --- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -448,11 +448,11 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI, // FIXME: The issue with predicated instruction is more complex. We are being // conservatively here because the kill markers cannot be trusted after // if-conversion: - // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] // ... - // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] - // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] - // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] + // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] + // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) // // The first R6 kill is not really a kill since it's killed by a predicated // instruction which may not be executed. The second R6 def may or may not diff --git a/lib/CodeGen/CriticalAntiDepBreaker.cpp b/lib/CodeGen/CriticalAntiDepBreaker.cpp index be364bf760a..83f08e082c3 100644 --- a/lib/CodeGen/CriticalAntiDepBreaker.cpp +++ b/lib/CodeGen/CriticalAntiDepBreaker.cpp @@ -170,11 +170,11 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) { // FIXME: The issue with predicated instruction is more complex. We are being // conservative here because the kill markers cannot be trusted after // if-conversion: - // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // %r6<def> = LDR %sp, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] // ... - // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] - // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] - // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // STR %r0, %r6<kill>, %reg0, 0, pred:0, pred:%cpsr; mem:ST4[%395] + // %r6<def> = LDR %sp, %reg0, 100, pred:0, pred:%cpsr; mem:LD4[FixedStack12] + // STR %r0, %r6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) // // The first R6 kill is not really a kill since it's killed by a predicated // instruction which may not be executed. The second R6 def may or may not diff --git a/lib/CodeGen/ExpandPostRAPseudos.cpp b/lib/CodeGen/ExpandPostRAPseudos.cpp index 651d67226dc..dc5040471f3 100644 --- a/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -104,8 +104,8 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { if (DstSubReg == InsReg) { // No need to insert an identity copy instruction. // Watch out for case like this: - // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3 - // We must leave %RAX live. + // %rax<def> = SUBREG_TO_REG 0, %eax<kill>, 3 + // We must leave %rax live. if (DstReg != InsReg) { MI->setDesc(TII->get(TargetOpcode::KILL)); MI->RemoveOperand(3); // SubIdx diff --git a/lib/CodeGen/ImplicitNullChecks.cpp b/lib/CodeGen/ImplicitNullChecks.cpp index d2dd7f13ce2..02c7eeb7a48 100644 --- a/lib/CodeGen/ImplicitNullChecks.cpp +++ b/lib/CodeGen/ImplicitNullChecks.cpp @@ -498,7 +498,7 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks( // Starting with a code fragment like: // - // test %RAX, %RAX + // test %rax, %rax // jne LblNotNull // // LblNull: @@ -508,13 +508,13 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks( // Inst0 // Inst1 // ... - // Def = Load (%RAX + <offset>) + // Def = Load (%rax + <offset>) // ... // // // we want to end up with // - // Def = FaultingLoad (%RAX + <offset>), LblNull + // Def = FaultingLoad (%rax + <offset>), LblNull // jmp LblNotNull ;; explicit or fallthrough // // LblNotNull: @@ -528,11 +528,11 @@ bool ImplicitNullChecks::analyzeBlockForNullChecks( // // To see why this is legal, consider the two possibilities: // - // 1. %RAX is null: since we constrain <offset> to be less than PageSize, the + // 1. %rax is null: since we constrain <offset> to be less than PageSize, the // load instruction dereferences the null page, causing a segmentation // fault. // - // 2. %RAX is not null: in this case we know that the load cannot fault, as + // 2. %rax is not null: in this case we know that the load cannot fault, as // otherwise the load would've faulted in the original program too and the // original program would've been undefined. // diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index b26628b3b5f..c55519387d1 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -698,11 +698,11 @@ void LiveIntervals::addKillFlags(const VirtRegMap *VRM) { // Check if any of the regunits are live beyond the end of RI. That could // happen when a physreg is defined as a copy of a virtreg: // - // %EAX = COPY %vreg5 - // FOO %vreg5 <--- MI, cancel kill because %EAX is live. - // BAR %EAX<kill> + // %eax = COPY %vreg5 + // FOO %vreg5 <--- MI, cancel kill because %eax is live. + // BAR %eax<kill> // - // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX. + // There should be no kill flag on FOO when %vreg5 is rewritten as %eax. for (auto &RUP : RU) { const LiveRange &RURange = *RUP.first; LiveRange::const_iterator &I = RUP.second; diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index aaac6ad9336..d26d53d87ca 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -623,12 +623,12 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) { // Go through implicit defs of CSMI and MI, and clear the kill flags on // their uses in all the instructions between CSMI and MI. // We might have made some of the kill flags redundant, consider: - // subs ... %NZCV<imp-def> <- CSMI - // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore - // subs ... %NZCV<imp-def> <- MI, to be eliminated - // csinc ... %NZCV<imp-use,kill> + // subs ... %nzcv<imp-def> <- CSMI + // csinc ... %nzcv<imp-use,kill> <- this kill flag isn't valid anymore + // subs ... %nzcv<imp-def> <- MI, to be eliminated + // csinc ... %nzcv<imp-use,kill> // Since we eliminated MI, and reused a register imp-def'd by CSMI - // (here %NZCV), that register, if it was killed before MI, should have + // (here %nzcv), that register, if it was killed before MI, should have // that kill flag removed, because it's lifetime was extended. if (CSMI->getParent() == MI->getParent()) { for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II) diff --git a/lib/CodeGen/MachineCopyPropagation.cpp b/lib/CodeGen/MachineCopyPropagation.cpp index f0cbcf6fcd2..1590b205def 100644 --- a/lib/CodeGen/MachineCopyPropagation.cpp +++ b/lib/CodeGen/MachineCopyPropagation.cpp @@ -226,19 +226,19 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) { // The two copies cancel out and the source of the first copy // hasn't been overridden, eliminate the second one. e.g. - // %ECX<def> = COPY %EAX - // ... nothing clobbered EAX. - // %EAX<def> = COPY %ECX + // %ecx<def> = COPY %eax + // ... nothing clobbered eax. + // %eax<def> = COPY %ecx // => - // %ECX<def> = COPY %EAX + // %ecx<def> = COPY %eax // // or // - // %ECX<def> = COPY %EAX - // ... nothing clobbered EAX. - // %ECX<def> = COPY %EAX + // %ecx<def> = COPY %eax + // ... nothing clobbered eax. + // %ecx<def> = COPY %eax // => - // %ECX<def> = COPY %EAX + // %ecx<def> = COPY %eax if (eraseIfRedundant(*MI, Def, Src) || eraseIfRedundant(*MI, Src, Def)) continue; diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 6f3753e88b8..11257d98e37 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -246,9 +246,9 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg, // BB#1: derived from LLVM BB %bb4.preheader // Predecessors according to CFG: BB#0 // ... - // %reg16385<def> = DEC64_32r %reg16437, %EFLAGS<imp-def,dead> + // %reg16385<def> = DEC64_32r %reg16437, %eflags<imp-def,dead> // ... - // JE_4 <BB#37>, %EFLAGS<imp-use> + // JE_4 <BB#37>, %eflags<imp-use> // Successors according to CFG: BB#37 BB#2 // // BB#2: derived from LLVM BB %bb.nph diff --git a/lib/CodeGen/PeepholeOptimizer.cpp b/lib/CodeGen/PeepholeOptimizer.cpp index e3dceac384f..dfad7615bca 100644 --- a/lib/CodeGen/PeepholeOptimizer.cpp +++ b/lib/CodeGen/PeepholeOptimizer.cpp @@ -1516,7 +1516,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( unsigned DstReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(1).getReg(); if (isNAPhysCopy(SrcReg) && TargetRegisterInfo::isVirtualRegister(DstReg)) { - // %vreg = COPY %PHYSREG + // %vreg = COPY %physreg // Avoid using a datastructure which can track multiple live non-allocatable // phys->virt copies since LLVM doesn't seem to do this. NAPhysToVirtMIs.insert({SrcReg, MI}); @@ -1526,7 +1526,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( if (!(TargetRegisterInfo::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg))) return false; - // %PHYSREG = COPY %vreg + // %physreg = COPY %vreg auto PrevCopy = NAPhysToVirtMIs.find(DstReg); if (PrevCopy == NAPhysToVirtMIs.end()) { // We can't remove the copy: there was an intervening clobber of the @@ -1696,8 +1696,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) { // Track when a non-allocatable physical register is copied to a virtual // register so that useless moves can be removed. // - // %PHYSREG is the map index; MI is the last valid `%vreg = COPY %PHYSREG` - // without any intervening re-definition of %PHYSREG. + // %physreg is the map index; MI is the last valid `%vreg = COPY %physreg` + // without any intervening re-definition of %physreg. DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs; // Set of virtual registers that are copied from. diff --git a/lib/CodeGen/README.txt b/lib/CodeGen/README.txt index 8f19e432ab7..2fcbd1280da 100644 --- a/lib/CodeGen/README.txt +++ b/lib/CodeGen/README.txt @@ -33,7 +33,7 @@ It also increase the likelihood the store may become dead. bb27 ... ... %reg1037 = ADDri %reg1039, 1 - %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 + %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10 Successors according to CFG: 0x8b03bf0 (#5) bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5): diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 18f9ab4ae5f..81f9a343dc1 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -1820,20 +1820,20 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) { MachineInstr *CopyMI; if (CP.isFlipped()) { // Physreg is copied into vreg - // %vregY = COPY %X - // ... //< no other def of %X here + // %vregY = COPY %x + // ... //< no other def of %x here // use %vregY // => // ... - // use %X + // use %x CopyMI = MRI->getVRegDef(SrcReg); } else { // VReg is copied into physreg: // %vregX = def - // ... //< no other def or use of %Y here - // %Y = COPY %vregX + // ... //< no other def or use of %y here + // %y = COPY %vregX // => - // %Y = def + // %y = def // ... if (!MRI->hasOneNonDBGUse(SrcReg)) { DEBUG(dbgs() << "\t\tMultiple vreg uses!\n"); diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp index 4e28c4781c2..cc5c1485608 100644 --- a/lib/CodeGen/TargetRegisterInfo.cpp +++ b/lib/CodeGen/TargetRegisterInfo.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -93,9 +94,10 @@ Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); else if (TargetRegisterInfo::isVirtualRegister(Reg)) OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); - else if (TRI && Reg < TRI->getNumRegs()) - OS << '%' << TRI->getName(Reg); - else + else if (TRI && Reg < TRI->getNumRegs()) { + OS << '%'; + printLowerCase(TRI->getName(Reg), OS); + } else OS << "%physreg" << Reg; if (SubIdx) { if (TRI) diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 650912f56a3..b996850d706 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -589,23 +589,23 @@ isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, // e.g. // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> + // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> // insert => %reg1030<def> = MOV8rr %reg1028 - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> // In this case, it might not be possible to coalesce the second MOV8rr // instruction if the first one is coalesced. So it would be profitable to // commute it: // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> + // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> // insert => %reg1030<def> = MOV8rr %reg1029 - // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %eflags<imp-def,dead> if (!isPlainlyKilled(MI, regC, LIS)) return false; // Ok, we have something like: - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> // let's see if it's worth commuting it. // Look for situations like this: diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 1533abde87e..df950b5d317 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -380,8 +380,8 @@ void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const { ++NumIdCopies; // Copies like: - // %R0 = COPY %R0<undef> - // %AL = COPY %AL, %EAX<imp-def> + // %r0 = COPY %r0<undef> + // %al = COPY %al, %eax<imp-def> // give us additional liveness information: The target (super-)register // must not be valid before this point. Replace the COPY with a KILL // instruction to maintain this information. diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index c4aa6bf139d..bf5f0f624af 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2801,11 +2801,11 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( LiveIntervals *LIS) const { // This is a bit of a hack. Consider this instruction: // - // %vreg0<def> = COPY %SP; GPR64all:%vreg0 + // %vreg0<def> = COPY %sp; GPR64all:%vreg0 // // We explicitly chose GPR64all for the virtual register so such a copy might // be eliminated by RegisterCoalescer. However, that may not be possible, and - // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all + // %vreg0 may even spill. We can't spill %sp, and since it is in the GPR64all // register class, TargetInstrInfo::foldMemoryOperand() is going to try. // // To prevent that, we are going to constrain the %vreg0 register class here. @@ -2830,12 +2830,12 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // Handle the case where a copy is being spilled or filled but the source // and destination register class don't match. For example: // - // %vreg0<def> = COPY %XZR; GPR64common:%vreg0 + // %vreg0<def> = COPY %xzr; GPR64common:%vreg0 // // In this case we can still safely fold away the COPY and generate the // following spill code: // - // STRXui %XZR, <fi#0> + // STRXui %xzr, <fi#0> // // This also eliminates spilled cross register class COPYs (e.g. between x and // d regs) of the same size. For example: @@ -2886,12 +2886,12 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl( // Handle cases like spilling def of: // - // %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64common:%vreg0 + // %vreg0:sub_32<def,read-undef> = COPY %wzr; GPR64common:%vreg0 // // where the physical register source can be widened and stored to the full // virtual reg destination stack slot, in this case producing: // - // STRXui %XZR, <fi#0> + // STRXui %xzr, <fi#0> // if (IsSpill && DstMO.isUndef() && TargetRegisterInfo::isPhysicalRegister(SrcReg)) { diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index c32b0dbca9b..de912244eeb 100644 --- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -830,8 +830,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I, if (SExtIdx != -1) { // Generate the sign extension for the proper result of the ldp. // I.e., with X1, that would be: - // %W1<def> = KILL %W1, %X1<imp-def> - // %X1<def> = SBFMXri %X1<kill>, 0, 31 + // %w1<def> = KILL %w1, %x1<imp-def> + // %x1<def> = SBFMXri %x1<kill>, 0, 31 MachineOperand &DstMO = MIB->getOperand(SExtIdx); // Right now, DstMO has the extended register, since it comes from an // extended opcode. diff --git a/lib/Target/AMDGPU/CaymanInstructions.td b/lib/Target/AMDGPU/CaymanInstructions.td index 0ba5acad680..429d28e753c 100644 --- a/lib/Target/AMDGPU/CaymanInstructions.td +++ b/lib/Target/AMDGPU/CaymanInstructions.td @@ -144,8 +144,8 @@ def VTX_READ_32_cm // to be caused by ALU instructions in the next instruction group that wrote // to the $src_gpr registers of the VTX_READ. // e.g. - // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 - // %T2_X<def> = MOV %ZERO + // %t3_x<def> = VTX_READ_PARAM_32_eg %t2_x<kill>, 24 + // %t2_x<def> = MOV %zero //Adding this constraint prevents this from happening. let Constraints = "$src_gpr.ptr = $dst_gpr"; } diff --git a/lib/Target/AMDGPU/EvergreenInstructions.td b/lib/Target/AMDGPU/EvergreenInstructions.td index bccad826d18..c25980eef85 100644 --- a/lib/Target/AMDGPU/EvergreenInstructions.td +++ b/lib/Target/AMDGPU/EvergreenInstructions.td @@ -212,8 +212,8 @@ def VTX_READ_32_eg // to be caused by ALU instructions in the next instruction group that wrote // to the $src_gpr registers of the VTX_READ. // e.g. - // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 - // %T2_X<def> = MOV %ZERO + // %t3_x<def> = VTX_READ_PARAM_32_eg %t2_x<kill>, 24 + // %t2_x<def> = MOV %zero //Adding this constraint prevents this from happening. let Constraints = "$src_gpr.ptr = $dst_gpr"; } diff --git a/lib/Target/AMDGPU/SIFoldOperands.cpp b/lib/Target/AMDGPU/SIFoldOperands.cpp index 0fa6712527f..2c52e16892c 100644 --- a/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -971,9 +971,9 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { // Prevent folding operands backwards in the function. For example, // the COPY opcode must not be replaced by 1 in this example: // - // %vreg3<def> = COPY %VGPR0; VGPR_32:%vreg3 + // %vreg3<def> = COPY %vgpr0; VGPR_32:%vreg3 // ... - // %VGPR0<def> = V_MOV_B32_e32 1, %EXEC<imp-use> + // %vgpr0<def> = V_MOV_B32_e32 1, %exec<imp-use> MachineOperand &Dst = MI.getOperand(0); if (Dst.isReg() && !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index 2561f7f09fe..2c7ef096d9c 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -6600,7 +6600,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG) return; - // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used. + // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used. // Note that subregs are packed, i.e. Lane==0 is the first bit set // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit // set, etc. diff --git a/lib/Target/AMDGPU/SILowerControlFlow.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp index 15210d2a31c..027974311da 100644 --- a/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -21,31 +21,31 @@ /// EXEC to update the predicates. /// /// For example: -/// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2 -/// %SGPR0 = SI_IF %VCC -/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 -/// %SGPR0 = SI_ELSE %SGPR0 -/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0 -/// SI_END_CF %SGPR0 +/// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2 +/// %sgpr0 = SI_IF %vcc +/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 +/// %sgpr0 = SI_ELSE %sgpr0 +/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr0 +/// SI_END_CF %sgpr0 /// /// becomes: /// -/// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask -/// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask +/// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc // Save and update the exec mask +/// %sgpr0 = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask /// S_CBRANCH_EXECZ label0 // This instruction is an optional /// // optimization which allows us to /// // branch if all the bits of /// // EXEC are zero. -/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch +/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch /// /// label0: -/// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block -/// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask +/// %sgpr0 = S_OR_SAVEEXEC_B64 %exec // Restore the exec mask for the Then block +/// %exec = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask /// S_BRANCH_EXECZ label1 // Use our branch optimization /// // instruction again. -/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block +/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr // Do the THEN block /// label1: -/// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits +/// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits //===----------------------------------------------------------------------===// #include "AMDGPU.h" diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index d60734ab144..e9a13b9802b 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -1832,12 +1832,12 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, if (!HasFP) { if (SavedRegs.test(ARM::R7)) { --RegDeficit; - DEBUG(dbgs() << "%R7 is saved low register, RegDeficit = " + DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::R7); DEBUG(dbgs() - << "%R7 is non-saved low register, adding to AvailableRegs\n"); + << "%r7 is non-saved low register, adding to AvailableRegs\n"); } } @@ -1859,11 +1859,11 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF, MF.getFrameInfo().isReturnAddressTaken())) { if (SavedRegs.test(ARM::LR)) { --RegDeficit; - DEBUG(dbgs() << "%LR is saved register, RegDeficit = " << RegDeficit + DEBUG(dbgs() << "%lr is saved register, RegDeficit = " << RegDeficit << "\n"); } else { AvailableRegs.push_back(ARM::LR); - DEBUG(dbgs() << "%LR is not saved, adding to AvailableRegs\n"); + DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index e989c2fce5d..2b63e0c842f 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1697,7 +1697,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, if (OddReg == EvenReg && EvenDeadKill) { // If the two source operands are the same, the kill marker is // probably on the first one. e.g. - // t2STRDi8 %R5<kill>, %R5, %R9<kill>, 0, 14, %reg0 + // t2STRDi8 %r5<kill>, %r5, %r9<kill>, 0, 14, %reg0 EvenDeadKill = false; OddDeadKill = true; } diff --git a/lib/Target/Hexagon/HexagonBlockRanges.cpp b/lib/Target/Hexagon/HexagonBlockRanges.cpp index 00db408b8ed..9ca7e5f0a3c 100644 --- a/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -368,7 +368,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, } } // Defs and clobbers can overlap, e.g. - // %D0<def,dead> = COPY %vreg5, %R0<imp-def>, %R1<imp-def> + // %d0<def,dead> = COPY %vreg5, %r0<imp-def>, %r1<imp-def> for (RegisterRef R : Defs) Clobbers.erase(R); diff --git a/lib/Target/Hexagon/HexagonConstPropagation.cpp b/lib/Target/Hexagon/HexagonConstPropagation.cpp index ed6c40deeba..e7c3290d151 100644 --- a/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -1974,7 +1974,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI, { const MachineOperand &VO = MI.getOperand(1); // The operand of CONST32 can be a blockaddress, e.g. - // %vreg0<def> = CONST32 <blockaddress(@eat, %L)> + // %vreg0<def> = CONST32 <blockaddress(@eat, %l)> // Do this check for all instructions for safety. if (!VO.isImm()) return false; @@ -3144,7 +3144,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, BrI.setDesc(JD); while (BrI.getNumOperands() > 0) BrI.RemoveOperand(0); - // This ensures that all implicit operands (e.g. %R31<imp-def>, etc) + // This ensures that all implicit operands (e.g. %r31<imp-def>, etc) // are present in the rewritten branch. for (auto &Op : NI->operands()) BrI.addOperand(Op); diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index a27993116d8..2dfd7b7f9c8 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -351,11 +351,11 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // kill flag for a register (a removeRegisterKilled() analogous to // addRegisterKilled) that handles aliased register correctly. // * or has a killed aliased register use of I1's use reg - // %D4<def> = A2_tfrpi 16 - // %R6<def> = A2_tfr %R9 - // %R8<def> = KILL %R8, %D4<imp-use,kill> + // %d4<def> = A2_tfrpi 16 + // %r6<def> = A2_tfr %r9 + // %r8<def> = KILL %r8, %d4<imp-use,kill> // If we want to move R6 = across the KILL instruction we would have - // to remove the %D4<imp-use,kill> operand. For now, we are + // to remove the %d4<imp-use,kill> operand. For now, we are // conservative and disallow the move. // we can't move I1 across it. if (MI.isDebugValue()) { diff --git a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index bec759a826d..b2244107ac4 100644 --- a/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -27,8 +27,8 @@ // // %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1 // %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0 -// J2_jumpt %vreg41<kill>, <BB#5>, %PC<imp-def,dead> -// J2_jump <BB#4>, %PC<imp-def,dead> +// J2_jumpt %vreg41<kill>, <BB#5>, %pc<imp-def,dead> +// J2_jump <BB#4>, %pc<imp-def,dead> // Successors according to CFG: BB#4(62) BB#5(62) // // BB#4: derived from LLVM BB %if.then @@ -42,8 +42,8 @@ // %vreg12<def> = PHI %vreg6, <BB#3>, %vreg11, <BB#4> // %vreg13<def> = A2_addp %vreg7, %vreg12 // %vreg42<def> = C2_cmpeqi %vreg9, 10 -// J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead> -// J2_jump <BB#6>, %PC<imp-def,dead> +// J2_jumpf %vreg42<kill>, <BB#3>, %pc<imp-def,dead> +// J2_jump <BB#6>, %pc<imp-def,dead> // Successors according to CFG: BB#6(4) BB#3(124) // // would become: @@ -55,8 +55,8 @@ // %vreg46<def> = PS_pselect %vreg41, %vreg6, %vreg11 // %vreg13<def> = A2_addp %vreg7, %vreg46 // %vreg42<def> = C2_cmpeqi %vreg9, 10 -// J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead> -// J2_jump <BB#6>, %PC<imp-def,dead> +// J2_jumpf %vreg42<kill>, <BB#3>, %pc<imp-def,dead> +// J2_jump <BB#6>, %pc<imp-def,dead> // Successors according to CFG: BB#6 BB#3 #include "Hexagon.h" diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 5ca8b0f30e0..56171f22148 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -1720,7 +1720,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { MachineOperand &MO = PredDef->getOperand(i); if (MO.isReg()) { // Skip all implicit references. In one case there was: - // %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use> + // %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %usr<imp-use> if (MO.isImplicit()) continue; if (MO.isUse()) { diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 3c0b3061688..4cdfd09c095 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1616,8 +1616,8 @@ DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState( } // Inspired by this pair: -// %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0] -// S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1] +// %r13<def> = L2_loadri_io %r29, 136; mem:LD4[FixedStack0] +// S2_storeri_io %r29, 132, %r1<kill>; flags: mem:ST4[FixedStack1] // Currently AA considers the addresses in these instructions to be aliasing. bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint( MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { @@ -3516,7 +3516,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::EH_RETURN_JMPR: case Hexagon::PS_jmpret: // jumpr r31 - // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>. + // Actual form JMPR %pc<imp-def>, %r31<imp-use>, %r0<imp-use,internal>. DstReg = MI.getOperand(0).getReg(); if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) return HexagonII::HSIG_L2; @@ -3706,7 +3706,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::C2_cmovenewif: // if ([!]P0[.new]) Rd = #0 // Actual form: - // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>; + // %r16<def> = C2_cmovenewit %p0<internal>, 0, %r16<imp-use,undef>; DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); if (isIntRegForSubInst(DstReg) && diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index cf7a5fff149..51cf6bbd8a2 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -129,9 +129,9 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic // before the callsite of this function // But we can not as it comes in the following fashion. - // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill> - // %R0<def> = KILL %R0, %D0<imp-use,kill> - // %P0<def> = CMPEQri %R0<kill>, 0 + // %d0<def> = Hexagon_S2_lsr_r_p %d0<kill>, %r2<kill> + // %r0<def> = KILL %r0, %d0<imp-use,kill> + // %p0<def> = CMPEQri %r0<kill>, 0 // Hence, we need to check if it's a KILL instruction. if (II->getOpcode() == TargetOpcode::KILL) return false; @@ -193,9 +193,9 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA, // to new value jump. If they are in the path, bail out. // KILL sets kill flag on the opcode. It also sets up a // single register, out of pair. - // %D0<def> = S2_lsr_r_p %D0<kill>, %R2<kill> - // %R0<def> = KILL %R0, %D0<imp-use,kill> - // %P0<def> = C2_cmpeqi %R0<kill>, 0 + // %d0<def> = S2_lsr_r_p %d0<kill>, %r2<kill> + // %r0<def> = KILL %r0, %d0<imp-use,kill> + // %p0<def> = C2_cmpeqi %r0<kill>, 0 // PHI can be anything after RA. // COPY can remateriaze things in between feeder, compare and nvj. if (MII->getOpcode() == TargetOpcode::KILL || diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index d794f83aaa4..0ef0e78c524 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -20,12 +20,12 @@ // ... // %vreg16<def> = NOT_p %vreg15<kill> // ... -// JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead> +// JMP_c %vreg16<kill>, <BB#1>, %pc<imp-def,dead> // // Into // %vreg15<def> = CMPGTrr %vreg6, %vreg2; // ... -// JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>; +// JMP_cNot %vreg15<kill>, <BB#1>, %pc<imp-def,dead>; // // Note: The peephole pass makes the instrucstions like // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill> diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 7ec4c34504b..7eed2898f61 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -220,21 +220,21 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1])) DAG->SUnits[su].addPred(SDep(&DAG->SUnits[su-1], SDep::Barrier)); // Prevent redundant register copies between two calls, which are caused by - // both the return value and the argument for the next call being in %R0. + // both the return value and the argument for the next call being in %r0. // Example: // 1: <call1> - // 2: %VregX = COPY %R0 - // 3: <use of %VregX> - // 4: %R0 = ... + // 2: %vregX = COPY %r0 + // 3: <use of %vregX> + // 4: %r0 = ... // 5: <call2> // The scheduler would often swap 3 and 4, so an additional register is // needed. This code inserts a Barrier dependence between 3 & 4 to prevent - // this. The same applies for %D0 and %V0/%W0, which are also handled. + // this. The same applies for %d0 and %v0/%w0, which are also handled. else if (SchedRetvalOptimization) { const MachineInstr *MI = DAG->SUnits[su].getInstr(); if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) || MI->readsRegister(Hexagon::V0, &TRI))) { - // %vregX = COPY %R0 + // %vregX = COPY %r0 VRegHoldingRet = MI->getOperand(0).getReg(); RetRegister = MI->getOperand(1).getReg(); LastUseOfRet = nullptr; @@ -242,7 +242,7 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { // <use of %vregX> LastUseOfRet = &DAG->SUnits[su]; else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI)) - // %R0 = ... + // %r0 = ... DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier)); } } diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index deb46f01c28..a8c5dea0d9e 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -772,8 +772,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI, // If data definition is because of implicit definition of the register, // do not newify the store. Eg. - // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def> - // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343] + // %r9<def> = ZXTH %r12, %d6<imp-use>, %r12<imp-def> + // S2_storerh_io %r8, 2, %r12<kill>; mem:ST2[%scevgep343] for (auto &MO : PacketMI.operands()) { if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) return false; @@ -787,8 +787,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI, // Handle imp-use of super reg case. There is a target independent side // change that should prevent this situation but I am handling it for // just-in-case. For example, we cannot newify R2 in the following case: - // %R3<def> = A2_tfrsi 0; - // S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>; + // %r3<def> = A2_tfrsi 0; + // S2_storeri_io %r0<kill>, 0, %r2<kill>, %d1<imp-use,kill>; for (auto &MO : MI.operands()) { if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg) return false; @@ -892,12 +892,12 @@ bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI, // Go through the packet instructions and search for an anti dependency between // them and DepReg from MI. Consider this case: // Trying to add -// a) %R1<def> = TFRI_cdNotPt %P3, 2 +// a) %r1<def> = TFRI_cdNotPt %p3, 2 // to this packet: // { -// b) %P0<def> = C2_or %P3<kill>, %P0<kill> -// c) %P3<def> = C2_tfrrp %R23 -// d) %R1<def> = C2_cmovenewit %P3, 4 +// b) %p0<def> = C2_or %p3<kill>, %p0<kill> +// c) %p3<def> = C2_tfrrp %r23 +// d) %r1<def> = C2_cmovenewit %p3, 4 // } // The P3 from a) and d) will be complements after // a)'s P3 is converted to .new form @@ -962,11 +962,11 @@ bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1, // One corner case deals with the following scenario: // Trying to add - // a) %R24<def> = A2_tfrt %P0, %R25 + // a) %r24<def> = A2_tfrt %p0, %r25 // to this packet: // { - // b) %R25<def> = A2_tfrf %P0, %R24 - // c) %P0<def> = C2_cmpeqi %R26, 1 + // b) %r25<def> = A2_tfrf %p0, %r24 + // c) %p0<def> = C2_cmpeqi %r26, 1 // } // // On general check a) and b) are complements, but presence of c) will @@ -1543,7 +1543,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { // There are certain anti-dependencies that cannot be ignored. // Specifically: - // J2_call ... %R0<imp-def> ; SUJ + // J2_call ... %r0<imp-def> ; SUJ // R0 = ... ; SUI // Those cannot be packetized together, since the call will observe // the effect of the assignment to R0. diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index a39b178805e..7dd89c6eb8e 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -272,7 +272,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { case Hexagon::J2_jumpr: case Hexagon::PS_jmpret: // jumpr r31 - // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>. + // Actual form JMPR %pc<imp-def>, %r31<imp-use>, %r0<imp-use,internal>. DstReg = MCI.getOperand(0).getReg(); if (Hexagon::R31 == DstReg) return HexagonII::HSIG_L2; @@ -471,7 +471,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { case Hexagon::C2_cmovenewif: // if ([!]P0[.new]) Rd = #0 // Actual form: - // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>; + // %r16<def> = C2_cmovenewit %p0<internal>, 0, %r16<imp-use,undef>; DstReg = MCI.getOperand(0).getReg(); // Rd PredReg = MCI.getOperand(1).getReg(); // P0 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index ea589c7a82a..3a4a41ccb40 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -113,9 +113,9 @@ bool llvm::HexagonMCShuffle(MCContext &Context, bool Fatal, if (!HexagonMCInstrInfo::bundleSize(MCB)) { // There once was a bundle: - // BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ... - // * %D2<def> = IMPLICIT_DEF; flags: - // * %D7<def> = IMPLICIT_DEF; flags: + // BUNDLE %d2<imp-def>, %r4<imp-def>, %r5<imp-def>, %d7<imp-def>, ... + // * %d2<def> = IMPLICIT_DEF; flags: + // * %d7<def> = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. DEBUG(dbgs() << "Skipping empty bundle"); @@ -137,9 +137,9 @@ llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, if (!HexagonMCInstrInfo::bundleSize(MCB)) { // There once was a bundle: - // BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ... - // * %D2<def> = IMPLICIT_DEF; flags: - // * %D7<def> = IMPLICIT_DEF; flags: + // BUNDLE %d2<imp-def>, %r4<imp-def>, %r5<imp-def>, %d7<imp-def>, ... + // * %d2<def> = IMPLICIT_DEF; flags: + // * %d7<def> = IMPLICIT_DEF; flags: // After the IMPLICIT_DEFs were removed by the asm printer, the bundle // became empty. DEBUG(dbgs() << "Skipping empty bundle"); diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 878497ca76f..74394d0e84c 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -480,7 +480,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an - // immediate 0 as an operand and requires the removal of it's %RA<imp-def> + // immediate 0 as an operand and requires the removal of it's %ra<imp-def> // implicit operand as copying the implicit operations of the instructio we're // looking at will give us the correct flags. if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 7fee5ff1bf8..855406330b9 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -521,7 +521,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return LowerPATCHPOINT(SM, *MI); case PPC::MoveGOTtoLR: { - // Transform %LR = MoveGOTtoLR + // Transform %lr = MoveGOTtoLR // Into this: bl _GLOBAL_OFFSET_TABLE_@local-4 // _GLOBAL_OFFSET_TABLE_@local-4 (instruction preceding // _GLOBAL_OFFSET_TABLE_) has exactly one instruction: @@ -542,7 +542,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case PPC::MovePCtoLR: case PPC::MovePCtoLR8: { - // Transform %LR = MovePCtoLR + // Transform %lr = MovePCtoLR // Into this, where the label is the PIC base: // bl L1$pb // L1$pb: @@ -560,9 +560,9 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::UpdateGBR: { - // Transform %Rd = UpdateGBR(%Rt, %Ri) - // Into: lwz %Rt, .L0$poff - .L0$pb(%Ri) - // add %Rd, %Rt, %Ri + // Transform %rd = UpdateGBR(%rt, %ri) + // Into: lwz %rt, .L0$poff - .L0$pb(%ri) + // add %rd, %rt, %ri // Get the offset from the GOT Base Register to the GOT LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); MCSymbol *PICOffset = @@ -577,7 +577,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MCOperand TR = TmpInst.getOperand(1); const MCOperand PICR = TmpInst.getOperand(0); - // Step 1: lwz %Rt, .L$poff - .L$pb(%Ri) + // Step 1: lwz %rt, .L$poff - .L$pb(%ri) TmpInst.getOperand(1) = MCOperand::createExpr(MCBinaryExpr::createSub(Exp, PB, OutContext)); TmpInst.getOperand(0) = TR; @@ -592,7 +592,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::LWZtoc: { - // Transform %R3 = LWZtoc <ga:@min1>, %R2 + // Transform %r3 = LWZtoc <ga:@min1>, %r2 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LWZ, and the global address operand to be a @@ -636,7 +636,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { case PPC::LDtocCPT: case PPC::LDtocBA: case PPC::LDtoc: { - // Transform %X3 = LDtoc <ga:@min1>, %X2 + // Transform %x3 = LDtoc <ga:@min1>, %x2 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD, and the global address operand to be a @@ -667,7 +667,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case PPC::ADDIStocHA: { - // Transform %Xd = ADDIStocHA %X2, <ga:@sym> + // Transform %xd = ADDIStocHA %x2, <ga:@sym> LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to ADDIS8. If the global address is external, has @@ -714,7 +714,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::LDtocL: { - // Transform %Xd = LDtocL <ga:@sym>, %Xs + // Transform %xd = LDtocL <ga:@sym>, %xs LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD. If the global address is external, has @@ -757,7 +757,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDItocL: { - // Transform %Xd = ADDItocL %Xs, <ga:@sym> + // Transform %xd = ADDItocL %xs, <ga:@sym> LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to ADDI8. If the global address is external, then @@ -788,8 +788,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDISgotTprelHA: { - // Transform: %Xd = ADDISgotTprelHA %X2, <ga:@sym> - // Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha + // Transform: %xd = ADDISgotTprelHA %x2, <ga:@sym> + // Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC"); const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); @@ -805,7 +805,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case PPC::LDgotTprelL: case PPC::LDgotTprelL32: { - // Transform %Xd = LDgotTprelL <ga:@sym>, %Xs + // Transform %xd = LDgotTprelL <ga:@sym>, %xs LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD. @@ -866,8 +866,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDIStlsgdHA: { - // Transform: %Xd = ADDIStlsgdHA %X2, <ga:@sym> - // Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha + // Transform: %xd = ADDIStlsgdHA %x2, <ga:@sym> + // Into: %xd = ADDIS8 %x2, sym@got@tlsgd@ha assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC"); const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); @@ -882,11 +882,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDItlsgdL: - // Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym> - // Into: %Xd = ADDI8 %Xs, sym@got@tlsgd@l + // Transform: %xd = ADDItlsgdL %xs, <ga:@sym> + // Into: %xd = ADDI8 %xs, sym@got@tlsgd@l case PPC::ADDItlsgdL32: { - // Transform: %Rd = ADDItlsgdL32 %Rs, <ga:@sym> - // Into: %Rd = ADDI %Rs, sym@got@tlsgd + // Transform: %rd = ADDItlsgdL32 %rs, <ga:@sym> + // Into: %rd = ADDI %rs, sym@got@tlsgd const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); MCSymbol *MOSymbol = getSymbol(GValue); @@ -902,17 +902,17 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::GETtlsADDR: - // Transform: %X3 = GETtlsADDR %X3, <ga:@sym> + // Transform: %x3 = GETtlsADDR %x3, <ga:@sym> // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd) case PPC::GETtlsADDR32: { - // Transform: %R3 = GETtlsADDR32 %R3, <ga:@sym> + // Transform: %r3 = GETtlsADDR32 %r3, <ga:@sym> // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD); return; } case PPC::ADDIStlsldHA: { - // Transform: %Xd = ADDIStlsldHA %X2, <ga:@sym> - // Into: %Xd = ADDIS8 %X2, sym@got@tlsld@ha + // Transform: %xd = ADDIStlsldHA %x2, <ga:@sym> + // Into: %xd = ADDIS8 %x2, sym@got@tlsld@ha assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC"); const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); @@ -927,11 +927,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDItlsldL: - // Transform: %Xd = ADDItlsldL %Xs, <ga:@sym> - // Into: %Xd = ADDI8 %Xs, sym@got@tlsld@l + // Transform: %xd = ADDItlsldL %xs, <ga:@sym> + // Into: %xd = ADDI8 %xs, sym@got@tlsld@l case PPC::ADDItlsldL32: { - // Transform: %Rd = ADDItlsldL32 %Rs, <ga:@sym> - // Into: %Rd = ADDI %Rs, sym@got@tlsld + // Transform: %rd = ADDItlsldL32 %rs, <ga:@sym> + // Into: %rd = ADDI %rs, sym@got@tlsld const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); MCSymbol *MOSymbol = getSymbol(GValue); @@ -947,20 +947,20 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::GETtlsldADDR: - // Transform: %X3 = GETtlsldADDR %X3, <ga:@sym> + // Transform: %x3 = GETtlsldADDR %x3, <ga:@sym> // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld) case PPC::GETtlsldADDR32: { - // Transform: %R3 = GETtlsldADDR32 %R3, <ga:@sym> + // Transform: %r3 = GETtlsldADDR32 %r3, <ga:@sym> // Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD); return; } case PPC::ADDISdtprelHA: - // Transform: %Xd = ADDISdtprelHA %Xs, <ga:@sym> - // Into: %Xd = ADDIS8 %Xs, sym@dtprel@ha + // Transform: %xd = ADDISdtprelHA %xs, <ga:@sym> + // Into: %xd = ADDIS8 %xs, sym@dtprel@ha case PPC::ADDISdtprelHA32: { - // Transform: %Rd = ADDISdtprelHA32 %Rs, <ga:@sym> - // Into: %Rd = ADDIS %Rs, sym@dtprel@ha + // Transform: %rd = ADDISdtprelHA32 %rs, <ga:@sym> + // Into: %rd = ADDIS %rs, sym@dtprel@ha const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); MCSymbol *MOSymbol = getSymbol(GValue); @@ -976,11 +976,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } case PPC::ADDIdtprelL: - // Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym> - // Into: %Xd = ADDI8 %Xs, sym@dtprel@l + // Transform: %xd = ADDIdtprelL %xs, <ga:@sym> + // Into: %xd = ADDI8 %xs, sym@dtprel@l case PPC::ADDIdtprelL32: { - // Transform: %Rd = ADDIdtprelL32 %Rs, <ga:@sym> - // Into: %Rd = ADDI %Rs, sym@dtprel@l + // Transform: %rd = ADDIdtprelL32 %rs, <ga:@sym> + // Into: %rd = ADDI %rs, sym@dtprel@l const MachineOperand &MO = MI->getOperand(2); const GlobalValue *GValue = MO.getGlobal(); MCSymbol *MOSymbol = getSymbol(GValue); @@ -997,8 +997,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { case PPC::MFOCRF: case PPC::MFOCRF8: if (!Subtarget->hasMFOCRF()) { - // Transform: %R3 = MFOCRF %CR7 - // Into: %R3 = MFCR ;; cr7 + // Transform: %r3 = MFOCRF %cr7 + // Into: %r3 = MFCR ;; cr7 unsigned NewOpcode = MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; OutStreamer->AddComment(PPCInstPrinter:: @@ -1011,8 +1011,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { case PPC::MTOCRF: case PPC::MTOCRF8: if (!Subtarget->hasMFOCRF()) { - // Transform: %CR7 = MTOCRF %R3 - // Into: MTCRF mask, %R3 ;; cr7 + // Transform: %cr7 = MTOCRF %r3 + // Into: MTCRF mask, %r3 ;; cr7 unsigned NewOpcode = MI->getOpcode() == PPC::MTOCRF ? PPC::MTCRF : PPC::MTCRF8; unsigned Mask = 0x80 >> OutContext.getRegisterInfo() diff --git a/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/lib/Target/PowerPC/PPCBranchCoalescing.cpp index 6e1cd1323e6..2af1913db55 100644 --- a/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -60,11 +60,11 @@ namespace llvm { /// expands to the following machine code: /// /// BB#0: derived from LLVM BB %entry -/// Live Ins: %F1 %F3 %X6 +/// Live Ins: %f1 %f3 %x6 /// <SNIP1> -/// %vreg0<def> = COPY %F1; F8RC:%vreg0 +/// %vreg0<def> = COPY %f1; F8RC:%vreg0 /// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>; +/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>; /// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 /// BCC 76, %vreg5, <BB#2>; CRRC:%vreg5 /// Successors according to CFG: BB#1(?%) BB#2(?%) @@ -90,7 +90,7 @@ namespace llvm { /// %vreg13<def> = PHI %vreg12, <BB#3>, %vreg2, <BB#2>; /// F8RC:%vreg13,%vreg12,%vreg2 /// <SNIP3> -/// BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use> +/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use> /// /// When this pattern is detected, branch coalescing will try to collapse /// it by moving code in BB#2 to BB#0 and/or BB#4 and removing BB#3. @@ -98,11 +98,11 @@ namespace llvm { /// If all conditions are meet, IR should collapse to: /// /// BB#0: derived from LLVM BB %entry -/// Live Ins: %F1 %F3 %X6 +/// Live Ins: %f1 %f3 %x6 /// <SNIP1> -/// %vreg0<def> = COPY %F1; F8RC:%vreg0 +/// %vreg0<def> = COPY %f1; F8RC:%vreg0 /// %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4 -/// %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>; +/// %vreg8<def> = LXSDX %zero8, %vreg7<kill>, %rm<imp-use>; /// mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7 /// <SNIP2> /// BCC 76, %vreg5, <BB#4>; CRRC:%vreg5 @@ -120,7 +120,7 @@ namespace llvm { /// %vreg13<def> = PHI %vreg12, <BB#1>, %vreg2, <BB#0>; /// F8RC:%vreg13,%vreg12,%vreg2 /// <SNIP3> -/// BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use> +/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use> /// /// Branch Coalescing does not split blocks, it moves everything in the same /// direction ensuring it does not break use/definition semantics. diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp index f34c2cd4285..402e29cdff7 100644 --- a/lib/Target/PowerPC/PPCFastISel.cpp +++ b/lib/Target/PowerPC/PPCFastISel.cpp @@ -1991,9 +1991,9 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { // or externally available linkage, a non-local function address, or a // jump table address (not yet needed), or if we are generating code // for large code model, we generate: - // LDtocL(GV, ADDIStocHA(%X2, GV)) + // LDtocL(GV, ADDIStocHA(%x2, GV)) // Otherwise we generate: - // ADDItocL(ADDIStocHA(%X2, GV), GV) + // ADDItocL(ADDIStocHA(%x2, GV), GV) // Either way, start with the ADDIStocHA: unsigned HighPartReg = createResultReg(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA), diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 531b95a662e..6289765c6b8 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -3218,9 +3218,9 @@ void PPCDAGToDAGISel::Select(SDNode *N) { // The first source operand is a TargetGlobalAddress or a TargetJumpTable. // If it must be toc-referenced according to PPCSubTarget, we generate: - // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>)) + // LDtocL(<ga:@sym>, ADDIStocHA(%x2, <ga:@sym>)) // Otherwise we generate: - // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>) + // ADDItocL(ADDIStocHA(%x2, <ga:@sym>), <ga:@sym>) SDValue GA = N->getOperand(0); SDValue TOCbase = N->getOperand(1); SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64, diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 22dd56b3338..adf77fa0646 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -262,7 +262,7 @@ namespace llvm { /// local dynamic TLS on PPC32. PPC32_PICGOT, - /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec + /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec /// TLS model, produces an ADDIS8 instruction that adds the GOT /// base to sym\@got\@tprel\@ha. ADDIS_GOT_TPREL_HA, @@ -281,18 +281,18 @@ namespace llvm { /// TLS sequence. ADD_TLS, - /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS + /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS /// model, produces an ADDIS8 instruction that adds the GOT base /// register to sym\@got\@tlsgd\@ha. ADDIS_TLSGD_HA, - /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS + /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS /// model, produces an ADDI8 instruction that adds G8RReg to /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by /// ADDIS_TLSGD_L_ADDR until after register assignment. ADDI_TLSGD_L, - /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS + /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by /// ADDIS_TLSGD_L_ADDR until after register assignment. GET_TLS_ADDR, @@ -302,18 +302,18 @@ namespace llvm { /// register assignment. ADDI_TLSGD_L_ADDR, - /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS + /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS /// model, produces an ADDIS8 instruction that adds the GOT base /// register to sym\@got\@tlsld\@ha. ADDIS_TLSLD_HA, - /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS + /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS /// model, produces an ADDI8 instruction that adds G8RReg to /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by /// ADDIS_TLSLD_L_ADDR until after register assignment. ADDI_TLSLD_L, - /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS + /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by /// ADDIS_TLSLD_L_ADDR until after register assignment. GET_TLSLD_ADDR, @@ -323,7 +323,7 @@ namespace llvm { /// following register assignment. ADDI_TLSLD_L_ADDR, - /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS + /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS /// model, produces an ADDIS8 instruction that adds X3 to /// sym\@dtprel\@ha. ADDIS_DTPREL_HA, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index f25b929c808..a035ec621b6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2315,10 +2315,10 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, // For a method return value, we check the ZExt/SExt flags in attribute. // We assume the following code sequence for method call. - // ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use> + // ADJCALLSTACKDOWN 32, %r1<imp-def,dead>, %r1<imp-use> // BL8_NOP <ga:@func>,... - // ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use> - // %vreg5<def> = COPY %X3; G8RC:%vreg5 + // ADJCALLSTACKUP 32, 0, %r1<imp-def,dead>, %r1<imp-use> + // %vreg5<def> = COPY %x3; G8RC:%vreg5 if (SrcReg == PPC::X3) { const MachineBasicBlock *MBB = MI.getParent(); MachineBasicBlock::const_instr_iterator II = diff --git a/lib/Target/PowerPC/PPCQPXLoadSplat.cpp b/lib/Target/PowerPC/PPCQPXLoadSplat.cpp index bc8652393f4..10394166ddf 100644 --- a/lib/Target/PowerPC/PPCQPXLoadSplat.cpp +++ b/lib/Target/PowerPC/PPCQPXLoadSplat.cpp @@ -79,8 +79,8 @@ bool PPCQPXLoadSplat::runOnMachineFunction(MachineFunction &MF) { } // We're looking for a sequence like this: - // %F0<def> = LFD 0, %X3<kill>, %QF0<imp-def>; mem:LD8[%a](tbaa=!2) - // %QF1<def> = QVESPLATI %QF0<kill>, 0, %RM<imp-use> + // %f0<def> = LFD 0, %x3<kill>, %qf0<imp-def>; mem:LD8[%a](tbaa=!2) + // %qf1<def> = QVESPLATI %qf0<kill>, 0, %rm<imp-use> for (auto SI = Splats.begin(); SI != Splats.end();) { MachineInstr *SMI = *SI; diff --git a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp index a57484e5abd..80b63b1c9df 100644 --- a/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -92,18 +92,18 @@ protected: // ... // %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, - // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 + // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 // ... // %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19, - // %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19 + // %rm<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19 // ... // Where we can eliminate the copy by changing from the A-type to the // M-type instruction. Specifically, for this example, this means: // %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16, - // %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 + // %rm<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16 // is replaced by: // %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9, - // %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9 + // %rm<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9 // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9 SlotIndex FMAIdx = LIS->getInstructionIndex(MI); @@ -150,7 +150,7 @@ protected: // walking the MIs we may as well test liveness here. // // FIXME: There is a case that occurs in practice, like this: - // %vreg9<def> = COPY %F1; VSSRC:%vreg9 + // %vreg9<def> = COPY %f1; VSSRC:%vreg9 // ... // %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9 // %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9 diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index c07cc213c3e..9864aa37235 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -306,8 +306,8 @@ bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const return !(MFI.hasCalls() // has calls || MRI.isPhysRegUsed(SP::L0) // Too many registers needed - || MRI.isPhysRegUsed(SP::O6) // %SP is used - || hasFP(MF)); // need %FP + || MRI.isPhysRegUsed(SP::O6) // %sp is used + || hasFP(MF)); // need %fp } void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const { diff --git a/lib/Target/SystemZ/SystemZElimCompare.cpp b/lib/Target/SystemZ/SystemZElimCompare.cpp index 449c2f8cb78..8009341eab7 100644 --- a/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -436,8 +436,8 @@ bool SystemZElimCompare::optimizeCompareZero( // Also do a forward search to handle cases where an instruction after the // compare can be converted like // - // LTEBRCompare %F0S, %F0S, %CC<imp-def> LTEBRCompare %F0S, %F0S, %CC<imp-def> - // %F2S<def> = LER %F0S + // LTEBRCompare %f0s, %f0s, %cc<imp-def> LTEBRCompare %f0s, %f0s, %cc<imp-def> + // %f2s<def> = LER %f0s // MBBI = Compare, MBBE = MBB.end(); while (++MBBI != MBBE) { diff --git a/lib/Target/X86/README-SSE.txt b/lib/Target/X86/README-SSE.txt index e6896e80556..ffc404d5e33 100644 --- a/lib/Target/X86/README-SSE.txt +++ b/lib/Target/X86/README-SSE.txt @@ -145,15 +145,15 @@ This is the llvm code after instruction scheduling: cond_next140 (0xa910740, LLVM BB @0xa90beb0): %reg1078 = MOV32ri -3 - %reg1079 = ADD32rm %reg1078, %reg1068, 1, %NOREG, 0 - %reg1037 = MOV32rm %reg1024, 1, %NOREG, 40 + %reg1079 = ADD32rm %reg1078, %reg1068, 1, %noreg, 0 + %reg1037 = MOV32rm %reg1024, 1, %noreg, 40 %reg1080 = IMUL32rr %reg1079, %reg1037 - %reg1081 = MOV32rm %reg1058, 1, %NOREG, 0 + %reg1081 = MOV32rm %reg1058, 1, %noreg, 0 %reg1038 = LEA32r %reg1081, 1, %reg1080, -3 - %reg1036 = MOV32rm %reg1024, 1, %NOREG, 32 + %reg1036 = MOV32rm %reg1024, 1, %noreg, 32 %reg1082 = SHL32ri %reg1038, 4 %reg1039 = ADD32rr %reg1036, %reg1082 - %reg1083 = MOVAPSrm %reg1059, 1, %NOREG, 0 + %reg1083 = MOVAPSrm %reg1059, 1, %noreg, 0 %reg1034 = SHUFPSrr %reg1083, %reg1083, 170 %reg1032 = SHUFPSrr %reg1083, %reg1083, 0 %reg1035 = SHUFPSrr %reg1083, %reg1083, 255 @@ -166,32 +166,32 @@ cond_next140 (0xa910740, LLVM BB @0xa90beb0): Still ok. After register allocation: cond_next140 (0xa910740, LLVM BB @0xa90beb0): - %EAX = MOV32ri -3 - %EDX = MOV32rm <fi#3>, 1, %NOREG, 0 - ADD32rm %EAX<def&use>, %EDX, 1, %NOREG, 0 - %EDX = MOV32rm <fi#7>, 1, %NOREG, 0 - %EDX = MOV32rm %EDX, 1, %NOREG, 40 - IMUL32rr %EAX<def&use>, %EDX - %ESI = MOV32rm <fi#5>, 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 0 - MOV32mr <fi#4>, 1, %NOREG, 0, %ESI - %EAX = LEA32r %ESI, 1, %EAX, -3 - %ESI = MOV32rm <fi#7>, 1, %NOREG, 0 - %ESI = MOV32rm %ESI, 1, %NOREG, 32 - %EDI = MOV32rr %EAX - SHL32ri %EDI<def&use>, 4 - ADD32rr %EDI<def&use>, %ESI - %XMM0 = MOVAPSrm %ECX, 1, %NOREG, 0 - %XMM1 = MOVAPSrr %XMM0 - SHUFPSrr %XMM1<def&use>, %XMM1, 170 - %XMM2 = MOVAPSrr %XMM0 - SHUFPSrr %XMM2<def&use>, %XMM2, 0 - %XMM3 = MOVAPSrr %XMM0 - SHUFPSrr %XMM3<def&use>, %XMM3, 255 - SHUFPSrr %XMM0<def&use>, %XMM0, 85 - %EBX = MOV32rr %EDI - AND32ri8 %EBX<def&use>, 15 - CMP32ri8 %EBX, 0 + %eax = MOV32ri -3 + %edx = MOV32rm <fi#3>, 1, %noreg, 0 + ADD32rm %eax<def&use>, %edx, 1, %noreg, 0 + %edx = MOV32rm <fi#7>, 1, %noreg, 0 + %edx = MOV32rm %edx, 1, %noreg, 40 + IMUL32rr %eax<def&use>, %edx + %esi = MOV32rm <fi#5>, 1, %noreg, 0 + %esi = MOV32rm %esi, 1, %noreg, 0 + MOV32mr <fi#4>, 1, %noreg, 0, %esi + %eax = LEA32r %esi, 1, %eax, -3 + %esi = MOV32rm <fi#7>, 1, %noreg, 0 + %esi = MOV32rm %esi, 1, %noreg, 32 + %edi = MOV32rr %eax + SHL32ri %edi<def&use>, 4 + ADD32rr %edi<def&use>, %esi + %xmm0 = MOVAPSrm %ecx, 1, %noreg, 0 + %xmm1 = MOVAPSrr %xmm0 + SHUFPSrr %xmm1<def&use>, %xmm1, 170 + %xmm2 = MOVAPSrr %xmm0 + SHUFPSrr %xmm2<def&use>, %xmm2, 0 + %xmm3 = MOVAPSrr %xmm0 + SHUFPSrr %xmm3<def&use>, %xmm3, 255 + SHUFPSrr %xmm0<def&use>, %xmm0, 85 + %ebx = MOV32rr %edi + AND32ri8 %ebx<def&use>, 15 + CMP32ri8 %ebx, 0 JE mbb<cond_next204,0xa914d30> This looks really bad. The problem is shufps is a destructive opcode. Since it diff --git a/lib/Target/X86/README-X86-64.txt b/lib/Target/X86/README-X86-64.txt index 09626e13849..13856486b14 100644 --- a/lib/Target/X86/README-X86-64.txt +++ b/lib/Target/X86/README-X86-64.txt @@ -103,13 +103,13 @@ LBB1_3: ## bb Before regalloc, we have: - %reg1025<def> = IMUL32rri8 %reg1024, 45, %EFLAGS<imp-def> + %reg1025<def> = IMUL32rri8 %reg1024, 45, %eflags<imp-def> JMP mbb<bb2,0x203afb0> Successors according to CFG: 0x203afb0 (#3) bb1: 0x203af60, LLVM BB @0x1e02310, ID#2: Predecessors according to CFG: 0x203aec0 (#0) - %reg1026<def> = IMUL32rri8 %reg1024, 78, %EFLAGS<imp-def> + %reg1026<def> = IMUL32rri8 %reg1024, 78, %eflags<imp-def> Successors according to CFG: 0x203afb0 (#3) bb2: 0x203afb0, LLVM BB @0x1e02340, ID#3: diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td index 2de9a5fbfe9..5d806fe60b8 100644 --- a/lib/Target/X86/X86CallingConv.td +++ b/lib/Target/X86/X86CallingConv.td @@ -500,7 +500,7 @@ def CC_X86_64_C : CallingConv<[ // A SwiftError is passed in R12. CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, - // For Swift Calling Convention, pass sret in %RAX. + // For Swift Calling Convention, pass sret in %rax. CCIfCC<"CallingConv::Swift", CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 9ea7590ce3a..03be87e467a 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1976,9 +1976,9 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { // Generate the DIV/IDIV instruction. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); - // For i8 remainder, we can't reference AH directly, as we'll end - // up with bogus copies like %R9B = COPY %AH. Reference AX - // instead to prevent AH references in a REX instruction. + // For i8 remainder, we can't reference ah directly, as we'll end + // up with bogus copies like %r9b = COPY %ah. Reference ax + // instead to prevent ah references in a rex instruction. // // The current assumption of the fast register allocator is that isel // won't generate explicit references to the GR8_NOREX registers. If diff --git a/lib/Target/X86/X86FixupBWInsts.cpp b/lib/Target/X86/X86FixupBWInsts.cpp index 9664c931c35..ce559323efc 100644 --- a/lib/Target/X86/X86FixupBWInsts.cpp +++ b/lib/Target/X86/X86FixupBWInsts.cpp @@ -189,17 +189,17 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) { /// So, it handles pattern like this: /// /// BB#2: derived from LLVM BB %if.then -/// Live Ins: %RDI +/// Live Ins: %rdi /// Predecessors according to CFG: BB#0 -/// %AX<def> = MOV16rm %RDI<kill>, 1, %noreg, 0, %noreg, %EAX<imp-def>; mem:LD2[%p] -/// No %EAX<imp-use> +/// %ax<def> = MOV16rm %rdi<kill>, 1, %noreg, 0, %noreg, %eax<imp-def>; mem:LD2[%p] +/// No %eax<imp-use> /// Successors according to CFG: BB#3(?%) /// /// BB#3: derived from LLVM BB %if.end -/// Live Ins: %EAX Only %AX is actually live +/// Live Ins: %eax Only %ax is actually live /// Predecessors according to CFG: BB#2 BB#1 -/// %AX<def> = KILL %AX, %EAX<imp-use,kill> -/// RET 0, %AX +/// %ax<def> = KILL %ax, %eax<imp-use,kill> +/// RET 0, %ax static bool isLive(const MachineInstr &MI, const LivePhysRegs &LiveRegs, const TargetRegisterInfo *TRI, diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index d43f7a15409..6db02f0bd05 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -516,7 +516,7 @@ void FPS::setupBlockStack() { // Push the fixed live-in registers. for (unsigned i = Bundle.FixCount; i > 0; --i) { - DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP" + DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %fp" << unsigned(Bundle.FixStack[i-1]) << '\n'); pushReg(Bundle.FixStack[i-1]); } @@ -893,7 +893,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { while (Kills && Defs) { unsigned KReg = countTrailingZeros(Kills); unsigned DReg = countTrailingZeros(Defs); - DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); + DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg << "\n"); std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); std::swap(RegMap[KReg], RegMap[DReg]); Kills &= ~(1 << KReg); @@ -907,7 +907,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { unsigned KReg = getStackEntry(0); if (!(Kills & (1 << KReg))) break; - DEBUG(dbgs() << "Popping %FP" << KReg << "\n"); + DEBUG(dbgs() << "Popping %fp" << KReg << "\n"); popStackAfter(I2); Kills &= ~(1 << KReg); } @@ -916,7 +916,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { // Manually kill the rest. while (Kills) { unsigned KReg = countTrailingZeros(Kills); - DEBUG(dbgs() << "Killing %FP" << KReg << "\n"); + DEBUG(dbgs() << "Killing %fp" << KReg << "\n"); freeStackSlotBefore(I, KReg); Kills &= ~(1 << KReg); } @@ -924,7 +924,7 @@ void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { // Load zeros for all the imp-defs. while(Defs) { unsigned DReg = countTrailingZeros(Defs); - DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); + DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); pushReg(DReg); Defs &= ~(1 << DReg); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index bd8d447fb88..c1414a1baa5 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -10879,7 +10879,7 @@ X86InstrInfo::getOutliningType(MachineInstr &MI) const { // FIXME: There are instructions which are being manually built without // explicit uses/defs so we also have to check the MCInstrDesc. We should be // able to remove the extra checks once those are fixed up. For example, - // sometimes we might get something like %RAX<def> = POP64r 1. This won't be + // sometimes we might get something like %rax<def> = POP64r 1. This won't be // caught by modifiesRegister or readsRegister even though the instruction // really ought to be formed so that modifiesRegister/readsRegister would // catch it. diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index a0a34056bf5..f537dc18909 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -961,7 +961,7 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, // This is an optimization that lets us get away without emitting a nop in // many cases. // - // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two + // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two // bytes too, so the check on MinSize is important. MCI.setOpcode(X86::PUSH64rmr); } else { diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll index 29b71e04261..3ad9442b674 100644 --- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll +++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll @@ -296,7 +296,7 @@ declare double @hh(double) #1 ; Check that we correctly deal with repeated operands. ; The following testcase creates: -; %D1<def> = FADDDrr %D0<kill>, %D0 +; %d1<def> = FADDDrr %d0<kill>, %d0 ; We'll get a crash if we naively look at the first operand, remove it ; from the substitution list then look at the second operand. diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll index ef8d6f3b4ef..a21b6f2b0d9 100644 --- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll +++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-ios -verify-machineinstrs | FileCheck %s ; LdStOpt bug created illegal instruction: -; %D1<def>, %D2<def> = LDPSi %X0, 1 +; %d1<def>, %d2<def> = LDPSi %x0, 1 ; rdar://11512047 %0 = type opaque diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll index 37cc5411aa3..b0059193d34 100644 --- a/test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -10,8 +10,8 @@ ; ; CHECK: Before post-MI-sched: ; CHECK-LABEL: # Machine code for function test1: -; CHECK: SU(2): STRWui %WZR -; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP +; CHECK: SU(2): STRWui %wzr +; CHECK: SU(3): %x21<def>, %x20<def> = LDPXi %sp ; CHECK: Predecessors: ; CHECK-NEXT: SU(0): Out ; CHECK-NEXT: SU(0): Out diff --git a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll index 1bbcf50ba73..03d05429308 100644 --- a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll +++ b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll @@ -3,7 +3,7 @@ ; Check that the dead register definition pass is considering implicit defs. ; When rematerializing through truncates, the coalescer may produce instructions ; with dead defs, but live implicit-defs of subregs: -; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32 +; E.g. %x1<def, dead> = MOVi64imm 2, %w1<imp-def>; %x1:GPR64, %w1:GPR32 ; These instructions are live, and their definitions should not be rewritten. ; ; <rdar://problem/16492408> diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 9cbf0cb3803..1b102e63569 100644 --- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -9,11 +9,11 @@ ; CHECK: Successors: ; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2 ; CHECK-NEXT: SU(4): Ord Latency=0 -; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 +; CHECK: SU(3): STRWui %wzr, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 ; CHECK: Successors: ; CHECK: SU(4): Ord Latency=0 -; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 -; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2 +; CHECK: SU(4): STRWui %wzr, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 +; CHECK: SU(5): %w0<def> = COPY %vreg2; GPR32:%vreg2 ; CHECK: ** ScheduleDAGMI::schedule picking next node define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { entry: diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll index 75f45da0e48..9d92f96a208 100644 --- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll +++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -8,11 +8,11 @@ ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. ; ; CHECK-LABEL: # Machine code for function foo: -; CHECK: SU(2): %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi +; CHECK: SU(2): %w{{[0-9]+}}<def>, %w{{[0-9]+}}<def> = LDPWi ; CHECK: Successors: ; CHECK-NOT: ch SU(4) ; CHECK: SU(3) -; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} +; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}} define i32 @foo() { entry: %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 diff --git a/test/CodeGen/AArch64/loh.mir b/test/CodeGen/AArch64/loh.mir index 6e4bb5cfaee..001e7755829 100644 --- a/test/CodeGen/AArch64/loh.mir +++ b/test/CodeGen/AArch64/loh.mir @@ -22,14 +22,14 @@ tracksRegLiveness: true body: | bb.0: ; CHECK: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3> - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4> + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4> ; CHECK-NEXT: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g2> - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g2> + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3> ; CHECK-NEXT: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %X0<def> = ADRP <ga:@g0> - ; CHECK-NEXT: %X0<def> = ADRP <ga:@g1> + ; CHECK-NEXT: %x0<def> = ADRP <ga:@g0> + ; CHECK-NEXT: %x0<def> = ADRP <ga:@g1> %x0 = ADRP target-flags(aarch64-page) @g0 %x0 = ADRP target-flags(aarch64-page) @g1 %x1 = ADRP target-flags(aarch64-page) @g2 @@ -38,11 +38,11 @@ body: | bb.1: ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %X20<def> = ADRP <ga:@g0> - ; CHECK-NEXT: %X3<def> = ADDXri %X20, <ga:@g0> + ; CHECK-NEXT: %x20<def> = ADRP <ga:@g0> + ; CHECK-NEXT: %x3<def> = ADDXri %x20, <ga:@g0> ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g0> - ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g0> + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g0> + ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g0> %x1 = ADRP target-flags(aarch64-page) @g0 %x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0 @@ -73,11 +73,11 @@ body: | bb.5: ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2> - ; CHECK-NEXT: %S6<def> = LDRSui %X5, <ga:@g2> + ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2> + ; CHECK-NEXT: %s6<def> = LDRSui %x5, <ga:@g2> ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2> - ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2> + ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2> + ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2> %x4 = ADRP target-flags(aarch64-page) @g2 %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2 %x5 = ADRP target-flags(aarch64-page) @g2 @@ -85,11 +85,11 @@ body: | bb.6: ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot: - ; CHECK-NEXT: %X5<def> = ADRP <ga:@g2> - ; CHECK-NEXT: %X6<def> = LDRXui %X5, <ga:@g2> + ; CHECK-NEXT: %x5<def> = ADRP <ga:@g2> + ; CHECK-NEXT: %x6<def> = LDRXui %x5, <ga:@g2> ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot: - ; CHECK-NEXT: %X4<def> = ADRP <ga:@g2> - ; CHECK-NEXT: %X4<def> = LDRXui %X4, <ga:@g2> + ; CHECK-NEXT: %x4<def> = ADRP <ga:@g2> + ; CHECK-NEXT: %x4<def> = LDRXui %x4, <ga:@g2> %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2 %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2 %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2 @@ -104,24 +104,24 @@ body: | bb.8: ; CHECK-NEXT: Adding MCLOH_AdrpAddLdr: - ; CHECK-NEXT: %X7<def> = ADRP <ga:@g3>[TF=1] - ; CHECK-NEXT: %X8<def> = ADDXri %X7, <ga:@g3> - ; CHECK-NEXT: %D1<def> = LDRDui %X8, 8 + ; CHECK-NEXT: %x7<def> = ADRP <ga:@g3>[TF=1] + ; CHECK-NEXT: %x8<def> = ADDXri %x7, <ga:@g3> + ; CHECK-NEXT: %d1<def> = LDRDui %x8, 8 %x7 = ADRP target-flags(aarch64-page) @g3 %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0 %d1 = LDRDui %x8, 8 bb.9: ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %X3<def> = ADRP <ga:@g3> - ; CHECK-NEXT: %X3<def> = ADDXri %X3, <ga:@g3> + ; CHECK-NEXT: %x3<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x3<def> = ADDXri %x3, <ga:@g3> ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %X5<def> = ADRP <ga:@g3> - ; CHECK-NEXT: %X2<def> = ADDXri %X5, <ga:@g3> + ; CHECK-NEXT: %x5<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x2<def> = ADDXri %x5, <ga:@g3> ; CHECK-NEXT: Adding MCLOH_AdrpAddStr: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g3> - ; CHECK-NEXT: %X1<def> = ADDXri %X1, <ga:@g3> - ; CHECK-NEXT: STRXui %XZR, %X1, 16 + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x1<def> = ADDXri %x1, <ga:@g3> + ; CHECK-NEXT: STRXui %xzr, %x1, 16 %x1 = ADRP target-flags(aarch64-page) @g3 %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0 STRXui %xzr, %x1, 16 @@ -138,12 +138,12 @@ body: | bb.10: ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %X2<def> = ADRP <ga:@g3> - ; CHECK-NEXT: %X2<def> = LDRXui %X2, <ga:@g3> + ; CHECK-NEXT: %x2<def> = ADRP <ga:@g3> + ; CHECK-NEXT: %x2<def> = LDRXui %x2, <ga:@g3> ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4> - ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4> - ; CHECK-NEXT: %X1<def> = LDRXui %X1, 24 + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4> + ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4> + ; CHECK-NEXT: %x1<def> = LDRXui %x1, 24 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4 %x1 = LDRXui %x1, 24 @@ -154,12 +154,12 @@ body: | bb.11: ; CHECK-NEXT: Adding MCLOH_AdrpLdr - ; CHECK-NEXT: %X5<def> = ADRP <ga:@g1> - ; CHECK-NEXT: %X5<def> = LDRXui %X5, <ga:@g1> + ; CHECK-NEXT: %x5<def> = ADRP <ga:@g1> + ; CHECK-NEXT: %x5<def> = LDRXui %x5, <ga:@g1> ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr: - ; CHECK-NEXT: %X1<def> = ADRP <ga:@g4> - ; CHECK-NEXT: %X1<def> = LDRXui %X1, <ga:@g4> - ; CHECK-NEXT: STRXui %XZR, %X1, 32 + ; CHECK-NEXT: %x1<def> = ADRP <ga:@g4> + ; CHECK-NEXT: %x1<def> = LDRXui %x1, <ga:@g4> + ; CHECK-NEXT: STRXui %xzr, %x1, 32 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4 STRXui %xzr, %x1, 32 @@ -171,9 +171,9 @@ body: | bb.12: ; CHECK-NOT: MCLOH_AdrpAdrp ; CHECK: Adding MCLOH_AdrpAddLdr - ; %X9<def> = ADRP <ga:@g4> - ; %X9<def> = ADDXri %X9, <ga:@g4> - ; %X5<def> = LDRXui %X9, 0 + ; %x9<def> = ADRP <ga:@g4> + ; %x9<def> = ADDXri %x9, <ga:@g4> + ; %x5<def> = LDRXui %x9, 0 %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0 %x5 = LDRXui %x9, 0 diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll index 6bacf852907..ed0955ccf48 100644 --- a/test/CodeGen/AArch64/machine-copy-prop.ll +++ b/test/CodeGen/AArch64/machine-copy-prop.ll @@ -2,12 +2,12 @@ ; This file check a bug in MachineCopyPropagation pass. The last COPY will be ; incorrectly removed if the machine instructions are as follows: -; %Q5_Q6<def> = COPY %Q2_Q3 -; %D5<def> = -; %D3<def> = -; %D3<def> = COPY %D6 +; %q5_q6<def> = COPY %q2_q3 +; %d5<def> = +; %d3<def> = +; %d3<def> = COPY %d6 ; This is caused by a bug in function SourceNoLongerAvailable(), which fails to -; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3". +; remove the relationship of D6 and "%q5_q6<def> = COPY %q2_q3". @failed = internal unnamed_addr global i1 false diff --git a/test/CodeGen/AArch64/phi-dbg.ll b/test/CodeGen/AArch64/phi-dbg.ll index a1adf0f50d9..80bc885afa5 100644 --- a/test/CodeGen/AArch64/phi-dbg.ll +++ b/test/CodeGen/AArch64/phi-dbg.ll @@ -30,7 +30,7 @@ define i32 @func(i32) #0 !dbg !8 { ; CHECK: ldr w[[REG:[0-9]+]], [sp, #8] ; CHECK-NEXT: .Ltmp call void @llvm.dbg.value(metadata i32 %.0, i64 0, metadata !15, metadata !13), !dbg !16 -; CHECK-NEXT: //DEBUG_VALUE: func:c <- %W[[REG]] +; CHECK-NEXT: //DEBUG_VALUE: func:c <- %w[[REG]] %5 = add nsw i32 %.0, %0, !dbg !22 call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !15, metadata !13), !dbg !16 ret i32 %5, !dbg !23 diff --git a/test/CodeGen/AArch64/scheduledag-constreg.mir b/test/CodeGen/AArch64/scheduledag-constreg.mir index 6b83dc715e0..1f97fe1360c 100644 --- a/test/CodeGen/AArch64/scheduledag-constreg.mir +++ b/test/CodeGen/AArch64/scheduledag-constreg.mir @@ -7,16 +7,16 @@ # Check that the instructions are not dependent on each other, even though # they all read/write to the zero register. # CHECK-LABEL: MI Scheduling -# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead> +# CHECK: SU(0): %wzr<def,dead> = SUBSWri %w1, 0, 0, %nzcv<imp-def,dead> # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(1): %W2<def> = COPY %WZR +# CHECK: SU(1): %w2<def> = COPY %wzr # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead> +# CHECK: SU(2): %wzr<def,dead> = SUBSWri %w3, 0, 0, %nzcv<imp-def,dead> # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(3): %W4<def> = COPY %WZR +# CHECK: SU(3): %w4<def> = COPY %wzr # CHECK: # succs left : 0 # CHECK-NOT: Successors: name: func diff --git a/test/CodeGen/AMDGPU/lds-output-queue.ll b/test/CodeGen/AMDGPU/lds-output-queue.ll index 8b7e9e6d6aa..e5df12a1e5a 100644 --- a/test/CodeGen/AMDGPU/lds-output-queue.ll +++ b/test/CodeGen/AMDGPU/lds-output-queue.ll @@ -45,20 +45,20 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; %2 = load i32, i32 addrspace(1)* %in ; ; The instruction selection phase will generate ISA that looks like this: -; %OQAP = LDS_READ_RET -; %vreg0 = MOV %OQAP +; %oqap = LDS_READ_RET +; %vreg0 = MOV %oqap ; %vreg1 = VTX_READ_32 ; %vreg2 = ADD_INT %vreg1, %vreg0 ; ; The bottom scheduler will schedule the two ALU instructions first: ; ; UNSCHEDULED: -; %OQAP = LDS_READ_RET +; %oqap = LDS_READ_RET ; %vreg1 = VTX_READ_32 ; ; SCHEDULED: ; -; vreg0 = MOV %OQAP +; vreg0 = MOV %oqap ; vreg2 = ADD_INT %vreg1, %vreg2 ; ; The lack of proper aliasing results in the local memory read (LDS_READ_RET) @@ -67,14 +67,14 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; final program which looks like this: ; ; Alu clause: -; %OQAP = LDS_READ_RET +; %oqap = LDS_READ_RET ; VTX clause: ; %vreg1 = VTX_READ_32 ; Alu clause: -; vreg0 = MOV %OQAP +; vreg0 = MOV %oqap ; vreg2 = ADD_INT %vreg1, %vreg2 ; -; This is an illegal program because the OQAP def and use know occur in +; This is an illegal program because the oqap def and use know occur in ; different ALU clauses. ; ; This test checks this scenario and makes sure it doesn't result in an diff --git a/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/test/CodeGen/AMDGPU/llvm.dbg.value.ll index c4a76de5989..8105fd44da9 100644 --- a/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -4,7 +4,7 @@ ; CHECK: s_load_dwordx2 s[4:5] ; FIXME: Why is the SGPR4_SGPR5 reference being removed from DBG_VALUE? -; CHECK: ; kill: %SGPR4_SGPR5<def> %SGPR4_SGPR5<kill> +; CHECK: ; kill: %sgpr4_sgpr5<def> %sgpr4_sgpr5<kill> ; CHECK-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- undef ; CHECK: buffer_store_dword diff --git a/test/CodeGen/AMDGPU/schedule-regpressure.mir b/test/CodeGen/AMDGPU/schedule-regpressure.mir index 3a20ec732e5..9d798a50c08 100644 --- a/test/CodeGen/AMDGPU/schedule-regpressure.mir +++ b/test/CodeGen/AMDGPU/schedule-regpressure.mir @@ -4,7 +4,7 @@ # Check there is no SReg_32 pressure created by DS_* instructions because of M0 use # CHECK: ScheduleDAGMILive::schedule starting -# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %M0<imp-use>, %EXEC<imp-use> +# CHECK: SU({{.*}} = DS_READ_B32 {{.*}} %m0<imp-use>, %exec<imp-use> # CHECK: Pressure Diff : {{$}} # CHECK: SU({{.*}} DS_WRITE_B32 diff --git a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index be87a2fb1c8..bb6f83c12fa 100644 --- a/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -4,7 +4,7 @@ define void @vst(i8* %m, [4 x i64] %v) { entry: ; CHECK: vst: -; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill> +; CHECK: VST1d64Q %r{{[0-9]+}}<kill>, 8, %d{{[0-9]+}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use,kill> %v0 = extractvalue [4 x i64] %v, 0 %v1 = extractvalue [4 x i64] %v, 1 @@ -37,7 +37,7 @@ entry: %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { ; CHECK: vtbx4: -; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use> +; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %q{{[0-9]+}}_q{{[0-9]+}}<imp-use> %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 diff --git a/test/CodeGen/ARM/Windows/vla-cpsr.ll b/test/CodeGen/ARM/Windows/vla-cpsr.ll index de0f0b68a4d..1eb2797ca2e 100644 --- a/test/CodeGen/ARM/Windows/vla-cpsr.ll +++ b/test/CodeGen/ARM/Windows/vla-cpsr.ll @@ -9,5 +9,5 @@ entry: ret void } -; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def>, %SP<imp-use>, %R4<imp-use,kill>, %R4<imp-def>, %R12<imp-def,dead>, %CPSR<imp-def,dead> +; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %lr<imp-def>, %sp<imp-use>, %r4<imp-use,kill>, %r4<imp-def>, %r12<imp-def,dead>, %cpsr<imp-def,dead> diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 026d45853d7..b72dc5f1d74 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -11,7 +11,7 @@ define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, metadata !13, metadata !DIExpression()), !dbg !21 tail call void @llvm.dbg.value(metadata i64 %x, metadata !14, metadata !DIExpression()), !dbg !22 tail call void @llvm.dbg.value(metadata i64 %y, metadata !17, metadata !DIExpression()), !dbg !23 -;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%R7+0] +;CHECK: @DEBUG_VALUE: foo:y <- [DW_OP_plus_uconst 8] [%r7+0] tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, metadata !18, metadata !DIExpression()), !dbg !24 tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, metadata !19, metadata !DIExpression()), !dbg !25 %1 = icmp eq %struct.tag_s* %c, null, !dbg !26 diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index 336fc27caac..15c153b720b 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -5,8 +5,8 @@ target triple = "thumbv7-apple-macosx10.6.7" ;CHECK: vadd.f32 q4, q8, q8 ;CHECK-NEXT: LBB0_1 -;CHECK: @DEBUG_VALUE: x <- %Q4{{$}} -;CHECK-NEXT: @DEBUG_VALUE: y <- %Q4{{$}} +;CHECK: @DEBUG_VALUE: x <- %q4{{$}} +;CHECK-NEXT: @DEBUG_VALUE: y <- %q4{{$}} ;CHECK: beq LBB0_1 diff --git a/test/CodeGen/ARM/sched-it-debug-nodes.mir b/test/CodeGen/ARM/sched-it-debug-nodes.mir index c055508e6c7..2d4fff16067 100644 --- a/test/CodeGen/ARM/sched-it-debug-nodes.mir +++ b/test/CodeGen/ARM/sched-it-debug-nodes.mir @@ -32,9 +32,9 @@ ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or ; hopefully, triggering an assert). - ; CHECK: BUNDLE %ITSTATE<imp-def,dead> - ; CHECK: * DBG_VALUE %R1, %noreg, !"u" - ; CHECK-NOT: * DBG_VALUE %R1<kill>, %noreg, !"u" + ; CHECK: BUNDLE %itstate<imp-def,dead> + ; CHECK: * DBG_VALUE %r1, %noreg, !"u" + ; CHECK-NOT: * DBG_VALUE %r1<kill>, %noreg, !"u" declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 diff --git a/test/CodeGen/BPF/sockex2.ll b/test/CodeGen/BPF/sockex2.ll index d5f070ea605..f3f3e450edc 100644 --- a/test/CodeGen/BPF/sockex2.ll +++ b/test/CodeGen/BPF/sockex2.ll @@ -311,7 +311,7 @@ flow_dissector.exit.thread: ; preds = %86, %12, %196, %199 ; CHECK-LABEL: bpf_prog2: ; CHECK: r0 = *(u16 *)skb[12] # encoding: [0x28,0x00,0x00,0x00,0x0c,0x00,0x00,0x00] ; CHECK: r0 = *(u16 *)skb[16] # encoding: [0x28,0x00,0x00,0x00,0x10,0x00,0x00,0x00] -; CHECK: implicit-def: %R1 +; CHECK: implicit-def: %r1 ; CHECK: r1 = ; CHECK: call 1 # encoding: [0x85,0x00,0x00,0x00,0x01,0x00,0x00,0x00] ; CHECK: call 2 # encoding: [0x85,0x00,0x00,0x00,0x02,0x00,0x00,0x00] diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index a036fafbe96..2f5349f641a 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -161,8 +161,8 @@ declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 { ; ALL-LABEL: thunk_undef_double: -; O32: # implicit-def: %A2 -; O32: # implicit-def: %A3 +; O32: # implicit-def: %a2 +; O32: # implicit-def: %a3 ; NOT-R6C: jr $[[TGT]] ; R6C: jrc $[[TGT]] diff --git a/test/CodeGen/PowerPC/addegluecrash.ll b/test/CodeGen/PowerPC/addegluecrash.ll index 7605340d305..f17b6dce9a9 100644 --- a/test/CodeGen/PowerPC/addegluecrash.ll +++ b/test/CodeGen/PowerPC/addegluecrash.ll @@ -23,7 +23,7 @@ define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* n ; CHECK-NEXT: cmpld 7, 4, 5 ; CHECK-NEXT: mfocrf 10, 1 ; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31 -; CHECK-NEXT: # implicit-def: %X4 +; CHECK-NEXT: # implicit-def: %x4 ; CHECK-NEXT: mr 4, 10 ; CHECK-NEXT: clrldi 4, 4, 32 ; CHECK-NEXT: std 4, 0(3) diff --git a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll index deacbd6a00f..c5651562f85 100644 --- a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll +++ b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll @@ -10,7 +10,7 @@ entry: lnext: %elementArray = load i32*, i32** %elementArrayPtr, align 8 ; CHECK: lwz [[LDREG:[0-9]+]], 124(1) # 4-byte Folded Reload -; CHECK: # implicit-def: %X[[TEMPREG:[0-9]+]] +; CHECK: # implicit-def: %x[[TEMPREG:[0-9]+]] %element = load i32, i32* %elementArray, align 4 ; CHECK: mr [[TEMPREG]], [[LDREG]] ; CHECK: clrldi 4, [[TEMPREG]], 32 diff --git a/test/CodeGen/PowerPC/byval-agg-info.ll b/test/CodeGen/PowerPC/byval-agg-info.ll index df87896e375..04869665797 100644 --- a/test/CodeGen/PowerPC/byval-agg-info.ll +++ b/test/CodeGen/PowerPC/byval-agg-info.ll @@ -13,5 +13,5 @@ entry: ; Make sure that the MMO on the store has no offset from the byval ; variable itself (we used to have mem:ST8[%v+64]). -; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16) +; CHECK: STD %x5<kill>, 176, %x1; mem:ST8[%v](align=16) diff --git a/test/CodeGen/PowerPC/fp64-to-int16.ll b/test/CodeGen/PowerPC/fp64-to-int16.ll index 10d58c2d766..0c5274d9426 100644 --- a/test/CodeGen/PowerPC/fp64-to-int16.ll +++ b/test/CodeGen/PowerPC/fp64-to-int16.ll @@ -10,7 +10,7 @@ define i1 @Test(double %a) { ; CHECK-NEXT: xori 3, 3, 65534 ; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: srwi 3, 3, 5 -; CHECK-NEXT: # implicit-def: %X4 +; CHECK-NEXT: # implicit-def: %x4 ; CHECK-NEXT: mr 4, 3 ; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: blr diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll index 5176cdcb600..4ca75a7e365 100644 --- a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -7,12 +7,12 @@ define signext i32 @fn1(i32 %baz) { %2 = zext i32 %1 to i64 %3 = shl i64 %2, 48 %4 = ashr exact i64 %3, 48 -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>; +; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def,dead>; ; CHECK: CMPLDI ; CHECK: BCC -; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>; -; CHECK: COPY %CR0 +; CHECK: ANDIo8 {{[^,]+}}, 65520, %cr0<imp-def>; +; CHECK: COPY %cr0 ; CHECK: BCC %5 = icmp eq i64 %4, 0 br i1 %5, label %foo, label %bar @@ -26,8 +26,8 @@ bar: ; CHECK-LABEL: fn2 define signext i32 @fn2(i64 %a, i64 %b) { -; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 +; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %cr0<imp-def>; +; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0 ; CHECK: BCC 12, [[CREG]]<kill> %1 = or i64 %b, %a %2 = icmp sgt i64 %1, -1 @@ -42,8 +42,8 @@ bar: ; CHECK-LABEL: fn3 define signext i32 @fn3(i32 %a) { -; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>; -; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0 +; CHECK: ANDIo {{[^, ]+}}, 10, %cr0<imp-def>; +; CHECK: [[CREG:[^, ]+]]<def> = COPY %cr0 ; CHECK: BCC 76, [[CREG]]<kill> %1 = and i32 %a, 10 %2 = icmp ne i32 %1, 0 diff --git a/test/CodeGen/PowerPC/quadint-return.ll b/test/CodeGen/PowerPC/quadint-return.ll index 8b407849718..2cc995f3f20 100644 --- a/test/CodeGen/PowerPC/quadint-return.ll +++ b/test/CodeGen/PowerPC/quadint-return.ll @@ -14,6 +14,6 @@ entry: ; CHECK: ********** Function: foo ; CHECK: ********** FAST REGISTER ALLOCATION ********** -; CHECK: %X3<def> = COPY %vreg -; CHECK-NEXT: %X4<def> = COPY %vreg +; CHECK: %x3<def> = COPY %vreg +; CHECK-NEXT: %x4<def> = COPY %vreg ; CHECK-NEXT: BLR diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll index 1442109dc23..618d356eafb 100644 --- a/test/CodeGen/SystemZ/int-div-01.ll +++ b/test/CodeGen/SystemZ/int-div-01.ll @@ -1,6 +1,6 @@ ; Test 32-bit signed division and remainder. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i32 @foo() diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll index 1a4b4d95c93..1fc57dd5774 100644 --- a/test/CodeGen/SystemZ/int-div-02.ll +++ b/test/CodeGen/SystemZ/int-div-02.ll @@ -1,6 +1,6 @@ ; Test 32-bit unsigned division and remainder. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i32 @foo() diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll index 37a7c4f748c..5f8d02eedb9 100644 --- a/test/CodeGen/SystemZ/int-div-03.ll +++ b/test/CodeGen/SystemZ/int-div-03.ll @@ -1,7 +1,7 @@ ; Test 64-bit signed division and remainder when the divisor is ; a signed-extended i32. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i64 @foo() diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll index e8c6f3e03c6..c7d394ce03d 100644 --- a/test/CodeGen/SystemZ/int-div-04.ll +++ b/test/CodeGen/SystemZ/int-div-04.ll @@ -1,6 +1,6 @@ ; Testg 64-bit signed division and remainder. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i64 @foo() diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll index f80a139238e..54d654ff122 100644 --- a/test/CodeGen/SystemZ/int-div-05.ll +++ b/test/CodeGen/SystemZ/int-div-05.ll @@ -1,6 +1,6 @@ ; Testg 64-bit unsigned division and remainder. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i64 @foo() diff --git a/test/CodeGen/SystemZ/int-div-06.ll b/test/CodeGen/SystemZ/int-div-06.ll index 8576b1b6270..9de717857d7 100644 --- a/test/CodeGen/SystemZ/int-div-06.ll +++ b/test/CodeGen/SystemZ/int-div-06.ll @@ -1,6 +1,6 @@ ; Test that divisions by constants are implemented as multiplications. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s ; Check signed 32-bit division. define i32 @f1(i32 %a) { diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll index c43089677ff..70282f09370 100644 --- a/test/CodeGen/SystemZ/int-mul-08.ll +++ b/test/CodeGen/SystemZ/int-mul-08.ll @@ -1,6 +1,6 @@ ; Test high-part i64->i128 multiplications. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s declare i64 @foo() diff --git a/test/CodeGen/SystemZ/int-mul-10.ll b/test/CodeGen/SystemZ/int-mul-10.ll index a4d80af36a3..fe863d3972c 100644 --- a/test/CodeGen/SystemZ/int-mul-10.ll +++ b/test/CodeGen/SystemZ/int-mul-10.ll @@ -1,6 +1,6 @@ ; Test signed high-part i64->i128 multiplications on z14. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -asm-verbose=0 | FileCheck %s declare i64 @foo() diff --git a/test/CodeGen/SystemZ/pr32505.ll b/test/CodeGen/SystemZ/pr32505.ll index 4604fa4b0eb..c5382b27181 100644 --- a/test/CodeGen/SystemZ/pr32505.ll +++ b/test/CodeGen/SystemZ/pr32505.ll @@ -10,8 +10,8 @@ define <2 x float> @pr32505(<2 x i8> * %a) { ; CHECK-NEXT: lbh %r1, 0(%r2) ; CHECK-NEXT: ldgr %f0, %r1 ; CHECK-NEXT: ldgr %f2, %r0 -; CHECK-NEXT: # kill: %F0S<def> %F0S<kill> %F0D<kill> -; CHECK-NEXT: # kill: %F2S<def> %F2S<kill> %F2D<kill> +; CHECK-NEXT: # kill: %f0s<def> %f0s<kill> %f0d<kill> +; CHECK-NEXT: # kill: %f2s<def> %f2s<kill> %f2d<kill> ; CHECK-NEXT: br %r14 %L17 = load <2 x i8>, <2 x i8>* %a %Se21 = sext <2 x i8> %L17 to <2 x i32> diff --git a/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll b/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll index 3cca10e268c..3040a26b046 100644 --- a/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll +++ b/test/CodeGen/X86/2010-03-05-EFLAGS-Redef.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -verify-machineinstrs ; ; This test case is transformed into a single basic block by the machine -; branch folding pass. That makes a complete mess of the %EFLAGS liveness, but +; branch folding pass. That makes a complete mess of the %eflags liveness, but ; we don't care about liveness this late anyway. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll index 5adf99e3e47..3dfc8cdbbb8 100644 --- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -2,8 +2,8 @@ ; rdar://7842028 ; Do not delete partially dead copy instructions. -; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> -; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<imp-use,kill>, %ESI<imp-use,kill> +; %rdi<def,dead> = MOV64rr %rax<kill>, %edi<imp-def> +; REP_MOVSD %ecx<imp-def,dead>, %edi<imp-def,dead>, %esi<imp-def,dead>, %ecx<imp-use,kill>, %edi<imp-use,kill>, %esi<imp-use,kill> %struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 } diff --git a/test/CodeGen/X86/2010-05-12-FastAllocKills.ll b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll index eb0b150378d..7a98f778bb9 100644 --- a/test/CodeGen/X86/2010-05-12-FastAllocKills.ll +++ b/test/CodeGen/X86/2010-05-12-FastAllocKills.ll @@ -6,23 +6,23 @@ target triple = "x86_64-apple-darwin" ;BB#5: derived from LLVM BB %bb10 ; Predecessors according to CFG: BB#4 BB#5 ; %reg1024<def> = MOV_Fp8080 %reg1034 -; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %reg1025<def> = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] ; %reg1034<def> = MOV_Fp8080 %reg1025 -; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def> +; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def> ; JMP_4 <BB#5> ; Successors according to CFG: BB#5 ; -; The X86FP pass needs good kill flags, like on %FP0 representing %reg1034: +; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034: ;BB#5: derived from LLVM BB %bb10 ; Predecessors according to CFG: BB#4 BB#5 -; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4) -; %FP1<def> = MOV_Fp8080 %FP0<kill> -; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] -; %FP0<def> = MOV_Fp8080 %FP2 -; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4) -; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4) -; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4) -; FP_REG_KILL %FP0<imp-def>, %FP1<imp-def>, %FP2<imp-def>, %FP3<imp-def>, %FP4<imp-def>, %FP5<imp-def>, %FP6<imp-def> +; %fp0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4) +; %fp1<def> = MOV_Fp8080 %fp0<kill> +; %fp2<def> = MUL_Fp80m32 %fp1, %rip, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool] +; %fp0<def> = MOV_Fp8080 %fp2 +; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %fp0<kill>; mem:ST10[FixedStack3](align=4) +; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %fp1<kill>; mem:ST10[FixedStack4](align=4) +; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %fp2<kill>; mem:ST10[FixedStack5](align=4) +; FP_REG_KILL %fp0<imp-def>, %fp1<imp-def>, %fp2<imp-def>, %fp3<imp-def>, %fp4<imp-def>, %fp5<imp-def>, %fp6<imp-def> ; JMP_4 <BB#5> ; Successors according to CFG: BB#5 diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll index 38bbe4e367b..fbb0b1079bd 100644 --- a/test/CodeGen/X86/2010-05-28-Crash.ll +++ b/test/CodeGen/X86/2010-05-28-Crash.ll @@ -45,7 +45,7 @@ entry: !18 = !DIFile(filename: "f.c", directory: "/tmp") !19 = !{} -;CHECK: DEBUG_VALUE: bar:x <- %E +;CHECK: DEBUG_VALUE: bar:x <- %e ;CHECK: Ltmp ;CHECK: DEBUG_VALUE: foo:y <- 1{{$}} !20 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll index 4b019abf5d5..435582e9b9c 100644 --- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll +++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll @@ -11,7 +11,7 @@ target triple = "x86_64-apple-darwin10.2" ; Function Attrs: noinline nounwind optsize readnone ssp define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) #0 align 2 !dbg !4 { entry: - ; CHECK: DEBUG_VALUE: baz:this <- %RDI{{$}} + ; CHECK: DEBUG_VALUE: baz:this <- %rdi{{$}} tail call void @llvm.dbg.value(metadata %struct.foo* %this, i64 0, metadata !13, metadata !16), !dbg !17 tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !18, metadata !16), !dbg !17 %0 = mul nsw i32 %x, 7, !dbg !19 diff --git a/test/CodeGen/X86/GlobalISel/add-scalar.ll b/test/CodeGen/X86/GlobalISel/add-scalar.ll index 4572e49deb9..cb30b2508a8 100644 --- a/test/CodeGen/X86/GlobalISel/add-scalar.ll +++ b/test/CodeGen/X86/GlobalISel/add-scalar.ll @@ -28,8 +28,8 @@ define i64 @test_add_i64(i64 %arg1, i64 %arg2) { define i32 @test_add_i32(i32 %arg1, i32 %arg2) { ; X64-LABEL: test_add_i32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: leal (%rsi,%rdi), %eax ; X64-NEXT: retq ; @@ -45,10 +45,10 @@ define i32 @test_add_i32(i32 %arg1, i32 %arg2) { define i16 @test_add_i16(i16 %arg1, i16 %arg2) { ; X64-LABEL: test_add_i16: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: leal (%rsi,%rdi), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-LABEL: test_add_i16: diff --git a/test/CodeGen/X86/GlobalISel/ext-x86-64.ll b/test/CodeGen/X86/GlobalISel/ext-x86-64.ll index 1168057039b..e8afafd0e12 100644 --- a/test/CodeGen/X86/GlobalISel/ext-x86-64.ll +++ b/test/CodeGen/X86/GlobalISel/ext-x86-64.ll @@ -6,7 +6,7 @@ define i64 @test_zext_i1(i8 %a) { ; X64-LABEL: test_zext_i1: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: andq $1, %rdi ; X64-NEXT: movq %rdi, %rax ; X64-NEXT: retq diff --git a/test/CodeGen/X86/GlobalISel/ext.ll b/test/CodeGen/X86/GlobalISel/ext.ll index 36af1778154..3b0b35797a8 100644 --- a/test/CodeGen/X86/GlobalISel/ext.ll +++ b/test/CodeGen/X86/GlobalISel/ext.ll @@ -13,7 +13,7 @@ define i8 @test_zext_i1toi8(i32 %a) { ; X32: # BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: andb $1, %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl %val = trunc i32 %a to i1 %r = zext i1 %val to i8 @@ -31,7 +31,7 @@ define i16 @test_zext_i1toi16(i32 %a) { ; X32: # BB#0: ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: andw $1, %ax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl %val = trunc i32 %a to i1 %r = zext i1 %val to i16 diff --git a/test/CodeGen/X86/GlobalISel/gep.ll b/test/CodeGen/X86/GlobalISel/gep.ll index 94da9fb4676..ee66accc77d 100644 --- a/test/CodeGen/X86/GlobalISel/gep.ll +++ b/test/CodeGen/X86/GlobalISel/gep.ll @@ -13,7 +13,7 @@ define i32* @test_gep_i8(i32 *%arr, i8 %ind) { ; ; X64-LABEL: test_gep_i8: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: movsbq %sil, %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: retq @@ -47,7 +47,7 @@ define i32* @test_gep_i16(i32 *%arr, i16 %ind) { ; ; X64-LABEL: test_gep_i16: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: movswq %si, %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: retq diff --git a/test/CodeGen/X86/add-sub-nsw-nuw.ll b/test/CodeGen/X86/add-sub-nsw-nuw.ll index d02736de55d..721b2fe7261 100644 --- a/test/CodeGen/X86/add-sub-nsw-nuw.ll +++ b/test/CodeGen/X86/add-sub-nsw-nuw.ll @@ -10,7 +10,7 @@ define i8 @PR30841(i64 %argc) { ; CHECK: ## BB#0: ## %entry ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: negl %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retl entry: %or = or i64 %argc, -4294967296 diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll index 634366bf05c..95368d100b2 100644 --- a/test/CodeGen/X86/add.ll +++ b/test/CodeGen/X86/add.ll @@ -176,14 +176,14 @@ define i64 @test6(i64 %A, i32 %B) nounwind { ; ; X64-LINUX-LABEL: test6: ; X64-LINUX: # BB#0: # %entry -; X64-LINUX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-LINUX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-LINUX-NEXT: shlq $32, %rsi ; X64-LINUX-NEXT: leaq (%rsi,%rdi), %rax ; X64-LINUX-NEXT: retq ; ; X64-WIN32-LABEL: test6: ; X64-WIN32: # BB#0: # %entry -; X64-WIN32-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> +; X64-WIN32-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> ; X64-WIN32-NEXT: shlq $32, %rdx ; X64-WIN32-NEXT: leaq (%rdx,%rcx), %rax ; X64-WIN32-NEXT: retq diff --git a/test/CodeGen/X86/addcarry.ll b/test/CodeGen/X86/addcarry.ll index 5fd045389bd..ebeb85c2c83 100644 --- a/test/CodeGen/X86/addcarry.ll +++ b/test/CodeGen/X86/addcarry.ll @@ -84,7 +84,7 @@ entry: define i8 @e(i32* nocapture %a, i32 %b) nounwind { ; CHECK-LABEL: e: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; CHECK-NEXT: movl (%rdi), %ecx ; CHECK-NEXT: leal (%rsi,%rcx), %edx ; CHECK-NEXT: addl %esi, %edx diff --git a/test/CodeGen/X86/anyext.ll b/test/CodeGen/X86/anyext.ll index 4f4218bdd63..00adcd625cb 100644 --- a/test/CodeGen/X86/anyext.ll +++ b/test/CodeGen/X86/anyext.ll @@ -8,7 +8,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) nounwind { ; X32-LABEL: foo: ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: andl $1, %eax @@ -17,7 +17,7 @@ define i32 @foo(i32 %p, i8 zeroext %x) nounwind { ; X64-LABEL: foo: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: andl $1, %eax @@ -35,7 +35,7 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind { ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: xorl %edx, %edx ; X32-NEXT: divw {{[0-9]+}}(%esp) -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; X32-NEXT: andl $1, %eax ; X32-NEXT: retl ; @@ -44,7 +44,7 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind { ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: movl %edi, %eax ; X64-NEXT: divw %si -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; X64-NEXT: andl $1, %eax ; X64-NEXT: retq %q = trunc i32 %p to i16 diff --git a/test/CodeGen/X86/atomic-eflags-reuse.ll b/test/CodeGen/X86/atomic-eflags-reuse.ll index 21568aaa518..260680eebf5 100644 --- a/test/CodeGen/X86/atomic-eflags-reuse.ll +++ b/test/CodeGen/X86/atomic-eflags-reuse.ll @@ -93,7 +93,7 @@ define i8 @test_add_1_setcc_slt(i64* %p) #0 { ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: lock xaddq %rax, (%rdi) ; CHECK-NEXT: shrq $63, %rax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %RAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %rax<kill> ; CHECK-NEXT: retq entry: %tmp0 = atomicrmw add i64* %p, i64 1 seq_cst diff --git a/test/CodeGen/X86/avx-cast.ll b/test/CodeGen/X86/avx-cast.ll index 87343880250..a3d42ef051d 100644 --- a/test/CodeGen/X86/avx-cast.ll +++ b/test/CodeGen/X86/avx-cast.ll @@ -9,7 +9,7 @@ define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp { ; AVX-LABEL: castA: ; AVX: ## BB#0: -; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX-NEXT: retq @@ -20,7 +20,7 @@ define <8 x float> @castA(<4 x float> %m) nounwind uwtable readnone ssp { define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp { ; AVX-LABEL: castB: ; AVX: ## BB#0: -; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; AVX-NEXT: retq @@ -33,14 +33,14 @@ define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp { define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp { ; AVX1-LABEL: castC: ; AVX1: ## BB#0: -; AVX1-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX1-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3] ; AVX1-NEXT: retq ; ; AVX2-LABEL: castC: ; AVX2: ## BB#0: -; AVX2-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: retq @@ -54,7 +54,7 @@ define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp { define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp { ; AVX-LABEL: castD: ; AVX: ## BB#0: -; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -64,7 +64,7 @@ define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp { define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp { ; AVX-LABEL: castE: ; AVX: ## BB#0: -; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1> @@ -74,7 +74,7 @@ define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp { define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp { ; AVX-LABEL: castF: ; AVX: ## BB#0: -; AVX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1> diff --git a/test/CodeGen/X86/avx-cmp.ll b/test/CodeGen/X86/avx-cmp.ll index 963878b0f56..be46b1bb3a3 100644 --- a/test/CodeGen/X86/avx-cmp.ll +++ b/test/CodeGen/X86/avx-cmp.ll @@ -197,7 +197,7 @@ define i32 @scalarcmpA() uwtable ssp { ; CHECK-NEXT: vcmpeqsd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: andl $1, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; CHECK-NEXT: retq %cmp29 = fcmp oeq double undef, 0.000000e+00 %res = zext i1 %cmp29 to i32 diff --git a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll index 1ae93dc747f..7e962801133 100644 --- a/test/CodeGen/X86/avx-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -316,12 +316,12 @@ define <4 x i64> @test_mm256_castpd_si256(<4 x double> %a0) nounwind { define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind { ; X32-LABEL: test_mm256_castpd128_pd256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castpd128_pd256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: retq %res = shufflevector <2 x double> %a0, <2 x double> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x double> %res @@ -330,13 +330,13 @@ define <4 x double> @test_mm256_castpd128_pd256(<2 x double> %a0) nounwind { define <2 x double> @test_mm256_castpd256_pd128(<4 x double> %a0) nounwind { ; X32-LABEL: test_mm256_castpd256_pd128: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castpd256_pd128: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = shufflevector <4 x double> %a0, <4 x double> %a0, <2 x i32> <i32 0, i32 1> @@ -370,12 +370,12 @@ define <4 x i64> @test_mm256_castps_si256(<8 x float> %a0) nounwind { define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind { ; X32-LABEL: test_mm256_castps128_ps256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castps128_ps256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: retq %res = shufflevector <4 x float> %a0, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> ret <8 x float> %res @@ -384,13 +384,13 @@ define <8 x float> @test_mm256_castps128_ps256(<4 x float> %a0) nounwind { define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind { ; X32-LABEL: test_mm256_castps256_ps128: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castps256_ps128: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = shufflevector <8 x float> %a0, <8 x float> %a0, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -400,12 +400,12 @@ define <4 x float> @test_mm256_castps256_ps128(<8 x float> %a0) nounwind { define <4 x i64> @test_mm256_castsi128_si256(<2 x i64> %a0) nounwind { ; X32-LABEL: test_mm256_castsi128_si256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castsi128_si256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: retq %res = shufflevector <2 x i64> %a0, <2 x i64> %a0, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x i64> %res @@ -438,13 +438,13 @@ define <8 x float> @test_mm256_castsi256_ps(<4 x i64> %a0) nounwind { define <2 x i64> @test_mm256_castsi256_si128(<4 x i64> %a0) nounwind { ; X32-LABEL: test_mm256_castsi256_si128: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_castsi256_si128: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = shufflevector <4 x i64> %a0, <4 x i64> %a0, <2 x i32> <i32 0, i32 1> @@ -1043,13 +1043,13 @@ define <4 x i64> @test_mm256_insert_epi64(<4 x i64> %a0, i64 %a1) nounwind { define <4 x double> @test_mm256_insertf128_pd(<4 x double> %a0, <2 x double> %a1) nounwind { ; X32-LABEL: test_mm256_insertf128_pd: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_insertf128_pd: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; X64-NEXT: retq %ext = shufflevector <2 x double> %a1, <2 x double> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> @@ -1075,13 +1075,13 @@ define <8 x float> @test_mm256_insertf128_ps(<8 x float> %a0, <4 x float> %a1) n define <4 x i64> @test_mm256_insertf128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind { ; X32-LABEL: test_mm256_insertf128_si256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X32-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_insertf128_si256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X64-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; X64-NEXT: retq %ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> @@ -2188,13 +2188,13 @@ define <4 x i64> @test_mm256_set_epi64x(i64 %a0, i64 %a1, i64 %a2, i64 %a3) noun define <8 x float> @test_mm256_set_m128(<4 x float> %a0, <4 x float> %a1) nounwind { ; X32-LABEL: test_mm256_set_m128: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_set_m128: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: retq %res = shufflevector <4 x float> %a1, <4 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -2204,13 +2204,13 @@ define <8 x float> @test_mm256_set_m128(<4 x float> %a0, <4 x float> %a1) nounwi define <4 x double> @test_mm256_set_m128d(<2 x double> %a0, <2 x double> %a1) nounwind { ; X32-LABEL: test_mm256_set_m128d: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_set_m128d: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: retq %arg0 = bitcast <2 x double> %a0 to <4 x float> @@ -2223,13 +2223,13 @@ define <4 x double> @test_mm256_set_m128d(<2 x double> %a0, <2 x double> %a1) no define <4 x i64> @test_mm256_set_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; X32-LABEL: test_mm256_set_m128i: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_set_m128i: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; X64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: retq %arg0 = bitcast <2 x i64> %a0 to <4 x float> @@ -2825,13 +2825,13 @@ define <4 x i64> @test_mm256_setr_epi64x(i64 %a0, i64 %a1, i64 %a2, i64 %a3) nou define <8 x float> @test_mm256_setr_m128(<4 x float> %a0, <4 x float> %a1) nounwind { ; X32-LABEL: test_mm256_setr_m128: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_setr_m128: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X64-NEXT: retq %res = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -2841,13 +2841,13 @@ define <8 x float> @test_mm256_setr_m128(<4 x float> %a0, <4 x float> %a1) nounw define <4 x double> @test_mm256_setr_m128d(<2 x double> %a0, <2 x double> %a1) nounwind { ; X32-LABEL: test_mm256_setr_m128d: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_setr_m128d: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X64-NEXT: retq %arg0 = bitcast <2 x double> %a0 to <4 x float> @@ -2860,13 +2860,13 @@ define <4 x double> @test_mm256_setr_m128d(<2 x double> %a0, <2 x double> %a1) n define <4 x i64> @test_mm256_setr_m128i(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; X32-LABEL: test_mm256_setr_m128i: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: test_mm256_setr_m128i: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X64-NEXT: retq %arg0 = bitcast <2 x i64> %a0 to <4 x float> diff --git a/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll index 0451f6fce46..0bd58b34fa8 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll @@ -39,7 +39,7 @@ define <8 x i32> @test_x86_avx_vinsertf128_si_256_1(<8 x i32> %a0, <4 x i32> %a1 define <8 x i32> @test_x86_avx_vinsertf128_si_256_2(<8 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: test_x86_avx_vinsertf128_si_256_2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; CHECK-NEXT: ret{{[l|q]}} %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> %a0, <4 x i32> %a1, i8 2) @@ -88,7 +88,7 @@ declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind read define <2 x double> @test_x86_avx_extractf128_pd_256_2(<4 x double> %a0) { ; CHECK-LABEL: test_x86_avx_extractf128_pd_256_2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} %res = call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a0, i8 2) diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll index e2dab79e6f1..402c4ca7f40 100644 --- a/test/CodeGen/X86/avx-load-store.ll +++ b/test/CodeGen/X86/avx-load-store.ll @@ -85,7 +85,7 @@ define <8 x float> @mov00(<8 x float> %v, float * %ptr) nounwind { ; CHECK_O0-LABEL: mov00: ; CHECK_O0: # BB#0: ; CHECK_O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; CHECK_O0-NEXT: # implicit-def: %YMM1 +; CHECK_O0-NEXT: # implicit-def: %ymm1 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 ; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK_O0-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3,4,5,6,7] @@ -104,7 +104,7 @@ define <4 x double> @mov01(<4 x double> %v, double * %ptr) nounwind { ; CHECK_O0-LABEL: mov01: ; CHECK_O0: # BB#0: ; CHECK_O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; CHECK_O0-NEXT: # implicit-def: %YMM1 +; CHECK_O0-NEXT: # implicit-def: %ymm1 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 ; CHECK_O0-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; CHECK_O0-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm2[1,2,3] @@ -121,7 +121,7 @@ define void @storev16i16(<16 x i16> %a) nounwind { ; ; CHECK_O0-LABEL: storev16i16: ; CHECK_O0: # BB#0: -; CHECK_O0-NEXT: # implicit-def: %RAX +; CHECK_O0-NEXT: # implicit-def: %rax ; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax) store <16 x i16> %a, <16 x i16>* undef, align 32 unreachable @@ -135,7 +135,7 @@ define void @storev16i16_01(<16 x i16> %a) nounwind { ; ; CHECK_O0-LABEL: storev16i16_01: ; CHECK_O0: # BB#0: -; CHECK_O0-NEXT: # implicit-def: %RAX +; CHECK_O0-NEXT: # implicit-def: %rax ; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax) store <16 x i16> %a, <16 x i16>* undef, align 4 unreachable @@ -148,7 +148,7 @@ define void @storev32i8(<32 x i8> %a) nounwind { ; ; CHECK_O0-LABEL: storev32i8: ; CHECK_O0: # BB#0: -; CHECK_O0-NEXT: # implicit-def: %RAX +; CHECK_O0-NEXT: # implicit-def: %rax ; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax) store <32 x i8> %a, <32 x i8>* undef, align 32 unreachable @@ -162,13 +162,13 @@ define void @storev32i8_01(<32 x i8> %a) nounwind { ; ; CHECK_O0-LABEL: storev32i8_01: ; CHECK_O0: # BB#0: -; CHECK_O0-NEXT: # implicit-def: %RAX +; CHECK_O0-NEXT: # implicit-def: %rax ; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax) store <32 x i8> %a, <32 x i8>* undef, align 4 unreachable } -; It is faster to make two saves, if the data is already in XMM registers. For +; It is faster to make two saves, if the data is already in xmm registers. For ; example, after making an integer operation. define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp { ; CHECK-LABEL: double_save: @@ -179,7 +179,7 @@ define void @double_save(<4 x i32> %A, <4 x i32> %B, <8 x i32>* %P) nounwind ssp ; ; CHECK_O0-LABEL: double_save: ; CHECK_O0: # BB#0: -; CHECK_O0-NEXT: # implicit-def: %YMM2 +; CHECK_O0-NEXT: # implicit-def: %ymm2 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2 ; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2 ; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi) @@ -211,13 +211,13 @@ define void @f_f() nounwind { ; ; CHECK_O0-LABEL: f_f: ; CHECK_O0: # BB#0: # %allocas -; CHECK_O0-NEXT: # implicit-def: %AL +; CHECK_O0-NEXT: # implicit-def: %al ; CHECK_O0-NEXT: testb $1, %al ; CHECK_O0-NEXT: jne .LBB8_1 ; CHECK_O0-NEXT: jmp .LBB8_2 ; CHECK_O0-NEXT: .LBB8_1: # %cif_mask_all ; CHECK_O0-NEXT: .LBB8_2: # %cif_mask_mixed -; CHECK_O0-NEXT: # implicit-def: %AL +; CHECK_O0-NEXT: # implicit-def: %al ; CHECK_O0-NEXT: testb $1, %al ; CHECK_O0-NEXT: jne .LBB8_3 ; CHECK_O0-NEXT: jmp .LBB8_4 @@ -225,8 +225,8 @@ define void @f_f() nounwind { ; CHECK_O0-NEXT: movl $-1, %eax ; CHECK_O0-NEXT: vmovd %eax, %xmm0 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm1 -; CHECK_O0-NEXT: # implicit-def: %RCX -; CHECK_O0-NEXT: # implicit-def: %YMM2 +; CHECK_O0-NEXT: # implicit-def: %rcx +; CHECK_O0-NEXT: # implicit-def: %ymm2 ; CHECK_O0-NEXT: vmaskmovps %ymm2, %ymm1, (%rcx) ; CHECK_O0-NEXT: .LBB8_4: # %cif_mixed_test_any_check allocas: @@ -259,7 +259,7 @@ define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind { ; CHECK_O0: # BB#0: ; CHECK_O0-NEXT: vmovdqu (%rsi), %xmm0 ; CHECK_O0-NEXT: vmovdqu 16(%rsi), %xmm1 -; CHECK_O0-NEXT: # implicit-def: %YMM2 +; CHECK_O0-NEXT: # implicit-def: %ymm2 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2 ; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2 ; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi) @@ -304,7 +304,7 @@ define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind { ; CHECK_O0: # BB#0: ; CHECK_O0-NEXT: vmovdqa (%rsi), %xmm0 ; CHECK_O0-NEXT: vmovdqa 16(%rsi), %xmm1 -; CHECK_O0-NEXT: # implicit-def: %YMM2 +; CHECK_O0-NEXT: # implicit-def: %ymm2 ; CHECK_O0-NEXT: vmovaps %xmm0, %xmm2 ; CHECK_O0-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2 ; CHECK_O0-NEXT: vmovdqu %ymm2, (%rdi) diff --git a/test/CodeGen/X86/avx-splat.ll b/test/CodeGen/X86/avx-splat.ll index 0f3f3e5fb6e..c6d0c5337c5 100644 --- a/test/CodeGen/X86/avx-splat.ll +++ b/test/CodeGen/X86/avx-splat.ll @@ -61,7 +61,7 @@ define <8 x float> @funcE() nounwind { ; CHECK: # BB#0: # %for_exit499 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: # implicit-def: %YMM0 +; CHECK-NEXT: # implicit-def: %ymm0 ; CHECK-NEXT: jne .LBB4_2 ; CHECK-NEXT: # BB#1: # %load.i1247 ; CHECK-NEXT: pushq %rbp diff --git a/test/CodeGen/X86/avx-vinsertf128.ll b/test/CodeGen/X86/avx-vinsertf128.ll index b7a4d5b5c30..2028e9c50aa 100644 --- a/test/CodeGen/X86/avx-vinsertf128.ll +++ b/test/CodeGen/X86/avx-vinsertf128.ll @@ -75,7 +75,7 @@ define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly { define <4 x double> @insert_undef_pd(<4 x double> %a0, <2 x double> %a1) { ; CHECK-LABEL: insert_undef_pd: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vmovaps %ymm1, %ymm0 ; CHECK-NEXT: retq %res = call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> undef, <2 x double> %a1, i8 0) @@ -86,7 +86,7 @@ declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double> define <8 x float> @insert_undef_ps(<8 x float> %a0, <4 x float> %a1) { ; CHECK-LABEL: insert_undef_ps: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vmovaps %ymm1, %ymm0 ; CHECK-NEXT: retq %res = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> undef, <4 x float> %a1, i8 0) @@ -97,7 +97,7 @@ declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i define <8 x i32> @insert_undef_si(<8 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: insert_undef_si: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vmovaps %ymm1, %ymm0 ; CHECK-NEXT: retq %res = call <8 x i32> @llvm.x86.avx.vinsertf128.si.256(<8 x i32> undef, <4 x i32> %a1, i8 0) diff --git a/test/CodeGen/X86/avx-vzeroupper.ll b/test/CodeGen/X86/avx-vzeroupper.ll index 016ddb9c5e7..244fb962af5 100644 --- a/test/CodeGen/X86/avx-vzeroupper.ll +++ b/test/CodeGen/X86/avx-vzeroupper.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=VZ --check-prefix=AVX512 -; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-YMM-ZMM +; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mattr=+avx,+fast-partial-ymm-or-zmm-write | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=FAST-ymm-zmm ; RUN: llc < %s -x86-use-vzeroupper -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s --check-prefix=ALL --check-prefix=NO-VZ --check-prefix=BTVER2 declare i32 @foo() @@ -82,14 +82,14 @@ define <4 x float> @test02(<8 x float> %a, <8 x float> %b) nounwind { ; VZ-LABEL: test02: ; VZ: # BB#0: ; VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0 -; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; VZ-NEXT: vzeroupper ; VZ-NEXT: jmp do_sse # TAILCALL ; ; NO-VZ-LABEL: test02: ; NO-VZ: # BB#0: ; NO-VZ-NEXT: vaddps %ymm1, %ymm0, %ymm0 -; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; NO-VZ-NEXT: jmp do_sse # TAILCALL %add.i = fadd <8 x float> %a, %b %add.low = call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %add.i, i8 0) @@ -222,10 +222,10 @@ define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind { ; VZ-LABEL: test04: ; VZ: # BB#0: ; VZ-NEXT: pushq %rax -; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; VZ-NEXT: callq do_avx -; VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; VZ-NEXT: popq %rax ; VZ-NEXT: vzeroupper ; VZ-NEXT: retq @@ -233,10 +233,10 @@ define <4 x float> @test04(<4 x float> %a, <4 x float> %b) nounwind { ; NO-VZ-LABEL: test04: ; NO-VZ: # BB#0: ; NO-VZ-NEXT: pushq %rax -; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; NO-VZ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NO-VZ-NEXT: callq do_avx -; NO-VZ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NO-VZ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; NO-VZ-NEXT: popq %rax ; NO-VZ-NEXT: retq %shuf = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> diff --git a/test/CodeGen/X86/avx2-conversions.ll b/test/CodeGen/X86/avx2-conversions.ll index 7b88d313770..3a6c65b0bce 100644 --- a/test/CodeGen/X86/avx2-conversions.ll +++ b/test/CodeGen/X86/avx2-conversions.ll @@ -7,7 +7,7 @@ define <4 x i32> @trunc4(<4 x i64> %A) nounwind { ; X32: # BB#0: ; X32-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; X32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -15,7 +15,7 @@ define <4 x i32> @trunc4(<4 x i64> %A) nounwind { ; X64: # BB#0: ; X64-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %B = trunc <4 x i64> %A to <4 x i32> @@ -27,7 +27,7 @@ define <8 x i16> @trunc8(<8 x i32> %A) nounwind { ; X32: # BB#0: ; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -35,7 +35,7 @@ define <8 x i16> @trunc8(<8 x i32> %A) nounwind { ; X64: # BB#0: ; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %B = trunc <8 x i32> %A to <8 x i16> diff --git a/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll b/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll index cf9f035c7c3..5cda99e0077 100644 --- a/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll @@ -355,7 +355,7 @@ define <4 x double> @test_mm256_broadcastsd_pd(<4 x double> %a0) { define <4 x i64> @test_mm256_broadcastsi128_si256(<2 x i64> %a0) { ; CHECK-LABEL: test_mm256_broadcastsi128_si256: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: ret{{[l|q]}} %res = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> @@ -1447,7 +1447,7 @@ define <4 x float> @test_mm256_mask_i64gather_ps(<4 x float> %a0, float *%a1, <4 define <4 x i64> @test0_mm256_inserti128_si256(<4 x i64> %a0, <2 x i64> %a1) nounwind { ; CHECK-LABEL: test0_mm256_inserti128_si256: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; CHECK-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; CHECK-NEXT: ret{{[l|q]}} %ext = shufflevector <2 x i64> %a1, <2 x i64> %a1, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/avx2-masked-gather.ll b/test/CodeGen/X86/avx2-masked-gather.ll index cf046512692..436fb775775 100644 --- a/test/CodeGen/X86/avx2-masked-gather.ll +++ b/test/CodeGen/X86/avx2-masked-gather.ll @@ -30,7 +30,7 @@ define <2 x i32> @masked_gather_v2i32(<2 x i32*>* %ptr, <2 x i1> %masks, <2 x i3 ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB0_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -80,7 +80,7 @@ define <4 x i32> @masked_gather_v2i32_concat(<2 x i32*>* %ptr, <2 x i1> %masks, ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB1_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -131,7 +131,7 @@ define <2 x float> @masked_gather_v2float(<2 x float*>* %ptr, <2 x i1> %masks, < ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB2_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -178,7 +178,7 @@ define <4 x float> @masked_gather_v2float_concat(<2 x float*>* %ptr, <2 x i1> %m ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB3_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -223,7 +223,7 @@ define <4 x i32> @masked_gather_v4i32(<4 x i32*> %ptrs, <4 x i1> %masks, <4 x i3 ; NOGATHER-LABEL: masked_gather_v4i32: ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vpextrb $0, %xmm1, %eax -; NOGATHER-NEXT: # implicit-def: %XMM3 +; NOGATHER-NEXT: # implicit-def: %xmm3 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB4_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -281,7 +281,7 @@ define <4 x float> @masked_gather_v4float(<4 x float*> %ptrs, <4 x i1> %masks, < ; NOGATHER-LABEL: masked_gather_v4float: ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vpextrb $0, %xmm1, %eax -; NOGATHER-NEXT: # implicit-def: %XMM3 +; NOGATHER-NEXT: # implicit-def: %xmm3 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB5_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -351,7 +351,7 @@ define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i3 ; NOGATHER-NEXT: vmovdqa (%rdi), %ymm4 ; NOGATHER-NEXT: vmovdqa 32(%rdi), %ymm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %YMM2 +; NOGATHER-NEXT: # implicit-def: %ymm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB6_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -466,7 +466,7 @@ define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, < ; NOGATHER-NEXT: vmovdqa (%rdi), %ymm4 ; NOGATHER-NEXT: vmovdqa 32(%rdi), %ymm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %YMM2 +; NOGATHER-NEXT: # implicit-def: %ymm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB7_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -579,7 +579,7 @@ define <4 x i64> @masked_gather_v4i64(<4 x i64*>* %ptr, <4 x i1> %masks, <4 x i6 ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %ymm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %YMM2 +; NOGATHER-NEXT: # implicit-def: %ymm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB8_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -656,7 +656,7 @@ define <4 x double> @masked_gather_v4double(<4 x double*>* %ptr, <4 x i1> %masks ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %ymm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %YMM2 +; NOGATHER-NEXT: # implicit-def: %ymm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB9_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -727,7 +727,7 @@ define <2 x i64> @masked_gather_v2i64(<2 x i64*>* %ptr, <2 x i1> %masks, <2 x i6 ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB10_2 ; NOGATHER-NEXT: # BB#1: # %cond.load @@ -772,7 +772,7 @@ define <2 x double> @masked_gather_v2double(<2 x double*>* %ptr, <2 x i1> %masks ; NOGATHER: # BB#0: # %entry ; NOGATHER-NEXT: vmovdqa (%rdi), %xmm3 ; NOGATHER-NEXT: vpextrb $0, %xmm0, %eax -; NOGATHER-NEXT: # implicit-def: %XMM2 +; NOGATHER-NEXT: # implicit-def: %xmm2 ; NOGATHER-NEXT: testb $1, %al ; NOGATHER-NEXT: je .LBB11_2 ; NOGATHER-NEXT: # BB#1: # %cond.load diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll index 650fdd3af01..8db4cae4970 100644 --- a/test/CodeGen/X86/avx2-shift.ll +++ b/test/CodeGen/X86/avx2-shift.ll @@ -532,7 +532,7 @@ define <8 x i16> @variable_shl16(<8 x i16> %lhs, <8 x i16> %rhs) { ; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -543,7 +543,7 @@ define <8 x i16> @variable_shl16(<8 x i16> %lhs, <8 x i16> %rhs) { ; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = shl <8 x i16> %lhs, %rhs @@ -582,7 +582,7 @@ define <8 x i16> @variable_lshr16(<8 x i16> %lhs, <8 x i16> %rhs) { ; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -593,7 +593,7 @@ define <8 x i16> @variable_lshr16(<8 x i16> %lhs, <8 x i16> %rhs) { ; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %res = lshr <8 x i16> %lhs, %rhs diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll index 36ab1be8a4a..f5909f22210 100644 --- a/test/CodeGen/X86/avx2-vector-shifts.ll +++ b/test/CodeGen/X86/avx2-vector-shifts.ll @@ -409,7 +409,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind { ; X32-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -420,7 +420,7 @@ define <8 x i16> @shl_8i16(<8 x i16> %r, <8 x i16> %a) nounwind { ; X64-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %shl = shl <8 x i16> %r, %a @@ -617,7 +617,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind { ; X32-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -628,7 +628,7 @@ define <8 x i16> @lshr_8i16(<8 x i16> %r, <8 x i16> %a) nounwind { ; X64-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; X64-NEXT: vzeroupper ; X64-NEXT: retq %lshr = lshr <8 x i16> %r, %a diff --git a/test/CodeGen/X86/avx512-arith.ll b/test/CodeGen/X86/avx512-arith.ll index 1bcd3c60e3b..51c3fb815c6 100644 --- a/test/CodeGen/X86/avx512-arith.ll +++ b/test/CodeGen/X86/avx512-arith.ll @@ -176,10 +176,10 @@ define <4 x i64> @imulq256(<4 x i64> %y, <4 x i64> %x) { ; ; AVX512DQ-LABEL: imulq256: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; SKX-LABEL: imulq256: @@ -229,10 +229,10 @@ define <2 x i64> @imulq128(<2 x i64> %y, <2 x i64> %x) { ; ; AVX512DQ-LABEL: imulq128: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vpmullq %zmm0, %zmm1, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -717,7 +717,7 @@ define <16 x float> @test_mask_vminps(<16 x float> %dst, <16 x float> %i, define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i, ; AVX512F-LABEL: test_mask_vminpd: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512F-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} @@ -732,7 +732,7 @@ define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i, ; ; AVX512BW-LABEL: test_mask_vminpd: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512BW-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} @@ -740,7 +740,7 @@ define <8 x double> @test_mask_vminpd(<8 x double> %dst, <8 x double> %i, ; ; AVX512DQ-LABEL: test_mask_vminpd: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512DQ-NEXT: vminpd %zmm2, %zmm1, %zmm0 {%k1} @@ -780,7 +780,7 @@ define <16 x float> @test_mask_vmaxps(<16 x float> %dst, <16 x float> %i, define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i, ; AVX512F-LABEL: test_mask_vmaxpd: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512F-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512F-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512F-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512F-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} @@ -795,7 +795,7 @@ define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i, ; ; AVX512BW-LABEL: test_mask_vmaxpd: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512BW-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512BW-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512BW-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512BW-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} @@ -803,7 +803,7 @@ define <8 x double> @test_mask_vmaxpd(<8 x double> %dst, <8 x double> %i, ; ; AVX512DQ-LABEL: test_mask_vmaxpd: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> +; AVX512DQ-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> ; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; AVX512DQ-NEXT: vpcmpneqd %zmm4, %zmm3, %k1 ; AVX512DQ-NEXT: vmaxpd %zmm2, %zmm1, %zmm0 {%k1} diff --git a/test/CodeGen/X86/avx512-build-vector.ll b/test/CodeGen/X86/avx512-build-vector.ll index 01c74de69ce..a79a053941d 100644 --- a/test/CodeGen/X86/avx512-build-vector.ll +++ b/test/CodeGen/X86/avx512-build-vector.ll @@ -14,7 +14,7 @@ define <16 x i32> @test2(<16 x i32> %x) { define <16 x float> @test3(<4 x float> %a) { ; CHECK-LABEL: test3: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; CHECK-NEXT: vmovaps {{.*#+}} zmm2 = [0,1,2,3,4,18,16,7,8,9,10,11,12,13,14,15] ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1 diff --git a/test/CodeGen/X86/avx512-calling-conv.ll b/test/CodeGen/X86/avx512-calling-conv.ll index fd7bc675cb3..60c454ae16c 100644 --- a/test/CodeGen/X86/avx512-calling-conv.ll +++ b/test/CodeGen/X86/avx512-calling-conv.ll @@ -124,7 +124,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) { ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: callq _func8xi1 ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL-NEXT: vpslld $31, %ymm0, %ymm0 @@ -152,7 +152,7 @@ define <8 x i32> @test5(<8 x i32>%a, <8 x i32>%b) { ; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0 -; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_X32-NEXT: calll _func8xi1 ; KNL_X32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL_X32-NEXT: vpslld $31, %ymm0, %ymm0 @@ -264,7 +264,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) { ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: callq _func8xi1 ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 @@ -299,7 +299,7 @@ define <8 x i1> @test7a(<8 x i32>%a, <8 x i32>%b) { ; KNL_X32-NEXT: .cfi_def_cfa_offset 16 ; KNL_X32-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; KNL_X32-NEXT: vpmovdw %zmm0, %ymm0 -; KNL_X32-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_X32-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_X32-NEXT: calll _func8xi1 ; KNL_X32-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL_X32-NEXT: vpsllq $63, %zmm0, %zmm0 diff --git a/test/CodeGen/X86/avx512-cmp-kor-sequence.ll b/test/CodeGen/X86/avx512-cmp-kor-sequence.ll index e29cf09718a..e8881294671 100644 --- a/test/CodeGen/X86/avx512-cmp-kor-sequence.ll +++ b/test/CodeGen/X86/avx512-cmp-kor-sequence.ll @@ -19,7 +19,7 @@ define zeroext i16 @cmp_kor_seq_16(<16 x float> %a, <16 x float> %b, <16 x float ; CHECK-NEXT: korw %k2, %k1, %k1 ; CHECK-NEXT: korw %k1, %k0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: %0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %x, i32 13, i16 -1, i32 4) diff --git a/test/CodeGen/X86/avx512-cvt.ll b/test/CodeGen/X86/avx512-cvt.ll index f9c1b421b24..e20a177f722 100644 --- a/test/CodeGen/X86/avx512-cvt.ll +++ b/test/CodeGen/X86/avx512-cvt.ll @@ -80,9 +80,9 @@ define <4 x double> @slto4f64(<4 x i64> %a) { ; ; AVX512DQ-LABEL: slto4f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq %b = sitofp <4 x i64> %a to <4 x double> ret <4 x double> %b @@ -105,9 +105,9 @@ define <2 x double> @slto2f64(<2 x i64> %a) { ; ; AVX512DQ-LABEL: slto2f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = sitofp <2 x i64> %a to <2 x double> @@ -133,9 +133,9 @@ define <2 x float> @sltof2f32(<2 x i64> %a) { ; ; AVX512DQ-LABEL: sltof2f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = sitofp <2 x i64> %a to <2 x float> @@ -170,7 +170,7 @@ define <4 x float> @slto4f32_mem(<4 x i64>* %a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovups (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %a1 = load <4 x i64>, <4 x i64>* %a, align 8 @@ -204,9 +204,9 @@ define <4 x i64> @f64to4sl(<4 x double> %a) { ; ; AVX512DQ-LABEL: f64to4sl: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq %b = fptosi <4 x double> %a to <4 x i64> ret <4 x i64> %b @@ -238,9 +238,9 @@ define <4 x i64> @f32to4sl(<4 x float> %a) { ; ; AVX512DQ-LABEL: f32to4sl: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq %b = fptosi <4 x float> %a to <4 x i64> ret <4 x i64> %b @@ -272,9 +272,9 @@ define <4 x float> @slto4f32(<4 x i64> %a) { ; ; AVX512DQ-LABEL: slto4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = sitofp <4 x i64> %a to <4 x float> @@ -307,9 +307,9 @@ define <4 x float> @ulto4f32(<4 x i64> %a) { ; ; AVX512DQ-LABEL: ulto4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = uitofp <4 x i64> %a to <4 x float> @@ -463,9 +463,9 @@ define <16 x i16> @f32to16us(<16 x float> %f) { define <8 x i32> @f32to8ui(<8 x float> %a) nounwind { ; NOVL-LABEL: f32to8ui: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0 -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: f32to8ui: @@ -479,9 +479,9 @@ define <8 x i32> @f32to8ui(<8 x float> %a) nounwind { define <4 x i32> @f32to4ui(<4 x float> %a) nounwind { ; NOVL-LABEL: f32to4ui: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; NOVL-NEXT: vcvttps2udq %zmm0, %zmm0 -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; NOVL-NEXT: vzeroupper ; NOVL-NEXT: retq ; @@ -507,7 +507,7 @@ define <8 x i16> @f64to8us(<8 x double> %f) { ; NOVL: # BB#0: ; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0 ; NOVL-NEXT: vpmovdw %zmm0, %ymm0 -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; NOVL-NEXT: vzeroupper ; NOVL-NEXT: retq ; @@ -526,7 +526,7 @@ define <8 x i8> @f64to8uc(<8 x double> %f) { ; NOVL: # BB#0: ; NOVL-NEXT: vcvttpd2dq %zmm0, %ymm0 ; NOVL-NEXT: vpmovdw %zmm0, %ymm0 -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; NOVL-NEXT: vzeroupper ; NOVL-NEXT: retq ; @@ -543,9 +543,9 @@ define <8 x i8> @f64to8uc(<8 x double> %f) { define <4 x i32> @f64to4ui(<4 x double> %a) nounwind { ; NOVL-LABEL: f64to4ui: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVL-NEXT: vcvttpd2udq %zmm0, %ymm0 -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; NOVL-NEXT: vzeroupper ; NOVL-NEXT: retq ; @@ -1266,9 +1266,9 @@ define <8 x double> @uito8f64_maskz(<8 x i32> %a, i8 %b) nounwind { define <4 x double> @uito4f64(<4 x i32> %a) nounwind { ; NOVL-LABEL: uito4f64: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; NOVL-NEXT: vcvtudq2pd %ymm0, %zmm0 -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: uito4f64: @@ -1300,9 +1300,9 @@ define <8 x double> @uito8f64(<8 x i32> %a) { define <8 x float> @uito8f32(<8 x i32> %a) nounwind { ; NOVL-LABEL: uito8f32: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: uito8f32: @@ -1316,9 +1316,9 @@ define <8 x float> @uito8f32(<8 x i32> %a) nounwind { define <4 x float> @uito4f32(<4 x i32> %a) nounwind { ; NOVL-LABEL: uito4f32: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; NOVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; NOVL-NEXT: vzeroupper ; NOVL-NEXT: retq ; @@ -1535,7 +1535,7 @@ define <8 x double> @sbto8f64(<8 x double> %a) { define <8 x float> @sbto8f32(<8 x float> %a) { ; NOVLDQ-LABEL: sbto8f32: ; NOVLDQ: # BB#0: -; NOVLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVLDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVLDQ-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; NOVLDQ-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; NOVLDQ-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} @@ -1562,7 +1562,7 @@ define <8 x float> @sbto8f32(<8 x float> %a) { ; ; AVX512DQ-LABEL: sbto8f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX512DQ-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0 @@ -1870,13 +1870,13 @@ define <16 x double> @ubto16f64(<16 x i32> %a) { define <8 x float> @ubto8f32(<8 x i32> %a) { ; NOVL-LABEL: ubto8f32: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; NOVL-NEXT: vpmovqd %zmm0, %ymm0 ; NOVL-NEXT: vcvtudq2ps %zmm0, %zmm0 -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NOVL-NEXT: retq ; ; VL-LABEL: ubto8f32: @@ -1894,7 +1894,7 @@ define <8 x float> @ubto8f32(<8 x i32> %a) { define <8 x double> @ubto8f64(<8 x i32> %a) { ; NOVL-LABEL: ubto8f64: ; NOVL: # BB#0: -; NOVL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NOVL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NOVL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; NOVL-NEXT: vpcmpgtd %zmm0, %zmm1, %k1 ; NOVL-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} diff --git a/test/CodeGen/X86/avx512-ext.ll b/test/CodeGen/X86/avx512-ext.ll index 50e8484874e..84698103d4a 100644 --- a/test/CodeGen/X86/avx512-ext.ll +++ b/test/CodeGen/X86/avx512-ext.ll @@ -348,7 +348,7 @@ define <8 x i32> @zext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind re ; KNL-NEXT: vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: zext_8x8mem_to_8x32: @@ -372,7 +372,7 @@ define <8 x i32> @sext_8x8mem_to_8x32(<8 x i8> *%i , <8 x i1> %mask) nounwind re ; KNL-NEXT: vpmovsxbd (%rdi), %ymm1 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: sext_8x8mem_to_8x32: @@ -705,7 +705,7 @@ define <8 x i32> @zext_8x16mem_to_8x32(<8 x i16> *%i , <8 x i1> %mask) nounwind ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: zext_8x16mem_to_8x32: @@ -729,7 +729,7 @@ define <8 x i32> @sext_8x16mem_to_8x32mask(<8 x i16> *%i , <8 x i1> %mask) nounw ; KNL-NEXT: vpmovsxwd (%rdi), %ymm1 ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: sext_8x16mem_to_8x32mask: @@ -763,7 +763,7 @@ define <8 x i32> @zext_8x16_to_8x32mask(<8 x i16> %a , <8 x i1> %mask) nounwind ; KNL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; KNL-NEXT: vmovdqa32 %zmm1, %zmm0 {%k1} -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: zext_8x16_to_8x32mask: @@ -1328,7 +1328,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) { ; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: trunc_16i8_to_16i1: @@ -1336,7 +1336,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) { ; SKX-NEXT: vpsllw $7, %xmm0, %xmm0 ; SKX-NEXT: vpmovb2m %xmm0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq %mask_b = trunc <16 x i8>%a to <16 x i1> %mask = bitcast <16 x i1> %mask_b to i16 @@ -1349,7 +1349,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i32> %a) { ; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: trunc_16i32_to_16i1: @@ -1357,7 +1357,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i32> %a) { ; SKX-NEXT: vpslld $31, %zmm0, %zmm0 ; SKX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %mask_b = trunc <16 x i32>%a to <16 x i1> @@ -1396,7 +1396,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) { ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: trunc_8i16_to_8i1: @@ -1404,7 +1404,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) { ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: vpmovw2m %xmm0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq %mask_b = trunc <8 x i16>%a to <8 x i1> %mask = bitcast <8 x i1> %mask_b to i8 @@ -1442,7 +1442,7 @@ define i16 @trunc_i32_to_i1(i32 %a) { ; KNL-NEXT: kmovw %edi, %k1 ; KNL-NEXT: korw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: trunc_i32_to_i1: @@ -1455,7 +1455,7 @@ define i16 @trunc_i32_to_i1(i32 %a) { ; SKX-NEXT: kmovw %edi, %k1 ; SKX-NEXT: korw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq %a_i = trunc i32 %a to i1 %maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0 @@ -1468,7 +1468,7 @@ define <8 x i16> @sext_8i1_8i16(<8 x i32> %a1, <8 x i32> %a2) nounwind { ; KNL: # BB#0: ; KNL-NEXT: vpcmpgtd %ymm0, %ymm1, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: sext_8i1_8i16: diff --git a/test/CodeGen/X86/avx512-extract-subvector.ll b/test/CodeGen/X86/avx512-extract-subvector.ll index 1b70955e62c..8a63f5b8c09 100644 --- a/test/CodeGen/X86/avx512-extract-subvector.ll +++ b/test/CodeGen/X86/avx512-extract-subvector.ll @@ -15,7 +15,7 @@ define <8 x i16> @extract_subvector128_v32i16(<32 x i16> %x) nounwind { define <8 x i16> @extract_subvector128_v32i16_first_element(<32 x i16> %x) nounwind { ; SKX-LABEL: extract_subvector128_v32i16_first_element: ; SKX: ## BB#0: -; SKX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %r1 = shufflevector <32 x i16> %x, <32 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -35,7 +35,7 @@ define <16 x i8> @extract_subvector128_v64i8(<64 x i8> %x) nounwind { define <16 x i8> @extract_subvector128_v64i8_first_element(<64 x i8> %x) nounwind { ; SKX-LABEL: extract_subvector128_v64i8_first_element: ; SKX: ## BB#0: -; SKX-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; SKX-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %r1 = shufflevector <64 x i8> %x, <64 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> diff --git a/test/CodeGen/X86/avx512-hadd-hsub.ll b/test/CodeGen/X86/avx512-hadd-hsub.ll index dbff628ed63..3b76050fa21 100644 --- a/test/CodeGen/X86/avx512-hadd-hsub.ll +++ b/test/CodeGen/X86/avx512-hadd-hsub.ll @@ -63,7 +63,7 @@ define float @fhadd_16(<16 x float> %x225) { ; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0 -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: fhadd_16: @@ -72,7 +72,7 @@ define float @fhadd_16(<16 x float> %x225) { ; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0 -; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -90,7 +90,7 @@ define float @fhsub_16(<16 x float> %x225) { ; KNL-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; KNL-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; KNL-NEXT: vsubps %zmm1, %zmm0, %zmm0 -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: fhsub_16: @@ -99,7 +99,7 @@ define float @fhsub_16(<16 x float> %x225) { ; SKX-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SKX-NEXT: vsubps %zmm1, %zmm0, %zmm0 -; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %x226 = shufflevector <16 x float> %x225, <16 x float> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -181,7 +181,7 @@ define <4 x double> @fadd_noundef_low(<8 x double> %x225, <8 x double> %x227) { ; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0 -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: fadd_noundef_low: @@ -189,7 +189,7 @@ define <4 x double> @fadd_noundef_low(<8 x double> %x225, <8 x double> %x227) { ; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0 -; SKX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; SKX-NEXT: retq %x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %x228 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5 ,i32 13, i32 7, i32 15> @@ -228,7 +228,7 @@ define <8 x i32> @hadd_16_3_sv(<16 x i32> %x225, <16 x i32> %x227) { ; KNL-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14] ; KNL-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15] ; KNL-NEXT: vpaddd %zmm0, %zmm2, %zmm0 -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: hadd_16_3_sv: @@ -236,7 +236,7 @@ define <8 x i32> @hadd_16_3_sv(<16 x i32> %x225, <16 x i32> %x227) { ; SKX-NEXT: vshufps {{.*#+}} zmm2 = zmm0[0,2],zmm1[0,2],zmm0[4,6],zmm1[4,6],zmm0[8,10],zmm1[8,10],zmm0[12,14],zmm1[12,14] ; SKX-NEXT: vshufps {{.*#+}} zmm0 = zmm0[1,3],zmm1[1,3],zmm0[5,7],zmm1[5,7],zmm0[9,11],zmm1[9,11],zmm0[13,15],zmm1[13,15] ; SKX-NEXT: vpaddd %zmm0, %zmm2, %zmm0 -; SKX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; SKX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; SKX-NEXT: retq %x226 = shufflevector <16 x i32> %x225, <16 x i32> %x227, <16 x i32> <i32 0, i32 2, i32 16, i32 18 , i32 4, i32 6, i32 20, i32 22, i32 8, i32 10, i32 24, i32 26, i32 12, i32 14, i32 28, i32 30> @@ -255,7 +255,7 @@ define double @fadd_noundef_eel(<8 x double> %x225, <8 x double> %x227) { ; KNL-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; KNL-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; KNL-NEXT: vaddpd %zmm0, %zmm2, %zmm0 -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: fadd_noundef_eel: @@ -263,7 +263,7 @@ define double @fadd_noundef_eel(<8 x double> %x225, <8 x double> %x227) { ; SKX-NEXT: vunpcklpd {{.*#+}} zmm2 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6] ; SKX-NEXT: vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7] ; SKX-NEXT: vaddpd %zmm0, %zmm2, %zmm0 -; SKX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; SKX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %x226 = shufflevector <8 x double> %x225, <8 x double> %x227, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll index 6c2b66b8c5c..091bb39d178 100644 --- a/test/CodeGen/X86/avx512-insert-extract.ll +++ b/test/CodeGen/X86/avx512-insert-extract.ll @@ -85,7 +85,7 @@ define float @test7(<16 x float> %x, i32 %ind) nounwind { ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -104,7 +104,7 @@ define double @test8(<8 x double> %x, i32 %ind) nounwind { ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero @@ -123,7 +123,7 @@ define float @test9(<8 x float> %x, i32 %ind) nounwind { ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -142,7 +142,7 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind { ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: movl (%rsp,%rdi,4), %eax @@ -237,7 +237,7 @@ define i16 @test13(i32 %a, i32 %b) { ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: korw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test13: @@ -252,7 +252,7 @@ define i16 @test13(i32 %a, i32 %b) { ; SKX-NEXT: kmovw %eax, %k1 ; SKX-NEXT: korw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq %cmp_res = icmp ult i32 %a, %b %maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0 @@ -318,7 +318,7 @@ define i16 @test16(i1 *%addr, i16 %a) { ; KNL-NEXT: vpslld $31, %zmm2, %zmm0 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -332,7 +332,7 @@ define i16 @test16(i1 *%addr, i16 %a) { ; SKX-NEXT: vpermi2d %zmm0, %zmm1, %zmm2 ; SKX-NEXT: vpmovd2m %zmm2, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %x = load i1 , i1 * %addr, align 128 @@ -355,7 +355,7 @@ define i8 @test17(i1 *%addr, i8 %a) { ; KNL-NEXT: vpsllq $63, %zmm2, %zmm0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -369,7 +369,7 @@ define i8 @test17(i1 *%addr, i8 %a) { ; SKX-NEXT: vpermi2q %zmm0, %zmm1, %zmm2 ; SKX-NEXT: vpmovq2m %zmm2, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %x = load i1 , i1 * %addr, align 128 @@ -465,7 +465,7 @@ define i16 @extract_v32i16(<32 x i16> %x, i16* %dst) { ; CHECK-NEXT: vpextrw $1, %xmm0, %eax ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vpextrw $1, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %r1 = extractelement <32 x i16> %x, i32 1 @@ -480,7 +480,7 @@ define i16 @extract_v16i16(<16 x i16> %x, i16* %dst) { ; CHECK-NEXT: vpextrw $1, %xmm0, %eax ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vpextrw $1, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %r1 = extractelement <16 x i16> %x, i32 1 @@ -494,7 +494,7 @@ define i16 @extract_v8i16(<8 x i16> %x, i16* %dst) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpextrw $1, %xmm0, %eax ; CHECK-NEXT: vpextrw $3, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %r1 = extractelement <8 x i16> %x, i32 1 %r2 = extractelement <8 x i16> %x, i32 3 @@ -508,7 +508,7 @@ define i8 @extract_v64i8(<64 x i8> %x, i8* %dst) { ; CHECK-NEXT: vpextrb $1, %xmm0, %eax ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vpextrb $1, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %r1 = extractelement <64 x i8> %x, i32 1 @@ -523,7 +523,7 @@ define i8 @extract_v32i8(<32 x i8> %x, i8* %dst) { ; CHECK-NEXT: vpextrb $1, %xmm0, %eax ; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vpextrb $1, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %r1 = extractelement <32 x i8> %x, i32 1 @@ -537,7 +537,7 @@ define i8 @extract_v16i8(<16 x i8> %x, i8* %dst) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpextrb $1, %xmm0, %eax ; CHECK-NEXT: vpextrb $3, %xmm0, (%rdi) -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %r1 = extractelement <16 x i8> %x, i32 1 %r2 = extractelement <16 x i8> %x, i32 3 @@ -1013,7 +1013,7 @@ define i8 @test_iinsertelement_v4i1(i32 %a, i32 %b, <4 x i32> %x , <4 x i32> %y) ; KNL-NEXT: vpsllq $63, %zmm2, %zmm0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -1029,7 +1029,7 @@ define i8 @test_iinsertelement_v4i1(i32 %a, i32 %b, <4 x i32> %x , <4 x i32> %y) ; SKX-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] ; SKX-NEXT: vpmovd2m %xmm0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq %cmp_res_i1 = icmp ult i32 %a, %b %cmp_cmp_vec = icmp ult <4 x i32> %x, %y @@ -1058,7 +1058,7 @@ define i8 @test_iinsertelement_v2i1(i32 %a, i32 %b, <2 x i64> %x , <2 x i64> %y) ; KNL-NEXT: vpsllq $63, %zmm2, %zmm0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -1073,7 +1073,7 @@ define i8 @test_iinsertelement_v2i1(i32 %a, i32 %b, <2 x i64> %x , <2 x i64> %y) ; SKX-NEXT: kshiftrw $1, %k0, %k0 ; SKX-NEXT: korw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq %cmp_res_i1 = icmp ult i32 %a, %b %cmp_cmp_vec = icmp ult <2 x i64> %x, %y @@ -1268,7 +1268,7 @@ define zeroext i8 @extractelement_v64i1_alt(<64 x i8> %a, <64 x i8> %b) { define i64 @test_extractelement_variable_v2i64(<2 x i64> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v2i64: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: movq -24(%rsp,%rdi,8), %rax @@ -1287,7 +1287,7 @@ define i64 @test_extractelement_variable_v4i64(<4 x i64> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $3, %edi ; CHECK-NEXT: movq (%rsp,%rdi,8), %rax @@ -1309,7 +1309,7 @@ define i64 @test_extractelement_variable_v8i64(<8 x i64> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: movq (%rsp,%rdi,8), %rax @@ -1324,7 +1324,7 @@ define i64 @test_extractelement_variable_v8i64(<8 x i64> %t1, i32 %index) { define double @test_extractelement_variable_v2f64(<2 x double> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v2f64: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero @@ -1343,7 +1343,7 @@ define double @test_extractelement_variable_v4f64(<4 x double> %t1, i32 %index) ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $3, %edi ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero @@ -1365,7 +1365,7 @@ define double @test_extractelement_variable_v8f64(<8 x double> %t1, i32 %index) ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero @@ -1380,7 +1380,7 @@ define double @test_extractelement_variable_v8f64(<8 x double> %t1, i32 %index) define i32 @test_extractelement_variable_v4i32(<4 x i32> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v4i32: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $3, %edi ; CHECK-NEXT: movl -24(%rsp,%rdi,4), %eax @@ -1399,7 +1399,7 @@ define i32 @test_extractelement_variable_v8i32(<8 x i32> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: movl (%rsp,%rdi,4), %eax @@ -1421,7 +1421,7 @@ define i32 @test_extractelement_variable_v16i32(<16 x i32> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: movl (%rsp,%rdi,4), %eax @@ -1436,7 +1436,7 @@ define i32 @test_extractelement_variable_v16i32(<16 x i32> %t1, i32 %index) { define float @test_extractelement_variable_v4f32(<4 x float> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v4f32: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $3, %edi ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -1455,7 +1455,7 @@ define float @test_extractelement_variable_v8f32(<8 x float> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -1477,7 +1477,7 @@ define float @test_extractelement_variable_v16f32(<16 x float> %t1, i32 %index) ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-64, %rsp ; CHECK-NEXT: subq $128, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %zmm0, (%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -1492,7 +1492,7 @@ define float @test_extractelement_variable_v16f32(<16 x float> %t1, i32 %index) define i16 @test_extractelement_variable_v8i16(<8 x i16> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v8i16: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $7, %edi ; CHECK-NEXT: movzwl -24(%rsp,%rdi,2), %eax @@ -1511,7 +1511,7 @@ define i16 @test_extractelement_variable_v16i16(<16 x i16> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: movzwl (%rsp,%rdi,2), %eax @@ -1533,7 +1533,7 @@ define i16 @test_extractelement_variable_v32i16(<32 x i16> %t1, i32 %index) { ; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: subq $128, %rsp -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: andl $31, %edi @@ -1552,7 +1552,7 @@ define i16 @test_extractelement_variable_v32i16(<32 x i16> %t1, i32 %index) { ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: andl $31, %edi ; SKX-NEXT: movzwl (%rsp,%rdi,2), %eax @@ -1567,7 +1567,7 @@ define i16 @test_extractelement_variable_v32i16(<32 x i16> %t1, i32 %index) { define i8 @test_extractelement_variable_v16i8(<16 x i8> %t1, i32 %index) { ; CHECK-LABEL: test_extractelement_variable_v16i8: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax @@ -1587,7 +1587,7 @@ define i8 @test_extractelement_variable_v32i8(<32 x i8> %t1, i32 %index) { ; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: andq $-32, %rsp ; CHECK-NEXT: subq $64, %rsp -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: vmovaps %ymm0, (%rsp) ; CHECK-NEXT: andl $31, %edi ; CHECK-NEXT: movq %rsp, %rax @@ -1611,7 +1611,7 @@ define i8 @test_extractelement_variable_v64i8(<64 x i8> %t1, i32 %index) { ; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: subq $128, %rsp -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp) ; KNL-NEXT: vmovaps %ymm0, (%rsp) ; KNL-NEXT: andl $63, %edi @@ -1631,7 +1631,7 @@ define i8 @test_extractelement_variable_v64i8(<64 x i8> %t1, i32 %index) { ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vmovaps %zmm0, (%rsp) ; SKX-NEXT: andl $63, %edi ; SKX-NEXT: movq %rsp, %rax @@ -1695,7 +1695,7 @@ define i8 @test_extractelement_variable_v64i8_indexi8(<64 x i8> %t1, i8 %index) define zeroext i8 @test_extractelement_varible_v2i1(<2 x i64> %a, <2 x i64> %b, i32 %index) { ; KNL-LABEL: test_extractelement_varible_v2i1: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0 @@ -1708,7 +1708,7 @@ define zeroext i8 @test_extractelement_varible_v2i1(<2 x i64> %a, <2 x i64> %b, ; ; SKX-LABEL: test_extractelement_varible_v2i1: ; SKX: ## BB#0: -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleuq %xmm1, %xmm0, %k0 ; SKX-NEXT: vpmovm2q %k0, %xmm0 ; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp) @@ -1725,7 +1725,7 @@ define zeroext i8 @test_extractelement_varible_v2i1(<2 x i64> %a, <2 x i64> %b, define zeroext i8 @test_extractelement_varible_v4i1(<4 x i32> %a, <4 x i32> %b, i32 %index) { ; KNL-LABEL: test_extractelement_varible_v4i1: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; KNL-NEXT: vpxor %xmm2, %xmm1, %xmm1 ; KNL-NEXT: vpxor %xmm2, %xmm0, %xmm0 @@ -1738,7 +1738,7 @@ define zeroext i8 @test_extractelement_varible_v4i1(<4 x i32> %a, <4 x i32> %b, ; ; SKX-LABEL: test_extractelement_varible_v4i1: ; SKX: ## BB#0: -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleud %xmm1, %xmm0, %k0 ; SKX-NEXT: vpmovm2d %k0, %xmm0 ; SKX-NEXT: vmovdqa %xmm0, -{{[0-9]+}}(%rsp) @@ -1762,9 +1762,9 @@ define zeroext i8 @test_extractelement_varible_v8i1(<8 x i32> %a, <8 x i32> %b, ; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: subq $128, %rsp -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> -; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> +; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1 ; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vmovdqa64 %zmm0, (%rsp) @@ -1785,7 +1785,7 @@ define zeroext i8 @test_extractelement_varible_v8i1(<8 x i32> %a, <8 x i32> %b, ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleud %ymm1, %ymm0, %k0 ; SKX-NEXT: vpmovm2q %k0, %zmm0 ; SKX-NEXT: vmovdqa64 %zmm0, (%rsp) @@ -1812,7 +1812,7 @@ define zeroext i8 @test_extractelement_varible_v16i1(<16 x i32> %a, <16 x i32> % ; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: andq $-64, %rsp ; KNL-NEXT: subq $128, %rsp -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vpcmpnleud %zmm1, %zmm0, %k1 ; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vmovdqa32 %zmm0, (%rsp) @@ -1833,7 +1833,7 @@ define zeroext i8 @test_extractelement_varible_v16i1(<16 x i32> %a, <16 x i32> % ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleud %zmm1, %zmm0, %k0 ; SKX-NEXT: vpmovm2d %k0, %zmm0 ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) @@ -1860,7 +1860,7 @@ define zeroext i8 @test_extractelement_varible_v32i1(<32 x i8> %a, <32 x i8> %b, ; KNL-NEXT: .cfi_def_cfa_register %rbp ; KNL-NEXT: andq $-32, %rsp ; KNL-NEXT: subq $64, %rsp -; KNL-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; KNL-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; KNL-NEXT: vmovdqa {{.*#+}} ymm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; KNL-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; KNL-NEXT: vpxor %ymm2, %ymm0, %ymm0 @@ -1884,7 +1884,7 @@ define zeroext i8 @test_extractelement_varible_v32i1(<32 x i8> %a, <32 x i8> %b, ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleub %ymm1, %ymm0, %k0 ; SKX-NEXT: vpmovm2w %k0, %zmm0 ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) diff --git a/test/CodeGen/X86/avx512-insert-extract_i1.ll b/test/CodeGen/X86/avx512-insert-extract_i1.ll index 37ca066c130..ebe99c1ec87 100644 --- a/test/CodeGen/X86/avx512-insert-extract_i1.ll +++ b/test/CodeGen/X86/avx512-insert-extract_i1.ll @@ -13,7 +13,7 @@ define zeroext i8 @test_extractelement_varible_v64i1(<64 x i8> %a, <64 x i8> %b, ; SKX-NEXT: .cfi_def_cfa_register %rbp ; SKX-NEXT: andq $-64, %rsp ; SKX-NEXT: subq $128, %rsp -; SKX-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; SKX-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; SKX-NEXT: vpcmpnleub %zmm1, %zmm0, %k0 ; SKX-NEXT: vpmovm2b %k0, %zmm0 ; SKX-NEXT: vmovdqa32 %zmm0, (%rsp) diff --git a/test/CodeGen/X86/avx512-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512-intrinsics-upgrade.ll index 8d712863efb..ef15a85e500 100644 --- a/test/CodeGen/X86/avx512-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512-intrinsics-upgrade.ll @@ -544,7 +544,7 @@ define i16 @test_pcmpeq_d(<16 x i32> %a, <16 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1) ret i16 %res @@ -556,7 +556,7 @@ define i16 @test_mask_pcmpeq_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.pcmpeq.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask) ret i16 %res @@ -569,7 +569,7 @@ define i8 @test_pcmpeq_q(<8 x i64> %a, <8 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1) ret i8 %res @@ -581,7 +581,7 @@ define i8 @test_mask_pcmpeq_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) ret i8 %res @@ -594,7 +594,7 @@ define i16 @test_pcmpgt_d(<16 x i32> %a, <16 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 -1) ret i16 %res @@ -606,7 +606,7 @@ define i16 @test_mask_pcmpgt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.pcmpgt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask) ret i16 %res @@ -619,7 +619,7 @@ define i8 @test_pcmpgt_q(<8 x i64> %a, <8 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 -1) ret i8 %res @@ -631,7 +631,7 @@ define i8 @test_mask_pcmpgt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask) ret i8 %res @@ -3095,7 +3095,7 @@ declare <16 x float> @llvm.x86.avx512.mask.insertf32x4.512(<16 x float>, <4 x fl define <16 x float>@test_int_x86_avx512_mask_insertf32x4_512(<16 x float> %x0, <4 x float> %x1, <16 x float> %x3, i16 %x4) { ; CHECK-LABEL: test_int_x86_avx512_mask_insertf32x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm3 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinsertf32x4 $1, %xmm1, %zmm0, %zmm2 {%k1} @@ -3116,7 +3116,7 @@ declare <16 x i32> @llvm.x86.avx512.mask.inserti32x4.512(<16 x i32>, <4 x i32>, define <16 x i32>@test_int_x86_avx512_mask_inserti32x4_512(<16 x i32> %x0, <4 x i32> %x1, <16 x i32> %x3, i16 %x4) { ; CHECK-LABEL: test_int_x86_avx512_mask_inserti32x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; CHECK-NEXT: vinserti32x4 $1, %xmm1, %zmm0, %zmm3 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinserti32x4 $1, %xmm1, %zmm0, %zmm2 {%k1} @@ -3560,7 +3560,7 @@ declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x4.512(<4 x float>, <16 x define <16 x float>@test_int_x86_avx512_mask_broadcastf32x4_512(<4 x float> %x0, <16 x float> %x2, i16 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; CHECK-NEXT: kmovw %edi, %k1 @@ -3594,7 +3594,7 @@ declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x4.512(<4 x double>, <8 x define <8 x double>@test_int_x86_avx512_mask_broadcastf64x4_512(<4 x double> %x0, <8 x double> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm1 {%k1} @@ -3628,7 +3628,7 @@ declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x4.512(<4 x i32>, <16 x i32 define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x4_512(<4 x i32> %x0, <16 x i32> %x2, i16 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 ; CHECK-NEXT: kmovw %edi, %k1 @@ -3663,7 +3663,7 @@ declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x4.512(<4 x i64>, <8 x i64>, define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x4_512(<4 x i64> %x0, <8 x i64> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x4_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm1 {%k1} @@ -3733,7 +3733,7 @@ define i8 @test_vptestmq(<8 x i64> %a0, <8 x i64> %a1, i8 %m) { ; CHECK-NEXT: vptestmq %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addb %cl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 -1) %res1 = call i8 @llvm.x86.avx512.ptestm.q.512(<8 x i64> %a0, <8 x i64> %a1, i8 %m) @@ -3751,7 +3751,7 @@ define i16 @test_vptestmd(<16 x i32> %a0, <16 x i32> %a1, i16 %m) { ; CHECK-NEXT: vptestmd %zmm1, %zmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 -1) %res1 = call i16 @llvm.x86.avx512.ptestm.d.512(<16 x i32> %a0, <16 x i32> %a1, i16 %m) @@ -3771,7 +3771,7 @@ define i16@test_int_x86_avx512_ptestnm_d_512(<16 x i32> %x0, <16 x i32> %x1, i16 ; CHECK-NEXT: kmovw %k1, %ecx ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.ptestnm.d.512(<16 x i32> %x0, <16 x i32> %x1, i16 %x2) %res1 = call i16 @llvm.x86.avx512.ptestnm.d.512(<16 x i32> %x0, <16 x i32> %x1, i16-1) @@ -3790,7 +3790,7 @@ define i8@test_int_x86_avx512_ptestnm_q_512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2 ; CHECK-NEXT: kmovw %k1, %ecx ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addb %cl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.ptestnm.q.512(<8 x i64> %x0, <8 x i64> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.q.512(<8 x i64> %x0, <8 x i64> %x1, i8-1) diff --git a/test/CodeGen/X86/avx512-intrinsics.ll b/test/CodeGen/X86/avx512-intrinsics.ll index 5c5be436033..c05a69c4e9a 100644 --- a/test/CodeGen/X86/avx512-intrinsics.ll +++ b/test/CodeGen/X86/avx512-intrinsics.ll @@ -40,7 +40,7 @@ define i16 @test_kand(i16 %a0, i16 %a1) { ; CHECK-NEXT: kandw %k0, %k1, %k0 ; CHECK-NEXT: kandw %k0, %k2, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %t1 = call i16 @llvm.x86.avx512.kand.w(i16 %a0, i16 8) %t2 = call i16 @llvm.x86.avx512.kand.w(i16 %t1, i16 %a1) @@ -58,7 +58,7 @@ define i16 @test_kandn(i16 %a0, i16 %a1) { ; CHECK-NEXT: kandnw %k2, %k1, %k1 ; CHECK-NEXT: kandnw %k0, %k1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %t1 = call i16 @llvm.x86.avx512.kandn.w(i16 %a0, i16 8) %t2 = call i16 @llvm.x86.avx512.kandn.w(i16 %t1, i16 %a1) @@ -72,7 +72,7 @@ define i16 @test_knot(i16 %a0) { ; CHECK-NEXT: kmovw %edi, %k0 ; CHECK-NEXT: knotw %k0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.knot.w(i16 %a0) ret i16 %res @@ -89,7 +89,7 @@ define i16 @test_kor(i16 %a0, i16 %a1) { ; CHECK-NEXT: korw %k0, %k1, %k0 ; CHECK-NEXT: korw %k0, %k2, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %t1 = call i16 @llvm.x86.avx512.kor.w(i16 %a0, i16 8) %t2 = call i16 @llvm.x86.avx512.kor.w(i16 %t1, i16 %a1) @@ -105,7 +105,7 @@ define i16 @unpckbw_test(i16 %a0, i16 %a1) { ; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: kunpckbw %k1, %k0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.kunpck.bw(i16 %a0, i16 %a1) ret i16 %res @@ -124,7 +124,7 @@ define i16 @test_kxnor(i16 %a0, i16 %a1) { ; CHECK-NEXT: kxorw %k0, %k1, %k0 ; CHECK-NEXT: kxorw %k0, %k2, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %t1 = call i16 @llvm.x86.avx512.kxnor.w(i16 %a0, i16 8) %t2 = call i16 @llvm.x86.avx512.kxnor.w(i16 %t1, i16 %a1) @@ -142,7 +142,7 @@ define i16 @test_kxor(i16 %a0, i16 %a1) { ; CHECK-NEXT: kxorw %k0, %k1, %k0 ; CHECK-NEXT: kxorw %k0, %k2, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %t1 = call i16 @llvm.x86.avx512.kxor.w(i16 %a0, i16 8) %t2 = call i16 @llvm.x86.avx512.kxor.w(i16 %t1, i16 %a1) @@ -808,7 +808,7 @@ declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly ; CHECK: ## BB#0: ; CHECK-NEXT: vcmpleps {sae}, %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %a, <16 x float> %b, i32 2, i16 -1, i32 8) ret i16 %res @@ -820,7 +820,7 @@ declare <8 x double> @llvm.x86.avx512.vbroadcast.sd.512(i8*) nounwind readonly ; CHECK: ## BB#0: ; CHECK-NEXT: vcmpneqpd %zmm1, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %a, <8 x double> %b, i32 4, i8 -1, i32 4) ret i8 %res @@ -3309,7 +3309,7 @@ define i8@test_int_x86_avx512_mask_cmp_sd(<2 x double> %x0, <2 x double> %x1, i8 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vcmpnltsd {sae}, %xmm1, %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res4 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 5, i8 %x3, i32 8) @@ -3331,7 +3331,7 @@ define i8@test_int_x86_avx512_mask_cmp_sd_all(<2 x double> %x0, <2 x double> %x1 ; CHECK-NEXT: orb %cl, %dl ; CHECK-NEXT: orb %sil, %al ; CHECK-NEXT: orb %dl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res1 = call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %x0, <2 x double> %x1, i32 2, i8 -1, i32 4) @@ -3353,7 +3353,7 @@ define i8@test_int_x86_avx512_mask_cmp_ss(<4 x float> %x0, <4 x float> %x1, i8 % ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 %x3, i32 4) @@ -3376,7 +3376,7 @@ define i8@test_int_x86_avx512_mask_cmp_ss_all(<4 x float> %x0, <4 x float> %x1, ; CHECK-NEXT: andb %cl, %dl ; CHECK-NEXT: andb %sil, %al ; CHECK-NEXT: andb %dl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res1 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 2, i8 -1, i32 4) %res2 = call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %x0, <4 x float> %x1, i32 3, i8 -1, i32 8) diff --git a/test/CodeGen/X86/avx512-mask-op.ll b/test/CodeGen/X86/avx512-mask-op.ll index b75bd8cc3ee..fe59d4c35c3 100644 --- a/test/CodeGen/X86/avx512-mask-op.ll +++ b/test/CodeGen/X86/avx512-mask-op.ll @@ -11,7 +11,7 @@ define i16 @mask16(i16 %x) { ; KNL-NEXT: kmovw %edi, %k0 ; KNL-NEXT: knotw %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: mask16: @@ -19,7 +19,7 @@ define i16 @mask16(i16 %x) { ; SKX-NEXT: kmovd %edi, %k0 ; SKX-NEXT: knotw %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: mask16: @@ -27,7 +27,7 @@ define i16 @mask16(i16 %x) { ; AVX512BW-NEXT: kmovd %edi, %k0 ; AVX512BW-NEXT: knotw %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: mask16: @@ -35,7 +35,7 @@ define i16 @mask16(i16 %x) { ; AVX512DQ-NEXT: kmovw %edi, %k0 ; AVX512DQ-NEXT: knotw %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i16 %x to <16 x i1> %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> @@ -84,7 +84,7 @@ define i8 @mask8(i8 %x) { ; KNL-NEXT: kmovw %edi, %k0 ; KNL-NEXT: knotw %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: mask8: @@ -92,7 +92,7 @@ define i8 @mask8(i8 %x) { ; SKX-NEXT: kmovd %edi, %k0 ; SKX-NEXT: knotb %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: mask8: @@ -100,7 +100,7 @@ define i8 @mask8(i8 %x) { ; AVX512BW-NEXT: kmovd %edi, %k0 ; AVX512BW-NEXT: knotw %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: mask8: @@ -108,7 +108,7 @@ define i8 @mask8(i8 %x) { ; AVX512DQ-NEXT: kmovw %edi, %k0 ; AVX512DQ-NEXT: knotb %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i8 %x to <8 x i1> %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> @@ -235,7 +235,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; KNL-NEXT: kxorw %k1, %k0, %k0 ; KNL-NEXT: korw %k0, %k2, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: mand16_mem: @@ -246,7 +246,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; SKX-NEXT: kxorw %k1, %k0, %k0 ; SKX-NEXT: korw %k0, %k2, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: mand16_mem: @@ -257,7 +257,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; AVX512BW-NEXT: korw %k0, %k2, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: mand16_mem: @@ -268,7 +268,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; AVX512DQ-NEXT: kxorw %k1, %k0, %k0 ; AVX512DQ-NEXT: korw %k0, %k2, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: retq %ma = load <16 x i1>, <16 x i1>* %x %mb = load <16 x i1>, <16 x i1>* %y @@ -285,7 +285,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; KNL-NEXT: kmovw %edi, %k0 ; KNL-NEXT: kshiftrw $8, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: shuf_test1: @@ -293,7 +293,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; SKX-NEXT: kmovd %edi, %k0 ; SKX-NEXT: kshiftrw $8, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: shuf_test1: @@ -301,7 +301,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; AVX512BW-NEXT: kmovd %edi, %k0 ; AVX512BW-NEXT: kshiftrw $8, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: shuf_test1: @@ -309,7 +309,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; AVX512DQ-NEXT: kmovw %edi, %k0 ; AVX512DQ-NEXT: kshiftrw $8, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: retq %v1 = bitcast i16 %v to <16 x i1> %mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -371,7 +371,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; KNL-NEXT: kshiftrw $15, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: andl $1, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -382,7 +382,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax ; SKX-NEXT: andl $1, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq ; @@ -393,7 +393,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; AVX512BW-NEXT: kshiftrw $15, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: andl $1, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -404,7 +404,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax ; AVX512DQ-NEXT: andl $1, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %cmp_res = icmp ugt <16 x i32> %a, %b @@ -421,7 +421,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; KNL-NEXT: kshiftrw $15, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: andb $1, %al -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -432,7 +432,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax ; SKX-NEXT: andb $1, %al -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq ; @@ -443,7 +443,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; AVX512BW-NEXT: kshiftrw $15, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: andb $1, %al -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -454,7 +454,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; AVX512DQ-NEXT: kshiftrw $15, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax ; AVX512DQ-NEXT: andb $1, %al -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %cmp_res = icmp ugt <16 x i32> %a, %b @@ -704,7 +704,7 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; AVX512BW-NEXT: vpcmpgtd %zmm2, %zmm0, %k0 ; AVX512BW-NEXT: LBB17_3: ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -774,7 +774,7 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; AVX512BW-NEXT: LBB18_3: ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -907,7 +907,7 @@ define <16 x i1> @test15(i32 %x, i32 %y) { ; AVX512BW-NEXT: cmovgw %ax, %cx ; AVX512BW-NEXT: kmovd %ecx, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1220,7 +1220,7 @@ define <8 x i1> @test18(i8 %a, i16 %y) { ; AVX512BW-NEXT: kshiftlw $7, %k0, %k0 ; AVX512BW-NEXT: korw %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1300,7 +1300,7 @@ define <32 x i16> @test21(<32 x i16> %x , <32 x i1> %mask) nounwind readnone { define void @test22(<4 x i1> %a, <4 x i1>* %addr) { ; KNL-LABEL: test22: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL-NEXT: vpslld $31, %ymm0, %ymm0 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax @@ -1317,7 +1317,7 @@ define void @test22(<4 x i1> %a, <4 x i1>* %addr) { ; ; AVX512BW-LABEL: test22: ; AVX512BW: ## BB#0: -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512BW-NEXT: vpslld $31, %ymm0, %ymm0 ; AVX512BW-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax @@ -1327,7 +1327,7 @@ define void @test22(<4 x i1> %a, <4 x i1>* %addr) { ; ; AVX512DQ-LABEL: test22: ; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vpslld $31, %ymm0, %ymm0 ; AVX512DQ-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512DQ-NEXT: kmovb %k0, (%rdi) @@ -1340,7 +1340,7 @@ define void @test22(<4 x i1> %a, <4 x i1>* %addr) { define void @test23(<2 x i1> %a, <2 x i1>* %addr) { ; KNL-LABEL: test23: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 ; KNL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax @@ -1357,7 +1357,7 @@ define void @test23(<2 x i1> %a, <2 x i1>* %addr) { ; ; AVX512BW-LABEL: test23: ; AVX512BW: ## BB#0: -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax @@ -1367,7 +1367,7 @@ define void @test23(<2 x i1> %a, <2 x i1>* %addr) { ; ; AVX512DQ-LABEL: test23: ; AVX512DQ: ## BB#0: -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512DQ-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512DQ-NEXT: kmovb %k0, (%rdi) @@ -2536,7 +2536,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a) { ; KNL-NEXT: movzbl (%rdi), %eax ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -2551,7 +2551,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a) { ; AVX512BW-NEXT: movzbl (%rdi), %eax ; AVX512BW-NEXT: kmovd %eax, %k1 ; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -2559,7 +2559,7 @@ define <2 x i16> @load_2i1(<2 x i1>* %a) { ; AVX512DQ: ## BB#0: ; AVX512DQ-NEXT: kmovb (%rdi), %k0 ; AVX512DQ-NEXT: vpmovm2q %k0, %zmm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = load <2 x i1>, <2 x i1>* %a @@ -2574,7 +2574,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a) { ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-NEXT: vpmovqd %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -2590,7 +2590,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a) { ; AVX512BW-NEXT: kmovd %eax, %k1 ; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512BW-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -2598,7 +2598,7 @@ define <4 x i16> @load_4i1(<4 x i1>* %a) { ; AVX512DQ: ## BB#0: ; AVX512DQ-NEXT: kmovb (%rdi), %k0 ; AVX512DQ-NEXT: vpmovm2d %k0, %zmm0 -; AVX512DQ-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %b = load <4 x i1>, <4 x i1>* %a @@ -3624,7 +3624,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kxorw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v16i1_add: @@ -3633,7 +3633,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kxorw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v16i1_add: @@ -3642,7 +3642,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v16i1_add: @@ -3651,7 +3651,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kxorw %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -3667,7 +3667,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kxorw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v16i1_sub: @@ -3676,7 +3676,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kxorw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v16i1_sub: @@ -3685,7 +3685,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v16i1_sub: @@ -3694,7 +3694,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kxorw %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -3710,7 +3710,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kandw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v16i1_mul: @@ -3719,7 +3719,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kandw %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v16i1_mul: @@ -3728,7 +3728,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kandw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v16i1_mul: @@ -3737,7 +3737,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kandw %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -3753,7 +3753,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kxorw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v8i1_add: @@ -3762,7 +3762,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kxorb %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v8i1_add: @@ -3771,7 +3771,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v8i1_add: @@ -3780,7 +3780,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kxorb %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> @@ -3796,7 +3796,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kxorw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v8i1_sub: @@ -3805,7 +3805,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kxorb %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v8i1_sub: @@ -3814,7 +3814,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v8i1_sub: @@ -3823,7 +3823,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kxorb %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> @@ -3839,7 +3839,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; KNL-NEXT: kmovw %esi, %k1 ; KNL-NEXT: kandw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; KNL-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test_v8i1_mul: @@ -3848,7 +3848,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 ; SKX-NEXT: kandb %k1, %k0, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq ; ; AVX512BW-LABEL: test_v8i1_mul: @@ -3857,7 +3857,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; AVX512BW-NEXT: kmovd %esi, %k1 ; AVX512BW-NEXT: kandw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQ-LABEL: test_v8i1_mul: @@ -3866,7 +3866,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; AVX512DQ-NEXT: kmovw %esi, %k1 ; AVX512DQ-NEXT: kandb %k1, %k0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax -; AVX512DQ-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512DQ-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; AVX512DQ-NEXT: retq %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> diff --git a/test/CodeGen/X86/avx512-memfold.ll b/test/CodeGen/X86/avx512-memfold.ll index 7490b99fd54..3184140102a 100644 --- a/test/CodeGen/X86/avx512-memfold.ll +++ b/test/CodeGen/X86/avx512-memfold.ll @@ -7,7 +7,7 @@ define i8 @test_int_x86_avx512_mask_cmp_ss(<4 x float> %a, float* %b, i8 %mask) ; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %b.val = load float, float* %b %bv0 = insertelement <4 x float> undef, float %b.val, i32 0 diff --git a/test/CodeGen/X86/avx512-regcall-Mask.ll b/test/CodeGen/X86/avx512-regcall-Mask.ll index bb541f46567..d31b3ec2669 100644 --- a/test/CodeGen/X86/avx512-regcall-Mask.ll +++ b/test/CodeGen/X86/avx512-regcall-Mask.ll @@ -310,9 +310,9 @@ define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> ; X32-NEXT: vpmovm2b %k2, %zmm0 ; X32-NEXT: vpmovm2b %k1, %zmm1 ; X32-NEXT: vpmovm2b %k0, %zmm2 -; X32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> -; X32-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill> -; X32-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill> +; X32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> +; X32-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill> +; X32-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill> ; X32-NEXT: calll _test_argv32i1helper ; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload ; X32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm5 # 16-byte Reload @@ -340,9 +340,9 @@ define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> ; WIN64-NEXT: vpmovm2b %k2, %zmm0 ; WIN64-NEXT: vpmovm2b %k1, %zmm1 ; WIN64-NEXT: vpmovm2b %k0, %zmm2 -; WIN64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> -; WIN64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill> -; WIN64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill> +; WIN64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> +; WIN64-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill> +; WIN64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill> ; WIN64-NEXT: callq test_argv32i1helper ; WIN64-NEXT: nop ; WIN64-NEXT: addq $32, %rsp @@ -384,9 +384,9 @@ define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> ; LINUXOSX64-NEXT: vpmovm2b %k2, %zmm0 ; LINUXOSX64-NEXT: vpmovm2b %k1, %zmm1 ; LINUXOSX64-NEXT: vpmovm2b %k0, %zmm2 -; LINUXOSX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> -; LINUXOSX64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<kill> -; LINUXOSX64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<kill> +; LINUXOSX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> +; LINUXOSX64-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<kill> +; LINUXOSX64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<kill> ; LINUXOSX64-NEXT: callq test_argv32i1helper ; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload ; LINUXOSX64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm9 # 16-byte Reload @@ -538,9 +538,9 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> ; X32-NEXT: vpmovm2b %k2, %zmm0 ; X32-NEXT: vpmovm2b %k1, %zmm1 ; X32-NEXT: vpmovm2b %k0, %zmm2 -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; X32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; X32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: calll _test_argv16i1helper ; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload @@ -568,9 +568,9 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> ; WIN64-NEXT: vpmovm2b %k2, %zmm0 ; WIN64-NEXT: vpmovm2b %k1, %zmm1 ; WIN64-NEXT: vpmovm2b %k0, %zmm2 -; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; WIN64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; WIN64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; WIN64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; WIN64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; WIN64-NEXT: vzeroupper ; WIN64-NEXT: callq test_argv16i1helper ; WIN64-NEXT: nop @@ -612,9 +612,9 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> ; LINUXOSX64-NEXT: vpmovm2b %k2, %zmm0 ; LINUXOSX64-NEXT: vpmovm2b %k1, %zmm1 ; LINUXOSX64-NEXT: vpmovm2b %k0, %zmm2 -; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; LINUXOSX64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; LINUXOSX64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; LINUXOSX64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; LINUXOSX64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; LINUXOSX64-NEXT: vzeroupper ; LINUXOSX64-NEXT: callq test_argv16i1helper ; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload @@ -705,9 +705,9 @@ define i16 @caller_retv16i1() #0 { ; X32-LABEL: caller_retv16i1: ; X32: # BB#0: # %entry ; X32-NEXT: calll _test_retv16i1 -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; X32-NEXT: incl %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; WIN64-LABEL: caller_retv16i1: @@ -724,9 +724,9 @@ define i16 @caller_retv16i1() #0 { ; WIN64-NEXT: .seh_savexmm 6, 0 ; WIN64-NEXT: .seh_endprologue ; WIN64-NEXT: callq test_retv16i1 -; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; WIN64-NEXT: incl %eax -; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; WIN64-NEXT: vmovaps (%rsp), %xmm6 # 16-byte Reload ; WIN64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm7 # 16-byte Reload ; WIN64-NEXT: addq $40, %rsp @@ -742,9 +742,9 @@ define i16 @caller_retv16i1() #0 { ; LINUXOSX64-NEXT: pushq %rax ; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16 ; LINUXOSX64-NEXT: callq test_retv16i1 -; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; LINUXOSX64-NEXT: incl %eax -; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; LINUXOSX64-NEXT: popq %rcx ; LINUXOSX64-NEXT: retq entry: @@ -771,9 +771,9 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) ; X32-NEXT: vpmovm2w %k2, %zmm0 ; X32-NEXT: vpmovm2w %k1, %zmm1 ; X32-NEXT: vpmovm2w %k0, %zmm2 -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; X32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; X32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; X32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; X32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: calll _test_argv8i1helper ; X32-NEXT: vmovups (%esp), %xmm4 # 16-byte Reload @@ -801,9 +801,9 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) ; WIN64-NEXT: vpmovm2w %k2, %zmm0 ; WIN64-NEXT: vpmovm2w %k1, %zmm1 ; WIN64-NEXT: vpmovm2w %k0, %zmm2 -; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; WIN64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; WIN64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; WIN64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; WIN64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; WIN64-NEXT: vzeroupper ; WIN64-NEXT: callq test_argv8i1helper ; WIN64-NEXT: nop @@ -845,9 +845,9 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) ; LINUXOSX64-NEXT: vpmovm2w %k2, %zmm0 ; LINUXOSX64-NEXT: vpmovm2w %k1, %zmm1 ; LINUXOSX64-NEXT: vpmovm2w %k0, %zmm2 -; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> -; LINUXOSX64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<kill> -; LINUXOSX64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<kill> +; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> +; LINUXOSX64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<kill> +; LINUXOSX64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<kill> ; LINUXOSX64-NEXT: vzeroupper ; LINUXOSX64-NEXT: callq test_argv8i1helper ; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload @@ -938,10 +938,10 @@ define <8 x i1> @caller_retv8i1() #0 { ; X32-LABEL: caller_retv8i1: ; X32: # BB#0: # %entry ; X32-NEXT: calll _test_retv8i1 -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<def> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<def> ; X32-NEXT: kmovd %eax, %k0 ; X32-NEXT: vpmovm2w %k0, %zmm0 -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; X32-NEXT: vzeroupper ; X32-NEXT: retl ; @@ -959,10 +959,10 @@ define <8 x i1> @caller_retv8i1() #0 { ; WIN64-NEXT: .seh_savexmm 6, 0 ; WIN64-NEXT: .seh_endprologue ; WIN64-NEXT: callq test_retv8i1 -; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<def> +; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<def> ; WIN64-NEXT: kmovd %eax, %k0 ; WIN64-NEXT: vpmovm2w %k0, %zmm0 -; WIN64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; WIN64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; WIN64-NEXT: vmovaps (%rsp), %xmm6 # 16-byte Reload ; WIN64-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm7 # 16-byte Reload ; WIN64-NEXT: addq $40, %rsp @@ -979,10 +979,10 @@ define <8 x i1> @caller_retv8i1() #0 { ; LINUXOSX64-NEXT: pushq %rax ; LINUXOSX64-NEXT: .cfi_def_cfa_offset 16 ; LINUXOSX64-NEXT: callq test_retv8i1 -; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<def> +; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<def> ; LINUXOSX64-NEXT: kmovd %eax, %k0 ; LINUXOSX64-NEXT: vpmovm2w %k0, %zmm0 -; LINUXOSX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; LINUXOSX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; LINUXOSX64-NEXT: popq %rax ; LINUXOSX64-NEXT: vzeroupper ; LINUXOSX64-NEXT: retq diff --git a/test/CodeGen/X86/avx512-regcall-NoMask.ll b/test/CodeGen/X86/avx512-regcall-NoMask.ll index 43a1871245b..82c435f2268 100644 --- a/test/CodeGen/X86/avx512-regcall-NoMask.ll +++ b/test/CodeGen/X86/avx512-regcall-NoMask.ll @@ -8,19 +8,19 @@ define x86_regcallcc i1 @test_argReti1(i1 %a) { ; X32-LABEL: test_argReti1: ; X32: # BB#0: ; X32-NEXT: incb %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; WIN64-LABEL: test_argReti1: ; WIN64: # BB#0: ; WIN64-NEXT: incb %al -; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; WIN64-NEXT: retq ; ; LINUXOSX64-LABEL: test_argReti1: ; LINUXOSX64: # BB#0: ; LINUXOSX64-NEXT: incb %al -; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; LINUXOSX64-NEXT: retq %add = add i1 %a, 1 ret i1 %add @@ -75,19 +75,19 @@ define x86_regcallcc i8 @test_argReti8(i8 %a) { ; X32-LABEL: test_argReti8: ; X32: # BB#0: ; X32-NEXT: incb %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; WIN64-LABEL: test_argReti8: ; WIN64: # BB#0: ; WIN64-NEXT: incb %al -; WIN64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; WIN64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; WIN64-NEXT: retq ; ; LINUXOSX64-LABEL: test_argReti8: ; LINUXOSX64: # BB#0: ; LINUXOSX64-NEXT: incb %al -; LINUXOSX64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; LINUXOSX64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; LINUXOSX64-NEXT: retq %add = add i8 %a, 1 ret i8 %add @@ -142,19 +142,19 @@ define x86_regcallcc i16 @test_argReti16(i16 %a) { ; X32-LABEL: test_argReti16: ; X32: # BB#0: ; X32-NEXT: incl %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; WIN64-LABEL: test_argReti16: ; WIN64: # BB#0: ; WIN64-NEXT: incl %eax -; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; WIN64-NEXT: retq ; ; LINUXOSX64-LABEL: test_argReti16: ; LINUXOSX64: # BB#0: ; LINUXOSX64-NEXT: incl %eax -; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; LINUXOSX64-NEXT: retq %add = add i16 %a, 1 ret i16 %add @@ -167,9 +167,9 @@ define x86_regcallcc i16 @test_CallargReti16(i16 %a) { ; X32-NEXT: pushl %esp ; X32-NEXT: incl %eax ; X32-NEXT: calll _test_argReti16 -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; X32-NEXT: incl %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: popl %esp ; X32-NEXT: retl ; @@ -180,9 +180,9 @@ define x86_regcallcc i16 @test_CallargReti16(i16 %a) { ; WIN64-NEXT: .seh_endprologue ; WIN64-NEXT: incl %eax ; WIN64-NEXT: callq test_argReti16 -; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; WIN64-NEXT: incl %eax -; WIN64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; WIN64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq ; WIN64-NEXT: .seh_handlerdata @@ -196,9 +196,9 @@ define x86_regcallcc i16 @test_CallargReti16(i16 %a) { ; LINUXOSX64-NEXT: .cfi_offset %rsp, -16 ; LINUXOSX64-NEXT: incl %eax ; LINUXOSX64-NEXT: callq test_argReti16 -; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def> +; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<def> ; LINUXOSX64-NEXT: incl %eax -; LINUXOSX64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; LINUXOSX64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; LINUXOSX64-NEXT: popq %rsp ; LINUXOSX64-NEXT: retq %b = add i16 %a, 1 @@ -849,7 +849,7 @@ define x86_regcallcc <16 x i32> @test_CallargRet512Vector(<16 x i32> %a) { ret <16 x i32> %c } -; Test regcall when running multiple input parameters - callee saved XMMs +; Test regcall when running multiple input parameters - callee saved xmms define x86_regcallcc <32 x float> @testf32_inp(<32 x float> %a, <32 x float> %b, <32 x float> %c) nounwind { ; X32-LABEL: testf32_inp: ; X32: # BB#0: diff --git a/test/CodeGen/X86/avx512-schedule.ll b/test/CodeGen/X86/avx512-schedule.ll index 8372fbdb9ab..af459ddc296 100755 --- a/test/CodeGen/X86/avx512-schedule.ll +++ b/test/CodeGen/X86/avx512-schedule.ll @@ -4335,7 +4335,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) { ; GENERIC-NEXT: vpsllw $7, %xmm0, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: vpmovb2m %xmm0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: trunc_16i8_to_16i1: @@ -4343,7 +4343,7 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) { ; SKX-NEXT: vpsllw $7, %xmm0, %xmm0 # sched: [1:0.50] ; SKX-NEXT: vpmovb2m %xmm0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %mask_b = trunc <16 x i8>%a to <16 x i1> %mask = bitcast <16 x i1> %mask_b to i16 @@ -4356,7 +4356,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i32> %a) { ; GENERIC-NEXT: vpslld $31, %zmm0, %zmm0 ; GENERIC-NEXT: vptestmd %zmm0, %zmm0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: vzeroupper ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -4365,7 +4365,7 @@ define i16 @trunc_16i32_to_16i1(<16 x i32> %a) { ; SKX-NEXT: vpslld $31, %zmm0, %zmm0 # sched: [1:0.50] ; SKX-NEXT: vptestmd %zmm0, %zmm0, %k0 # sched: [3:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper # sched: [4:1.00] ; SKX-NEXT: retq # sched: [7:1.00] %mask_b = trunc <16 x i32>%a to <16 x i1> @@ -4405,7 +4405,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) { ; GENERIC-NEXT: vpsllw $15, %xmm0, %xmm0 # sched: [1:1.00] ; GENERIC-NEXT: vpmovw2m %xmm0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: trunc_8i16_to_8i1: @@ -4413,7 +4413,7 @@ define i8 @trunc_8i16_to_8i1(<8 x i16> %a) { ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 # sched: [1:0.50] ; SKX-NEXT: vpmovw2m %xmm0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %mask_b = trunc <8 x i16>%a to <8 x i1> %mask = bitcast <8 x i1> %mask_b to i8 @@ -4450,7 +4450,7 @@ define i16 @trunc_i32_to_i1(i32 %a) { ; GENERIC-NEXT: kmovw %edi, %k1 ; GENERIC-NEXT: korw %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: trunc_i32_to_i1: @@ -4463,7 +4463,7 @@ define i16 @trunc_i32_to_i1(i32 %a) { ; SKX-NEXT: kmovw %edi, %k1 # sched: [1:1.00] ; SKX-NEXT: korw %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %a_i = trunc i32 %a to i1 %maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %a_i, i32 0 @@ -6740,7 +6740,7 @@ define i16 @mask16(i16 %x) { ; GENERIC-NEXT: kmovd %edi, %k0 ; GENERIC-NEXT: knotw %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: mask16: @@ -6748,7 +6748,7 @@ define i16 @mask16(i16 %x) { ; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00] ; SKX-NEXT: knotw %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i16 %x to <16 x i1> %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> @@ -6783,7 +6783,7 @@ define i8 @mask8(i8 %x) { ; GENERIC-NEXT: kmovd %edi, %k0 ; GENERIC-NEXT: knotb %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: mask8: @@ -6791,7 +6791,7 @@ define i8 @mask8(i8 %x) { ; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00] ; SKX-NEXT: knotb %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i8 %x to <8 x i1> %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> @@ -6900,7 +6900,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; GENERIC-NEXT: kxorw %k1, %k0, %k0 ; GENERIC-NEXT: korw %k0, %k2, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: mand16_mem: @@ -6911,7 +6911,7 @@ define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) { ; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: korw %k0, %k2, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %ma = load <16 x i1>, <16 x i1>* %x %mb = load <16 x i1>, <16 x i1>* %y @@ -6928,7 +6928,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; GENERIC-NEXT: kmovd %edi, %k0 ; GENERIC-NEXT: kshiftrw $8, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: shuf_test1: @@ -6936,7 +6936,7 @@ define i8 @shuf_test1(i16 %v) nounwind { ; SKX-NEXT: kmovd %edi, %k0 # sched: [1:1.00] ; SKX-NEXT: kshiftrw $8, %k0, %k0 # sched: [3:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %v1 = bitcast i16 %v to <16 x i1> %mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -6978,7 +6978,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; GENERIC-NEXT: kshiftrw $15, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax ; GENERIC-NEXT: andl $1, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: vzeroupper ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -6989,7 +6989,7 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 # sched: [3:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] ; SKX-NEXT: andl $1, %eax # sched: [1:0.25] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper # sched: [4:1.00] ; SKX-NEXT: retq # sched: [7:1.00] %cmp_res = icmp ugt <16 x i32> %a, %b @@ -7006,7 +7006,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; GENERIC-NEXT: kshiftrw $15, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax ; GENERIC-NEXT: andb $1, %al # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: vzeroupper ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -7017,7 +7017,7 @@ define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) { ; SKX-NEXT: kshiftrw $15, %k0, %k0 # sched: [3:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] ; SKX-NEXT: andb $1, %al # sched: [1:0.25] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: vzeroupper # sched: [4:1.00] ; SKX-NEXT: retq # sched: [7:1.00] %cmp_res = icmp ugt <16 x i32> %a, %b @@ -8133,7 +8133,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kxorw %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v16i1_add: @@ -8142,7 +8142,7 @@ define i16 @test_v16i1_add(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -8158,7 +8158,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kxorw %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v16i1_sub: @@ -8167,7 +8167,7 @@ define i16 @test_v16i1_sub(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kxorw %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -8183,7 +8183,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kandw %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v16i1_mul: @@ -8192,7 +8192,7 @@ define i16 @test_v16i1_mul(i16 %x, i16 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kandw %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i16 %x to <16 x i1> %m1 = bitcast i16 %y to <16 x i1> @@ -8208,7 +8208,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kxorb %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v8i1_add: @@ -8217,7 +8217,7 @@ define i8 @test_v8i1_add(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kxorb %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> @@ -8233,7 +8233,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kxorb %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v8i1_sub: @@ -8242,7 +8242,7 @@ define i8 @test_v8i1_sub(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kxorb %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> @@ -8258,7 +8258,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; GENERIC-NEXT: kmovd %esi, %k1 ; GENERIC-NEXT: kandb %k1, %k0, %k0 ; GENERIC-NEXT: kmovd %k0, %eax -; GENERIC-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SKX-LABEL: test_v8i1_mul: @@ -8267,7 +8267,7 @@ define i8 @test_v8i1_mul(i8 %x, i8 %y) { ; SKX-NEXT: kmovd %esi, %k1 # sched: [1:1.00] ; SKX-NEXT: kandb %k1, %k0, %k0 # sched: [1:1.00] ; SKX-NEXT: kmovd %k0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SKX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] %m0 = bitcast i8 %x to <8 x i1> %m1 = bitcast i8 %y to <8 x i1> diff --git a/test/CodeGen/X86/avx512-select.ll b/test/CodeGen/X86/avx512-select.ll index 43cf9ee7358..b73e307c868 100644 --- a/test/CodeGen/X86/avx512-select.ll +++ b/test/CodeGen/X86/avx512-select.ll @@ -155,7 +155,7 @@ define i8 @select05_mem(<8 x i1>* %a.0, <8 x i1>* %m) { ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: korw %k1, %k0, %k0 ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: select05_mem: @@ -166,7 +166,7 @@ define i8 @select05_mem(<8 x i1>* %a.0, <8 x i1>* %m) { ; X64-NEXT: kmovw %eax, %k1 ; X64-NEXT: korw %k1, %k0, %k0 ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %mask = load <8 x i1> , <8 x i1>* %m %a = load <8 x i1> , <8 x i1>* %a.0 @@ -205,7 +205,7 @@ define i8 @select06_mem(<8 x i1>* %a.0, <8 x i1>* %m) { ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: kandw %k1, %k0, %k0 ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: select06_mem: @@ -216,7 +216,7 @@ define i8 @select06_mem(<8 x i1>* %a.0, <8 x i1>* %m) { ; X64-NEXT: kmovw %eax, %k1 ; X64-NEXT: kandw %k1, %k0, %k0 ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %mask = load <8 x i1> , <8 x i1>* %m %a = load <8 x i1> , <8 x i1>* %a.0 @@ -237,7 +237,7 @@ define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) { ; X86-NEXT: kandw %k0, %k1, %k0 ; X86-NEXT: korw %k2, %k0, %k0 ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: select07: @@ -249,7 +249,7 @@ define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) { ; X64-NEXT: kandw %k0, %k1, %k0 ; X64-NEXT: korw %k2, %k0, %k0 ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %mask = bitcast i8 %m to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1> diff --git a/test/CodeGen/X86/avx512-shift.ll b/test/CodeGen/X86/avx512-shift.ll index ce2b010ec0f..c18efd922c3 100644 --- a/test/CodeGen/X86/avx512-shift.ll +++ b/test/CodeGen/X86/avx512-shift.ll @@ -34,7 +34,7 @@ define <4 x i64> @shift_4_i64(<4 x i64> %a) { ; KNL-NEXT: vpsrlq $1, %ymm0, %ymm0 ; KNL-NEXT: vpsllq $12, %ymm0, %ymm0 ; KNL-NEXT: vpsraq $12, %zmm0, %zmm0 -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: shift_4_i64: @@ -106,10 +106,10 @@ define <8 x i64> @variable_sra2(<8 x i64> %x, <8 x i64> %y) { define <4 x i64> @variable_sra3(<4 x i64> %x, <4 x i64> %y) { ; KNL-LABEL: variable_sra3: ; KNL: # BB#0: -; KNL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpsravq %zmm1, %zmm0, %zmm0 -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: variable_sra3: @@ -127,7 +127,7 @@ define <8 x i16> @variable_sra4(<8 x i16> %x, <8 x i16> %y) { ; KNL-NEXT: vpmovsxwd %xmm0, %ymm0 ; KNL-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: variable_sra4: diff --git a/test/CodeGen/X86/avx512-shuffles/partial_permute.ll b/test/CodeGen/X86/avx512-shuffles/partial_permute.ll index 66363c7ec0f..947013b0555 100644 --- a/test/CodeGen/X86/avx512-shuffles/partial_permute.ll +++ b/test/CodeGen/X86/avx512-shuffles/partial_permute.ll @@ -839,7 +839,7 @@ define <8 x i16> @test_32xi16_to_8xi16_perm_mem_mask0(<32 x i16>* %vp) { ; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 ; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <16,17,5,1,14,14,13,17,u,u,u,u,u,u,u,u> ; CHECK-NEXT: vpermi2w %ymm1, %ymm2, %ymm0 -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %vec = load <32 x i16>, <32 x i16>* %vp @@ -967,7 +967,7 @@ define <8 x i16> @test_32xi16_to_8xi16_perm_mem_mask3(<32 x i16>* %vp) { ; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 ; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <19,1,5,31,9,12,17,9,u,u,u,u,u,u,u,u> ; CHECK-NEXT: vpermi2w %ymm2, %ymm1, %ymm0 -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %vec = load <32 x i16>, <32 x i16>* %vp @@ -1493,7 +1493,7 @@ define <4 x i32> @test_16xi32_to_4xi32_perm_mask0(<16 x i32> %vec) { ; CHECK-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,0,3,4,6,4,7] ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6],ymm1[7] ; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3] -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %res = shufflevector <16 x i32> %vec, <16 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 12> @@ -1814,7 +1814,7 @@ define <4 x i32> @test_16xi32_to_4xi32_perm_mem_mask0(<16 x i32>* %vp) { ; CHECK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 ; CHECK-NEXT: vmovdqa {{.*#+}} ymm0 = <13,0,0,6,u,u,u,u> ; CHECK-NEXT: vpermi2d %ymm2, %ymm1, %ymm0 -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %vec = load <16 x i32>, <16 x i32>* %vp @@ -3857,7 +3857,7 @@ define <4 x float> @test_16xfloat_to_4xfloat_perm_mem_mask3(<16 x float>* %vp) { ; CHECK-NEXT: vextractf64x4 $1, %zmm1, %ymm2 ; CHECK-NEXT: vmovaps {{.*#+}} ymm0 = <3,3,15,9,u,u,u,u> ; CHECK-NEXT: vpermi2ps %ymm2, %ymm1, %ymm0 -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %vec = load <16 x float>, <16 x float>* %vp @@ -4329,7 +4329,7 @@ define <2 x double> @test_8xdouble_to_2xdouble_perm_mask0(<8 x double> %vec) { ; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1 ; CHECK-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] ; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3] -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %res = shufflevector <8 x double> %vec, <8 x double> undef, <2 x i32> <i32 0, i32 6> @@ -4727,7 +4727,7 @@ define <2 x double> @test_8xdouble_to_2xdouble_perm_mem_mask0(<8 x double>* %vp) ; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm1 ; CHECK-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1],ymm1[0],ymm0[3],ymm1[2] ; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,3,2,3] -; CHECK-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; CHECK-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %vec = load <8 x double>, <8 x double>* %vp diff --git a/test/CodeGen/X86/avx512-trunc.ll b/test/CodeGen/X86/avx512-trunc.ll index 46a22a2d8bb..cf9a12deaad 100644 --- a/test/CodeGen/X86/avx512-trunc.ll +++ b/test/CodeGen/X86/avx512-trunc.ll @@ -57,9 +57,9 @@ define void @trunc_qb_512_mem(<8 x i64> %i, <8 x i8>* %res) #0 { define <4 x i8> @trunc_qb_256(<4 x i64> %i) #0 { ; KNL-LABEL: trunc_qb_256: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -75,7 +75,7 @@ define <4 x i8> @trunc_qb_256(<4 x i64> %i) #0 { define void @trunc_qb_256_mem(<4 x i64> %i, <4 x i8>* %res) #0 { ; KNL-LABEL: trunc_qb_256_mem: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 ; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] ; KNL-NEXT: vmovd %xmm0, (%rdi) @@ -140,9 +140,9 @@ define void @trunc_qw_512_mem(<8 x i64> %i, <8 x i16>* %res) #0 { define <4 x i16> @trunc_qw_256(<4 x i64> %i) #0 { ; KNL-LABEL: trunc_qw_256: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -158,7 +158,7 @@ define <4 x i16> @trunc_qw_256(<4 x i64> %i) #0 { define void @trunc_qw_256_mem(<4 x i64> %i, <4 x i16>* %res) #0 { ; KNL-LABEL: trunc_qw_256_mem: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 ; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; KNL-NEXT: vmovq %xmm0, (%rdi) @@ -223,9 +223,9 @@ define void @trunc_qd_512_mem(<8 x i64> %i, <8 x i32>* %res) #0 { define <4 x i32> @trunc_qd_256(<4 x i64> %i) #0 { ; KNL-LABEL: trunc_qd_256: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -241,7 +241,7 @@ define <4 x i32> @trunc_qd_256(<4 x i64> %i) #0 { define void @trunc_qd_256_mem(<4 x i64> %i, <4 x i32>* %res) #0 { ; KNL-LABEL: trunc_qd_256_mem: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovqd %zmm0, %ymm0 ; KNL-NEXT: vmovdqa %xmm0, (%rdi) ; KNL-NEXT: vzeroupper @@ -305,9 +305,9 @@ define void @trunc_db_512_mem(<16 x i32> %i, <16 x i8>* %res) #0 { define <8 x i8> @trunc_db_256(<8 x i32> %i) #0 { ; KNL-LABEL: trunc_db_256: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -323,7 +323,7 @@ define <8 x i8> @trunc_db_256(<8 x i32> %i) #0 { define void @trunc_db_256_mem(<8 x i32> %i, <8 x i8>* %res) #0 { ; KNL-LABEL: trunc_db_256_mem: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; KNL-NEXT: vmovq %xmm0, (%rdi) @@ -387,9 +387,9 @@ define void @trunc_dw_512_mem(<16 x i32> %i, <16 x i16>* %res) #0 { define <8 x i16> @trunc_dw_256(<8 x i32> %i) #0 { ; KNL-LABEL: trunc_dw_256: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovdw %zmm0, %ymm0 -; KNL-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -405,7 +405,7 @@ define <8 x i16> @trunc_dw_256(<8 x i32> %i) #0 { define void @trunc_dw_256_mem(<8 x i32> %i, <8 x i16>* %res) #0 { ; KNL-LABEL: trunc_dw_256_mem: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-NEXT: vmovdqa %xmm0, (%rdi) ; KNL-NEXT: vzeroupper diff --git a/test/CodeGen/X86/avx512-vbroadcast.ll b/test/CodeGen/X86/avx512-vbroadcast.ll index 584968f1c6e..08956556683 100644 --- a/test/CodeGen/X86/avx512-vbroadcast.ll +++ b/test/CodeGen/X86/avx512-vbroadcast.ll @@ -124,7 +124,7 @@ define <8 x double> @_inreg8xdouble(double %a) { define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) { ; ALL-LABEL: _sd8xdouble_mask: ; ALL: # BB#0: -; ALL-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> +; ALL-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> ; ALL-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; ALL-NEXT: vpcmpneqd %zmm3, %zmm2, %k1 ; ALL-NEXT: vbroadcastsd %xmm0, %zmm1 {%k1} @@ -140,7 +140,7 @@ define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %m define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) { ; ALL-LABEL: _sd8xdouble_maskz: ; ALL: # BB#0: -; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; ALL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ; ALL-NEXT: vbroadcastsd %xmm0, %zmm0 {%k1} {z} @@ -166,7 +166,7 @@ define <8 x double> @_sd8xdouble_load(double* %a.ptr) { define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) { ; ALL-LABEL: _sd8xdouble_mask_load: ; ALL: # BB#0: -; ALL-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; ALL-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; ALL-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; ALL-NEXT: vpcmpneqd %zmm2, %zmm1, %k1 ; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} @@ -182,7 +182,7 @@ define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) { ; ALL-LABEL: _sd8xdouble_maskz_load: ; ALL: # BB#0: -; ALL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; ALL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; ALL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; ALL-NEXT: vpcmpneqd %zmm1, %zmm0, %k1 ; ALL-NEXT: vbroadcastsd (%rdi), %zmm0 {%k1} {z} diff --git a/test/CodeGen/X86/avx512-vec-cmp.ll b/test/CodeGen/X86/avx512-vec-cmp.ll index 56259c6f01e..1af9ffebeb3 100644 --- a/test/CodeGen/X86/avx512-vec-cmp.ll +++ b/test/CodeGen/X86/avx512-vec-cmp.ll @@ -111,11 +111,11 @@ define <2 x double> @test8(<2 x double> %a, <2 x double> %b) { define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind { ; KNL-LABEL: test9: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpcmpeqd %zmm1, %zmm0, %k1 ; KNL-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test9: @@ -131,11 +131,11 @@ define <8 x i32> @test9(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x float> @test10(<8 x float> %x, <8 x float> %y) nounwind { ; KNL-LABEL: test10: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vcmpeqps %zmm1, %zmm0, %k1 ; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1} -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test10: @@ -166,7 +166,7 @@ define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind { ; KNL-NEXT: vpcmpeqq %zmm3, %zmm1, %k1 ; KNL-NEXT: kunpckbw %k0, %k1, %k0 ; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; KNL-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; @@ -176,7 +176,7 @@ define i16 @test12(<16 x i64> %a, <16 x i64> %b) nounwind { ; SKX-NEXT: vpcmpeqq %zmm3, %zmm1, %k1 ; SKX-NEXT: kunpckbw %k0, %k1, %k0 ; SKX-NEXT: kmovd %k0, %eax -; SKX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq %res = icmp eq <16 x i64> %a, %b @@ -1007,12 +1007,12 @@ define <4 x float> @test34(<4 x float> %x, <4 x float> %x1, <4 x float>* %yp) no define <8 x float> @test35(<8 x float> %x, <8 x float> %x1, <8 x float>* %yp) nounwind { ; KNL-LABEL: test35: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vmovups (%rdi), %ymm2 ; KNL-NEXT: vcmpltps %zmm2, %zmm0, %k1 ; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1} -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test35: @@ -1121,12 +1121,12 @@ define <16 x float> @test40(<16 x float> %x, <16 x float> %x1, float* %ptr) n define <8 x float> @test41(<8 x float> %x, <8 x float> %x1, float* %ptr) nounwind { ; KNL-LABEL: test41: ; KNL: ## BB#0: -; KNL-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vbroadcastss (%rdi), %ymm2 ; KNL-NEXT: vcmpltps %zmm2, %zmm0, %k1 ; KNL-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1} -; KNL-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; KNL-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; KNL-NEXT: retq ; ; SKX-LABEL: test41: diff --git a/test/CodeGen/X86/avx512-vec3-crash.ll b/test/CodeGen/X86/avx512-vec3-crash.ll index 281456c235b..1da07c11ded 100644 --- a/test/CodeGen/X86/avx512-vec3-crash.ll +++ b/test/CodeGen/X86/avx512-vec3-crash.ll @@ -20,9 +20,9 @@ define <3 x i8 > @foo(<3 x i8>%x, <3 x i8>%a, <3 x i8>%b) { ; CHECK-NEXT: vpextrb $0, %xmm0, %eax ; CHECK-NEXT: vpextrb $4, %xmm0, %edx ; CHECK-NEXT: vpextrb $8, %xmm0, %ecx -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; CHECK-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; CHECK-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; CHECK-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; CHECK-NEXT: retq %cmp.i = icmp slt <3 x i8> %x, %a %res = sext <3 x i1> %cmp.i to <3 x i8> diff --git a/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll index a0e4ffa2dd6..c12dc8075bc 100644 --- a/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll @@ -1999,7 +1999,7 @@ define i64 @test_mask_cmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %mask) { ; AVX512F-32-NEXT: vpblendvb %ymm0, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 -; AVX512F-32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> %EAX<def> +; AVX512F-32-NEXT: # kill: %al<def> %al<kill> %eax<kill> %eax<def> ; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 @@ -2368,7 +2368,7 @@ define i64 @test_mask_cmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %mask) { ; AVX512F-32-NEXT: vpblendvb %ymm7, %ymm4, %ymm0, %ymm0 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0 -; AVX512F-32-NEXT: # kill: %BL<def> %BL<kill> %EBX<kill> %EBX<def> +; AVX512F-32-NEXT: # kill: %bl<def> %bl<kill> %ebx<kill> %ebx<def> ; AVX512F-32-NEXT: shrb $7, %bl ; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm0 @@ -2883,7 +2883,7 @@ define i64 @test_mask_x86_avx512_ucmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %m ; AVX512F-32-NEXT: vpblendvb %ymm0, %ymm3, %ymm2, %ymm2 ; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3],zmm3[4,5,6,7] ; AVX512F-32-NEXT: vpmovb2m %zmm2, %k0 -; AVX512F-32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> %EAX<def> +; AVX512F-32-NEXT: # kill: %al<def> %al<kill> %eax<kill> %eax<def> ; AVX512F-32-NEXT: shrb $7, %al ; AVX512F-32-NEXT: kmovd %eax, %k1 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm2 @@ -3252,7 +3252,7 @@ define i64 @test_mask_x86_avx512_ucmp_b_512(<64 x i8> %a0, <64 x i8> %a1, i64 %m ; AVX512F-32-NEXT: vpblendvb %ymm7, %ymm4, %ymm0, %ymm0 ; AVX512F-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512F-32-NEXT: vpmovb2m %zmm0, %k0 -; AVX512F-32-NEXT: # kill: %BL<def> %BL<kill> %EBX<kill> %EBX<def> +; AVX512F-32-NEXT: # kill: %bl<def> %bl<kill> %ebx<kill> %ebx<def> ; AVX512F-32-NEXT: shrb $7, %bl ; AVX512F-32-NEXT: kmovd %ebx, %k1 ; AVX512F-32-NEXT: vpmovm2b %k1, %zmm0 diff --git a/test/CodeGen/X86/avx512bw-mov.ll b/test/CodeGen/X86/avx512bw-mov.ll index cce62c4dc6b..ab099d911d3 100644 --- a/test/CodeGen/X86/avx512bw-mov.ll +++ b/test/CodeGen/X86/avx512bw-mov.ll @@ -105,7 +105,7 @@ define <16 x i8> @test_mask_load_16xi8(<16 x i1> %mask, <16 x i8>* %addr, <16 x ; CHECK-NEXT: kshiftlq $48, %k0, %k0 ; CHECK-NEXT: kshiftrq $48, %k0, %k1 ; CHECK-NEXT: vmovdqu8 (%rdi), %zmm0 {%k1} {z} -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; CHECK-NEXT: retq %res = call <16 x i8> @llvm.masked.load.v16i8(<16 x i8>* %addr, i32 4, <16 x i1>%mask, <16 x i8> undef) ret <16 x i8> %res @@ -120,7 +120,7 @@ define <32 x i8> @test_mask_load_32xi8(<32 x i1> %mask, <32 x i8>* %addr, <32 x ; CHECK-NEXT: kshiftlq $32, %k0, %k0 ; CHECK-NEXT: kshiftrq $32, %k0, %k1 ; CHECK-NEXT: vmovdqu8 (%rdi), %zmm0 {%k1} {z} -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; CHECK-NEXT: retq %res = call <32 x i8> @llvm.masked.load.v32i8(<32 x i8>* %addr, i32 4, <32 x i1>%mask, <32 x i8> zeroinitializer) ret <32 x i8> %res @@ -135,7 +135,7 @@ define <8 x i16> @test_mask_load_8xi16(<8 x i1> %mask, <8 x i16>* %addr, <8 x i1 ; CHECK-NEXT: kshiftld $24, %k0, %k0 ; CHECK-NEXT: kshiftrd $24, %k0, %k1 ; CHECK-NEXT: vmovdqu16 (%rdi), %zmm0 {%k1} {z} -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; CHECK-NEXT: retq %res = call <8 x i16> @llvm.masked.load.v8i16(<8 x i16>* %addr, i32 4, <8 x i1>%mask, <8 x i16> undef) ret <8 x i16> %res @@ -150,7 +150,7 @@ define <16 x i16> @test_mask_load_16xi16(<16 x i1> %mask, <16 x i16>* %addr, <16 ; CHECK-NEXT: kshiftld $16, %k0, %k0 ; CHECK-NEXT: kshiftrd $16, %k0, %k1 ; CHECK-NEXT: vmovdqu16 (%rdi), %zmm0 {%k1} {z} -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; CHECK-NEXT: retq %res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer) ret <16 x i16> %res @@ -160,7 +160,7 @@ declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i define void @test_mask_store_16xi8(<16 x i1> %mask, <16 x i8>* %addr, <16 x i8> %val) { ; CHECK-LABEL: test_mask_store_16xi8: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0 ; CHECK-NEXT: vpmovb2m %zmm0, %k0 ; CHECK-NEXT: kshiftlq $48, %k0, %k0 @@ -175,7 +175,7 @@ declare void @llvm.masked.store.v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>) define void @test_mask_store_32xi8(<32 x i1> %mask, <32 x i8>* %addr, <32 x i8> %val) { ; CHECK-LABEL: test_mask_store_32xi8: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0 ; CHECK-NEXT: vpmovb2m %zmm0, %k0 ; CHECK-NEXT: kshiftlq $32, %k0, %k0 @@ -190,7 +190,7 @@ declare void @llvm.masked.store.v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>) define void @test_mask_store_8xi16(<8 x i1> %mask, <8 x i16>* %addr, <8 x i16> %val) { ; CHECK-LABEL: test_mask_store_8xi16: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0 ; CHECK-NEXT: vpmovw2m %zmm0, %k0 ; CHECK-NEXT: kshiftld $24, %k0, %k0 @@ -205,7 +205,7 @@ declare void @llvm.masked.store.v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) define void @test_mask_store_16xi16(<16 x i1> %mask, <16 x i16>* %addr, <16 x i16> %val) { ; CHECK-LABEL: test_mask_store_16xi16: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; CHECK-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0 ; CHECK-NEXT: vpmovb2m %zmm0, %k0 ; CHECK-NEXT: kshiftld $16, %k0, %k0 diff --git a/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll index 956ab124a4d..4f4f700a4c2 100644 --- a/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll @@ -503,7 +503,7 @@ define i16 @test_pcmpeq_w_256(<16 x i16> %a, <16 x i16> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x75,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpeq.w.256(<16 x i16> %a, <16 x i16> %b, i16 -1) @@ -516,7 +516,7 @@ define i16 @test_mask_pcmpeq_w_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpeqw %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x75,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpeq.w.256(<16 x i16> %a, <16 x i16> %b, i16 %mask) @@ -555,7 +555,7 @@ define i16 @test_pcmpgt_w_256(<16 x i16> %a, <16 x i16> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x65,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpgt.w.256(<16 x i16> %a, <16 x i16> %b, i16 -1) @@ -568,7 +568,7 @@ define i16 @test_mask_pcmpgt_w_256(<16 x i16> %a, <16 x i16> %b, i16 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x65,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpgt.w.256(<16 x i16> %a, <16 x i16> %b, i16 %mask) @@ -582,7 +582,7 @@ define i16 @test_pcmpeq_b_128(<16 x i8> %a, <16 x i8> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x74,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpeq.b.128(<16 x i8> %a, <16 x i8> %b, i16 -1) ret i16 %res @@ -594,7 +594,7 @@ define i16 @test_mask_pcmpeq_b_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpeqb %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x74,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpeq.b.128(<16 x i8> %a, <16 x i8> %b, i16 %mask) ret i16 %res @@ -607,7 +607,7 @@ define i8 @test_pcmpeq_w_128(<8 x i16> %a, <8 x i16> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x75,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.w.128(<8 x i16> %a, <8 x i16> %b, i8 -1) ret i8 %res @@ -619,7 +619,7 @@ define i8 @test_mask_pcmpeq_w_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x75,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.w.128(<8 x i16> %a, <8 x i16> %b, i8 %mask) ret i8 %res @@ -632,7 +632,7 @@ define i16 @test_pcmpgt_b_128(<16 x i8> %a, <16 x i8> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x64,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpgt.b.128(<16 x i8> %a, <16 x i8> %b, i16 -1) ret i16 %res @@ -644,7 +644,7 @@ define i16 @test_mask_pcmpgt_b_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x64,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.mask.pcmpgt.b.128(<16 x i8> %a, <16 x i8> %b, i16 %mask) ret i16 %res @@ -657,7 +657,7 @@ define i8 @test_pcmpgt_w_128(<8 x i16> %a, <8 x i16> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x65,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.w.128(<8 x i16> %a, <8 x i16> %b, i8 -1) ret i8 %res @@ -669,7 +669,7 @@ define i8 @test_mask_pcmpgt_w_128(<8 x i16> %a, <8 x i16> %b, i8 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ## encoding: [0xc5,0xfb,0x92,0xcf] ; CHECK-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x65,0xc1] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.w.128(<8 x i16> %a, <8 x i16> %b, i8 %mask) ret i8 %res @@ -3683,7 +3683,7 @@ define i16@test_int_x86_avx512_ptestm_b_128(<16 x i8> %x0, <16 x i8> %x1, i16 %x ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.ptestm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2) %res1 = call i16 @llvm.x86.avx512.ptestm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16-1) @@ -3721,7 +3721,7 @@ define i8@test_int_x86_avx512_ptestm_w_128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2) ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8-1) @@ -3740,7 +3740,7 @@ define i16@test_int_x86_avx512_ptestm_w_256(<16 x i16> %x0, <16 x i16> %x1, i16 ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.ptestm.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2) @@ -3760,7 +3760,7 @@ define i16@test_int_x86_avx512_ptestnm_b_128(<16 x i8> %x0, <16 x i8> %x1, i16 % ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.ptestnm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16 %x2) %res1 = call i16 @llvm.x86.avx512.ptestnm.b.128(<16 x i8> %x0, <16 x i8> %x1, i16-1) @@ -3798,7 +3798,7 @@ define i8@test_int_x86_avx512_ptestnm_w_128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2 ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestnm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.w.128(<8 x i16> %x0, <8 x i16> %x1, i8-1) @@ -3817,7 +3817,7 @@ define i16@test_int_x86_avx512_ptestnm_w_256(<16 x i16> %x0, <16 x i16> %x1, i16 ; CHECK-NEXT: kmovd %k1, %ecx ## encoding: [0xc5,0xfb,0x93,0xc9] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: addl %ecx, %eax ## encoding: [0x01,0xc8] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.ptestnm.w.256(<16 x i16> %x0, <16 x i16> %x1, i16 %x2) diff --git a/test/CodeGen/X86/avx512bwvl-intrinsics.ll b/test/CodeGen/X86/avx512bwvl-intrinsics.ll index 8ec43460771..89bbe36282b 100644 --- a/test/CodeGen/X86/avx512bwvl-intrinsics.ll +++ b/test/CodeGen/X86/avx512bwvl-intrinsics.ll @@ -2311,7 +2311,7 @@ define i16@test_int_x86_avx512_cvtb2mask_128(<16 x i8> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovb2m %xmm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x08,0x29,0xc0] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.cvtb2mask.128(<16 x i8> %x0) ret i16 %res @@ -2336,7 +2336,7 @@ define i8@test_int_x86_avx512_cvtw2mask_128(<8 x i16> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovw2m %xmm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x08,0x29,0xc0] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.cvtw2mask.128(<8 x i16> %x0) ret i8 %res @@ -2349,7 +2349,7 @@ define i16@test_int_x86_avx512_cvtw2mask_256(<16 x i16> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovw2m %ymm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x28,0x29,0xc0] ; CHECK-NEXT: kmovd %k0, %eax ## encoding: [0xc5,0xfb,0x93,0xc0] -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i16 @llvm.x86.avx512.cvtw2mask.256(<16 x i16> %x0) ret i16 %res diff --git a/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll b/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll index 44075deb1d9..73135c27630 100644 --- a/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll +++ b/test/CodeGen/X86/avx512bwvl-vec-test-testn.ll @@ -7,7 +7,7 @@ define zeroext i16 @TEST_mm_test_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) local ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -24,7 +24,7 @@ define zeroext i16 @TEST_mm_mask_test_epi8_mask(i16 zeroext %__U, <2 x i64> %__A ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -42,7 +42,7 @@ define zeroext i8 @TEST_mm_test_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) local ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -59,7 +59,7 @@ define zeroext i8 @TEST_mm_mask_test_epi16_mask(i8 zeroext %__U, <2 x i64> %__A, ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -77,7 +77,7 @@ define zeroext i16 @TEST_mm_testn_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) loca ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -94,7 +94,7 @@ define zeroext i16 @TEST_mm_mask_testn_epi8_mask(i16 zeroext %__U, <2 x i64> %__ ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -112,7 +112,7 @@ define zeroext i8 @TEST_mm_testn_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) loca ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -129,7 +129,7 @@ define zeroext i8 @TEST_mm_mask_testn_epi16_mask(i8 zeroext %__U, <2 x i64> %__A ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -182,7 +182,7 @@ define zeroext i16 @TEST_mm256_test_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) l ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -200,7 +200,7 @@ define zeroext i16 @TEST_mm256_mask_test_epi16_mask(i16 zeroext %__U, <4 x i64> ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -254,7 +254,7 @@ define zeroext i16 @TEST_mm256_testn_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -272,7 +272,7 @@ define zeroext i16 @TEST_mm256_mask_testn_epi16_mask(i16 zeroext %__U, <4 x i64> ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: diff --git a/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll index c652e63408e..d59d9f82321 100644 --- a/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll @@ -161,7 +161,7 @@ declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x8.512(<8 x float>, <16 x define <16 x float>@test_int_x86_avx512_mask_broadcastf32x8_512(<8 x float> %x0, <16 x float> %x2, i16 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x8_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinsertf32x8 $1, %ymm0, %zmm0, %zmm1 {%k1} @@ -195,7 +195,7 @@ declare <8 x double> @llvm.x86.avx512.mask.broadcastf64x2.512(<2 x double>, <8 x define <8 x double>@test_int_x86_avx512_mask_broadcastf64x2_512(<2 x double> %x0, <8 x double> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 @@ -230,7 +230,7 @@ declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x8.512(<8 x i32>, <16 x i32 define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x8_512(<8 x i32> %x0, <16 x i32> %x2, i16 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x8_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vinserti32x8 $1, %ymm0, %zmm0, %zmm1 {%k1} @@ -264,7 +264,7 @@ declare <8 x i64> @llvm.x86.avx512.mask.broadcasti64x2.512(<2 x i64>, <8 x i64>, define <8 x i64>@test_int_x86_avx512_mask_broadcasti64x2_512(<2 x i64> %x0, <8 x i64> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 @@ -299,7 +299,7 @@ declare <16 x float> @llvm.x86.avx512.mask.broadcastf32x2.512(<4 x float>, <16 x define <16 x float>@test_int_x86_avx512_mask_broadcastf32x2_512(<4 x float> %x0, <16 x float> %x2, i16 %x3) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 @@ -321,7 +321,7 @@ declare <16 x i32> @llvm.x86.avx512.mask.broadcasti32x2.512(<4 x i32>, <16 x i32 define <16 x i32>@test_int_x86_avx512_mask_broadcasti32x2_512(<4 x i32> %x0, <16 x i32> %x2, i16 %x3) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_512: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm2 ; CHECK-NEXT: kmovw %edi, %k1 diff --git a/test/CodeGen/X86/avx512dq-intrinsics.ll b/test/CodeGen/X86/avx512dq-intrinsics.ll index 529f58d6d6e..6e3358e4a17 100644 --- a/test/CodeGen/X86/avx512dq-intrinsics.ll +++ b/test/CodeGen/X86/avx512dq-intrinsics.ll @@ -351,7 +351,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0, i8 %x1) { ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addb %cl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1) @@ -369,7 +369,7 @@ define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0, i16 %x1) { ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 %x1) %res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1) @@ -388,7 +388,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0, i8 %x1) { ; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addb %cl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 2, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1) @@ -401,7 +401,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd_load(<2 x double>* %x0ptr) { ; CHECK: ## BB#0: ; CHECK-NEXT: vfpclasssd $4, (%rdi), %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %x0 = load <2 x double>, <2 x double>* %x0ptr %res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1) @@ -419,7 +419,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) { ; CHECK-NEXT: vfpclassss $4, %xmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: addb %cl, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1) @@ -432,7 +432,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss_load(<4 x float>* %x0ptr, i8 %x1) ; CHECK: ## BB#0: ; CHECK-NEXT: vfpclassss $4, (%rdi), %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %x0 = load <4 x float>, <4 x float>* %x0ptr %res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1) @@ -446,7 +446,7 @@ define i16@test_int_x86_avx512_cvtd2mask_512(<16 x i32> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovd2m %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.cvtd2mask.512(<16 x i32> %x0) ret i16 %res @@ -459,7 +459,7 @@ define i8@test_int_x86_avx512_cvtq2mask_512(<8 x i64> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovq2m %zmm0, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i8 @llvm.x86.avx512.cvtq2mask.512(<8 x i64> %x0) ret i8 %res diff --git a/test/CodeGen/X86/avx512dq-mask-op.ll b/test/CodeGen/X86/avx512dq-mask-op.ll index f0ae1b0129a..ec7672912a1 100644 --- a/test/CodeGen/X86/avx512dq-mask-op.ll +++ b/test/CodeGen/X86/avx512dq-mask-op.ll @@ -7,7 +7,7 @@ define i8 @mask8(i8 %x) { ; CHECK-NEXT: kmovd %edi, %k0 ; CHECK-NEXT: knotb %k0, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %m0 = bitcast i8 %x to <8 x i1> %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1> @@ -57,7 +57,7 @@ define i8 @mand8_mem(<8 x i1>* %x, <8 x i1>* %y) { ; CHECK-NEXT: kxorb %k1, %k0, %k0 ; CHECK-NEXT: korb %k0, %k2, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %ma = load <8 x i1>, <8 x i1>* %x %mb = load <8 x i1>, <8 x i1>* %y diff --git a/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll index 20e5d3f78f1..dc1dd08e6b4 100644 --- a/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll @@ -1673,7 +1673,7 @@ declare <4 x double> @llvm.x86.avx512.mask.broadcastf64x2.256(<2 x double>, <4 x define <4 x double>@test_int_x86_avx512_mask_broadcastf64x2_256(<2 x double> %x0, <4 x double> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf64x2_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01] ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vinsertf64x2 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x18,0xc8,0x01] @@ -1708,7 +1708,7 @@ declare <4 x i64> @llvm.x86.avx512.mask.broadcasti64x2.256(<2 x i64>, <4 x i64>, define <4 x i64>@test_int_x86_avx512_mask_broadcasti64x2_256(<2 x i64> %x0, <4 x i64> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti64x2_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x38,0xd0,0x01] ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vinserti64x2 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0xfd,0x29,0x38,0xc8,0x01] @@ -1743,7 +1743,7 @@ declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x2.256(<4 x float>, <8 x f define <8 x float>@test_int_x86_avx512_mask_broadcastf32x2_256(<4 x float> %x0, <8 x float> %x2, i8 %x3) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x2_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01] ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vinsertf32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x18,0xc8,0x01] @@ -1764,7 +1764,7 @@ declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x2.256(<4 x i32>, <8 x i32>, define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x2_256(<4 x i32> %x0, <8 x i32> %x2, i8 %x3, i64 * %y_ptr) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x2_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vmovq (%rsi), %xmm2 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7e,0x16] ; CHECK-NEXT: ## xmm2 = mem[0],zero ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] diff --git a/test/CodeGen/X86/avx512dqvl-intrinsics.ll b/test/CodeGen/X86/avx512dqvl-intrinsics.ll index a3c876cb7d3..863d2341737 100644 --- a/test/CodeGen/X86/avx512dqvl-intrinsics.ll +++ b/test/CodeGen/X86/avx512dqvl-intrinsics.ll @@ -560,7 +560,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0, i8 %x1) { ; CHECK-NEXT: vfpclassps $4, %xmm0, %k0 ## encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 2, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.128(<4 x float> %x0, i32 4, i8 -1) @@ -579,7 +579,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0, i8 %x1) { ; CHECK-NEXT: vfpclassps $4, %ymm0, %k0 ## encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 2, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.ps.256(<8 x float> %x0, i32 4, i8 -1) @@ -598,7 +598,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0, i8 %x1) { ; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 ## encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 4, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.128(<2 x double> %x0, i32 2, i8 -1) @@ -617,7 +617,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0, i8 %x1) { ; CHECK-NEXT: vfpclasspd $4, %ymm0, %k0 ## encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 2, i8 %x1) %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.256(<4 x double> %x0, i32 4, i8 -1) @@ -632,7 +632,7 @@ define i8@test_int_x86_avx512_cvtd2mask_128(<4 x i32> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovd2m %xmm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x08,0x39,0xc0] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.cvtd2mask.128(<4 x i32> %x0) ret i8 %res @@ -645,7 +645,7 @@ define i8@test_int_x86_avx512_cvtd2mask_256(<8 x i32> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovd2m %ymm0, %k0 ## encoding: [0x62,0xf2,0x7e,0x28,0x39,0xc0] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.cvtd2mask.256(<8 x i32> %x0) ret i8 %res @@ -658,7 +658,7 @@ define i8@test_int_x86_avx512_cvtq2mask_128(<2 x i64> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovq2m %xmm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x08,0x39,0xc0] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.cvtq2mask.128(<2 x i64> %x0) ret i8 %res @@ -671,7 +671,7 @@ define i8@test_int_x86_avx512_cvtq2mask_256(<4 x i64> %x0) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpmovq2m %ymm0, %k0 ## encoding: [0x62,0xf2,0xfe,0x28,0x39,0xc0] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.cvtq2mask.256(<4 x i64> %x0) ret i8 %res diff --git a/test/CodeGen/X86/avx512f-vec-test-testn.ll b/test/CodeGen/X86/avx512f-vec-test-testn.ll index e9cdacc354f..7067c902d37 100644 --- a/test/CodeGen/X86/avx512f-vec-test-testn.ll +++ b/test/CodeGen/X86/avx512f-vec-test-testn.ll @@ -7,7 +7,7 @@ define zeroext i8 @TEST_mm512_test_epi64_mask(<8 x i64> %__A, <8 x i64> %__B) lo ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -23,7 +23,7 @@ define zeroext i16 @TEST_mm512_test_epi32_mask(<8 x i64> %__A, <8 x i64> %__B) l ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestmd %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -41,7 +41,7 @@ define zeroext i8 @TEST_mm512_mask_test_epi64_mask(i8 %__U, <8 x i64> %__A, <8 x ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -60,7 +60,7 @@ define zeroext i16 @TEST_mm512_mask_test_epi32_mask(i16 %__U, <8 x i64> %__A, <8 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -79,7 +79,7 @@ define zeroext i8 @TEST_mm512_testn_epi64_mask(<8 x i64> %__A, <8 x i64> %__B) l ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -95,7 +95,7 @@ define zeroext i16 @TEST_mm512_testn_epi32_mask(<8 x i64> %__A, <8 x i64> %__B) ; CHECK: # BB#0: # %entry ; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -113,7 +113,7 @@ define zeroext i8 @TEST_mm512_mask_testn_epi64_mask(i8 %__U, <8 x i64> %__A, <8 ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: @@ -132,7 +132,7 @@ define zeroext i16 @TEST_mm512_mask_testn_epi32_mask(i16 %__U, <8 x i64> %__A, < ; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1} ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq entry: diff --git a/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll b/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll index 3ff1de1a54a..2fad69e4b71 100644 --- a/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll +++ b/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll @@ -1064,7 +1064,7 @@ define i8 @test_pcmpeq_d_256(<8 x i32> %a, <8 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x76,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.256(<8 x i32> %a, <8 x i32> %b, i8 -1) ret i8 %res @@ -1076,7 +1076,7 @@ define i8 @test_mask_pcmpeq_d_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x76,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.256(<8 x i32> %a, <8 x i32> %b, i8 %mask) ret i8 %res @@ -1089,7 +1089,7 @@ define i8 @test_pcmpeq_q_256(<4 x i64> %a, <4 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x28,0x29,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.256(<4 x i64> %a, <4 x i64> %b, i8 -1) ret i8 %res @@ -1101,7 +1101,7 @@ define i8 @test_mask_pcmpeq_q_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x29,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.256(<4 x i64> %a, <4 x i64> %b, i8 %mask) ret i8 %res @@ -1114,7 +1114,7 @@ define i8 @test_pcmpgt_d_256(<8 x i32> %a, <8 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x28,0x66,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.256(<8 x i32> %a, <8 x i32> %b, i8 -1) ret i8 %res @@ -1126,7 +1126,7 @@ define i8 @test_mask_pcmpgt_d_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0x66,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.256(<8 x i32> %a, <8 x i32> %b, i8 %mask) ret i8 %res @@ -1139,7 +1139,7 @@ define i8 @test_pcmpgt_q_256(<4 x i64> %a, <4 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x28,0x37,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.256(<4 x i64> %a, <4 x i64> %b, i8 -1) ret i8 %res @@ -1151,7 +1151,7 @@ define i8 @test_mask_pcmpgt_q_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x29,0x37,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.256(<4 x i64> %a, <4 x i64> %b, i8 %mask) ret i8 %res @@ -1164,7 +1164,7 @@ define i8 @test_pcmpeq_d_128(<4 x i32> %a, <4 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x76,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.128(<4 x i32> %a, <4 x i32> %b, i8 -1) ret i8 %res @@ -1176,7 +1176,7 @@ define i8 @test_mask_pcmpeq_d_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x76,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.d.128(<4 x i32> %a, <4 x i32> %b, i8 %mask) ret i8 %res @@ -1189,7 +1189,7 @@ define i8 @test_pcmpeq_q_128(<2 x i64> %a, <2 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x08,0x29,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.128(<2 x i64> %a, <2 x i64> %b, i8 -1) ret i8 %res @@ -1201,7 +1201,7 @@ define i8 @test_mask_pcmpeq_q_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x29,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpeq.q.128(<2 x i64> %a, <2 x i64> %b, i8 %mask) ret i8 %res @@ -1214,7 +1214,7 @@ define i8 @test_pcmpgt_d_128(<4 x i32> %a, <4 x i32> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7d,0x08,0x66,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.128(<4 x i32> %a, <4 x i32> %b, i8 -1) ret i8 %res @@ -1226,7 +1226,7 @@ define i8 @test_mask_pcmpgt_d_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0x66,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.d.128(<4 x i32> %a, <4 x i32> %b, i8 %mask) ret i8 %res @@ -1239,7 +1239,7 @@ define i8 @test_pcmpgt_q_128(<2 x i64> %a, <2 x i64> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf2,0xfd,0x08,0x37,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.128(<2 x i64> %a, <2 x i64> %b, i8 -1) ret i8 %res @@ -1251,7 +1251,7 @@ define i8 @test_mask_pcmpgt_q_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) { ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ## encoding: [0x62,0xf2,0xfd,0x09,0x37,0xc1] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.pcmpgt.q.128(<2 x i64> %a, <2 x i64> %b, i8 %mask) ret i8 %res @@ -5867,7 +5867,7 @@ declare <8 x float> @llvm.x86.avx512.mask.broadcastf32x4.256(<4 x float>, <8 x f define <8 x float>@test_int_x86_avx512_mask_broadcastf32x4_256(<4 x float> %x0, <8 x float> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcastf32x4_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x18,0xd0,0x01] ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vinsertf32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x18,0xc8,0x01] @@ -5900,7 +5900,7 @@ declare <8 x i32> @llvm.x86.avx512.mask.broadcasti32x4.256(<4 x i32>, <8 x i32>, define <8 x i32>@test_int_x86_avx512_mask_broadcasti32x4_256(<4 x i32> %x0, <8 x i32> %x2, i8 %mask) { ; CHECK-LABEL: test_int_x86_avx512_mask_broadcasti32x4_256: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm2 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x38,0xd0,0x01] ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf] ; CHECK-NEXT: vinserti32x4 $1, %xmm0, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf3,0x7d,0x29,0x38,0xc8,0x01] @@ -6003,7 +6003,7 @@ define i8@test_int_x86_avx512_ptestm_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8-1) @@ -6022,7 +6022,7 @@ define i8@test_int_x86_avx512_ptestm_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8-1) @@ -6041,7 +6041,7 @@ define i8@test_int_x86_avx512_ptestm_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8-1) @@ -6060,7 +6060,7 @@ define i8@test_int_x86_avx512_ptestm_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8-1) @@ -6079,7 +6079,7 @@ define i8@test_int_x86_avx512_ptestnm_d_128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2 ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestnm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.d.128(<4 x i32> %x0, <4 x i32> %x1, i8-1) @@ -6098,7 +6098,7 @@ define i8@test_int_x86_avx512_ptestnm_d_256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2 ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestnm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.d.256(<8 x i32> %x0, <8 x i32> %x1, i8-1) @@ -6117,7 +6117,7 @@ define i8@test_int_x86_avx512_ptestnm_q_128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2 ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestnm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.q.128(<2 x i64> %x0, <2 x i64> %x1, i8-1) @@ -6136,7 +6136,7 @@ define i8@test_int_x86_avx512_ptestnm_q_256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2 ; CHECK-NEXT: kmovw %k1, %ecx ## encoding: [0xc5,0xf8,0x93,0xc9] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: addb %cl, %al ## encoding: [0x00,0xc8] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.ptestnm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8 %x2) %res1 = call i8 @llvm.x86.avx512.ptestnm.q.256(<4 x i64> %x0, <4 x i64> %x1, i8-1) diff --git a/test/CodeGen/X86/avx512vl-intrinsics.ll b/test/CodeGen/X86/avx512vl-intrinsics.ll index 492d0d8a35f..0eb0cab1326 100644 --- a/test/CodeGen/X86/avx512vl-intrinsics.ll +++ b/test/CodeGen/X86/avx512vl-intrinsics.ll @@ -718,7 +718,7 @@ define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x28,0xc2,0xc1,0x02] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %a, <8 x float> %b, i32 2, i8 -1) ret i8 %res @@ -730,7 +730,7 @@ define i8 @test_cmpps_128(<4 x float> %a, <4 x float> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vcmpleps %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0x7c,0x08,0xc2,0xc1,0x02] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %a, <4 x float> %b, i32 2, i8 -1) ret i8 %res @@ -742,7 +742,7 @@ define i8 @test_cmppd_256(<4 x double> %a, <4 x double> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vcmplepd %ymm1, %ymm0, %k0 ## encoding: [0x62,0xf1,0xfd,0x28,0xc2,0xc1,0x02] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %a, <4 x double> %b, i32 2, i8 -1) ret i8 %res @@ -754,7 +754,7 @@ define i8 @test_cmppd_128(<2 x double> %a, <2 x double> %b) { ; CHECK: ## BB#0: ; CHECK-NEXT: vcmplepd %xmm1, %xmm0, %k0 ## encoding: [0x62,0xf1,0xfd,0x08,0xc2,0xc1,0x02] ; CHECK-NEXT: kmovw %k0, %eax ## encoding: [0xc5,0xf8,0x93,0xc0] -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ## encoding: [0xc3] %res = call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %a, <2 x double> %b, i32 2, i8 -1) ret i8 %res diff --git a/test/CodeGen/X86/avx512vl-vec-cmp.ll b/test/CodeGen/X86/avx512vl-vec-cmp.ll index caad3e10fce..e42b8d9a1bd 100644 --- a/test/CodeGen/X86/avx512vl-vec-cmp.ll +++ b/test/CodeGen/X86/avx512vl-vec-cmp.ll @@ -45,12 +45,12 @@ define <8 x i32> @test256_3(<8 x i32> %x, <8 x i32> %y, <8 x i32> %x1) nounwind ; ; NoVLX-LABEL: test256_3: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k1 ; NoVLX-NEXT: vpblendmd %zmm2, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %mask = icmp sge <8 x i32> %x, %y %max = select <8 x i1> %mask, <8 x i32> %x1, <8 x i32> %y @@ -86,12 +86,12 @@ define <8 x i32> @test256_5(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwin ; ; NoVLX-LABEL: test256_5: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpeqd %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp eq <8 x i32> %x, %y @@ -108,12 +108,12 @@ define <8 x i32> @test256_5b(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwi ; ; NoVLX-LABEL: test256_5b: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpeqd %zmm0, %zmm2, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp eq <8 x i32> %y, %x @@ -130,12 +130,12 @@ define <8 x i32> @test256_6(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) noun ; ; NoVLX-LABEL: test256_6: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpgtd %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp sgt <8 x i32> %x, %y @@ -152,12 +152,12 @@ define <8 x i32> @test256_6b(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nou ; ; NoVLX-LABEL: test256_6b: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpgtd %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp slt <8 x i32> %y, %x @@ -174,12 +174,12 @@ define <8 x i32> @test256_7(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) noun ; ; NoVLX-LABEL: test256_7: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp sle <8 x i32> %x, %y @@ -196,12 +196,12 @@ define <8 x i32> @test256_7b(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nou ; ; NoVLX-LABEL: test256_7b: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp sge <8 x i32> %y, %x @@ -218,12 +218,12 @@ define <8 x i32> @test256_8(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) noun ; ; NoVLX-LABEL: test256_8: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpleud %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp ule <8 x i32> %x, %y @@ -240,12 +240,12 @@ define <8 x i32> @test256_8b(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %y.ptr) nou ; ; NoVLX-LABEL: test256_8b: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpnltud %zmm0, %zmm2, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 %mask = icmp uge <8 x i32> %y, %x @@ -263,14 +263,14 @@ define <8 x i32> @test256_9(<8 x i32> %x, <8 x i32> %y, <8 x i32> %x1, <8 x i32> ; ; NoVLX-LABEL: test256_9: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM3<def> %YMM3<kill> %ZMM3<def> -; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm3<def> %ymm3<kill> %zmm3<def> +; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm3, %zmm2, %k1 {%k1} ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %mask1 = icmp eq <8 x i32> %x1, %y1 %mask0 = icmp eq <8 x i32> %x, %y @@ -336,14 +336,14 @@ define <8 x i32> @test256_12(<8 x i32> %x, <8 x i32>* %y.ptr, <8 x i32> %x1, <8 ; ; NoVLX-LABEL: test256_12: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm3 ; NoVLX-NEXT: vpcmpleud %zmm3, %zmm0, %k1 ; NoVLX-NEXT: vpcmpled %zmm1, %zmm2, %k1 {%k1} ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %mask1 = icmp sge <8 x i32> %x1, %y1 %y = load <8 x i32>, <8 x i32>* %y.ptr, align 4 @@ -383,12 +383,12 @@ define <8 x i32> @test256_14(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1) nounwind ; ; NoVLX-LABEL: test256_14: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpled %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %yb = load i32, i32* %yb.ptr, align 4 %y.0 = insertelement <8 x i32> undef, i32 %yb, i32 0 @@ -408,14 +408,14 @@ define <8 x i32> @test256_15(<8 x i32> %x, i32* %yb.ptr, <8 x i32> %x1, <8 x i32 ; ; NoVLX-LABEL: test256_15: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm3 ; NoVLX-NEXT: vpcmpgtd %zmm3, %zmm0, %k1 ; NoVLX-NEXT: vpcmpled %zmm1, %zmm2, %k1 {%k1} ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %mask1 = icmp sge <8 x i32> %x1, %y1 %yb = load i32, i32* %yb.ptr, align 4 @@ -462,12 +462,12 @@ define <8 x i32> @test256_17(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwi ; ; NoVLX-LABEL: test256_17: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpneqd %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp ne <8 x i32> %x, %y @@ -484,12 +484,12 @@ define <8 x i32> @test256_18(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwi ; ; NoVLX-LABEL: test256_18: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpneqd %zmm0, %zmm2, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp ne <8 x i32> %y, %x @@ -506,12 +506,12 @@ define <8 x i32> @test256_19(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwi ; ; NoVLX-LABEL: test256_19: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpnltud %zmm2, %zmm0, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp uge <8 x i32> %x, %y @@ -528,12 +528,12 @@ define <8 x i32> @test256_20(<8 x i32> %x, <8 x i32> %x1, <8 x i32>* %yp) nounwi ; ; NoVLX-LABEL: test256_20: ; NoVLX: # BB#0: -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqu (%rdi), %ymm2 ; NoVLX-NEXT: vpcmpnltud %zmm0, %zmm2, %k1 ; NoVLX-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; NoVLX-NEXT: retq %y = load <8 x i32>, <8 x i32>* %yp, align 4 %mask = icmp uge <8 x i32> %y, %x diff --git a/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll b/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll index 673e442a008..e4b626f52a8 100644 --- a/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll +++ b/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll @@ -1208,7 +1208,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v16i1_mask: @@ -1218,7 +1218,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -1235,7 +1235,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqw (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqw_v8i1_v16i1_mask_mem: @@ -1245,7 +1245,7 @@ define zeroext i16 @test_vpcmpeqw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -1264,7 +1264,7 @@ define zeroext i16 @test_masked_vpcmpeqw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v16i1_mask: @@ -1275,7 +1275,7 @@ define zeroext i16 @test_masked_vpcmpeqw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x i ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -1295,7 +1295,7 @@ define zeroext i16 @test_masked_vpcmpeqw_v8i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqw_v8i1_v16i1_mask_mem: @@ -1306,7 +1306,7 @@ define zeroext i16 @test_masked_vpcmpeqw_v8i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4200,7 +4200,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask: @@ -4239,7 +4239,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4256,7 +4256,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* % ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask_mem: @@ -4295,7 +4295,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* % ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4314,7 +4314,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i64 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask: @@ -4371,7 +4371,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i64 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4392,7 +4392,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask_mem: @@ -4449,7 +4449,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4471,7 +4471,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v8i1_mask_mem_b: @@ -4511,7 +4511,7 @@ define zeroext i8 @test_vpcmpeqd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4531,7 +4531,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v8i1_mask_mem_b: @@ -4589,7 +4589,7 @@ define zeroext i8 @test_masked_vpcmpeqd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4612,7 +4612,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask: @@ -4650,7 +4650,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4667,7 +4667,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask_mem: @@ -4705,7 +4705,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4724,7 +4724,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask: @@ -4780,7 +4780,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x i ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4801,7 +4801,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask_mem: @@ -4857,7 +4857,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4879,7 +4879,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v4i1_v16i1_mask_mem_b: @@ -4918,7 +4918,7 @@ define zeroext i16 @test_vpcmpeqd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -4938,7 +4938,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v16i1_mask_mem_b: @@ -4995,7 +4995,7 @@ define zeroext i16 @test_masked_vpcmpeqd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5698,19 +5698,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5727,19 +5727,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5758,20 +5758,20 @@ define zeroext i16 @test_masked_vpcmpeqd_v8i1_v16i1_mask(i8 zeroext %__u, <4 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5791,20 +5791,20 @@ define zeroext i16 @test_masked_vpcmpeqd_v8i1_v16i1_mask_mem(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5825,19 +5825,19 @@ define zeroext i16 @test_vpcmpeqd_v8i1_v16i1_mask_mem_b(<4 x i64> %__a, i32* %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5857,20 +5857,20 @@ define zeroext i16 @test_masked_vpcmpeqd_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -5904,8 +5904,8 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v32i1_mask(<4 x i64> %__a, <4 x i64> %__b ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -5977,7 +5977,7 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v32i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6052,8 +6052,8 @@ define zeroext i32 @test_masked_vpcmpeqd_v8i1_v32i1_mask(i8 zeroext %__u, <4 x i ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6129,7 +6129,7 @@ define zeroext i32 @test_masked_vpcmpeqd_v8i1_v32i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} @@ -6207,7 +6207,7 @@ define zeroext i32 @test_vpcmpeqd_v8i1_v32i1_mask_mem_b(<4 x i64> %__a, i32* %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6283,7 +6283,7 @@ define zeroext i32 @test_masked_vpcmpeqd_v8i1_v32i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} @@ -6362,8 +6362,8 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v64i1_mask(<4 x i64> %__a, <4 x i64> %__b ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -6440,7 +6440,7 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v64i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6520,8 +6520,8 @@ define zeroext i64 @test_masked_vpcmpeqd_v8i1_v64i1_mask(i8 zeroext %__u, <4 x i ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6602,7 +6602,7 @@ define zeroext i64 @test_masked_vpcmpeqd_v8i1_v64i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} @@ -6685,7 +6685,7 @@ define zeroext i64 @test_vpcmpeqd_v8i1_v64i1_mask_mem_b(<4 x i64> %__a, i32* %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -6766,7 +6766,7 @@ define zeroext i64 @test_masked_vpcmpeqd_v8i1_v64i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} @@ -8520,7 +8520,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask: @@ -8543,7 +8543,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8560,7 +8560,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* % ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask_mem: @@ -8583,7 +8583,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* % ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8602,7 +8602,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i64 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask: @@ -8635,7 +8635,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i64 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8656,7 +8656,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask_mem: @@ -8689,7 +8689,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8711,7 +8711,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v8i1_mask_mem_b: @@ -8735,7 +8735,7 @@ define zeroext i8 @test_vpcmpeqq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8755,7 +8755,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v8i1_mask_mem_b: @@ -8789,7 +8789,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8812,7 +8812,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask: @@ -8834,7 +8834,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__b ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8851,7 +8851,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask_mem: @@ -8873,7 +8873,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8892,7 +8892,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask: @@ -8924,7 +8924,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x i ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8945,7 +8945,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask_mem: @@ -8977,7 +8977,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -8999,7 +8999,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v16i1_mask_mem_b: @@ -9022,7 +9022,7 @@ define zeroext i16 @test_vpcmpeqq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -9042,7 +9042,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpeqq_v2i1_v16i1_mask_mem_b: @@ -9075,7 +9075,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -9730,7 +9730,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -9771,7 +9771,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -9788,7 +9788,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* % ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -9829,7 +9829,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* % ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -9848,7 +9848,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i64 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -9907,7 +9907,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i64 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -9928,7 +9928,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -9987,7 +9987,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 x ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10009,7 +10009,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10051,7 +10051,7 @@ define zeroext i8 @test_vpcmpeqq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10071,7 +10071,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10131,7 +10131,7 @@ define zeroext i8 @test_masked_vpcmpeqq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, <4 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10154,7 +10154,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10194,7 +10194,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__b ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10211,7 +10211,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10251,7 +10251,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10270,7 +10270,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10328,7 +10328,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x i ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10349,7 +10349,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask_mem(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10407,7 +10407,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10429,7 +10429,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10470,7 +10470,7 @@ define zeroext i16 @test_vpcmpeqq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -10490,7 +10490,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -10549,7 +10549,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11276,7 +11276,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11284,7 +11284,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__b ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11301,7 +11301,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11309,7 +11309,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64>* ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpeqq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11328,7 +11328,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x i ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11337,7 +11337,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x i ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11357,7 +11357,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask_mem(i8 zeroext %__u, <8 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11366,7 +11366,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask_mem(i8 zeroext %__u, <8 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11387,7 +11387,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11395,7 +11395,7 @@ define zeroext i16 @test_vpcmpeqq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %__ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpeqq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -11415,7 +11415,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -11424,7 +11424,7 @@ define zeroext i16 @test_masked_vpcmpeqq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpeqq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -13569,7 +13569,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v16i1_mask: @@ -13579,7 +13579,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -13596,7 +13596,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtw (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtw_v8i1_v16i1_mask_mem: @@ -13606,7 +13606,7 @@ define zeroext i16 @test_vpcmpsgtw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -13625,7 +13625,7 @@ define zeroext i16 @test_masked_vpcmpsgtw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v16i1_mask: @@ -13636,7 +13636,7 @@ define zeroext i16 @test_masked_vpcmpsgtw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -13656,7 +13656,7 @@ define zeroext i16 @test_masked_vpcmpsgtw_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtw_v8i1_v16i1_mask_mem: @@ -13667,7 +13667,7 @@ define zeroext i16 @test_masked_vpcmpsgtw_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16561,7 +16561,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask: @@ -16600,7 +16600,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16617,7 +16617,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask_mem: @@ -16656,7 +16656,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16675,7 +16675,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask: @@ -16732,7 +16732,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16753,7 +16753,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem: @@ -16810,7 +16810,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16832,7 +16832,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v8i1_mask_mem_b: @@ -16872,7 +16872,7 @@ define zeroext i8 @test_vpcmpsgtd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16892,7 +16892,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem_b: @@ -16950,7 +16950,7 @@ define zeroext i8 @test_masked_vpcmpsgtd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -16973,7 +16973,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask: @@ -17011,7 +17011,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -17028,7 +17028,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask_mem: @@ -17066,7 +17066,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -17085,7 +17085,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask: @@ -17141,7 +17141,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -17162,7 +17162,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem: @@ -17218,7 +17218,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -17240,7 +17240,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v4i1_v16i1_mask_mem_b: @@ -17279,7 +17279,7 @@ define zeroext i16 @test_vpcmpsgtd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -17299,7 +17299,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem_b: @@ -17356,7 +17356,7 @@ define zeroext i16 @test_masked_vpcmpsgtd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18059,19 +18059,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18088,19 +18088,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18119,20 +18119,20 @@ define zeroext i16 @test_masked_vpcmpsgtd_v8i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18152,20 +18152,20 @@ define zeroext i16 @test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18186,19 +18186,19 @@ define zeroext i16 @test_vpcmpsgtd_v8i1_v16i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18218,20 +18218,20 @@ define zeroext i16 @test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -18265,8 +18265,8 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_v32i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -18338,7 +18338,7 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_v32i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -18413,8 +18413,8 @@ define zeroext i32 @test_masked_vpcmpsgtd_v8i1_v32i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -18490,7 +18490,7 @@ define zeroext i32 @test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} @@ -18568,7 +18568,7 @@ define zeroext i32 @test_vpcmpsgtd_v8i1_v32i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -18644,7 +18644,7 @@ define zeroext i32 @test_masked_vpcmpsgtd_v8i1_v32i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} @@ -18723,8 +18723,8 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_v64i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -18801,7 +18801,7 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_v64i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -18881,8 +18881,8 @@ define zeroext i64 @test_masked_vpcmpsgtd_v8i1_v64i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -18963,7 +18963,7 @@ define zeroext i64 @test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} @@ -19046,7 +19046,7 @@ define zeroext i64 @test_vpcmpsgtd_v8i1_v64i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -19127,7 +19127,7 @@ define zeroext i64 @test_masked_vpcmpsgtd_v8i1_v64i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 {%k1} @@ -20881,7 +20881,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask: @@ -20904,7 +20904,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -20921,7 +20921,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask_mem: @@ -20944,7 +20944,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -20963,7 +20963,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask: @@ -20996,7 +20996,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21017,7 +21017,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem: @@ -21050,7 +21050,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21072,7 +21072,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v8i1_mask_mem_b: @@ -21096,7 +21096,7 @@ define zeroext i8 @test_vpcmpsgtq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21116,7 +21116,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem_b: @@ -21150,7 +21150,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21173,7 +21173,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask: @@ -21195,7 +21195,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21212,7 +21212,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask_mem: @@ -21234,7 +21234,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21253,7 +21253,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask: @@ -21285,7 +21285,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21306,7 +21306,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem: @@ -21338,7 +21338,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21360,7 +21360,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v16i1_mask_mem_b: @@ -21383,7 +21383,7 @@ define zeroext i16 @test_vpcmpsgtq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -21403,7 +21403,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem_b: @@ -21436,7 +21436,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22091,7 +22091,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22132,7 +22132,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22149,7 +22149,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22190,7 +22190,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22209,7 +22209,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22268,7 +22268,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22289,7 +22289,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22348,7 +22348,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22370,7 +22370,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22412,7 +22412,7 @@ define zeroext i8 @test_vpcmpsgtq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22432,7 +22432,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22492,7 +22492,7 @@ define zeroext i8 @test_masked_vpcmpsgtq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22515,7 +22515,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22555,7 +22555,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22572,7 +22572,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22612,7 +22612,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22631,7 +22631,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22689,7 +22689,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22710,7 +22710,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22768,7 +22768,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22790,7 +22790,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22831,7 +22831,7 @@ define zeroext i16 @test_vpcmpsgtq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -22851,7 +22851,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -22910,7 +22910,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23637,7 +23637,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23645,7 +23645,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23662,7 +23662,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23670,7 +23670,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpgtq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23689,7 +23689,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23698,7 +23698,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23718,7 +23718,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23727,7 +23727,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23748,7 +23748,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23756,7 +23756,7 @@ define zeroext i16 @test_vpcmpsgtq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpgtq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -23776,7 +23776,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -23785,7 +23785,7 @@ define zeroext i16 @test_masked_vpcmpsgtq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpgtq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -25960,7 +25960,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v16i1_mask: @@ -25972,7 +25972,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -25989,7 +25989,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltw (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgew_v8i1_v16i1_mask_mem: @@ -26002,7 +26002,7 @@ define zeroext i16 @test_vpcmpsgew_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -26021,7 +26021,7 @@ define zeroext i16 @test_masked_vpcmpsgew_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmplew %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v16i1_mask: @@ -26034,7 +26034,7 @@ define zeroext i16 @test_masked_vpcmpsgew_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -26054,7 +26054,7 @@ define zeroext i16 @test_masked_vpcmpsgew_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgew_v8i1_v16i1_mask_mem: @@ -26068,7 +26068,7 @@ define zeroext i16 @test_masked_vpcmpsgew_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29018,7 +29018,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask: @@ -29059,7 +29059,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29076,7 +29076,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask_mem: @@ -29118,7 +29118,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29137,7 +29137,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask: @@ -29194,7 +29194,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29215,7 +29215,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask_mem: @@ -29273,7 +29273,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29295,7 +29295,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v8i1_mask_mem_b: @@ -29337,7 +29337,7 @@ define zeroext i8 @test_vpcmpsged_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29357,7 +29357,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v8i1_mask_mem_b: @@ -29415,7 +29415,7 @@ define zeroext i8 @test_masked_vpcmpsged_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29438,7 +29438,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask: @@ -29478,7 +29478,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29495,7 +29495,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask_mem: @@ -29536,7 +29536,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29555,7 +29555,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpled %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask: @@ -29611,7 +29611,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29632,7 +29632,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask_mem: @@ -29689,7 +29689,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29711,7 +29711,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v4i1_v16i1_mask_mem_b: @@ -29752,7 +29752,7 @@ define zeroext i16 @test_vpcmpsged_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -29772,7 +29772,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v4i1_v16i1_mask_mem_b: @@ -29829,7 +29829,7 @@ define zeroext i16 @test_masked_vpcmpsged_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30548,19 +30548,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30577,19 +30577,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30608,20 +30608,20 @@ define zeroext i16 @test_masked_vpcmpsged_v8i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpled %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30641,20 +30641,20 @@ define zeroext i16 @test_masked_vpcmpsged_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30675,19 +30675,19 @@ define zeroext i16 @test_vpcmpsged_v8i1_v16i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltd (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsged_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30707,20 +30707,20 @@ define zeroext i16 @test_masked_vpcmpsged_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltd (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsged_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -30754,8 +30754,8 @@ define zeroext i32 @test_vpcmpsged_v8i1_v32i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -30827,7 +30827,7 @@ define zeroext i32 @test_vpcmpsged_v8i1_v32i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -30902,8 +30902,8 @@ define zeroext i32 @test_masked_vpcmpsged_v8i1_v32i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -30979,7 +30979,7 @@ define zeroext i32 @test_masked_vpcmpsged_v8i1_v32i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} @@ -31057,7 +31057,7 @@ define zeroext i32 @test_vpcmpsged_v8i1_v32i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -31133,7 +31133,7 @@ define zeroext i32 @test_masked_vpcmpsged_v8i1_v32i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} @@ -31212,8 +31212,8 @@ define zeroext i64 @test_vpcmpsged_v8i1_v64i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -31290,7 +31290,7 @@ define zeroext i64 @test_vpcmpsged_v8i1_v64i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -31370,8 +31370,8 @@ define zeroext i64 @test_masked_vpcmpsged_v8i1_v64i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -31452,7 +31452,7 @@ define zeroext i64 @test_masked_vpcmpsged_v8i1_v64i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} @@ -31535,7 +31535,7 @@ define zeroext i64 @test_vpcmpsged_v8i1_v64i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -31616,7 +31616,7 @@ define zeroext i64 @test_masked_vpcmpsged_v8i1_v64i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpled %zmm0, %zmm1, %k0 {%k1} @@ -33378,7 +33378,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask: @@ -33403,7 +33403,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33420,7 +33420,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask_mem: @@ -33446,7 +33446,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33465,7 +33465,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask: @@ -33498,7 +33498,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33519,7 +33519,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem: @@ -33553,7 +33553,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33575,7 +33575,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v8i1_mask_mem_b: @@ -33601,7 +33601,7 @@ define zeroext i8 @test_vpcmpsgeq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33621,7 +33621,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem_b: @@ -33655,7 +33655,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33678,7 +33678,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask: @@ -33702,7 +33702,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33719,7 +33719,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask_mem: @@ -33744,7 +33744,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33763,7 +33763,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpleq %xmm0, %xmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask: @@ -33795,7 +33795,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33816,7 +33816,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem: @@ -33849,7 +33849,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33871,7 +33871,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v16i1_mask_mem_b: @@ -33896,7 +33896,7 @@ define zeroext i16 @test_vpcmpsgeq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -33916,7 +33916,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem_b: @@ -33949,7 +33949,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34620,7 +34620,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -34663,7 +34663,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34680,7 +34680,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -34724,7 +34724,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34743,7 +34743,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -34804,7 +34804,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34825,7 +34825,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -34887,7 +34887,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34909,7 +34909,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -34953,7 +34953,7 @@ define zeroext i8 @test_vpcmpsgeq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -34973,7 +34973,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35035,7 +35035,7 @@ define zeroext i8 @test_masked_vpcmpsgeq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35058,7 +35058,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35100,7 +35100,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35117,7 +35117,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35160,7 +35160,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35179,7 +35179,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpleq %ymm0, %ymm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35239,7 +35239,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35260,7 +35260,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35321,7 +35321,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35343,7 +35343,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35386,7 +35386,7 @@ define zeroext i16 @test_vpcmpsgeq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -35406,7 +35406,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -35467,7 +35467,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36222,7 +36222,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36230,7 +36230,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36247,7 +36247,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36255,7 +36255,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpnltq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36274,7 +36274,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36283,7 +36283,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36303,7 +36303,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36312,7 +36312,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpnltq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36333,7 +36333,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpnltq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36341,7 +36341,7 @@ define zeroext i16 @test_vpcmpsgeq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpnltq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -36361,7 +36361,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpnltq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -36370,7 +36370,7 @@ define zeroext i16 @test_masked_vpcmpsgeq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpnltq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -38551,7 +38551,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultw_v8i1_v16i1_mask: @@ -38564,7 +38564,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -38581,7 +38581,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuw (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultw_v8i1_v16i1_mask_mem: @@ -38594,7 +38594,7 @@ define zeroext i16 @test_vpcmpultw_v8i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpsllq $63, %zmm0, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -38613,7 +38613,7 @@ define zeroext i16 @test_masked_vpcmpultw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuw %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v16i1_mask: @@ -38627,7 +38627,7 @@ define zeroext i16 @test_masked_vpcmpultw_v8i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -38647,7 +38647,7 @@ define zeroext i16 @test_masked_vpcmpultw_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuw (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultw_v8i1_v16i1_mask_mem: @@ -38661,7 +38661,7 @@ define zeroext i16 @test_masked_vpcmpultw_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41623,7 +41623,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask: @@ -41665,7 +41665,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41682,7 +41682,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask_mem: @@ -41724,7 +41724,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41743,7 +41743,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask: @@ -41803,7 +41803,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41824,7 +41824,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask_mem: @@ -41884,7 +41884,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41906,7 +41906,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v8i1_mask_mem_b: @@ -41949,7 +41949,7 @@ define zeroext i8 @test_vpcmpultd_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, i32* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -41969,7 +41969,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v8i1_mask_mem_b: @@ -42030,7 +42030,7 @@ define zeroext i8 @test_masked_vpcmpultd_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42053,7 +42053,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask: @@ -42094,7 +42094,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42111,7 +42111,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask_mem: @@ -42152,7 +42152,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42171,7 +42171,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask: @@ -42230,7 +42230,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42251,7 +42251,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask_mem: @@ -42310,7 +42310,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42332,7 +42332,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v4i1_v16i1_mask_mem_b: @@ -42374,7 +42374,7 @@ define zeroext i16 @test_vpcmpultd_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, i32* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -42394,7 +42394,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v4i1_v16i1_mask_mem_b: @@ -42454,7 +42454,7 @@ define zeroext i16 @test_masked_vpcmpultd_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43193,19 +43193,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43222,19 +43222,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43253,20 +43253,20 @@ define zeroext i16 @test_masked_vpcmpultd_v8i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43286,20 +43286,20 @@ define zeroext i16 @test_masked_vpcmpultd_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43320,19 +43320,19 @@ define zeroext i16 @test_vpcmpultd_v8i1_v16i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltud (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43352,20 +43352,20 @@ define zeroext i16 @test_masked_vpcmpultd_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltud (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultd_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -43399,8 +43399,8 @@ define zeroext i32 @test_vpcmpultd_v8i1_v32i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -43472,7 +43472,7 @@ define zeroext i32 @test_vpcmpultd_v8i1_v32i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -43547,8 +43547,8 @@ define zeroext i32 @test_masked_vpcmpultd_v8i1_v32i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -43624,7 +43624,7 @@ define zeroext i32 @test_masked_vpcmpultd_v8i1_v32i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} @@ -43702,7 +43702,7 @@ define zeroext i32 @test_vpcmpultd_v8i1_v32i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -43778,7 +43778,7 @@ define zeroext i32 @test_masked_vpcmpultd_v8i1_v32i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} @@ -43857,8 +43857,8 @@ define zeroext i64 @test_vpcmpultd_v8i1_v64i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -43935,7 +43935,7 @@ define zeroext i64 @test_vpcmpultd_v8i1_v64i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -44015,8 +44015,8 @@ define zeroext i64 @test_masked_vpcmpultd_v8i1_v64i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -44097,7 +44097,7 @@ define zeroext i64 @test_masked_vpcmpultd_v8i1_v64i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovdqa (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} @@ -44180,7 +44180,7 @@ define zeroext i64 @test_vpcmpultd_v8i1_v64i1_mask_mem_b(<4 x i64> %__a, i32* %_ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rdi), %ymm1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -44261,7 +44261,7 @@ define zeroext i64 @test_masked_vpcmpultd_v8i1_v64i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vpbroadcastd (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltud %zmm1, %zmm0, %k0 {%k1} @@ -46033,7 +46033,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask: @@ -46059,7 +46059,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46076,7 +46076,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask_mem: @@ -46102,7 +46102,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46121,7 +46121,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask: @@ -46157,7 +46157,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask(i8 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46178,7 +46178,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask_mem: @@ -46214,7 +46214,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask_mem(i8 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46236,7 +46236,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v8i1_mask_mem_b: @@ -46263,7 +46263,7 @@ define zeroext i8 @test_vpcmpultq_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46283,7 +46283,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v8i1_mask_mem_b: @@ -46320,7 +46320,7 @@ define zeroext i8 @test_masked_vpcmpultq_v2i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46343,7 +46343,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask: @@ -46368,7 +46368,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46385,7 +46385,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask_mem: @@ -46410,7 +46410,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46429,7 +46429,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask: @@ -46464,7 +46464,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask(i8 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46485,7 +46485,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask_mem: @@ -46520,7 +46520,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46542,7 +46542,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vpcmpultq_v2i1_v16i1_mask_mem_b: @@ -46568,7 +46568,7 @@ define zeroext i16 @test_vpcmpultq_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -46588,7 +46588,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vpcmpultq_v2i1_v16i1_mask_mem_b: @@ -46624,7 +46624,7 @@ define zeroext i16 @test_masked_vpcmpultq_v2i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47315,7 +47315,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47359,7 +47359,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47376,7 +47376,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47420,7 +47420,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47439,7 +47439,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47501,7 +47501,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask(i8 zeroext %__u, <4 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47522,7 +47522,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47584,7 +47584,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask_mem(i8 zeroext %__u, <4 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47606,7 +47606,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47651,7 +47651,7 @@ define zeroext i8 @test_vpcmpultq_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, i64* %__b ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47671,7 +47671,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47734,7 +47734,7 @@ define zeroext i8 @test_masked_vpcmpultq_v4i1_v8i1_mask_mem_b(i8 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47757,7 +47757,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47800,7 +47800,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47817,7 +47817,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47860,7 +47860,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47879,7 +47879,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -47940,7 +47940,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -47961,7 +47961,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48022,7 +48022,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -48044,7 +48044,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48088,7 +48088,7 @@ define zeroext i16 @test_vpcmpultq_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, i64* %_ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -48108,7 +48108,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48170,7 +48170,7 @@ define zeroext i16 @test_masked_vpcmpultq_v4i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -48933,7 +48933,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48941,7 +48941,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -48958,7 +48958,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48966,7 +48966,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpltuq (%rdi), %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -48985,7 +48985,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -48994,7 +48994,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -49014,7 +49014,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -49023,7 +49023,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltuq (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -49044,7 +49044,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -49052,7 +49052,7 @@ define zeroext i16 @test_vpcmpultq_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, i64* %_ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vpcmpltuq (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -49072,7 +49072,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -49081,7 +49081,7 @@ define zeroext i16 @test_masked_vpcmpultq_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vpcmpltuq (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50026,7 +50026,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask: @@ -50065,7 +50065,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50082,7 +50082,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask_mem: @@ -50121,7 +50121,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50139,7 +50139,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, float* %_ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v8i1_mask_mem_b: @@ -50179,7 +50179,7 @@ define zeroext i8 @test_vcmpoeqps_v4i1_v8i1_mask_mem_b(<2 x i64> %__a, float* %_ ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50200,7 +50200,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask(i4 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask: @@ -50245,7 +50245,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask(i4 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50266,7 +50266,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask_mem(i4 zeroext %__u, <2 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask_mem: @@ -50311,7 +50311,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask_mem(i4 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50333,7 +50333,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask_mem_b(i4 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v8i1_mask_mem_b: @@ -50379,7 +50379,7 @@ define zeroext i8 @test_masked_vcmpoeqps_v4i1_v8i1_mask_mem_b(i4 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50402,7 +50402,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask: @@ -50440,7 +50440,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50457,7 +50457,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask_mem: @@ -50495,7 +50495,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50513,7 +50513,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, float* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi){1to4}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v4i1_v16i1_mask_mem_b: @@ -50552,7 +50552,7 @@ define zeroext i16 @test_vcmpoeqps_v4i1_v16i1_mask_mem_b(<2 x i64> %__a, float* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50573,7 +50573,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask(i4 zeroext %__u, <2 x ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask: @@ -50617,7 +50617,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask(i4 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50638,7 +50638,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask_mem(i4 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask_mem: @@ -50682,7 +50682,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask_mem(i4 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -50704,7 +50704,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask_mem_b(i4 zeroext %__u, ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqps (%rsi){1to4}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v4i1_v16i1_mask_mem_b: @@ -50749,7 +50749,7 @@ define zeroext i16 @test_masked_vcmpoeqps_v4i1_v16i1_mask_mem_b(i4 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51380,19 +51380,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51409,19 +51409,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51439,19 +51439,19 @@ define zeroext i16 @test_vcmpoeqps_v8i1_v16i1_mask_mem_b(<4 x i64> %__a, float* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqps (%rdi){1to8}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqps_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51471,20 +51471,20 @@ define zeroext i16 @test_masked_vcmpoeqps_v8i1_v16i1_mask(i8 zeroext %__u, <4 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqps %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51504,20 +51504,20 @@ define zeroext i16 @test_masked_vcmpoeqps_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqps (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask_mem: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51538,20 +51538,20 @@ define zeroext i16 @test_masked_vcmpoeqps_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqps (%rsi){1to8}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqps_v8i1_v16i1_mask_mem_b: ; NoVLX: # BB#0: # %entry -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kshiftlw $8, %k0, %k0 ; NoVLX-NEXT: kshiftrw $8, %k0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -51586,8 +51586,8 @@ define zeroext i32 @test_vcmpoeqps_v8i1_v32i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -51659,7 +51659,7 @@ define zeroext i32 @test_vcmpoeqps_v8i1_v32i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -51733,7 +51733,7 @@ define zeroext i32 @test_vcmpoeqps_v8i1_v32i1_mask_mem_b(<4 x i64> %__a, float* ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -51809,8 +51809,8 @@ define zeroext i32 @test_masked_vcmpoeqps_v8i1_v32i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -51886,7 +51886,7 @@ define zeroext i32 @test_masked_vcmpoeqps_v8i1_v32i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} @@ -51964,7 +51964,7 @@ define zeroext i32 @test_masked_vcmpoeqps_v8i1_v32i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $32, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} @@ -52044,8 +52044,8 @@ define zeroext i64 @test_vcmpoeqps_v8i1_v64i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 ; NoVLX-NEXT: kmovw %k1, {{[0-9]+}}(%rsp) @@ -52122,7 +52122,7 @@ define zeroext i64 @test_vcmpoeqps_v8i1_v64i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -52201,7 +52201,7 @@ define zeroext i64 @test_vcmpoeqps_v8i1_v64i1_mask_mem_b(<4 x i64> %__a, float* ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rdi), %ymm1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -52282,8 +52282,8 @@ define zeroext i64 @test_masked_vcmpoeqps_v8i1_v64i1_mask(i8 zeroext %__u, <4 x ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kxorw %k0, %k0, %k1 @@ -52364,7 +52364,7 @@ define zeroext i64 @test_masked_vcmpoeqps_v8i1_v64i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vmovaps (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} @@ -52447,7 +52447,7 @@ define zeroext i64 @test_masked_vcmpoeqps_v8i1_v64i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: .cfi_def_cfa_register %rbp ; NoVLX-NEXT: andq $-32, %rsp ; NoVLX-NEXT: subq $64, %rsp -; NoVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; NoVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; NoVLX-NEXT: vbroadcastss (%rsi), %ymm1 ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqps %zmm1, %zmm0, %k0 {%k1} @@ -54281,7 +54281,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask: @@ -54304,7 +54304,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask(<2 x i64> %__a, <2 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54321,7 +54321,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask_mem: @@ -54344,7 +54344,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask_mem(<2 x i64> %__a, <2 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54362,7 +54362,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, double* % ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v8i1_mask_mem_b: @@ -54386,7 +54386,7 @@ define zeroext i8 @test_vcmpoeqpd_v2i1_v8i1_mask_mem_b(<2 x i64> %__a, double* % ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54407,7 +54407,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask(i2 zeroext %__u, <2 x i6 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask: @@ -54435,7 +54435,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask(i2 zeroext %__u, <2 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54456,7 +54456,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem(i2 zeroext %__u, <2 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem: @@ -54484,7 +54484,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem(i2 zeroext %__u, <2 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54506,7 +54506,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem_b(i2 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem_b: @@ -54535,7 +54535,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v2i1_v8i1_mask_mem_b(i2 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54558,7 +54558,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask: @@ -54580,7 +54580,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask(<2 x i64> %__a, <2 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54597,7 +54597,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi), %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask_mem: @@ -54619,7 +54619,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask_mem(<2 x i64> %__a, <2 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54637,7 +54637,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, double* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi){1to2}, %xmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v16i1_mask_mem_b: @@ -54660,7 +54660,7 @@ define zeroext i16 @test_vcmpoeqpd_v2i1_v16i1_mask_mem_b(<2 x i64> %__a, double* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54681,7 +54681,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask(i2 zeroext %__u, <2 x ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd %xmm1, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask: @@ -54708,7 +54708,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask(i2 zeroext %__u, <2 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54729,7 +54729,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem(i2 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi), %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem: @@ -54756,7 +54756,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem(i2 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -54778,7 +54778,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem_b(i2 zeroext %__u, ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi){1to2}, %xmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: retq ; ; NoVLX-LABEL: test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem_b: @@ -54806,7 +54806,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v2i1_v16i1_mask_mem_b(i2 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55431,7 +55431,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55472,7 +55472,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask(<4 x i64> %__a, <4 x i64> %__b) ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55489,7 +55489,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55530,7 +55530,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask_mem(<4 x i64> %__a, <4 x i64>* ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55548,7 +55548,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, double* % ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55590,7 +55590,7 @@ define zeroext i8 @test_vcmpoeqpd_v4i1_v8i1_mask_mem_b(<4 x i64> %__a, double* % ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55611,7 +55611,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask(i4 zeroext %__u, <4 x i6 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55658,7 +55658,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask(i4 zeroext %__u, <4 x i6 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55679,7 +55679,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask_mem(i4 zeroext %__u, <4 ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55726,7 +55726,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask_mem(i4 zeroext %__u, <4 ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55748,7 +55748,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask_mem_b(i4 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55796,7 +55796,7 @@ define zeroext i8 @test_masked_vcmpoeqpd_v4i1_v8i1_mask_mem_b(i4 zeroext %__u, < ; NoVLX-NEXT: vpsllq $63, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmq %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55819,7 +55819,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55859,7 +55859,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask(<4 x i64> %__a, <4 x i64> %__ ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55876,7 +55876,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi), %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55916,7 +55916,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask_mem(<4 x i64> %__a, <4 x i64> ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55934,7 +55934,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, double* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi){1to4}, %ymm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -55975,7 +55975,7 @@ define zeroext i16 @test_vcmpoeqpd_v4i1_v16i1_mask_mem_b(<4 x i64> %__a, double* ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -55996,7 +55996,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask(i4 zeroext %__u, <4 x ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd %ymm1, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56042,7 +56042,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask(i4 zeroext %__u, <4 x ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56063,7 +56063,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask_mem(i4 zeroext %__u, < ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi), %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56109,7 +56109,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask_mem(i4 zeroext %__u, < ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56131,7 +56131,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask_mem_b(i4 zeroext %__u, ; VLX-NEXT: kmovb -{{[0-9]+}}(%rsp), %k1 ; VLX-NEXT: vcmpeqpd (%rsi){1to4}, %ymm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56178,7 +56178,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v4i1_v16i1_mask_mem_b(i4 zeroext %__u, ; NoVLX-NEXT: vpslld $31, %zmm2, %zmm0 ; NoVLX-NEXT: vptestmd %zmm0, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56833,7 +56833,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56841,7 +56841,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask(<8 x i64> %__a, <8 x i64> %__ ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56858,7 +56858,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56866,7 +56866,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask_mem(<8 x i64> %__a, <8 x i64> ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vcmpeqpd (%rdi), %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56884,7 +56884,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, double* ; VLX: # BB#0: # %entry ; VLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56892,7 +56892,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_mask_mem_b(<8 x i64> %__a, double* ; NoVLX: # BB#0: # %entry ; NoVLX-NEXT: vcmpeqpd (%rdi){1to8}, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56912,7 +56912,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56921,7 +56921,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask(i8 zeroext %__u, <8 x ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56941,7 +56941,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56950,7 +56950,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask_mem(i8 zeroext %__u, < ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqpd (%rsi), %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -56971,7 +56971,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; VLX-NEXT: kmovd %edi, %k1 ; VLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -56980,7 +56980,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_mask_mem_b(i8 zeroext %__u, ; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: vcmpeqpd (%rsi){1to8}, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -57004,7 +57004,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_sae_mask(<8 x i64> %__a, <8 x i64> ; VLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 ; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: movzbl %al, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -57013,7 +57013,7 @@ define zeroext i16 @test_vcmpoeqpd_v8i1_v16i1_sae_mask(<8 x i64> %__a, <8 x i64> ; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 ; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: movzbl %al, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: @@ -57031,7 +57031,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask(i8 zeroext %__u, < ; VLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 {%k1} ; VLX-NEXT: kmovd %k0, %eax ; VLX-NEXT: movzbl %al, %eax -; VLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VLX-NEXT: vzeroupper ; VLX-NEXT: retq ; @@ -57041,7 +57041,7 @@ define zeroext i16 @test_masked_vcmpoeqpd_v8i1_v16i1_sae_mask(i8 zeroext %__u, < ; NoVLX-NEXT: vcmplepd {sae}, %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: movzbl %al, %eax -; NoVLX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NoVLX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: retq entry: diff --git a/test/CodeGen/X86/avx512vl-vec-test-testn.ll b/test/CodeGen/X86/avx512vl-vec-test-testn.ll index 32de0254efa..b0dd9c24359 100644 --- a/test/CodeGen/X86/avx512vl-vec-test-testn.ll +++ b/test/CodeGen/X86/avx512vl-vec-test-testn.ll @@ -8,14 +8,14 @@ define zeroext i8 @TEST_mm_test_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) local ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestmq %xmm0, %xmm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_test_epi64_mask: ; I386: # BB#0: # %entry ; I386-NEXT: vptestmq %xmm0, %xmm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -31,14 +31,14 @@ define zeroext i8 @TEST_mm_test_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) local ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestmd %xmm0, %xmm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_test_epi32_mask: ; I386: # BB#0: # %entry ; I386-NEXT: vptestmd %xmm0, %xmm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -55,7 +55,7 @@ define zeroext i8 @TEST_mm256_test_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) lo ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestmq %ymm0, %ymm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -63,7 +63,7 @@ define zeroext i8 @TEST_mm256_test_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) lo ; I386: # BB#0: # %entry ; I386-NEXT: vptestmq %ymm0, %ymm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -80,7 +80,7 @@ define zeroext i8 @TEST_mm256_test_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) lo ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestmd %ymm0, %ymm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -88,7 +88,7 @@ define zeroext i8 @TEST_mm256_test_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) lo ; I386: # BB#0: # %entry ; I386-NEXT: vptestmd %ymm0, %ymm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -106,7 +106,7 @@ define zeroext i8 @TEST_mm_mask_test_epi64_mask(i8 %__U, <2 x i64> %__A, <2 x i6 ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_mask_test_epi64_mask: @@ -115,7 +115,7 @@ define zeroext i8 @TEST_mm_mask_test_epi64_mask(i8 %__U, <2 x i64> %__A, <2 x i6 ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -135,7 +135,7 @@ define zeroext i8 @TEST_mm_mask_test_epi32_mask(i8 %__U, <2 x i64> %__A, <2 x i6 ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_mask_test_epi32_mask: @@ -144,7 +144,7 @@ define zeroext i8 @TEST_mm_mask_test_epi32_mask(i8 %__U, <2 x i64> %__A, <2 x i6 ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -166,7 +166,7 @@ define zeroext i8 @TEST_mm256_mask_test_epi64_mask(i8 %__U, <4 x i64> %__A, <4 x ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -176,7 +176,7 @@ define zeroext i8 @TEST_mm256_mask_test_epi64_mask(i8 %__U, <4 x i64> %__A, <4 x ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -197,7 +197,7 @@ define zeroext i8 @TEST_mm256_mask_test_epi32_mask(i8 %__U, <4 x i64> %__A, <4 x ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -207,7 +207,7 @@ define zeroext i8 @TEST_mm256_mask_test_epi32_mask(i8 %__U, <4 x i64> %__A, <4 x ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -226,14 +226,14 @@ define zeroext i8 @TEST_mm_testn_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) loca ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestnmq %xmm0, %xmm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_testn_epi64_mask: ; I386: # BB#0: # %entry ; I386-NEXT: vptestnmq %xmm0, %xmm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -249,14 +249,14 @@ define zeroext i8 @TEST_mm_testn_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) loca ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestnmd %xmm0, %xmm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_testn_epi32_mask: ; I386: # BB#0: # %entry ; I386-NEXT: vptestnmd %xmm0, %xmm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -273,7 +273,7 @@ define zeroext i8 @TEST_mm256_testn_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) l ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestnmq %ymm0, %ymm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -281,7 +281,7 @@ define zeroext i8 @TEST_mm256_testn_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) l ; I386: # BB#0: # %entry ; I386-NEXT: vptestnmq %ymm0, %ymm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -298,7 +298,7 @@ define zeroext i8 @TEST_mm256_testn_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) l ; X86_64: # BB#0: # %entry ; X86_64-NEXT: vptestnmd %ymm0, %ymm1, %k0 ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -306,7 +306,7 @@ define zeroext i8 @TEST_mm256_testn_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) l ; I386: # BB#0: # %entry ; I386-NEXT: vptestnmd %ymm0, %ymm1, %k0 ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -324,7 +324,7 @@ define zeroext i8 @TEST_mm_mask_testn_epi64_mask(i8 %__U, <2 x i64> %__A, <2 x i ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_mask_testn_epi64_mask: @@ -333,7 +333,7 @@ define zeroext i8 @TEST_mm_mask_testn_epi64_mask(i8 %__U, <2 x i64> %__A, <2 x i ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -353,7 +353,7 @@ define zeroext i8 @TEST_mm_mask_testn_epi32_mask(i8 %__U, <2 x i64> %__A, <2 x i ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: retq ; ; I386-LABEL: TEST_mm_mask_testn_epi32_mask: @@ -362,7 +362,7 @@ define zeroext i8 @TEST_mm_mask_testn_epi32_mask(i8 %__U, <2 x i64> %__A, <2 x i ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: retl entry: %and.i.i = and <2 x i64> %__B, %__A @@ -384,7 +384,7 @@ define zeroext i8 @TEST_mm256_mask_testn_epi64_mask(i8 %__U, <4 x i64> %__A, <4 ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -394,7 +394,7 @@ define zeroext i8 @TEST_mm256_mask_testn_epi64_mask(i8 %__U, <4 x i64> %__A, <4 ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: @@ -415,7 +415,7 @@ define zeroext i8 @TEST_mm256_mask_testn_epi32_mask(i8 %__U, <4 x i64> %__A, <4 ; X86_64-NEXT: kmovw %edi, %k1 ; X86_64-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; X86_64-NEXT: kmovw %k0, %eax -; X86_64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86_64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86_64-NEXT: vzeroupper ; X86_64-NEXT: retq ; @@ -425,7 +425,7 @@ define zeroext i8 @TEST_mm256_mask_testn_epi32_mask(i8 %__U, <4 x i64> %__A, <4 ; I386-NEXT: kmovw %eax, %k1 ; I386-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; I386-NEXT: kmovw %k0, %eax -; I386-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; I386-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; I386-NEXT: vzeroupper ; I386-NEXT: retl entry: diff --git a/test/CodeGen/X86/base-pointer-and-cmpxchg.ll b/test/CodeGen/X86/base-pointer-and-cmpxchg.ll index 8de6d64428e..a79509b039a 100644 --- a/test/CodeGen/X86/base-pointer-and-cmpxchg.ll +++ b/test/CodeGen/X86/base-pointer-and-cmpxchg.ll @@ -19,23 +19,23 @@ ; USE_BASE_64: movq %rsp, %rbx ; USE_BASE_32: movl %esp, %ebx ; -; Make sure the base pointer is saved before the RBX argument for +; Make sure the base pointer is saved before the rbx argument for ; cmpxchg16b is set. ; -; Because of how the test is written, we spill SAVE_RBX. +; Because of how the test is written, we spill SAVE_rbx. ; However, it would have been perfectly fine to just keep it in register. -; USE_BASE: movq %rbx, [[SAVE_RBX_SLOT:[0-9]*\(%[er]bx\)]] +; USE_BASE: movq %rbx, [[SAVE_rbx_SLOT:[0-9]*\(%[er]bx\)]] ; -; SAVE_RBX must be in register before we clobber rbx. +; SAVE_rbx must be in register before we clobber rbx. ; It is fine to use any register but rbx and the ones defined and use ; by cmpxchg. Since such regex would be complicated to write, just stick ; to the numbered registers. The bottom line is: if this test case fails ; because of that regex, this is likely just the regex being too conservative. -; USE_BASE: movq [[SAVE_RBX_SLOT]], [[SAVE_RBX:%r[0-9]+]] +; USE_BASE: movq [[SAVE_rbx_SLOT]], [[SAVE_rbx:%r[0-9]+]] ; ; USE_BASE: movq {{[^ ]+}}, %rbx ; USE_BASE-NEXT: cmpxchg16b -; USE_BASE-NEXT: movq [[SAVE_RBX]], %rbx +; USE_BASE-NEXT: movq [[SAVE_rbx]], %rbx ; ; DONT_USE_BASE-NOT: movq %rsp, %rbx ; DONT_USE_BASE-NOT: movl %esp, %ebx diff --git a/test/CodeGen/X86/bitcast-and-setcc-128.ll b/test/CodeGen/X86/bitcast-and-setcc-128.ll index 2ea93aef009..ef062aeb3f0 100644 --- a/test/CodeGen/X86/bitcast-and-setcc-128.ll +++ b/test/CodeGen/X86/bitcast-and-setcc-128.ll @@ -14,7 +14,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i16: @@ -24,7 +24,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v8i16: @@ -38,7 +38,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -47,7 +47,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { ; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k1 ; AVX512BW-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq %x0 = icmp sgt <8 x i16> %a, %b %x1 = icmp sgt <8 x i16> %c, %d @@ -63,7 +63,7 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; SSE2-SSSE3-NEXT: pcmpgtd %xmm3, %xmm2 ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i32: @@ -72,7 +72,7 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; AVX12-NEXT: vpcmpgtd %xmm3, %xmm2, %xmm1 ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i32: @@ -106,7 +106,7 @@ define i4 @v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) ; SSE2-SSSE3-NEXT: cmpltps %xmm2, %xmm3 ; SSE2-SSSE3-NEXT: andps %xmm1, %xmm3 ; SSE2-SSSE3-NEXT: movmskps %xmm3, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4f32: @@ -115,7 +115,7 @@ define i4 @v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) ; AVX12-NEXT: vcmpltps %xmm2, %xmm3, %xmm1 ; AVX12-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4f32: @@ -149,7 +149,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { ; SSE2-SSSE3-NEXT: pcmpgtb %xmm3, %xmm2 ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v16i8: @@ -158,7 +158,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { ; AVX12-NEXT: vpcmpgtb %xmm3, %xmm2, %xmm1 ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v16i8: @@ -172,7 +172,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { ; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -181,7 +181,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { ; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm0, %k1 ; AVX512BW-NEXT: vpcmpgtb %xmm3, %xmm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq %x0 = icmp sgt <16 x i8> %a, %b %x1 = icmp sgt <16 x i8> %c, %d @@ -244,7 +244,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) { ; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i8: @@ -273,7 +273,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) { ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i8: @@ -302,7 +302,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) { ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i8: @@ -399,7 +399,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) { ; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i16: @@ -428,7 +428,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) { ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i16: @@ -457,7 +457,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) { ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i16: @@ -546,7 +546,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) { ; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0 ; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i32: @@ -571,7 +571,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) { ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i32: @@ -596,7 +596,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) { ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i32: @@ -665,7 +665,7 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { ; SSE2-SSSE3-NEXT: por %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v2i64: @@ -674,7 +674,7 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { ; AVX12-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm1 ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskpd %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v2i64: @@ -708,7 +708,7 @@ define i2 @v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> ; SSE2-SSSE3-NEXT: cmpltpd %xmm2, %xmm3 ; SSE2-SSSE3-NEXT: andpd %xmm1, %xmm3 ; SSE2-SSSE3-NEXT: movmskpd %xmm3, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v2f64: @@ -717,7 +717,7 @@ define i2 @v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> ; AVX12-NEXT: vcmpltpd %xmm2, %xmm3, %xmm1 ; AVX12-NEXT: vandpd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskpd %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v2f64: @@ -759,7 +759,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i8> %d) { ; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i8: @@ -776,7 +776,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i8> %d) { ; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i8: @@ -834,7 +834,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { ; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i16: @@ -851,7 +851,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { ; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i16: @@ -910,7 +910,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { ; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i8: @@ -928,7 +928,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { ; AVX12-NEXT: vpand %xmm2, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v8i8: @@ -950,7 +950,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -967,7 +967,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) { ; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k1 ; AVX512BW-NEXT: vpcmpgtw %xmm3, %xmm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq %x0 = icmp sgt <8 x i8> %a, %b %x1 = icmp sgt <8 x i8> %c, %d diff --git a/test/CodeGen/X86/bitcast-and-setcc-256.ll b/test/CodeGen/X86/bitcast-and-setcc-256.ll index e197713c679..3fb66e400ce 100644 --- a/test/CodeGen/X86/bitcast-and-setcc-256.ll +++ b/test/CodeGen/X86/bitcast-and-setcc-256.ll @@ -54,7 +54,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) { ; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2] ; SSE2-SSSE3-NEXT: andps %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v4i64: @@ -71,7 +71,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) { ; AVX1-NEXT: vpackssdw %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskps %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -85,7 +85,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) { ; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskps %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -126,7 +126,7 @@ define i4 @v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x double> ; SSE2-SSSE3-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm7[0,2] ; SSE2-SSSE3-NEXT: andps %xmm2, %xmm6 ; SSE2-SSSE3-NEXT: movmskps %xmm6, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4f64: @@ -139,7 +139,7 @@ define i4 @v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x double> ; AVX12-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; @@ -180,7 +180,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { ; SSE2-SSSE3-NEXT: packsswb %xmm5, %xmm4 ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4 ; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax -; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v16i16: @@ -197,7 +197,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { ; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -211,7 +211,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { ; AVX2-NEXT: vpacksswb %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -226,7 +226,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { ; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -235,7 +235,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { ; AVX512BW-NEXT: vpcmpgtw %ymm1, %ymm0, %k1 ; AVX512BW-NEXT: vpcmpgtw %ymm3, %ymm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = icmp sgt <16 x i16> %a, %b @@ -257,7 +257,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm4 ; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v8i32: @@ -275,7 +275,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -290,7 +290,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -299,7 +299,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; AVX512F-NEXT: vpcmpgtd %ymm1, %ymm0, %k1 ; AVX512F-NEXT: vpcmpgtd %ymm3, %ymm2, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -308,7 +308,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) { ; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm0, %k1 ; AVX512BW-NEXT: vpcmpgtd %ymm3, %ymm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = icmp sgt <8 x i32> %a, %b @@ -330,7 +330,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) ; SSE2-SSSE3-NEXT: pand %xmm2, %xmm6 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm6 ; SSE2-SSSE3-NEXT: pmovmskb %xmm6, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8f32: @@ -344,7 +344,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; @@ -353,7 +353,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) ; AVX512F-NEXT: vcmpltps %ymm0, %ymm1, %k1 ; AVX512F-NEXT: vcmpltps %ymm2, %ymm3, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -362,7 +362,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) ; AVX512BW-NEXT: vcmpltps %ymm0, %ymm1, %k1 ; AVX512BW-NEXT: vcmpltps %ymm2, %ymm3, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = fcmp ogt <8 x float> %a, %b diff --git a/test/CodeGen/X86/bitcast-and-setcc-512.ll b/test/CodeGen/X86/bitcast-and-setcc-512.ll index f6cfbbb4044..ef128913b1e 100644 --- a/test/CodeGen/X86/bitcast-and-setcc-512.ll +++ b/test/CodeGen/X86/bitcast-and-setcc-512.ll @@ -41,7 +41,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) { ; SSE-NEXT: psraw $15, %xmm8 ; SSE-NEXT: packsswb %xmm0, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v8i64: @@ -76,7 +76,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) { ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -104,7 +104,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) { ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -113,7 +113,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) { ; AVX512F-NEXT: vpcmpgtq %zmm1, %zmm0, %k1 ; AVX512F-NEXT: vpcmpgtq %zmm3, %zmm2, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -122,7 +122,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) { ; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k1 ; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = icmp sgt <8 x i64> %a, %b @@ -168,7 +168,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> ; SSE-NEXT: psraw $15, %xmm8 ; SSE-NEXT: packsswb %xmm0, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX12-LABEL: v8f64: @@ -195,7 +195,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; @@ -204,7 +204,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> ; AVX512F-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; AVX512F-NEXT: vcmpltpd %zmm2, %zmm3, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -213,7 +213,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> ; AVX512BW-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; AVX512BW-NEXT: vcmpltpd %zmm2, %zmm3, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = fcmp ogt <8 x double> %a, %b @@ -634,7 +634,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) { ; SSE-NEXT: packsswb %xmm10, %xmm8 ; SSE-NEXT: pand %xmm0, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v16i32: @@ -663,7 +663,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) { ; AVX1-NEXT: vpacksswb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -685,7 +685,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) { ; AVX2-NEXT: vpacksswb %xmm1, %xmm2, %xmm1 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -694,7 +694,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) { ; AVX512F-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; AVX512F-NEXT: vpcmpgtd %zmm3, %zmm2, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -703,7 +703,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i32> %d) { ; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; AVX512BW-NEXT: vpcmpgtd %zmm3, %zmm2, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = icmp sgt <16 x i32> %a, %b @@ -736,7 +736,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x floa ; SSE-NEXT: packsswb %xmm10, %xmm8 ; SSE-NEXT: pand %xmm4, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX12-LABEL: v16f32: @@ -757,7 +757,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x floa ; AVX12-NEXT: vpacksswb %xmm1, %xmm2, %xmm1 ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; @@ -766,7 +766,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x floa ; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; AVX512F-NEXT: vcmpltps %zmm2, %zmm3, %k0 {%k1} ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -775,7 +775,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x floa ; AVX512BW-NEXT: vcmpltps %zmm0, %zmm1, %k1 ; AVX512BW-NEXT: vcmpltps %zmm2, %zmm3, %k0 {%k1} ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x0 = fcmp ogt <16 x float> %a, %b diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll index 984d2b818fc..988cbe1e6df 100644 --- a/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll +++ b/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll @@ -12,7 +12,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; SSE2-SSSE3-LABEL: ext_i2_2i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -24,7 +24,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; ; AVX1-LABEL: ext_i2_2i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -34,7 +34,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; ; AVX2-LABEL: ext_i2_2i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -49,7 +49,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512-NEXT: kmovd %eax, %k1 ; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = bitcast i2 %a0 to <2 x i1> @@ -93,7 +93,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) { ; AVX512-NEXT: kmovd %eax, %k1 ; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z} -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = bitcast i4 %a0 to <4 x i1> @@ -197,7 +197,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) { define <4 x i64> @ext_i4_4i64(i4 %a0) { ; SSE2-SSSE3-LABEL: ext_i4_4i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -215,7 +215,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; ; AVX1-LABEL: ext_i4_4i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 @@ -232,7 +232,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; ; AVX2-LABEL: ext_i4_4i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %ymm0 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8] @@ -247,7 +247,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512-NEXT: kmovd %eax, %k1 ; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %1 = bitcast i4 %a0 to <4 x i1> %2 = sext <4 x i1> %1 to <4 x i64> @@ -422,7 +422,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) { define <8 x i64> @ext_i8_8i64(i8 %a0) { ; SSE2-SSSE3-LABEL: ext_i8_8i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -452,7 +452,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) { ; ; AVX1-LABEL: ext_i8_8i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 @@ -476,7 +476,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) { ; ; AVX2-LABEL: ext_i8_8i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8] diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll index 6d4fd919062..cab849d4987 100644 --- a/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll +++ b/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll @@ -13,7 +13,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; SSE2-SSSE3-LABEL: ext_i2_2i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -26,7 +26,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; ; AVX1-LABEL: ext_i2_2i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -37,7 +37,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; ; AVX2-LABEL: ext_i2_2i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -53,7 +53,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; AVX512F-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -64,7 +64,7 @@ define <2 x i64> @ext_i2_2i64(i2 %a0) { ; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512VLBW-NEXT: kmovd %eax, %k1 ; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} -; AVX512VLBW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VLBW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VLBW-NEXT: vzeroupper ; AVX512VLBW-NEXT: retq %1 = bitcast i2 %a0 to <2 x i1> @@ -111,7 +111,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) { ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -122,7 +122,7 @@ define <4 x i32> @ext_i4_4i32(i4 %a0) { ; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512VLBW-NEXT: kmovd %eax, %k1 ; AVX512VLBW-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z} -; AVX512VLBW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VLBW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VLBW-NEXT: vzeroupper ; AVX512VLBW-NEXT: retq %1 = bitcast i4 %a0 to <4 x i1> @@ -253,7 +253,7 @@ define <16 x i8> @ext_i16_16i8(i16 %a0) { define <4 x i64> @ext_i4_4i64(i4 %a0) { ; SSE2-SSSE3-LABEL: ext_i4_4i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -273,7 +273,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; ; AVX1-LABEL: ext_i4_4i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 @@ -292,7 +292,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; ; AVX2-LABEL: ext_i4_4i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %ymm0 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8] @@ -308,7 +308,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; AVX512F-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VLBW-LABEL: ext_i4_4i64: @@ -318,7 +318,7 @@ define <4 x i64> @ext_i4_4i64(i4 %a0) { ; AVX512VLBW-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512VLBW-NEXT: kmovd %eax, %k1 ; AVX512VLBW-NEXT: vpbroadcastq {{.*}}(%rip), %zmm0 {%k1} {z} -; AVX512VLBW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VLBW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VLBW-NEXT: retq %1 = bitcast i4 %a0 to <4 x i1> %2 = zext <4 x i1> %1 to <4 x i64> @@ -550,7 +550,7 @@ define <32 x i8> @ext_i32_32i8(i32 %a0) { define <8 x i64> @ext_i8_8i64(i8 %a0) { ; SSE2-SSSE3-LABEL: ext_i8_8i64: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -584,7 +584,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) { ; ; AVX1-LABEL: ext_i8_8i64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 @@ -612,7 +612,7 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) { ; ; AVX2-LABEL: ext_i8_8i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8] diff --git a/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/test/CodeGen/X86/bitcast-int-to-vector-bool.ll index 1cc644e5d55..5010d5c78c3 100644 --- a/test/CodeGen/X86/bitcast-int-to-vector-bool.ll +++ b/test/CodeGen/X86/bitcast-int-to-vector-bool.ll @@ -8,7 +8,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) { ; SSE2-SSSE3-LABEL: bitcast_i2_2i1: ; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-SSSE3-NEXT: movq %rdi, %xmm0 ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1] ; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm0 = [1,2] @@ -21,7 +21,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) { ; ; AVX1-LABEL: bitcast_i2_2i1: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: vmovq %rdi, %xmm0 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -32,7 +32,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) { ; ; AVX2-LABEL: bitcast_i2_2i1: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: vmovq %rdi, %xmm0 ; AVX2-NEXT: vpbroadcastq %xmm0, %xmm0 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2] @@ -47,7 +47,7 @@ define <2 x i1> @bitcast_i2_2i1(i2 zeroext %a0) { ; AVX512-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; AVX512-NEXT: kmovd %eax, %k1 ; AVX512-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = bitcast i2 %a0 to <2 x i1> @@ -92,7 +92,7 @@ define <4 x i1> @bitcast_i4_4i1(i4 zeroext %a0) { ; AVX512-NEXT: kmovd %eax, %k1 ; AVX512-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 ; AVX512-NEXT: vmovdqa32 %ymm0, %ymm0 {%k1} {z} -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = bitcast i4 %a0 to <4 x i1> diff --git a/test/CodeGen/X86/bitcast-int-to-vector.ll b/test/CodeGen/X86/bitcast-int-to-vector.ll index 4285dcca521..a260ac3706f 100644 --- a/test/CodeGen/X86/bitcast-int-to-vector.ll +++ b/test/CodeGen/X86/bitcast-int-to-vector.ll @@ -10,7 +10,7 @@ define i1 @foo(i64 %a) { ; X86-NEXT: flds {{[0-9]+}}(%esp) ; X86-NEXT: fucompp ; X86-NEXT: fnstsw %ax -; X86-NEXT: # kill: %AH<def> %AH<kill> %AX<kill> +; X86-NEXT: # kill: %ah<def> %ah<kill> %ax<kill> ; X86-NEXT: sahf ; X86-NEXT: setp %al ; X86-NEXT: retl diff --git a/test/CodeGen/X86/bitcast-setcc-128.ll b/test/CodeGen/X86/bitcast-setcc-128.ll index b8a176a71d7..d68bdfa5356 100644 --- a/test/CodeGen/X86/bitcast-setcc-128.ll +++ b/test/CodeGen/X86/bitcast-setcc-128.ll @@ -12,7 +12,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) { ; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i16: @@ -20,7 +20,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) { ; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v8i16: @@ -30,7 +30,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -38,7 +38,7 @@ define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq %x = icmp sgt <8 x i16> %a, %b %res = bitcast <8 x i1> %x to i8 @@ -50,14 +50,14 @@ define i4 @v4i32(<4 x i32> %a, <4 x i32> %b) { ; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i32: ; AVX12: # BB#0: ; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i32: @@ -85,14 +85,14 @@ define i4 @v4f32(<4 x float> %a, <4 x float> %b) { ; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3-NEXT: cmpltps %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskps %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4f32: ; AVX12: # BB#0: ; AVX12-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4f32: @@ -120,14 +120,14 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b) { ; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v16i8: ; AVX12: # BB#0: ; AVX12-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX12-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v16i8: @@ -137,7 +137,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b) { ; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -145,7 +145,7 @@ define i16 @v16i8(<16 x i8> %a, <16 x i8> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtb %xmm1, %xmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: retq %x = icmp sgt <16 x i8> %a, %b %res = bitcast <16 x i1> %x to i16 @@ -181,7 +181,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b) { ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i8: @@ -198,7 +198,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b) { ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i8: @@ -215,7 +215,7 @@ define i2 @v2i8(<2 x i8> %a, <2 x i8> %b) { ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i8: @@ -275,7 +275,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b) { ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i16: @@ -292,7 +292,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b) { ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i16: @@ -309,7 +309,7 @@ define i2 @v2i16(<2 x i16> %a, <2 x i16> %b) { ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i16: @@ -365,7 +365,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b) { ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v2i32: @@ -380,7 +380,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b) { ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmovmskpd %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: retq ; ; AVX2-LABEL: v2i32: @@ -395,7 +395,7 @@ define i2 @v2i32(<2 x i32> %a, <2 x i32> %b) { ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vmovmskpd %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v2i32: @@ -441,14 +441,14 @@ define i2 @v2i64(<2 x i64> %a, <2 x i64> %b) { ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v2i64: ; AVX12: # BB#0: ; AVX12-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskpd %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v2i64: @@ -476,14 +476,14 @@ define i2 @v2f64(<2 x double> %a, <2 x double> %b) { ; SSE2-SSSE3: # BB#0: ; SSE2-SSSE3-NEXT: cmpltpd %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v2f64: ; AVX12: # BB#0: ; AVX12-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 ; AVX12-NEXT: vmovmskpd %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v2f64: @@ -515,7 +515,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b) { ; SSE2-SSSE3-NEXT: psrad $24, %xmm0 ; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i8: @@ -526,7 +526,7 @@ define i4 @v4i8(<4 x i8> %a, <4 x i8> %b) { ; AVX12-NEXT: vpsrad $24, %xmm0, %xmm0 ; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i8: @@ -566,7 +566,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16> %b) { ; SSE2-SSSE3-NEXT: psrad $16, %xmm0 ; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4i16: @@ -577,7 +577,7 @@ define i4 @v4i16(<4 x i16> %a, <4 x i16> %b) { ; AVX12-NEXT: vpsrad $16, %xmm0, %xmm0 ; AVX12-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vmovmskps %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v4i16: @@ -618,7 +618,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) { ; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i8: @@ -630,7 +630,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) { ; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX12-NEXT: vpmovmskb %xmm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: retq ; ; AVX512F-LABEL: v8i8: @@ -644,7 +644,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -656,7 +656,7 @@ define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) { ; AVX512BW-NEXT: vpsraw $8, %xmm0, %xmm0 ; AVX512BW-NEXT: vpcmpgtw %xmm1, %xmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: retq %x = icmp sgt <8 x i8> %a, %b %res = bitcast <8 x i1> %x to i8 diff --git a/test/CodeGen/X86/bitcast-setcc-256.ll b/test/CodeGen/X86/bitcast-setcc-256.ll index ee2dac1d466..4b2a0d116e3 100644 --- a/test/CodeGen/X86/bitcast-setcc-256.ll +++ b/test/CodeGen/X86/bitcast-setcc-256.ll @@ -13,7 +13,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE2-SSSE3-NEXT: pcmpgtw %xmm2, %xmm0 ; SSE2-SSSE3-NEXT: packsswb %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v16i16: @@ -24,7 +24,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX1-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -34,7 +34,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -45,7 +45,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -53,7 +53,7 @@ define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = icmp sgt <16 x i16> %a, %b @@ -69,7 +69,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) { ; SSE2-SSSE3-NEXT: packssdw %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v8i32: @@ -80,7 +80,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vmovmskps %ymm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -88,7 +88,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX2: # BB#0: ; AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vmovmskps %ymm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -96,7 +96,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -104,7 +104,7 @@ define i8 @v8i32(<8 x i32> %a, <8 x i32> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = icmp sgt <8 x i32> %a, %b @@ -120,14 +120,14 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b) { ; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm2 ; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v8f32: ; AVX12: # BB#0: ; AVX12-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 ; AVX12-NEXT: vmovmskps %ymm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; @@ -135,7 +135,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vcmpltps %ymm0, %ymm1, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -143,7 +143,7 @@ define i8 @v8f32(<8 x float> %a, <8 x float> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vcmpltps %ymm0, %ymm1, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = fcmp ogt <8 x float> %a, %b @@ -244,7 +244,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b) { ; SSE2-SSSE3-NEXT: por %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm1 ; SSE2-SSSE3-NEXT: movmskps %xmm1, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: v4i64: @@ -255,7 +255,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vmovmskpd %ymm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -263,7 +263,7 @@ define i4 @v4i64(<4 x i64> %a, <4 x i64> %b) { ; AVX2: # BB#0: ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vmovmskpd %ymm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -296,14 +296,14 @@ define i4 @v4f64(<4 x double> %a, <4 x double> %b) { ; SSE2-SSSE3-NEXT: cmpltpd %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: packssdw %xmm3, %xmm2 ; SSE2-SSSE3-NEXT: movmskps %xmm2, %eax -; SSE2-SSSE3-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-SSSE3-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: v4f64: ; AVX12: # BB#0: ; AVX12-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX12-NEXT: vmovmskpd %ymm0, %eax -; AVX12-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX12-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX12-NEXT: vzeroupper ; AVX12-NEXT: retq ; diff --git a/test/CodeGen/X86/bitcast-setcc-512.ll b/test/CodeGen/X86/bitcast-setcc-512.ll index 2b73c6e16bd..93b5ddefb9d 100644 --- a/test/CodeGen/X86/bitcast-setcc-512.ll +++ b/test/CodeGen/X86/bitcast-setcc-512.ll @@ -228,7 +228,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) { ; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packsswb %xmm2, %xmm0 ; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v16i32: @@ -245,7 +245,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) { ; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -258,7 +258,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) { ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -266,7 +266,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -274,7 +274,7 @@ define i16 @v16i32(<16 x i32> %a, <16 x i32> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = icmp sgt <16 x i32> %a, %b @@ -293,7 +293,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b) { ; SSE-NEXT: packssdw %xmm5, %xmm4 ; SSE-NEXT: packsswb %xmm6, %xmm4 ; SSE-NEXT: pmovmskb %xmm4, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v16f32: @@ -306,7 +306,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b) { ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -319,7 +319,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b) { ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -327,7 +327,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -335,7 +335,7 @@ define i16 @v16f32(<16 x float> %a, <16 x float> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = fcmp ogt <16 x float> %a, %b @@ -1047,7 +1047,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b) { ; SSE-NEXT: packssdw %xmm2, %xmm0 ; SSE-NEXT: packsswb %xmm0, %xmm0 ; SSE-NEXT: pmovmskb %xmm0, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v8i64: @@ -1064,7 +1064,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b) { ; AVX1-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vmovmskps %ymm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -1075,7 +1075,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b) { ; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX2-NEXT: vmovmskps %ymm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1083,7 +1083,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1091,7 +1091,7 @@ define i8 @v8i64(<8 x i64> %a, <8 x i64> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = icmp sgt <8 x i64> %a, %b @@ -1111,7 +1111,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { ; SSE-NEXT: packssdw %xmm6, %xmm4 ; SSE-NEXT: packsswb %xmm0, %xmm4 ; SSE-NEXT: pmovmskb %xmm4, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: v8f64: @@ -1124,7 +1124,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vmovmskps %ymm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -1135,7 +1135,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { ; AVX2-NEXT: vpackssdw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX2-NEXT: vmovmskps %ymm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1143,7 +1143,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vcmpltpd %zmm0, %zmm1, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1151,7 +1151,7 @@ define i8 @v8f64(<8 x double> %a, <8 x double> %b) { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vcmpltpd %zmm0, %zmm1, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax -; AVX512BW-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512BW-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %x = fcmp ogt <8 x double> %a, %b diff --git a/test/CodeGen/X86/bitreverse.ll b/test/CodeGen/X86/bitreverse.ll index 04176b097d0..8e10499eb26 100644 --- a/test/CodeGen/X86/bitreverse.ll +++ b/test/CodeGen/X86/bitreverse.ll @@ -46,8 +46,8 @@ define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind { ; X86-NEXT: andl $43690, %ecx # imm = 0xAAAA ; X86-NEXT: shrl %ecx ; X86-NEXT: leal (%ecx,%edx,2), %edx -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; X86-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; X86-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_bitreverse_v2i16: @@ -191,7 +191,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; ; X64-LABEL: test_bitreverse_i32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: bswapl %edi ; X64-NEXT: movl %edi, %eax ; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F @@ -242,7 +242,7 @@ define i24 @test_bitreverse_i24(i24 %a) nounwind { ; ; X64-LABEL: test_bitreverse_i24: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: bswapl %edi ; X64-NEXT: movl %edi, %eax ; X64-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F @@ -289,12 +289,12 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; X86-NEXT: andl $43690, %eax # imm = 0xAAAA ; X86-NEXT: shrl %eax ; X86-NEXT: leal (%eax,%ecx,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_bitreverse_i16: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: rolw $8, %di ; X64-NEXT: movl %edi, %eax ; X64-NEXT: andl $3855, %eax # imm = 0xF0F @@ -312,7 +312,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; X64-NEXT: andl $43690, %eax # imm = 0xAAAA ; X64-NEXT: shrl %eax ; X64-NEXT: leal (%rax,%rcx,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %b = call i16 @llvm.bitreverse.i16(i16 %a) ret i16 %b diff --git a/test/CodeGen/X86/bmi-schedule.ll b/test/CodeGen/X86/bmi-schedule.ll index 2ba1c454f75..d42548110ec 100644 --- a/test/CodeGen/X86/bmi-schedule.ll +++ b/test/CodeGen/X86/bmi-schedule.ll @@ -14,7 +14,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; GENERIC-NEXT: notl %edi # sched: [1:0.33] ; GENERIC-NEXT: andw (%rdx), %di # sched: [6:0.50] ; GENERIC-NEXT: addl %edi, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_andn_i16: @@ -23,7 +23,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; HASWELL-NEXT: notl %edi # sched: [1:0.25] ; HASWELL-NEXT: andw (%rdx), %di # sched: [1:0.50] ; HASWELL-NEXT: addl %edi, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_andn_i16: @@ -32,7 +32,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; BROADWELL-NEXT: notl %edi # sched: [1:0.25] ; BROADWELL-NEXT: andw (%rdx), %di # sched: [6:0.50] ; BROADWELL-NEXT: addl %edi, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_andn_i16: @@ -41,7 +41,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; SKYLAKE-NEXT: notl %edi # sched: [1:0.25] ; SKYLAKE-NEXT: andw (%rdx), %di # sched: [6:0.50] ; SKYLAKE-NEXT: addl %edi, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_andn_i16: @@ -50,7 +50,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; BTVER2-NEXT: notl %edi # sched: [1:0.50] ; BTVER2-NEXT: andw (%rdx), %di # sched: [4:1.00] ; BTVER2-NEXT: addl %edi, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_andn_i16: @@ -59,7 +59,7 @@ define i16 @test_andn_i16(i16 zeroext %a0, i16 zeroext %a1, i16 *%a2) { ; ZNVER1-NEXT: notl %edi # sched: [1:0.25] ; ZNVER1-NEXT: andw (%rdx), %di # sched: [5:0.50] ; ZNVER1-NEXT: addl %edi, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = load i16, i16 *%a2 %2 = xor i16 %a0, -1 @@ -581,7 +581,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; GENERIC-NEXT: tzcntw (%rsi), %cx ; GENERIC-NEXT: tzcntw %di, %ax ; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_cttz_i16: @@ -589,7 +589,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; HASWELL-NEXT: tzcntw (%rsi), %cx # sched: [3:1.00] ; HASWELL-NEXT: tzcntw %di, %ax # sched: [3:1.00] ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_cttz_i16: @@ -597,7 +597,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; BROADWELL-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00] ; BROADWELL-NEXT: tzcntw %di, %ax # sched: [3:1.00] ; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_cttz_i16: @@ -605,7 +605,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; SKYLAKE-NEXT: tzcntw (%rsi), %cx # sched: [8:1.00] ; SKYLAKE-NEXT: tzcntw %di, %ax # sched: [3:1.00] ; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_cttz_i16: @@ -613,7 +613,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; BTVER2-NEXT: tzcntw (%rsi), %cx ; BTVER2-NEXT: tzcntw %di, %ax ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_cttz_i16: @@ -621,7 +621,7 @@ define i16 @test_cttz_i16(i16 zeroext %a0, i16 *%a1) { ; ZNVER1-NEXT: tzcntw (%rsi), %cx # sched: [6:0.50] ; ZNVER1-NEXT: tzcntw %di, %ax # sched: [2:0.25] ; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = load i16, i16 *%a1 %2 = tail call i16 @llvm.cttz.i16( i16 %1, i1 false ) diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll index de9b0bbbdc6..b2f0309e562 100644 --- a/test/CodeGen/X86/bmi.ll +++ b/test/CodeGen/X86/bmi.ll @@ -13,7 +13,7 @@ define i8 @t1(i8 %x) { ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: orl $256, %eax # imm = 0x100 ; CHECK-NEXT: tzcntl %eax, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false ) ret i8 %tmp @@ -61,7 +61,7 @@ define i8 @t5(i8 %x) { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: tzcntl %eax, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true ) ret i8 %tmp @@ -516,7 +516,7 @@ define i32 @bzhi32d(i32 %a, i32 %b) { ; BMI1-NEXT: movl $32, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: movl $-1, %eax -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrl %cl, %eax ; BMI1-NEXT: andl %edi, %eax ; BMI1-NEXT: retq @@ -538,7 +538,7 @@ define i32 @bzhi32e(i32 %a, i32 %b) { ; BMI1-NEXT: movl $32, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: shll %cl, %edi -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrl %cl, %edi ; BMI1-NEXT: movl %edi, %eax ; BMI1-NEXT: retq @@ -566,7 +566,7 @@ define i64 @bzhi64b(i64 %x, i8 zeroext %index) { ; ; BMI2-LABEL: bzhi64b: ; BMI2: # BB#0: # %entry -; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; BMI2-NEXT: bzhiq %rsi, %rdi, %rax ; BMI2-NEXT: retq entry: @@ -583,7 +583,7 @@ define i64 @bzhi64c(i64 %a, i64 %b) { ; BMI1-NEXT: movl $64, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: movq $-1, %rax -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrq %cl, %rax ; BMI1-NEXT: andq %rdi, %rax ; BMI1-NEXT: retq @@ -605,14 +605,14 @@ define i64 @bzhi64d(i64 %a, i32 %b) { ; BMI1-NEXT: movl $64, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: movq $-1, %rax -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrq %cl, %rax ; BMI1-NEXT: andq %rdi, %rax ; BMI1-NEXT: retq ; ; BMI2-LABEL: bzhi64d: ; BMI2: # BB#0: # %entry -; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; BMI2-NEXT: bzhiq %rsi, %rdi, %rax ; BMI2-NEXT: retq entry: @@ -629,7 +629,7 @@ define i64 @bzhi64e(i64 %a, i64 %b) { ; BMI1-NEXT: movl $64, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: shlq %cl, %rdi -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrq %cl, %rdi ; BMI1-NEXT: movq %rdi, %rax ; BMI1-NEXT: retq @@ -651,14 +651,14 @@ define i64 @bzhi64f(i64 %a, i32 %b) { ; BMI1-NEXT: movl $64, %ecx ; BMI1-NEXT: subl %esi, %ecx ; BMI1-NEXT: shlq %cl, %rdi -; BMI1-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; BMI1-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; BMI1-NEXT: shrq %cl, %rdi ; BMI1-NEXT: movq %rdi, %rax ; BMI1-NEXT: retq ; ; BMI2-LABEL: bzhi64f: ; BMI2: # BB#0: # %entry -; BMI2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; BMI2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; BMI2-NEXT: bzhiq %rsi, %rdi, %rax ; BMI2-NEXT: retq entry: diff --git a/test/CodeGen/X86/bool-simplify.ll b/test/CodeGen/X86/bool-simplify.ll index 7f7f9791d90..951a83c5c54 100644 --- a/test/CodeGen/X86/bool-simplify.ll +++ b/test/CodeGen/X86/bool-simplify.ll @@ -55,7 +55,7 @@ define i16 @rnd16(i16 %arg) nounwind { ; CHECK-NEXT: rdrandw %cx ; CHECK-NEXT: cmovbw %di, %ax ; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind %2 = extractvalue { i16, i32 } %1, 0 @@ -107,7 +107,7 @@ define i16 @seed16(i16 %arg) nounwind { ; CHECK-NEXT: rdseedw %cx ; CHECK-NEXT: cmovbw %di, %ax ; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %1 = tail call { i16, i32 } @llvm.x86.rdseed.16() nounwind %2 = extractvalue { i16, i32 } %1, 0 diff --git a/test/CodeGen/X86/bool-vector.ll b/test/CodeGen/X86/bool-vector.ll index eb40744c54d..03f0debdf12 100644 --- a/test/CodeGen/X86/bool-vector.ll +++ b/test/CodeGen/X86/bool-vector.ll @@ -138,10 +138,10 @@ define i32 @PR15215_good(<4 x i32> %input) { ; ; X64-LABEL: PR15215_good: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; X64-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; X64-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: andl $1, %edi ; X64-NEXT: andl $1, %esi ; X64-NEXT: andl $1, %edx diff --git a/test/CodeGen/X86/broadcastm-lowering.ll b/test/CodeGen/X86/broadcastm-lowering.ll index fc7b192c2f8..e0e3adcaefb 100644 --- a/test/CodeGen/X86/broadcastm-lowering.ll +++ b/test/CodeGen/X86/broadcastm-lowering.ll @@ -106,8 +106,8 @@ entry: define <8 x i64> @test_mm512_epi64(<8 x i32> %a, <8 x i32> %b) { ; AVX512CD-LABEL: test_mm512_epi64: ; AVX512CD: # BB#0: # %entry -; AVX512CD-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; AVX512CD-NEXT: vpbroadcastmb2q %k0, %zmm0 ; AVX512CD-NEXT: retq @@ -140,8 +140,8 @@ entry: define <4 x i64> @test_mm256_epi64(<8 x i32> %a, <8 x i32> %b) { ; AVX512CD-LABEL: test_mm256_epi64: ; AVX512CD: # BB#0: # %entry -; AVX512CD-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 ; AVX512CD-NEXT: kmovw %k0, %eax ; AVX512CD-NEXT: vpxor %xmm0, %xmm0, %xmm0 diff --git a/test/CodeGen/X86/bypass-slow-division-32.ll b/test/CodeGen/X86/bypass-slow-division-32.ll index 9f266647d8a..32a1a5f7413 100644 --- a/test/CodeGen/X86/bypass-slow-division-32.ll +++ b/test/CodeGen/X86/bypass-slow-division-32.ll @@ -17,7 +17,7 @@ define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: retl ; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: retl @@ -41,7 +41,7 @@ define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: retl ; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %ah, %eax # NOREX ; CHECK-NEXT: retl @@ -65,7 +65,7 @@ define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: retl ; CHECK-NEXT: .LBB2_1: ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %ah, %edx # NOREX ; CHECK-NEXT: movzbl %al, %eax @@ -103,14 +103,14 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: jmp .LBB3_6 ; CHECK-NEXT: .LBB3_1: ; CHECK-NEXT: movzbl %cl, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %bl ; CHECK-NEXT: movzbl %al, %esi ; CHECK-NEXT: testl $-256, %edi ; CHECK-NEXT: jne .LBB3_5 ; CHECK-NEXT: .LBB3_4: ; CHECK-NEXT: movzbl %cl, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %bl ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: .LBB3_6: @@ -208,7 +208,7 @@ define i32 @Test_use_div_imm_reg(i32 %a) nounwind { ; CHECK-NEXT: .LBB8_1: ; CHECK-NEXT: movb $4, %al ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: retl @@ -230,7 +230,7 @@ define i32 @Test_use_rem_imm_reg(i32 %a) nounwind { ; CHECK-NEXT: .LBB9_1: ; CHECK-NEXT: movb $4, %al ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: retl diff --git a/test/CodeGen/X86/bypass-slow-division-64.ll b/test/CodeGen/X86/bypass-slow-division-64.ll index b067f9e1503..d85e7d70fcc 100644 --- a/test/CodeGen/X86/bypass-slow-division-64.ll +++ b/test/CodeGen/X86/bypass-slow-division-64.ll @@ -20,7 +20,7 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: divl %esi -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<def> ; CHECK-NEXT: retq %result = sdiv i64 %a, %b ret i64 %result @@ -43,7 +43,7 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: divl %esi -; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> +; CHECK-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: retq %result = srem i64 %a, %b @@ -67,8 +67,8 @@ define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: divl %esi -; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def> +; CHECK-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<def> ; CHECK-NEXT: addq %rdx, %rax ; CHECK-NEXT: retq %resultdiv = sdiv i64 %a, %b diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index 9d827fc88b3..4e479365fb8 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -19,28 +19,28 @@ define i8 @cttz_i8(i8 %x) { ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: bsfl %eax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: cttz_i8: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsfl %eax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: cttz_i8: ; X32-CLZ: # BB#0: ; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-CLZ-NEXT: tzcntl %eax, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: cttz_i8: ; X64-CLZ: # BB#0: ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: tzcntl %eax, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true ) ret i8 %tmp @@ -144,7 +144,7 @@ define i8 @ctlz_i8(i8 %x) { ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: bsrl %eax, %eax ; X32-NEXT: xorl $7, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: ctlz_i8: @@ -152,7 +152,7 @@ define i8 @ctlz_i8(i8 %x) { ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsrl %eax, %eax ; X64-NEXT: xorl $7, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: ctlz_i8: @@ -160,7 +160,7 @@ define i8 @ctlz_i8(i8 %x) { ; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-CLZ-NEXT: lzcntl %eax, %eax ; X32-CLZ-NEXT: addl $-24, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: ctlz_i8: @@ -168,7 +168,7 @@ define i8 @ctlz_i8(i8 %x) { ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: lzcntl %eax, %eax ; X64-CLZ-NEXT: addl $-24, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true ) ret i8 %tmp2 @@ -179,14 +179,14 @@ define i16 @ctlz_i16(i16 %x) { ; X32: # BB#0: ; X32-NEXT: bsrw {{[0-9]+}}(%esp), %ax ; X32-NEXT: xorl $15, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: ctlz_i16: ; X64: # BB#0: ; X64-NEXT: bsrw %di, %ax ; X64-NEXT: xorl $15, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: ctlz_i16: @@ -286,11 +286,11 @@ define i8 @ctlz_i8_zero_test(i8 %n) { ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: bsrl %eax, %eax ; X32-NEXT: xorl $7, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: .LBB8_1: ; X32-NEXT: movb $8, %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: ctlz_i8_zero_test: @@ -301,11 +301,11 @@ define i8 @ctlz_i8_zero_test(i8 %n) { ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsrl %eax, %eax ; X64-NEXT: xorl $7, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: .LBB8_1: ; X64-NEXT: movb $8, %al -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: ctlz_i8_zero_test: @@ -313,7 +313,7 @@ define i8 @ctlz_i8_zero_test(i8 %n) { ; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-CLZ-NEXT: lzcntl %eax, %eax ; X32-CLZ-NEXT: addl $-24, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: ctlz_i8_zero_test: @@ -321,7 +321,7 @@ define i8 @ctlz_i8_zero_test(i8 %n) { ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: lzcntl %eax, %eax ; X64-CLZ-NEXT: addl $-24, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %tmp1 = call i8 @llvm.ctlz.i8(i8 %n, i1 false) ret i8 %tmp1 @@ -337,11 +337,11 @@ define i16 @ctlz_i16_zero_test(i16 %n) { ; X32-NEXT: # BB#2: # %cond.false ; X32-NEXT: bsrw %ax, %ax ; X32-NEXT: xorl $15, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: .LBB9_1: ; X32-NEXT: movw $16, %ax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: ctlz_i16_zero_test: @@ -351,11 +351,11 @@ define i16 @ctlz_i16_zero_test(i16 %n) { ; X64-NEXT: # BB#2: # %cond.false ; X64-NEXT: bsrw %di, %ax ; X64-NEXT: xorl $15, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: .LBB9_1: ; X64-NEXT: movw $16, %ax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: ctlz_i16_zero_test: @@ -480,11 +480,11 @@ define i8 @cttz_i8_zero_test(i8 %n) { ; X32-NEXT: # BB#2: # %cond.false ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: bsfl %eax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: .LBB12_1 ; X32-NEXT: movb $8, %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: cttz_i8_zero_test: @@ -494,11 +494,11 @@ define i8 @cttz_i8_zero_test(i8 %n) { ; X64-NEXT: # BB#2: # %cond.false ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsfl %eax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: .LBB12_1: ; X64-NEXT: movb $8, %al -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: cttz_i8_zero_test: @@ -506,7 +506,7 @@ define i8 @cttz_i8_zero_test(i8 %n) { ; X32-CLZ-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-CLZ-NEXT: orl $256, %eax # imm = 0x100 ; X32-CLZ-NEXT: tzcntl %eax, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: cttz_i8_zero_test: @@ -514,7 +514,7 @@ define i8 @cttz_i8_zero_test(i8 %n) { ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: orl $256, %eax # imm = 0x100 ; X64-CLZ-NEXT: tzcntl %eax, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %tmp1 = call i8 @llvm.cttz.i8(i8 %n, i1 false) ret i8 %tmp1 @@ -786,7 +786,7 @@ define i8 @cttz_i8_knownbits(i8 %x) { ; X32-NEXT: orb $2, %al ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: bsfl %eax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: cttz_i8_knownbits: @@ -794,7 +794,7 @@ define i8 @cttz_i8_knownbits(i8 %x) { ; X64-NEXT: orb $2, %dil ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsfl %eax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: cttz_i8_knownbits: @@ -803,7 +803,7 @@ define i8 @cttz_i8_knownbits(i8 %x) { ; X32-CLZ-NEXT: orb $2, %al ; X32-CLZ-NEXT: movzbl %al, %eax ; X32-CLZ-NEXT: tzcntl %eax, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: cttz_i8_knownbits: @@ -811,7 +811,7 @@ define i8 @cttz_i8_knownbits(i8 %x) { ; X64-CLZ-NEXT: orb $2, %dil ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: tzcntl %eax, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %x2 = or i8 %x, 2 %tmp = call i8 @llvm.cttz.i8(i8 %x2, i1 true ) @@ -827,7 +827,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) { ; X32-NEXT: movzbl %al, %eax ; X32-NEXT: bsrl %eax, %eax ; X32-NEXT: xorl $7, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: ctlz_i8_knownbits: @@ -836,7 +836,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) { ; X64-NEXT: movzbl %dil, %eax ; X64-NEXT: bsrl %eax, %eax ; X64-NEXT: xorl $7, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-CLZ-LABEL: ctlz_i8_knownbits: @@ -846,7 +846,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) { ; X32-CLZ-NEXT: movzbl %al, %eax ; X32-CLZ-NEXT: lzcntl %eax, %eax ; X32-CLZ-NEXT: addl $-24, %eax -; X32-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-CLZ-NEXT: retl ; ; X64-CLZ-LABEL: ctlz_i8_knownbits: @@ -855,7 +855,7 @@ define i8 @ctlz_i8_knownbits(i8 %x) { ; X64-CLZ-NEXT: movzbl %dil, %eax ; X64-CLZ-NEXT: lzcntl %eax, %eax ; X64-CLZ-NEXT: addl $-24, %eax -; X64-CLZ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-CLZ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-CLZ-NEXT: retq %x2 = or i8 %x, 64 diff --git a/test/CodeGen/X86/cmov-into-branch.ll b/test/CodeGen/X86/cmov-into-branch.ll index 0a2246700e6..4a29bb4e1db 100644 --- a/test/CodeGen/X86/cmov-into-branch.ll +++ b/test/CodeGen/X86/cmov-into-branch.ll @@ -65,7 +65,7 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) { define void @test6(i32 %a, i32 %x, i32* %y.ptr, i64* %z.ptr) { ; CHECK-LABEL: test6: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: cmovnsl (%rdx), %esi ; CHECK-NEXT: movq %rsi, (%rcx) diff --git a/test/CodeGen/X86/cmov-promotion.ll b/test/CodeGen/X86/cmov-promotion.ll index bb88f370c0c..7d8c0f492f6 100644 --- a/test/CodeGen/X86/cmov-promotion.ll +++ b/test/CodeGen/X86/cmov-promotion.ll @@ -12,7 +12,7 @@ define i16 @cmov_zpromotion_8_to_16(i1 %c) { ; CMOV-NEXT: movb $-19, %al ; CMOV-NEXT: .LBB0_2: ; CMOV-NEXT: movzbl %al, %eax -; CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CMOV-NEXT: retq ; ; NO_CMOV-LABEL: cmov_zpromotion_8_to_16: @@ -24,7 +24,7 @@ define i16 @cmov_zpromotion_8_to_16(i1 %c) { ; NO_CMOV-NEXT: movb $-19, %al ; NO_CMOV-NEXT: .LBB0_2: ; NO_CMOV-NEXT: movzbl %al, %eax -; NO_CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NO_CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NO_CMOV-NEXT: retl %t0 = select i1 %c, i8 117, i8 -19 %ret = zext i8 %t0 to i16 @@ -167,7 +167,7 @@ define i16 @cmov_spromotion_8_to_16(i1 %c) { ; CMOV-NEXT: movb $-19, %al ; CMOV-NEXT: .LBB6_2: ; CMOV-NEXT: movsbl %al, %eax -; CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CMOV-NEXT: retq ; ; NO_CMOV-LABEL: cmov_spromotion_8_to_16: @@ -179,7 +179,7 @@ define i16 @cmov_spromotion_8_to_16(i1 %c) { ; NO_CMOV-NEXT: movb $-19, %al ; NO_CMOV-NEXT: .LBB6_2: ; NO_CMOV-NEXT: movsbl %al, %eax -; NO_CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; NO_CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; NO_CMOV-NEXT: retl %t0 = select i1 %c, i8 117, i8 -19 %ret = sext i8 %t0 to i16 diff --git a/test/CodeGen/X86/cmov.ll b/test/CodeGen/X86/cmov.ll index f7fecd25aa7..1bb5964b48a 100644 --- a/test/CodeGen/X86/cmov.ll +++ b/test/CodeGen/X86/cmov.ll @@ -83,7 +83,7 @@ define i1 @test4() nounwind { ; CHECK-NEXT: shrb $7, %al ; CHECK-NEXT: movzbl %al, %ecx ; CHECK-NEXT: xorl $1, %ecx -; CHECK-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; CHECK-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; CHECK-NEXT: sarl %cl, %edx ; CHECK-NEXT: movb {{.*}}(%rip), %al ; CHECK-NEXT: testb %al, %al diff --git a/test/CodeGen/X86/coalescer-dce.ll b/test/CodeGen/X86/coalescer-dce.ll index 208d70660fa..8d039ac6f7b 100644 --- a/test/CodeGen/X86/coalescer-dce.ll +++ b/test/CodeGen/X86/coalescer-dce.ll @@ -16,7 +16,7 @@ target triple = "x86_64-apple-macosx10.7.0" ; Considering merging %vreg7 with %vreg10 ; RHS = %vreg7 = [208d,272d:0)[304L,480L:0) 0@208d ; LHS = %vreg10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4) 0@352d 1@64L-phidef 2@16d-phikill 3@272d-phikill 4@400d -; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %EFLAGS<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10 +; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %eflags<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10 ; Shrink: %vreg7 = [208d,272d:0)[304L,480L:0) 0@208d ; live-in at 240L ; live-in at 416L diff --git a/test/CodeGen/X86/combine-abs.ll b/test/CodeGen/X86/combine-abs.ll index a53a13ac00a..2f1804021fd 100644 --- a/test/CodeGen/X86/combine-abs.ll +++ b/test/CodeGen/X86/combine-abs.ll @@ -77,9 +77,9 @@ define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) { ; ; AVX512F-LABEL: combine_v4i64_abs_abs: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpabsq %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: combine_v4i64_abs_abs: diff --git a/test/CodeGen/X86/compress_expand.ll b/test/CodeGen/X86/compress_expand.ll index 9237544ea95..7456d68b8d9 100644 --- a/test/CodeGen/X86/compress_expand.ll +++ b/test/CodeGen/X86/compress_expand.ll @@ -72,11 +72,11 @@ define <4 x float> @test4(float* %base, <4 x float> %src0) { ; ; KNL-LABEL: test4: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: movw $7, %ax ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vexpandps (%rdi), %zmm0 {%k1} -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq %res = call <4 x float> @llvm.masked.expandload.v4f32(float* %base, <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> %src0) ret <4 x float>%res @@ -92,11 +92,11 @@ define <2 x i64> @test5(i64* %base, <2 x i64> %src0) { ; ; KNL-LABEL: test5: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: movb $2, %al ; KNL-NEXT: kmovw %eax, %k1 ; KNL-NEXT: vpexpandq (%rdi), %zmm0 {%k1} -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq %res = call <2 x i64> @llvm.masked.expandload.v2i64(i64* %base, <2 x i1> <i1 false, i1 true>, <2 x i64> %src0) ret <2 x i64>%res @@ -137,7 +137,7 @@ define void @test7(float* %base, <8 x float> %V, <8 x i1> %mask) { ; ; KNL-LABEL: test7: ; KNL: # BB#0: -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpmovsxwq %xmm1, %zmm1 ; KNL-NEXT: vpsllq $63, %zmm1, %zmm1 ; KNL-NEXT: vptestmq %zmm1, %zmm1, %k1 @@ -198,7 +198,7 @@ define void @test10(i64* %base, <4 x i64> %V, <4 x i1> %mask) { ; ; KNL-LABEL: test10: ; KNL: # BB#0: -; KNL-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -221,7 +221,7 @@ define void @test11(i64* %base, <2 x i64> %V, <2 x i1> %mask) { ; ; KNL-LABEL: test11: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: vpsllq $63, %xmm1, %xmm1 ; KNL-NEXT: vpsraq $63, %zmm1, %zmm1 ; KNL-NEXT: vmovdqa %xmm1, %xmm1 @@ -243,7 +243,7 @@ define void @test12(float* %base, <4 x float> %V, <4 x i1> %mask) { ; ; KNL-LABEL: test12: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL-NEXT: vmovdqa %xmm1, %xmm1 @@ -266,7 +266,7 @@ define <2 x float> @test13(float* %base, <2 x float> %src0, <2 x i32> %trigger) ; ; KNL-LABEL: test13: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] ; KNL-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1 @@ -275,7 +275,7 @@ define <2 x float> @test13(float* %base, <2 x float> %src0, <2 x i32> %trigger) ; KNL-NEXT: vpslld $31, %zmm1, %zmm1 ; KNL-NEXT: vptestmd %zmm1, %zmm1, %k1 ; KNL-NEXT: vexpandps (%rdi), %zmm0 {%k1} -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; KNL-NEXT: retq %mask = icmp eq <2 x i32> %trigger, zeroinitializer %res = call <2 x float> @llvm.masked.expandload.v2f32(float* %base, <2 x i1> %mask, <2 x float> %src0) @@ -293,7 +293,7 @@ define void @test14(float* %base, <2 x float> %V, <2 x i32> %trigger) { ; ; KNL-LABEL: test14: ; KNL: # BB#0: -; KNL-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] ; KNL-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1 diff --git a/test/CodeGen/X86/critical-edge-split-2.ll b/test/CodeGen/X86/critical-edge-split-2.ll index 9dd13cabac5..f503d5fc790 100644 --- a/test/CodeGen/X86/critical-edge-split-2.ll +++ b/test/CodeGen/X86/critical-edge-split-2.ll @@ -25,7 +25,7 @@ define i16 @test1(i1 zeroext %C, i8** nocapture %argv) nounwind ssp { ; CHECK-NEXT: divl %esi ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: .LBB0_2: # %cond.end.i -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq entry: br i1 %C, label %cond.end.i, label %cond.false.i diff --git a/test/CodeGen/X86/ctpop-combine.ll b/test/CodeGen/X86/ctpop-combine.ll index bbfc2ead04c..87e43a1e109 100644 --- a/test/CodeGen/X86/ctpop-combine.ll +++ b/test/CodeGen/X86/ctpop-combine.ll @@ -55,7 +55,7 @@ define i8 @test4(i8 %x) nounwind readnone { ; CHECK: # BB#0: ; CHECK-NEXT: andl $127, %edi ; CHECK-NEXT: popcntw %di, %ax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %AX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %ax<kill> ; CHECK-NEXT: retq %x2 = and i8 %x, 127 %count = tail call i8 @llvm.ctpop.i8(i8 %x2) diff --git a/test/CodeGen/X86/dagcombine-cse.ll b/test/CodeGen/X86/dagcombine-cse.ll index 726e30fce63..c617a8c6cae 100644 --- a/test/CodeGen/X86/dagcombine-cse.ll +++ b/test/CodeGen/X86/dagcombine-cse.ll @@ -19,8 +19,8 @@ define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) n ; ; X64-LABEL: t: ; X64: ## BB#0: ## %entry -; X64-NEXT: ## kill: %EDX<def> %EDX<kill> %RDX<def> -; X64-NEXT: ## kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: ## kill: %edx<def> %edx<kill> %rdx<def> +; X64-NEXT: ## kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: imull %ecx, %esi ; X64-NEXT: leal (%rsi,%rdx), %eax ; X64-NEXT: cltq diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index 16930488b9d..cb95da1b87e 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -8,14 +8,14 @@ define zeroext i16 @test1(i16 zeroext %x) nounwind { ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: imull $63551, %eax, %eax # imm = 0xF83F ; X32-NEXT: shrl $21, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test1: ; X64: # BB#0: # %entry ; X64-NEXT: imull $63551, %edi, %eax # imm = 0xF83F ; X64-NEXT: shrl $21, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq entry: %div = udiv i16 %x, 33 @@ -28,14 +28,14 @@ define zeroext i16 @test2(i8 signext %x, i16 zeroext %c) nounwind readnone ssp n ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: imull $43691, %eax, %eax # imm = 0xAAAB ; X32-NEXT: shrl $17, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test2: ; X64: # BB#0: # %entry ; X64-NEXT: imull $43691, %esi, %eax # imm = 0xAAAB ; X64-NEXT: shrl $17, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq entry: %div = udiv i16 %c, 3 @@ -50,7 +50,7 @@ define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp nor ; X32-NEXT: imull $171, %eax, %eax ; X32-NEXT: shrl $9, %eax ; X32-NEXT: movzwl %ax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test3: @@ -58,7 +58,7 @@ define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) nounwind readnone ssp nor ; X64-NEXT: imull $171, %esi, %eax ; X64-NEXT: shrl $9, %eax ; X64-NEXT: movzwl %ax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq entry: %div = udiv i8 %c, 3 @@ -74,7 +74,7 @@ define signext i16 @test4(i16 signext %x) nounwind { ; X32-NEXT: shrl $31, %ecx ; X32-NEXT: shrl $16, %eax ; X32-NEXT: addl %ecx, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test4: @@ -84,7 +84,7 @@ define signext i16 @test4(i16 signext %x) nounwind { ; X64-NEXT: shrl $31, %ecx ; X64-NEXT: shrl $16, %eax ; X64-NEXT: addl %ecx, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq entry: %div = sdiv i16 %x, 33 ; <i32> [#uses=1] @@ -105,7 +105,7 @@ define i32 @test5(i32 %A) nounwind { ; X64-NEXT: movl %edi, %eax ; X64-NEXT: imulq $365384439, %rax, %rax # imm = 0x15C752F7 ; X64-NEXT: shrq $59, %rax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-NEXT: retq %tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1] ret i32 %tmp1 @@ -120,7 +120,7 @@ define signext i16 @test6(i16 signext %x) nounwind { ; X32-NEXT: shrl $31, %ecx ; X32-NEXT: sarl $18, %eax ; X32-NEXT: addl %ecx, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test6: @@ -130,7 +130,7 @@ define signext i16 @test6(i16 signext %x) nounwind { ; X64-NEXT: shrl $31, %ecx ; X64-NEXT: sarl $18, %eax ; X64-NEXT: addl %ecx, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq entry: %div = sdiv i16 %x, 10 @@ -149,11 +149,11 @@ define i32 @test7(i32 %x) nounwind { ; ; X64-LABEL: test7: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shrl $2, %edi ; X64-NEXT: imulq $613566757, %rdi, %rax # imm = 0x24924925 ; X64-NEXT: shrq $32, %rax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-NEXT: retq %div = udiv i32 %x, 28 ret i32 %div @@ -169,7 +169,7 @@ define i8 @test8(i8 %x) nounwind { ; X32-NEXT: imull $211, %eax, %eax ; X32-NEXT: shrl $13, %eax ; X32-NEXT: movzwl %ax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test8: @@ -179,7 +179,7 @@ define i8 @test8(i8 %x) nounwind { ; X64-NEXT: imull $211, %eax, %eax ; X64-NEXT: shrl $13, %eax ; X64-NEXT: movzwl %ax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %div = udiv i8 %x, 78 ret i8 %div @@ -194,7 +194,7 @@ define i8 @test9(i8 %x) nounwind { ; X32-NEXT: imull $71, %eax, %eax ; X32-NEXT: shrl $11, %eax ; X32-NEXT: movzwl %ax, %eax -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test9: @@ -204,7 +204,7 @@ define i8 @test9(i8 %x) nounwind { ; X64-NEXT: imull $71, %eax, %eax ; X64-NEXT: shrl $11, %eax ; X64-NEXT: movzwl %ax, %eax -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %div = udiv i8 %x, 116 ret i8 %div diff --git a/test/CodeGen/X86/divrem.ll b/test/CodeGen/X86/divrem.ll index 73d16060be7..cbd6f7adae7 100644 --- a/test/CodeGen/X86/divrem.ll +++ b/test/CodeGen/X86/divrem.ll @@ -262,7 +262,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i8* %q) nounwind { ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %ah, %ebx # NOREX ; X32-NEXT: movb %al, (%edx) @@ -273,7 +273,7 @@ define void @ui8(i8 %x, i8 %y, i8* %p, i8* %q) nounwind { ; X64-LABEL: ui8: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %esi # NOREX ; X64-NEXT: movb %al, (%rdx) diff --git a/test/CodeGen/X86/divrem8_ext.ll b/test/CodeGen/X86/divrem8_ext.ll index c49be4b2d04..70a5ca83da2 100644 --- a/test/CodeGen/X86/divrem8_ext.ll +++ b/test/CodeGen/X86/divrem8_ext.ll @@ -6,7 +6,7 @@ define zeroext i8 @test_udivrem_zext_ah(i8 %x, i8 %y) { ; X32-LABEL: test_udivrem_zext_ah: ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %ah, %ecx # NOREX ; X32-NEXT: movb %al, z @@ -16,7 +16,7 @@ define zeroext i8 @test_udivrem_zext_ah(i8 %x, i8 %y) { ; X64-LABEL: test_udivrem_zext_ah: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %ecx # NOREX ; X64-NEXT: movb %al, {{.*}}(%rip) @@ -32,19 +32,19 @@ define zeroext i8 @test_urem_zext_ah(i8 %x, i8 %y) { ; X32-LABEL: test_urem_zext_ah: ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %ah, %eax # NOREX -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test_urem_zext_ah: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %eax # NOREX -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %1 = urem i8 %x, %y ret i8 %1 @@ -55,21 +55,21 @@ define i8 @test_urem_noext_ah(i8 %x, i8 %y) { ; X32: # BB#0: ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb %cl ; X32-NEXT: movzbl %ah, %eax # NOREX ; X32-NEXT: addb %cl, %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test_urem_noext_ah: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %eax # NOREX ; X64-NEXT: addb %sil, %al -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %1 = urem i8 %x, %y %2 = add i8 %1, %y @@ -80,7 +80,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i8 %y) { ; X32-LABEL: test_urem_zext64_ah: ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %ah, %eax # NOREX ; X32-NEXT: xorl %edx, %edx @@ -89,7 +89,7 @@ define i64 @test_urem_zext64_ah(i8 %x, i8 %y) { ; X64-LABEL: test_urem_zext64_ah: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %eax # NOREX ; X64-NEXT: retq @@ -131,7 +131,7 @@ define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) { ; X32-NEXT: cbtw ; X32-NEXT: idivb {{[0-9]+}}(%esp) ; X32-NEXT: movsbl %ah, %eax # NOREX -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test_srem_sext_ah: @@ -140,7 +140,7 @@ define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) { ; X64-NEXT: cbtw ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %eax # NOREX -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %1 = srem i8 %x, %y ret i8 %1 @@ -155,7 +155,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8 %y) { ; X32-NEXT: idivb %cl ; X32-NEXT: movsbl %ah, %eax # NOREX ; X32-NEXT: addb %cl, %al -; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X32-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test_srem_noext_ah: @@ -165,7 +165,7 @@ define i8 @test_srem_noext_ah(i8 %x, i8 %y) { ; X64-NEXT: idivb %sil ; X64-NEXT: movsbl %ah, %eax # NOREX ; X64-NEXT: addb %sil, %al -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %1 = srem i8 %x, %y %2 = add i8 %1, %y @@ -200,7 +200,7 @@ define i64 @pr25754(i8 %a, i8 %c) { ; X32-LABEL: pr25754: ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X32-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X32-NEXT: divb {{[0-9]+}}(%esp) ; X32-NEXT: movzbl %ah, %ecx # NOREX ; X32-NEXT: movzbl %al, %eax @@ -211,7 +211,7 @@ define i64 @pr25754(i8 %a, i8 %c) { ; X64-LABEL: pr25754: ; X64: # BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %ecx # NOREX ; X64-NEXT: movzbl %al, %eax diff --git a/test/CodeGen/X86/eflags-copy-expansion.mir b/test/CodeGen/X86/eflags-copy-expansion.mir index 28f47c3c249..11d4c81b925 100644 --- a/test/CodeGen/X86/eflags-copy-expansion.mir +++ b/test/CodeGen/X86/eflags-copy-expansion.mir @@ -48,7 +48,7 @@ body: | ; Save AL. ; CHECK: PUSH32r killed %eax - ; Copy EDI into EFLAGS + ; Copy edi into EFLAGS ; CHECK-NEXT: %eax = MOV32rr %edi ; CHECK-NEXT: %al = ADD8ri %al, 127, implicit-def %eflags ; CHECK-NEXT: SAHF implicit-def %eflags, implicit %ah diff --git a/test/CodeGen/X86/extractelement-index.ll b/test/CodeGen/X86/extractelement-index.ll index 8a6cdaf203c..14762f38c42 100644 --- a/test/CodeGen/X86/extractelement-index.ll +++ b/test/CodeGen/X86/extractelement-index.ll @@ -13,19 +13,19 @@ define i8 @extractelement_v16i8_1(<16 x i8> %a) nounwind { ; SSE2: # BB#0: ; SSE2-NEXT: movd %xmm0, %eax ; SSE2-NEXT: shrl $8, %eax -; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-NEXT: retq ; ; SSE41-LABEL: extractelement_v16i8_1: ; SSE41: # BB#0: ; SSE41-NEXT: pextrb $1, %xmm0, %eax -; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE41-NEXT: retq ; ; AVX-LABEL: extractelement_v16i8_1: ; AVX: # BB#0: ; AVX-NEXT: vpextrb $1, %xmm0, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: retq %b = extractelement <16 x i8> %a, i256 1 ret i8 %b @@ -36,19 +36,19 @@ define i8 @extractelement_v16i8_11(<16 x i8> %a) nounwind { ; SSE2: # BB#0: ; SSE2-NEXT: pextrw $5, %xmm0, %eax ; SSE2-NEXT: shrl $8, %eax -; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-NEXT: retq ; ; SSE41-LABEL: extractelement_v16i8_11: ; SSE41: # BB#0: ; SSE41-NEXT: pextrb $11, %xmm0, %eax -; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE41-NEXT: retq ; ; AVX-LABEL: extractelement_v16i8_11: ; AVX: # BB#0: ; AVX-NEXT: vpextrb $11, %xmm0, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: retq %b = extractelement <16 x i8> %a, i256 11 ret i8 %b @@ -58,19 +58,19 @@ define i8 @extractelement_v16i8_14(<16 x i8> %a) nounwind { ; SSE2-LABEL: extractelement_v16i8_14: ; SSE2: # BB#0: ; SSE2-NEXT: pextrw $7, %xmm0, %eax -; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-NEXT: retq ; ; SSE41-LABEL: extractelement_v16i8_14: ; SSE41: # BB#0: ; SSE41-NEXT: pextrb $14, %xmm0, %eax -; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE41-NEXT: retq ; ; AVX-LABEL: extractelement_v16i8_14: ; AVX: # BB#0: ; AVX-NEXT: vpextrb $14, %xmm0, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: retq %b = extractelement <16 x i8> %a, i256 14 ret i8 %b @@ -81,19 +81,19 @@ define i8 @extractelement_v32i8_1(<32 x i8> %a) nounwind { ; SSE2: # BB#0: ; SSE2-NEXT: movd %xmm0, %eax ; SSE2-NEXT: shrl $8, %eax -; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-NEXT: retq ; ; SSE41-LABEL: extractelement_v32i8_1: ; SSE41: # BB#0: ; SSE41-NEXT: pextrb $1, %xmm0, %eax -; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE41-NEXT: retq ; ; AVX-LABEL: extractelement_v32i8_1: ; AVX: # BB#0: ; AVX-NEXT: vpextrb $1, %xmm0, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %b = extractelement <32 x i8> %a, i256 1 @@ -105,20 +105,20 @@ define i8 @extractelement_v32i8_17(<32 x i8> %a) nounwind { ; SSE2: # BB#0: ; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: shrl $8, %eax -; SSE2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE2-NEXT: retq ; ; SSE41-LABEL: extractelement_v32i8_17: ; SSE41: # BB#0: ; SSE41-NEXT: pextrb $1, %xmm1, %eax -; SSE41-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE41-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE41-NEXT: retq ; ; AVX1-LABEL: extractelement_v32i8_17: ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpextrb $1, %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -126,7 +126,7 @@ define i8 @extractelement_v32i8_17(<32 x i8> %a) nounwind { ; AVX2: # BB#0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vpextrb $1, %xmm0, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq %b = extractelement <32 x i8> %a, i256 17 @@ -137,13 +137,13 @@ define i16 @extractelement_v8i16_0(<8 x i16> %a, i256 %i) nounwind { ; SSE-LABEL: extractelement_v8i16_0: ; SSE: # BB#0: ; SSE-NEXT: movd %xmm0, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: extractelement_v8i16_0: ; AVX: # BB#0: ; AVX-NEXT: vmovd %xmm0, %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: retq %b = extractelement <8 x i16> %a, i256 0 ret i16 %b @@ -153,13 +153,13 @@ define i16 @extractelement_v8i16_3(<8 x i16> %a, i256 %i) nounwind { ; SSE-LABEL: extractelement_v8i16_3: ; SSE: # BB#0: ; SSE-NEXT: pextrw $3, %xmm0, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: extractelement_v8i16_3: ; AVX: # BB#0: ; AVX-NEXT: vpextrw $3, %xmm0, %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: retq %b = extractelement <8 x i16> %a, i256 3 ret i16 %b @@ -169,13 +169,13 @@ define i16 @extractelement_v16i16_0(<16 x i16> %a, i256 %i) nounwind { ; SSE-LABEL: extractelement_v16i16_0: ; SSE: # BB#0: ; SSE-NEXT: movd %xmm0, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: extractelement_v16i16_0: ; AVX: # BB#0: ; AVX-NEXT: vmovd %xmm0, %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %b = extractelement <16 x i16> %a, i256 0 @@ -186,14 +186,14 @@ define i16 @extractelement_v16i16_13(<16 x i16> %a, i256 %i) nounwind { ; SSE-LABEL: extractelement_v16i16_13: ; SSE: # BB#0: ; SSE-NEXT: pextrw $5, %xmm1, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: extractelement_v16i16_13: ; AVX1: # BB#0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpextrw $5, %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -201,7 +201,7 @@ define i16 @extractelement_v16i16_13(<16 x i16> %a, i256 %i) nounwind { ; AVX2: # BB#0: ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vpextrw $5, %xmm0, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq %b = extractelement <16 x i16> %a, i256 13 diff --git a/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll b/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll index f66c53e8ee6..a78b72cd424 100644 --- a/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/f16c-intrinsics-fast-isel.ll @@ -43,7 +43,7 @@ define i16 @test_cvtss_sh(float %a0) nounwind { ; X32-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; X32-NEXT: vcvtps2ph $0, %xmm0, %xmm0 ; X32-NEXT: vmovd %xmm0, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test_cvtss_sh: @@ -52,7 +52,7 @@ define i16 @test_cvtss_sh(float %a0) nounwind { ; X64-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; X64-NEXT: vcvtps2ph $0, %xmm0, %xmm0 ; X64-NEXT: vmovd %xmm0, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %ins0 = insertelement <4 x float> undef, float %a0, i32 0 %ins1 = insertelement <4 x float> %ins0, float 0.000000e+00, i32 1 diff --git a/test/CodeGen/X86/fast-isel-cmp.ll b/test/CodeGen/X86/fast-isel-cmp.ll index 0fae0c290ae..6ffb22e215e 100644 --- a/test/CodeGen/X86/fast-isel-cmp.ll +++ b/test/CodeGen/X86/fast-isel-cmp.ll @@ -10,7 +10,7 @@ define zeroext i1 @fcmp_oeq(float %x, float %y) { ; SDAG-NEXT: cmpeqss %xmm1, %xmm0 ; SDAG-NEXT: movd %xmm0, %eax ; SDAG-NEXT: andl $1, %eax -; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SDAG-NEXT: retq ; ; FAST_NOAVX-LABEL: fcmp_oeq: @@ -354,7 +354,7 @@ define zeroext i1 @fcmp_une(float %x, float %y) { ; SDAG-NEXT: cmpneqss %xmm1, %xmm0 ; SDAG-NEXT: movd %xmm0, %eax ; SDAG-NEXT: andl $1, %eax -; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SDAG-NEXT: retq ; ; FAST_NOAVX-LABEL: fcmp_une: @@ -594,7 +594,7 @@ define zeroext i1 @fcmp_oeq3(float %x) { ; SDAG-NEXT: cmpeqss %xmm0, %xmm1 ; SDAG-NEXT: movd %xmm1, %eax ; SDAG-NEXT: andl $1, %eax -; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SDAG-NEXT: retq ; ; FAST_NOAVX-LABEL: fcmp_oeq3: @@ -1249,7 +1249,7 @@ define zeroext i1 @fcmp_une3(float %x) { ; SDAG-NEXT: cmpneqss %xmm0, %xmm1 ; SDAG-NEXT: movd %xmm1, %eax ; SDAG-NEXT: andl $1, %eax -; SDAG-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; SDAG-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; SDAG-NEXT: retq ; ; FAST_NOAVX-LABEL: fcmp_une3: diff --git a/test/CodeGen/X86/fast-isel-nontemporal.ll b/test/CodeGen/X86/fast-isel-nontemporal.ll index 80117588f5d..b9fbc7a743d 100644 --- a/test/CodeGen/X86/fast-isel-nontemporal.ll +++ b/test/CodeGen/X86/fast-isel-nontemporal.ll @@ -547,7 +547,7 @@ define <8 x float> @test_load_nt8xfloat(<8 x float>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt8xfloat: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -589,7 +589,7 @@ define <4 x double> @test_load_nt4xdouble(<4 x double>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt4xdouble: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -631,7 +631,7 @@ define <32 x i8> @test_load_nt32xi8(<32 x i8>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt32xi8: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -673,7 +673,7 @@ define <16 x i16> @test_load_nt16xi16(<16 x i16>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt16xi16: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -715,7 +715,7 @@ define <8 x i32> @test_load_nt8xi32(<8 x i32>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt8xi32: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -757,7 +757,7 @@ define <4 x i64> @test_load_nt4xi64(<4 x i64>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt4xi64: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 @@ -997,12 +997,12 @@ define <16 x float> @test_load_nt16xfloat(<16 x float>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt16xfloat: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 @@ -1051,12 +1051,12 @@ define <8 x double> @test_load_nt8xdouble(<8 x double>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt8xdouble: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 @@ -1105,12 +1105,12 @@ define <64 x i8> @test_load_nt64xi8(<64 x i8>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt64xi8: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 @@ -1171,12 +1171,12 @@ define <32 x i16> @test_load_nt32xi16(<32 x i16>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt32xi16: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 @@ -1237,12 +1237,12 @@ define <16 x i32> @test_load_nt16xi32(<16 x i32>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt16xi32: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 @@ -1291,12 +1291,12 @@ define <8 x i64> @test_load_nt8xi64(<8 x i64>* nocapture %ptr) { ; AVX1-LABEL: test_load_nt8xi64: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vmovntdqa (%rdi), %xmm0 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm0, %xmm1 ; AVX1-NEXT: vmovntdqa 16(%rdi), %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vmovntdqa 32(%rdi), %xmm2 -; AVX1-NEXT: # implicit-def: %YMM1 +; AVX1-NEXT: # implicit-def: %ymm1 ; AVX1-NEXT: vmovaps %xmm2, %xmm1 ; AVX1-NEXT: vmovntdqa 48(%rdi), %xmm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 diff --git a/test/CodeGen/X86/fast-isel-sext-zext.ll b/test/CodeGen/X86/fast-isel-sext-zext.ll index 17aaea05d12..e467faea774 100644 --- a/test/CodeGen/X86/fast-isel-sext-zext.ll +++ b/test/CodeGen/X86/fast-isel-sext-zext.ll @@ -30,7 +30,7 @@ define i16 @test2(i16 %x) nounwind { ; X32-NEXT: andb $1, %al ; X32-NEXT: negb %al ; X32-NEXT: movsbl %al, %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: ## -- End function ; @@ -39,7 +39,7 @@ define i16 @test2(i16 %x) nounwind { ; X64-NEXT: andb $1, %dil ; X64-NEXT: negb %dil ; X64-NEXT: movsbl %dil, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: ## -- End function %z = trunc i16 %x to i1 @@ -116,7 +116,7 @@ define i16 @test6(i16 %x) nounwind { ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X32-NEXT: andb $1, %al ; X32-NEXT: movzbl %al, %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: ## -- End function ; @@ -124,7 +124,7 @@ define i16 @test6(i16 %x) nounwind { ; X64: ## BB#0: ; X64-NEXT: andb $1, %dil ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: ## -- End function %z = trunc i16 %x to i1 @@ -176,14 +176,14 @@ define i16 @test9(i8 %x) nounwind { ; X32-LABEL: test9: ; X32: ## BB#0: ; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: ## -- End function ; ; X64-LABEL: test9: ; X64: ## BB#0: ; X64-NEXT: movsbl %dil, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: ## -- End function %u = sext i8 %x to i16 @@ -228,14 +228,14 @@ define i16 @test12(i8 %x) nounwind { ; X32-LABEL: test12: ; X32: ## BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; X32-NEXT: ## -- End function ; ; X64-LABEL: test12: ; X64: ## BB#0: ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; X64-NEXT: ## -- End function %u = zext i8 %x to i16 diff --git a/test/CodeGen/X86/fast-isel-shift.ll b/test/CodeGen/X86/fast-isel-shift.ll index 7e5e31bd52c..2205976f3cb 100644 --- a/test/CodeGen/X86/fast-isel-shift.ll +++ b/test/CodeGen/X86/fast-isel-shift.ll @@ -16,7 +16,7 @@ define i16 @shl_i16(i16 %a, i16 %b) { ; CHECK-LABEL: shl_i16: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %CX<kill> +; CHECK-NEXT: ## kill: %cl<def> %cx<kill> ; CHECK-NEXT: shlw %cl, %di ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -28,7 +28,7 @@ define i32 @shl_i32(i32 %a, i32 %b) { ; CHECK-LABEL: shl_i32: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %ECX<kill> +; CHECK-NEXT: ## kill: %cl<def> %ecx<kill> ; CHECK-NEXT: shll %cl, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -40,7 +40,7 @@ define i64 @shl_i64(i64 %a, i64 %b) { ; CHECK-LABEL: shl_i64: ; CHECK: ## BB#0: ; CHECK-NEXT: movq %rsi, %rcx -; CHECK-NEXT: ## kill: %CL<def> %RCX<kill> +; CHECK-NEXT: ## kill: %cl<def> %rcx<kill> ; CHECK-NEXT: shlq %cl, %rdi ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq @@ -63,7 +63,7 @@ define i16 @lshr_i16(i16 %a, i16 %b) { ; CHECK-LABEL: lshr_i16: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %CX<kill> +; CHECK-NEXT: ## kill: %cl<def> %cx<kill> ; CHECK-NEXT: shrw %cl, %di ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -75,7 +75,7 @@ define i32 @lshr_i32(i32 %a, i32 %b) { ; CHECK-LABEL: lshr_i32: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %ECX<kill> +; CHECK-NEXT: ## kill: %cl<def> %ecx<kill> ; CHECK-NEXT: shrl %cl, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -87,7 +87,7 @@ define i64 @lshr_i64(i64 %a, i64 %b) { ; CHECK-LABEL: lshr_i64: ; CHECK: ## BB#0: ; CHECK-NEXT: movq %rsi, %rcx -; CHECK-NEXT: ## kill: %CL<def> %RCX<kill> +; CHECK-NEXT: ## kill: %cl<def> %rcx<kill> ; CHECK-NEXT: shrq %cl, %rdi ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq @@ -110,7 +110,7 @@ define i16 @ashr_i16(i16 %a, i16 %b) { ; CHECK-LABEL: ashr_i16: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %CX<kill> +; CHECK-NEXT: ## kill: %cl<def> %cx<kill> ; CHECK-NEXT: sarw %cl, %di ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -122,7 +122,7 @@ define i32 @ashr_i32(i32 %a, i32 %b) { ; CHECK-LABEL: ashr_i32: ; CHECK: ## BB#0: ; CHECK-NEXT: movl %esi, %ecx -; CHECK-NEXT: ## kill: %CL<def> %ECX<kill> +; CHECK-NEXT: ## kill: %cl<def> %ecx<kill> ; CHECK-NEXT: sarl %cl, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq @@ -134,7 +134,7 @@ define i64 @ashr_i64(i64 %a, i64 %b) { ; CHECK-LABEL: ashr_i64: ; CHECK: ## BB#0: ; CHECK-NEXT: movq %rsi, %rcx -; CHECK-NEXT: ## kill: %CL<def> %RCX<kill> +; CHECK-NEXT: ## kill: %cl<def> %rcx<kill> ; CHECK-NEXT: sarq %cl, %rdi ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq @@ -155,9 +155,9 @@ define i8 @shl_imm1_i8(i8 %a) { define i16 @shl_imm1_i16(i16 %a) { ; CHECK-LABEL: shl_imm1_i16: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal (,%rdi,2), %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %c = shl i16 %a, 1 ret i16 %c @@ -166,7 +166,7 @@ define i16 @shl_imm1_i16(i16 %a) { define i32 @shl_imm1_i32(i32 %a) { ; CHECK-LABEL: shl_imm1_i32: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal (,%rdi,2), %eax ; CHECK-NEXT: retq %c = shl i32 %a, 1 diff --git a/test/CodeGen/X86/fixup-bw-copy.ll b/test/CodeGen/X86/fixup-bw-copy.ll index 9067dfd29c1..d9d822ff475 100644 --- a/test/CodeGen/X86/fixup-bw-copy.ll +++ b/test/CodeGen/X86/fixup-bw-copy.ll @@ -54,7 +54,7 @@ define i8 @test_movb_hreg(i16 %a0) { ; X64-NEXT: movl %edi, %eax ; X64-NEXT: shrl $8, %eax ; X64-NEXT: addb %dil, %al -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-LABEL: test_movb_hreg: diff --git a/test/CodeGen/X86/fp_load_cast_fold.ll b/test/CodeGen/X86/fp_load_cast_fold.ll index 771196674b1..5ef9d479df5 100644 --- a/test/CodeGen/X86/fp_load_cast_fold.ll +++ b/test/CodeGen/X86/fp_load_cast_fold.ll @@ -20,7 +20,7 @@ define double @long(i64* %P) { ; CHECK: long ; CHECK: fild -; CHECK-NOT: ESP +; CHECK-NOT: esp ; CHECK-NOT: esp ; CHECK: {{$}} ; CHECK: ret diff --git a/test/CodeGen/X86/ghc-cc.ll b/test/CodeGen/X86/ghc-cc.ll index 16e4db60502..1a03c6ae706 100644 --- a/test/CodeGen/X86/ghc-cc.ll +++ b/test/CodeGen/X86/ghc-cc.ll @@ -2,10 +2,10 @@ ; Test the GHC call convention works (x86-32) -@base = external global i32 ; assigned to register: EBX -@sp = external global i32 ; assigned to register: EBP -@hp = external global i32 ; assigned to register: EDI -@r1 = external global i32 ; assigned to register: ESI +@base = external global i32 ; assigned to register: ebx +@sp = external global i32 ; assigned to register: ebp +@hp = external global i32 ; assigned to register: edi +@r1 = external global i32 ; assigned to register: esi define void @zap(i32 %a, i32 %b) nounwind { entry: diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll index c4ce8cfdef1..e8b0f06fe24 100644 --- a/test/CodeGen/X86/ghc-cc64.ll +++ b/test/CodeGen/X86/ghc-cc64.ll @@ -3,22 +3,22 @@ ; Check the GHC call convention works (x86-64) @base = external global i64 ; assigned to register: R13 -@sp = external global i64 ; assigned to register: RBP +@sp = external global i64 ; assigned to register: rbp @hp = external global i64 ; assigned to register: R12 -@r1 = external global i64 ; assigned to register: RBX +@r1 = external global i64 ; assigned to register: rbx @r2 = external global i64 ; assigned to register: R14 -@r3 = external global i64 ; assigned to register: RSI -@r4 = external global i64 ; assigned to register: RDI +@r3 = external global i64 ; assigned to register: rsi +@r4 = external global i64 ; assigned to register: rdi @r5 = external global i64 ; assigned to register: R8 @r6 = external global i64 ; assigned to register: R9 @splim = external global i64 ; assigned to register: R15 -@f1 = external global float ; assigned to register: XMM1 -@f2 = external global float ; assigned to register: XMM2 -@f3 = external global float ; assigned to register: XMM3 -@f4 = external global float ; assigned to register: XMM4 -@d1 = external global double ; assigned to register: XMM5 -@d2 = external global double ; assigned to register: XMM6 +@f1 = external global float ; assigned to register: xmm1 +@f2 = external global float ; assigned to register: xmm2 +@f3 = external global float ; assigned to register: xmm3 +@f4 = external global float ; assigned to register: xmm4 +@d1 = external global double ; assigned to register: xmm5 +@d2 = external global double ; assigned to register: xmm6 define void @zap(i64 %a, i64 %b) nounwind { entry: diff --git a/test/CodeGen/X86/gpr-to-mask.ll b/test/CodeGen/X86/gpr-to-mask.ll index 52a59ad310f..842faaae9b1 100644 --- a/test/CodeGen/X86/gpr-to-mask.ll +++ b/test/CodeGen/X86/gpr-to-mask.ll @@ -167,8 +167,8 @@ exit: define void @test_shl1(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) { ; CHECK-LABEL: test_shl1: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: je .LBB5_2 ; CHECK-NEXT: # BB#1: # %if @@ -205,8 +205,8 @@ exit: define void @test_shr1(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) { ; CHECK-LABEL: test_shr1: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: je .LBB6_2 ; CHECK-NEXT: # BB#1: # %if @@ -244,8 +244,8 @@ exit: define void @test_shr2(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) { ; CHECK-LABEL: test_shr2: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: je .LBB7_2 ; CHECK-NEXT: # BB#1: # %if @@ -282,8 +282,8 @@ exit: define void @test_shl(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) { ; CHECK-LABEL: test_shl: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: je .LBB8_2 ; CHECK-NEXT: # BB#1: # %if @@ -320,8 +320,8 @@ exit: define void @test_add(i1 %cond, i8* %ptr1, i8* %ptr2, <8 x float> %fvec1, <8 x float> %fvec2, <8 x float>* %fptrvec) { ; CHECK-LABEL: test_add: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; CHECK-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; CHECK-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; CHECK-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; CHECK-NEXT: kmovb (%rsi), %k0 ; CHECK-NEXT: kmovb (%rdx), %k1 ; CHECK-NEXT: testb $1, %dil diff --git a/test/CodeGen/X86/half.ll b/test/CodeGen/X86/half.ll index 18083dfe6b3..9b0aa0ef931 100644 --- a/test/CodeGen/X86/half.ll +++ b/test/CodeGen/X86/half.ll @@ -777,7 +777,7 @@ define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) #0 { ; BWON-F16C-NEXT: callq __truncdfhf2 ; BWON-F16C-NEXT: movl %eax, %r15d ; BWON-F16C-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; BWON-F16C-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; BWON-F16C-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; BWON-F16C-NEXT: vzeroupper ; BWON-F16C-NEXT: callq __truncdfhf2 ; BWON-F16C-NEXT: movl %eax, %ebp diff --git a/test/CodeGen/X86/handle-move.ll b/test/CodeGen/X86/handle-move.ll index dcad6c83aaa..8acfd7ff209 100644 --- a/test/CodeGen/X86/handle-move.ll +++ b/test/CodeGen/X86/handle-move.ll @@ -5,10 +5,10 @@ ; Test the LiveIntervals::handleMove() function. ; ; Moving the DIV32r instruction exercises the regunit update code because -; %EDX has a live range into the function and is used by the DIV32r. +; %edx has a live range into the function and is used by the DIV32r. ; ; Here sinking a kill + dead def: -; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> +; 144B -> 180B: DIV32r %vreg4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> ; %vreg4: [48r,144r:0) 0@48r ; --> [48r,180r:0) 0@48r ; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r @@ -25,7 +25,7 @@ entry: } ; Same as above, but moving a kill + live def: -; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use> +; 144B -> 180B: DIV32r %vreg4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> ; %vreg4: [48r,144r:0) 0@48r ; --> [48r,180r:0) 0@48r ; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r @@ -59,7 +59,7 @@ entry: } ; Move EFLAGS dead def across another def: -; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead> +; handleMove 208B -> 36B: %edx<def> = MOV32r0 %EFLAGS<imp-def,dead> ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208r 1@224r 2@272r 3@160r 4@20r 5@304r ; --> [20r,20d:4)[36r,36d:0)[160r,160d:3)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@36r 1@224r 2@272r 3@160r 4@20r 5@304r ; diff --git a/test/CodeGen/X86/horizontal-reduce-smax.ll b/test/CodeGen/X86/horizontal-reduce-smax.ll index 956a9b1c732..71294904b22 100644 --- a/test/CodeGen/X86/horizontal-reduce-smax.ll +++ b/test/CodeGen/X86/horizontal-reduce-smax.ll @@ -206,7 +206,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v8i16: @@ -216,7 +216,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v8i16: @@ -226,7 +226,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vmovd %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v8i16: @@ -239,7 +239,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v8i16: @@ -249,7 +249,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v8i16: @@ -259,7 +259,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vmovd %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp sgt <8 x i16> %a0, %1 @@ -304,7 +304,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm2, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i8: @@ -320,7 +320,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v16i8: @@ -334,7 +334,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v16i8: @@ -366,7 +366,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm2, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i8: @@ -382,7 +382,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v16i8: @@ -396,7 +396,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp sgt <16 x i8> %a0, %1 @@ -746,7 +746,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i16: @@ -757,7 +757,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v16i16: @@ -769,7 +769,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -782,7 +782,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -797,7 +797,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i16: @@ -808,7 +808,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v16i16: @@ -820,7 +820,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -833,7 +833,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -846,7 +846,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -900,7 +900,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: por %xmm1, %xmm2 ; X86-SSE2-NEXT: movd %xmm2, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i8: @@ -917,7 +917,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i8: @@ -933,7 +933,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -950,7 +950,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -988,7 +988,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm2 ; X64-SSE2-NEXT: por %xmm1, %xmm2 ; X64-SSE2-NEXT: movd %xmm2, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i8: @@ -1005,7 +1005,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i8: @@ -1021,7 +1021,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1038,7 +1038,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1055,7 +1055,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1552,7 +1552,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i16: @@ -1565,7 +1565,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i16: @@ -1580,7 +1580,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1594,7 +1594,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1611,7 +1611,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pmaxsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i16: @@ -1624,7 +1624,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i16: @@ -1639,7 +1639,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1653,7 +1653,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1668,7 +1668,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1735,7 +1735,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm2, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v64i8: @@ -1754,7 +1754,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v64i8: @@ -1773,7 +1773,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1791,7 +1791,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1839,7 +1839,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm2, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v64i8: @@ -1858,7 +1858,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v64i8: @@ -1877,7 +1877,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1895,7 +1895,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1914,7 +1914,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpmaxsb %zmm1, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/horizontal-reduce-smin.ll b/test/CodeGen/X86/horizontal-reduce-smin.ll index cee519547b4..45025bf7cc7 100644 --- a/test/CodeGen/X86/horizontal-reduce-smin.ll +++ b/test/CodeGen/X86/horizontal-reduce-smin.ll @@ -208,7 +208,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v8i16: @@ -218,7 +218,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v8i16: @@ -228,7 +228,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vmovd %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v8i16: @@ -241,7 +241,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v8i16: @@ -251,7 +251,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v8i16: @@ -261,7 +261,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vmovd %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp slt <8 x i16> %a0, %1 @@ -306,7 +306,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm2, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i8: @@ -322,7 +322,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v16i8: @@ -336,7 +336,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v16i8: @@ -368,7 +368,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm2, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i8: @@ -384,7 +384,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v16i8: @@ -398,7 +398,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp slt <16 x i8> %a0, %1 @@ -750,7 +750,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i16: @@ -761,7 +761,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v16i16: @@ -773,7 +773,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -786,7 +786,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -801,7 +801,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i16: @@ -812,7 +812,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v16i16: @@ -824,7 +824,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -837,7 +837,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -850,7 +850,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -904,7 +904,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: por %xmm1, %xmm2 ; X86-SSE2-NEXT: movd %xmm2, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i8: @@ -921,7 +921,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i8: @@ -937,7 +937,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -954,7 +954,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -992,7 +992,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm2 ; X64-SSE2-NEXT: por %xmm1, %xmm2 ; X64-SSE2-NEXT: movd %xmm2, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i8: @@ -1009,7 +1009,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i8: @@ -1025,7 +1025,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1042,7 +1042,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1059,7 +1059,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1554,7 +1554,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE2-NEXT: psrld $16, %xmm1 ; X86-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i16: @@ -1567,7 +1567,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i16: @@ -1582,7 +1582,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1596,7 +1596,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1613,7 +1613,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE2-NEXT: psrld $16, %xmm1 ; X64-SSE2-NEXT: pminsw %xmm0, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i16: @@ -1626,7 +1626,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i16: @@ -1641,7 +1641,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1655,7 +1655,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1670,7 +1670,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1737,7 +1737,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm2, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v64i8: @@ -1756,7 +1756,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v64i8: @@ -1775,7 +1775,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1793,7 +1793,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1841,7 +1841,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm2, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v64i8: @@ -1860,7 +1860,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminsb %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v64i8: @@ -1879,7 +1879,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1897,7 +1897,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1916,7 +1916,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpminsb %zmm1, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/horizontal-reduce-umax.ll b/test/CodeGen/X86/horizontal-reduce-umax.ll index 97235a825b4..35d94e88f80 100644 --- a/test/CodeGen/X86/horizontal-reduce-umax.ll +++ b/test/CodeGen/X86/horizontal-reduce-umax.ll @@ -254,7 +254,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm3 ; X86-SSE2-NEXT: por %xmm2, %xmm3 ; X86-SSE2-NEXT: movd %xmm3, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v8i16: @@ -264,7 +264,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v8i16: @@ -274,7 +274,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vmovd %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v8i16: @@ -308,7 +308,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm3 ; X64-SSE2-NEXT: por %xmm2, %xmm3 ; X64-SSE2-NEXT: movd %xmm3, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v8i16: @@ -318,7 +318,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v8i16: @@ -328,7 +328,7 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vmovd %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp ugt <8 x i16> %a0, %1 @@ -357,7 +357,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i8: @@ -373,7 +373,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v16i8: @@ -387,7 +387,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v16i8: @@ -403,7 +403,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i8: @@ -419,7 +419,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v16i8: @@ -433,7 +433,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp ugt <16 x i8> %a0, %1 @@ -863,7 +863,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm3, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i16: @@ -874,7 +874,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v16i16: @@ -886,7 +886,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -899,7 +899,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -942,7 +942,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm3, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i16: @@ -953,7 +953,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v16i16: @@ -965,7 +965,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -978,7 +978,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -991,7 +991,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1025,7 +1025,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i8: @@ -1042,7 +1042,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i8: @@ -1058,7 +1058,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1075,7 +1075,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1093,7 +1093,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i8: @@ -1110,7 +1110,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i8: @@ -1126,7 +1126,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1143,7 +1143,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1160,7 +1160,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1787,7 +1787,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: por %xmm1, %xmm2 ; X86-SSE2-NEXT: movd %xmm2, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i16: @@ -1800,7 +1800,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: pxor %xmm1, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i16: @@ -1815,7 +1815,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1829,7 +1829,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1888,7 +1888,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm2 ; X64-SSE2-NEXT: por %xmm1, %xmm2 ; X64-SSE2-NEXT: movd %xmm2, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i16: @@ -1901,7 +1901,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: pxor %xmm1, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i16: @@ -1916,7 +1916,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1930,7 +1930,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1945,7 +1945,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1984,7 +1984,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v64i8: @@ -2003,7 +2003,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v64i8: @@ -2022,7 +2022,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -2040,7 +2040,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -2060,7 +2060,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v64i8: @@ -2079,7 +2079,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pmaxub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v64i8: @@ -2098,7 +2098,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -2116,7 +2116,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -2135,7 +2135,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpmaxub %zmm1, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/horizontal-reduce-umin.ll b/test/CodeGen/X86/horizontal-reduce-umin.ll index ba290751f12..9c2e3788b1c 100644 --- a/test/CodeGen/X86/horizontal-reduce-umin.ll +++ b/test/CodeGen/X86/horizontal-reduce-umin.ll @@ -256,21 +256,21 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm1 ; X86-SSE2-NEXT: por %xmm3, %xmm1 ; X86-SSE2-NEXT: movd %xmm1, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v8i16: ; X86-SSE42: ## BB#0: ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v8i16: ; X86-AVX: ## BB#0: ; X86-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX-NEXT: vmovd %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v8i16: @@ -304,21 +304,21 @@ define i16 @test_reduce_v8i16(<8 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm1 ; X64-SSE2-NEXT: por %xmm3, %xmm1 ; X64-SSE2-NEXT: movd %xmm1, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v8i16: ; X64-SSE42: ## BB#0: ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v8i16: ; X64-AVX: ## BB#0: ; X64-AVX-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX-NEXT: vmovd %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp ult <8 x i16> %a0, %1 @@ -347,7 +347,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pminub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i8: @@ -363,7 +363,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX-LABEL: test_reduce_v16i8: @@ -377,7 +377,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX-NEXT: retl ; ; X64-SSE2-LABEL: test_reduce_v16i8: @@ -393,7 +393,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pminub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i8: @@ -409,7 +409,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX-LABEL: test_reduce_v16i8: @@ -423,7 +423,7 @@ define i8 @test_reduce_v16i8(<16 x i8> %a0) { ; X64-AVX-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX-NEXT: retq %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %2 = icmp ult <16 x i8> %a0, %1 @@ -857,7 +857,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: por %xmm4, %xmm2 ; X86-SSE2-NEXT: movd %xmm2, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v16i16: @@ -865,7 +865,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-SSE42-NEXT: pminuw %xmm1, %xmm0 ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v16i16: @@ -874,7 +874,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -884,7 +884,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X86-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -927,7 +927,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm2 ; X64-SSE2-NEXT: por %xmm4, %xmm2 ; X64-SSE2-NEXT: movd %xmm2, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v16i16: @@ -935,7 +935,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-SSE42-NEXT: pminuw %xmm1, %xmm0 ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v16i16: @@ -944,7 +944,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX1-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -954,7 +954,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -964,7 +964,7 @@ define i16 @test_reduce_v16i16(<16 x i16> %a0) { ; X64-AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <16 x i16> %a0, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -998,7 +998,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pminub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i8: @@ -1015,7 +1015,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i8: @@ -1031,7 +1031,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1048,7 +1048,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1066,7 +1066,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pminub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i8: @@ -1083,7 +1083,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i8: @@ -1099,7 +1099,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1116,7 +1116,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1133,7 +1133,7 @@ define i8 @test_reduce_v32i8(<32 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i8> %a0, <32 x i8> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1758,7 +1758,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: por %xmm2, %xmm4 ; X86-SSE2-NEXT: movd %xmm4, %eax -; X86-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v32i16: @@ -1768,7 +1768,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-SSE42-NEXT: pminuw %xmm1, %xmm0 ; X86-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X86-SSE42-NEXT: movd %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v32i16: @@ -1780,7 +1780,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX1-NEXT: vpminuw %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX1-NEXT: vmovd %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1791,7 +1791,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X86-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X86-AVX2-NEXT: vmovd %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -1850,7 +1850,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE2-NEXT: pandn %xmm0, %xmm4 ; X64-SSE2-NEXT: por %xmm2, %xmm4 ; X64-SSE2-NEXT: movd %xmm4, %eax -; X64-SSE2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v32i16: @@ -1860,7 +1860,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-SSE42-NEXT: pminuw %xmm1, %xmm0 ; X64-SSE42-NEXT: phminposuw %xmm0, %xmm0 ; X64-SSE42-NEXT: movd %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v32i16: @@ -1872,7 +1872,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX1-NEXT: vpminuw %xmm2, %xmm0, %xmm0 ; X64-AVX1-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX1-NEXT: vmovd %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -1883,7 +1883,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX2-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X64-AVX2-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -1895,7 +1895,7 @@ define i16 @test_reduce_v32i16(<32 x i16> %a0) { ; X64-AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; X64-AVX512-NEXT: vphminposuw %xmm0, %xmm0 ; X64-AVX512-NEXT: vmovd %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <32 x i16> %a0, <32 x i16> undef, <32 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -1934,7 +1934,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: pminub %xmm1, %xmm0 ; X86-SSE2-NEXT: movd %xmm0, %eax -; X86-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE2-NEXT: retl ; ; X86-SSE42-LABEL: test_reduce_v64i8: @@ -1953,7 +1953,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-SSE42-NEXT: psrlw $8, %xmm0 ; X86-SSE42-NEXT: pminub %xmm1, %xmm0 ; X86-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X86-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-SSE42-NEXT: retl ; ; X86-AVX1-LABEL: test_reduce_v64i8: @@ -1972,7 +1972,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: retl ; @@ -1990,7 +1990,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X86-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X86-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X86-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X86-AVX2-NEXT: vzeroupper ; X86-AVX2-NEXT: retl ; @@ -2010,7 +2010,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: pminub %xmm1, %xmm0 ; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE2-NEXT: retq ; ; X64-SSE42-LABEL: test_reduce_v64i8: @@ -2029,7 +2029,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-SSE42-NEXT: psrlw $8, %xmm0 ; X64-SSE42-NEXT: pminub %xmm1, %xmm0 ; X64-SSE42-NEXT: pextrb $0, %xmm0, %eax -; X64-SSE42-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-SSE42-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-SSE42-NEXT: retq ; ; X64-AVX1-LABEL: test_reduce_v64i8: @@ -2048,7 +2048,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX1-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX1-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX1-NEXT: vzeroupper ; X64-AVX1-NEXT: retq ; @@ -2066,7 +2066,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX2-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX2-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; X64-AVX2-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX2-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX2-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX2-NEXT: vzeroupper ; X64-AVX2-NEXT: retq ; @@ -2085,7 +2085,7 @@ define i8 @test_reduce_v64i8(<64 x i8> %a0) { ; X64-AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; X64-AVX512-NEXT: vpminub %zmm1, %zmm0, %zmm0 ; X64-AVX512-NEXT: vpextrb $0, %xmm0, %eax -; X64-AVX512-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; X64-AVX512-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; X64-AVX512-NEXT: vzeroupper ; X64-AVX512-NEXT: retq %1 = shufflevector <64 x i8> %a0, <64 x i8> undef, <64 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/iabs.ll b/test/CodeGen/X86/iabs.ll index 4088f023978..952c31c7814 100644 --- a/test/CodeGen/X86/iabs.ll +++ b/test/CodeGen/X86/iabs.ll @@ -41,7 +41,7 @@ define i16 @test_i16(i16 %a) nounwind { ; X86-NO-CMOV-NEXT: sarw $15, %cx ; X86-NO-CMOV-NEXT: addl %ecx, %eax ; X86-NO-CMOV-NEXT: xorl %ecx, %eax -; X86-NO-CMOV-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NO-CMOV-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NO-CMOV-NEXT: retl ; ; X86-CMOV-LABEL: test_i16: diff --git a/test/CodeGen/X86/illegal-bitfield-loadstore.ll b/test/CodeGen/X86/illegal-bitfield-loadstore.ll index fd503aa6c6e..39e11f2b96e 100644 --- a/test/CodeGen/X86/illegal-bitfield-loadstore.ll +++ b/test/CodeGen/X86/illegal-bitfield-loadstore.ll @@ -116,7 +116,7 @@ define void @i56_or(i56* %a) { ; X64-NEXT: movzwl 4(%rdi), %eax ; X64-NEXT: movzbl 6(%rdi), %ecx ; X64-NEXT: movb %cl, 6(%rdi) -; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def> +; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<kill> %rcx<def> ; X64-NEXT: shll $16, %ecx ; X64-NEXT: orl %eax, %ecx ; X64-NEXT: shlq $32, %rcx @@ -148,7 +148,7 @@ define void @i56_and_or(i56* %a) { ; X64-NEXT: movzwl 4(%rdi), %eax ; X64-NEXT: movzbl 6(%rdi), %ecx ; X64-NEXT: movb %cl, 6(%rdi) -; X64-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def> +; X64-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<kill> %rcx<def> ; X64-NEXT: shll $16, %ecx ; X64-NEXT: orl %eax, %ecx ; X64-NEXT: shlq $32, %rcx @@ -186,7 +186,7 @@ define void @i56_insert_bit(i56* %a, i1 zeroext %bit) { ; X64-NEXT: movzwl 4(%rdi), %ecx ; X64-NEXT: movzbl 6(%rdi), %edx ; X64-NEXT: movb %dl, 6(%rdi) -; X64-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def> +; X64-NEXT: # kill: %edx<def> %edx<kill> %rdx<kill> %rdx<def> ; X64-NEXT: shll $16, %edx ; X64-NEXT: orl %ecx, %edx ; X64-NEXT: shlq $32, %rdx diff --git a/test/CodeGen/X86/imul.ll b/test/CodeGen/X86/imul.ll index e364b001f94..7aa698e0570 100644 --- a/test/CodeGen/X86/imul.ll +++ b/test/CodeGen/X86/imul.ll @@ -218,7 +218,7 @@ entry: define i32 @test2(i32 %a) { ; X64-LABEL: test2: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movl %edi, %eax ; X64-NEXT: shll $5, %eax ; X64-NEXT: leal (%rax,%rdi), %eax @@ -239,7 +239,7 @@ entry: define i32 @test3(i32 %a) { ; X64-LABEL: test3: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movl %edi, %eax ; X64-NEXT: shll $5, %eax ; X64-NEXT: leal (%rax,%rdi), %eax diff --git a/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll b/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll index fa04530e5cf..c4bdfb6a103 100644 --- a/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll +++ b/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll @@ -1,133 +1,133 @@ ; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t -define <4 x float> @testXMM_1(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_1(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_2(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_2(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "movapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_3(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_3(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_4(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_4(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vmpsadbw $$0, $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_5(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_5(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, i32 %_l) ret <4 x float> %0 } -define i32 @testXMM_6(i32 returned %_l) { +define i32 @testxmm_6(i32 returned %_l) { ; CHECK: error: inline assembly requires more registers than available entry: tail call void asm sideeffect "vmovd $0, %eax", "v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l) ret i32 %_l } -define <4 x float> @testXMM_7(<4 x float> returned %_xmm0) { +define <4 x float> @testxmm_7(<4 x float> returned %_xmm0) { ; CHECK: error: inline assembly requires more registers than available entry: tail call void asm sideeffect "vmovmskps $0, %eax", "v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0) ret <4 x float> %_xmm0 } -define i32 @testXMM_8(<4 x float> %_xmm0, i32 %_l) { +define i32 @testxmm_8(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call i32 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0) ret i32 %0 } -define <4 x float> @testXMM_9(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_9(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_10(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_10(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "pabsb $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_11(<4 x float> %_xmm0, i32 %_l) { +define <4 x float> @testxmm_11(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vpabsd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i32 %_l) ret <4 x float> %0 } -define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmulps $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmulpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) diff --git a/test/CodeGen/X86/inline-asm-avx-v-constraint.ll b/test/CodeGen/X86/inline-asm-avx-v-constraint.ll index 408dcb75da4..2c8de16fd37 100644 --- a/test/CodeGen/X86/inline-asm-avx-v-constraint.ll +++ b/test/CodeGen/X86/inline-asm-avx-v-constraint.ll @@ -1,133 +1,133 @@ ; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx | FileCheck %s ; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512f | FileCheck %s -define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vmovhlps %xmm1, %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) { ; CHECK: movapd %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "movapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vmovapd %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_4(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_4(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vmpsadbw $0, %xmm1, %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vmpsadbw $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vminpd %xmm0, %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l) ret <4 x float> %0 } -define i64 @testXMM_6(i64 returned %_l) { +define i64 @testxmm_6(i64 returned %_l) { ; CHECK: vmovd %xmm0, %eax entry: tail call void asm sideeffect "vmovd $0, %eax", "v,~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret i64 %_l } -define <4 x float> @testXMM_7(<4 x float> returned %_xmm0) { +define <4 x float> @testxmm_7(<4 x float> returned %_xmm0) { ; CHECK: vmovmskps %xmm0, %eax entry: tail call void asm sideeffect "vmovmskps $0, %rax", "v,~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0) ret <4 x float> %_xmm0 } -define i64 @testXMM_8(<4 x float> %_xmm0, i64 %_l) { +define i64 @testxmm_8(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vmulsd %xmm1, %xmm0, %xmm0 entry: %0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret i64 %0 } -define <4 x float> @testXMM_9(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_9(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vorpd %xmm1, %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_10(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_10(<4 x float> %_xmm0, i64 %_l) { ; CHECK: pabsb %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "pabsb $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_11(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_11(<4 x float> %_xmm0, i64 %_l) { ; CHECK: vpabsd %xmm0, %xmm0 entry: %0 = tail call <4 x float> asm "vpabsd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmovsldup %ymm0, %ymm0 entry: %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmovapd %ymm1, %ymm0 entry: %0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vminpd %ymm1, %ymm0, %ymm0 entry: %0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vorpd %ymm1, %ymm0, %ymm0 entry: %0 = tail call <8 x float> asm "vorpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmulps %ymm1, %ymm0, %ymm0 entry: %0 = tail call <8 x float> asm "vmulps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmulpd %ymm1, %ymm0, %ymm0 entry: %0 = tail call <8 x float> asm "vmulpd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmovups %ymm1, %ymm0 entry: %0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: vmovupd %ymm1, %ymm0 entry: %0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) diff --git a/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll b/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll index 5b792d145ed..019973ba935 100644 --- a/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll +++ b/test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512f | FileCheck %s -define <16 x float> @testZMM_1(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_1(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpternlogd $0, %zmm1, %zmm0, %zmm0 %0 = tail call <16 x float> asm "vpternlogd $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm0) ret <16 x float> %0 } -define <16 x float> @testZMM_2(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_2(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpabsq %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpabsq $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1) @@ -15,7 +15,7 @@ entry: } -define <16 x float> @testZMM_3(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_3(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpaddd %zmm1, %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpaddd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1) @@ -23,7 +23,7 @@ entry: } -define <16 x float> @testZMM_4(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_4(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpaddq %zmm1, %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpaddq $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1) @@ -31,7 +31,7 @@ entry: } -define <16 x float> @testZMM_5(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_5(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpandd %zmm1, %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1) @@ -39,7 +39,7 @@ entry: } -define <16 x float> @testZMM_6(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_6(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpandnd %zmm1, %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1) @@ -47,7 +47,7 @@ entry: } -define <16 x float> @testZMM_7(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_7(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vpmaxsd %zmm1, %zmm1, %zmm0 %0 = tail call <16 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm1) @@ -55,7 +55,7 @@ entry: } -define <16 x float> @testZMM_8(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_8(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vmovups %zmm1, %zmm0 %0 = tail call <16 x float> asm "vmovups $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1) @@ -63,7 +63,7 @@ entry: } -define <16 x float> @testZMM_9(<16 x float> %_zmm0, <16 x float> %_zmm1) { +define <16 x float> @testzmm_9(<16 x float> %_zmm0, <16 x float> %_zmm1) { entry: ; CHECK: vmovupd %zmm1, %zmm0 %0 = tail call <16 x float> asm "vmovupd $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1) diff --git a/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll b/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll index 81d17d3ac9a..7278089348e 100644 --- a/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll +++ b/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll @@ -1,7 +1,7 @@ ; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t -define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) @@ -9,7 +9,7 @@ entry: } -define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l) @@ -17,7 +17,7 @@ entry: } -define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l) @@ -25,7 +25,7 @@ entry: } -define i64 @testXMM_4(<4 x float> %_xmm0, i64 %_l) { +define i64 @testxmm_4(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) @@ -33,7 +33,7 @@ entry: } -define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vpabsq $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(i64 %_l) @@ -41,7 +41,7 @@ entry: } -define <4 x float> @testXMM_6(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_6(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l) @@ -49,7 +49,7 @@ entry: } -define <4 x float> @testXMM_7(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_7(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <4 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l) @@ -57,7 +57,7 @@ entry: } -define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) @@ -65,7 +65,7 @@ entry: } -define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) @@ -73,7 +73,7 @@ entry: } -define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm1) @@ -81,7 +81,7 @@ entry: } -define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vpabsq $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) @@ -89,7 +89,7 @@ entry: } -define <8 x float> @testYMM_5(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_5(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) @@ -97,7 +97,7 @@ entry: } -define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) @@ -105,7 +105,7 @@ entry: } -define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vpminud $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) @@ -113,7 +113,7 @@ entry: } -define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) @@ -121,7 +121,7 @@ entry: } -define <8 x float> @testYMM_9(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_9(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) @@ -129,7 +129,7 @@ entry: } -define <8 x float> @testYMM_10(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_10(<8 x float> %_ymm0, <8 x float> %_ymm1) { ; CHECK: error: inline assembly requires more registers than available entry: %0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) diff --git a/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll b/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll index 42910cb10ba..4b01814b2e2 100644 --- a/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll +++ b/test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll @@ -1,118 +1,118 @@ ; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -mattr +avx512vl | FileCheck %s -define <4 x float> @testXMM_1(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vmovhlps %xmm17, %xmm16, %xmm16 %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret <4 x float> %0 } -define <4 x float> @testXMM_2(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_2(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vmovapd %xmm16, %xmm16 %0 = tail call <4 x float> asm "vmovapd $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_3(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_3(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vminpd %xmm16, %xmm16, %xmm16 %0 = tail call <4 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, i64 %_l) ret <4 x float> %0 } -define i64 @testXMM_4(<4 x float> %_xmm0, i64 %_l) { +define i64 @testxmm_4(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vmulsd %xmm17, %xmm16, %xmm16 %0 = tail call i64 asm "vmulsd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0) ret i64 %0 } -define <4 x float> @testXMM_5(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_5(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vpabsq %xmm16, %xmm16 %0 = tail call <4 x float> asm "vpabsq $1, $0", "=v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_6(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_6(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vpandd %xmm16, %xmm17, %xmm16 %0 = tail call <4 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l) ret <4 x float> %0 } -define <4 x float> @testXMM_7(<4 x float> %_xmm0, i64 %_l) { +define <4 x float> @testxmm_7(<4 x float> %_xmm0, i64 %_l) { entry: ; CHECK: vpandnd %xmm16, %xmm17, %xmm16 %0 = tail call <4 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(<4 x float> %_xmm0, i64 %_l) ret <4 x float> %0 } -define <8 x float> @testYMM_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_1(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vmovsldup %ymm16, %ymm16 %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_2(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vmovapd %ymm16, %ymm16 %0 = tail call <8 x float> asm "vmovapd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_3(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vminpd %ymm16, %ymm16, %ymm16 %0 = tail call <8 x float> asm "vminpd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_4(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vpabsq %ymm16, %ymm16 %0 = tail call <8 x float> asm "vpabsq $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_5(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_5(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vpandd %ymm16, %ymm17, %ymm16 %0 = tail call <8 x float> asm "vpandd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_6(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vpandnd %ymm16, %ymm17, %ymm16 %0 = tail call <8 x float> asm "vpandnd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_7(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vpminud %ymm16, %ymm17, %ymm16 %0 = tail call <8 x float> asm "vpminud $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_8(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vpmaxsd %ymm16, %ymm17, %ymm16 %0 = tail call <8 x float> asm "vpmaxsd $1, $2, $0", "=v,v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1, <8 x float> %_ymm0) ret <8 x float> %0 } -define <8 x float> @testYMM_9(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_9(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vmovups %ymm16, %ymm16 %0 = tail call <8 x float> asm "vmovups $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) ret <8 x float> %0 } -define <8 x float> @testYMM_10(<8 x float> %_ymm0, <8 x float> %_ymm1) { +define <8 x float> @testymm_10(<8 x float> %_ymm0, <8 x float> %_ymm1) { entry: ; CHECK: vmovupd %ymm16, %ymm16 %0 = tail call <8 x float> asm "vmovupd $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm1) diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll index f873b708f20..61870d8d417 100644 --- a/test/CodeGen/X86/inline-asm-fpstack.ll +++ b/test/CodeGen/X86/inline-asm-fpstack.ll @@ -437,9 +437,9 @@ entry: ; inline-asm instruction and the ST register was live across another ; inline-asm instruction. ; -; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %ST0<tied3>, $2:[clobber], %EFLAGS<earlyclobber,imp-def,dead> -; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %EAX<undef>, 1, %noreg, 0, %noreg, $1:[clobber], %EFLAGS<earlyclobber,imp-def,dead> -; %FP0<def> = COPY %ST0 +; INLINEASM <es:frndint> [sideeffect] [attdialect], $0:[regdef], %st0<imp-def,tied5>, $1:[reguse tiedto:$0], %st0<tied3>, $2:[clobber], %eflags<earlyclobber,imp-def,dead> +; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %eax<undef>, 1, %noreg, 0, %noreg, $1:[clobber], %eflags<earlyclobber,imp-def,dead> +; %fp0<def> = COPY %st0 %struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] } %struct.anon1 = type { i32, i32, i32 } diff --git a/test/CodeGen/X86/inline-asm-stack-realign.ll b/test/CodeGen/X86/inline-asm-stack-realign.ll index cfbe260a33a..14ee9702243 100644 --- a/test/CodeGen/X86/inline-asm-stack-realign.ll +++ b/test/CodeGen/X86/inline-asm-stack-realign.ll @@ -1,6 +1,6 @@ ; RUN: not llc -mtriple=i686-pc-win32 < %s 2>&1 | FileCheck %s -; FIXME: This is miscompiled due to our unconditional use of ESI as the base +; FIXME: This is miscompiled due to our unconditional use of esi as the base ; pointer. ; XFAIL: * diff --git a/test/CodeGen/X86/inline-asm-tied.ll b/test/CodeGen/X86/inline-asm-tied.ll index db63a804883..7363e613a56 100644 --- a/test/CodeGen/X86/inline-asm-tied.ll +++ b/test/CodeGen/X86/inline-asm-tied.ll @@ -14,7 +14,7 @@ entry: ; CHECK-DAG: movl 4(%esp), %eax ; CHECK: ## InlineAsm Start ; CHECK: ## InlineAsm End -; Everything is set up in EAX:EDX, return immediately. +; Everything is set up in eax:edx, return immediately. ; CHECK-NEXT: retl ; The tied operands are not necessarily in the same order as the defs. diff --git a/test/CodeGen/X86/lea-3.ll b/test/CodeGen/X86/lea-3.ll index 5b009d69008..09154e4fb78 100644 --- a/test/CodeGen/X86/lea-3.ll +++ b/test/CodeGen/X86/lea-3.ll @@ -36,25 +36,25 @@ define i64 @test2(i64 %a) { define i32 @test(i32 %a) { ; LNX1-LABEL: test: ; LNX1: # BB#0: -; LNX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; LNX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; LNX1-NEXT: leal (%rdi,%rdi,2), %eax ; LNX1-NEXT: retq ; ; LNX2-LABEL: test: ; LNX2: # BB#0: -; LNX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; LNX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; LNX2-NEXT: leal (%rdi,%rdi,2), %eax ; LNX2-NEXT: retq ; ; NACL-LABEL: test: ; NACL: # BB#0: -; NACL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; NACL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; NACL-NEXT: leal (%rdi,%rdi,2), %eax ; NACL-NEXT: retq ; ; WIN-LABEL: test: ; WIN: # BB#0: -; WIN-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; WIN-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; WIN-NEXT: leal (%rcx,%rcx,2), %eax ; WIN-NEXT: retq %tmp2 = mul i32 %a, 3 diff --git a/test/CodeGen/X86/lea-opt-cse3.ll b/test/CodeGen/X86/lea-opt-cse3.ll index 87949b40d48..48ab3130bf0 100644 --- a/test/CodeGen/X86/lea-opt-cse3.ll +++ b/test/CodeGen/X86/lea-opt-cse3.ll @@ -5,8 +5,8 @@ define i32 @foo(i32 %a, i32 %b) local_unnamed_addr #0 { ; X64-LABEL: foo: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 4(%rdi,%rsi,2), %ecx ; X64-NEXT: leal 4(%rdi,%rsi,4), %eax ; X64-NEXT: imull %ecx, %eax @@ -33,8 +33,8 @@ entry: define i32 @foo1(i32 %a, i32 %b) local_unnamed_addr #0 { ; X64-LABEL: foo1: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 4(%rdi,%rsi,4), %ecx ; X64-NEXT: leal 4(%rdi,%rsi,8), %eax ; X64-NEXT: imull %ecx, %eax @@ -61,8 +61,8 @@ entry: define i32 @foo1_mult_basic_blocks(i32 %a, i32 %b) local_unnamed_addr #0 { ; X64-LABEL: foo1_mult_basic_blocks: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 4(%rdi,%rsi,4), %ecx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl $10, %ecx @@ -113,8 +113,8 @@ exit: define i32 @foo1_mult_basic_blocks_illegal_scale(i32 %a, i32 %b) local_unnamed_addr #0 { ; X64-LABEL: foo1_mult_basic_blocks_illegal_scale: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 4(%rdi,%rsi,2), %ecx ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: cmpl $10, %ecx diff --git a/test/CodeGen/X86/lea32-schedule.ll b/test/CodeGen/X86/lea32-schedule.ll index 18a165009ea..5ba3ddd3a3b 100644 --- a/test/CodeGen/X86/lea32-schedule.ll +++ b/test/CodeGen/X86/lea32-schedule.ll @@ -14,13 +14,13 @@ define i32 @test_lea_offset(i32) { ; GENERIC-LABEL: test_lea_offset: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_offset: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal -24(%rdi), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -32,43 +32,43 @@ define i32 @test_lea_offset(i32) { ; ; SLM-LABEL: test_lea_offset: ; SLM: # BB#0: -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal -24(%rdi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_offset: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_offset: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_offset: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_offset: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_offset: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal -24(%rdi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_offset: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal -24(%rdi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %2 = add nsw i32 %0, -24 @@ -78,13 +78,13 @@ define i32 @test_lea_offset(i32) { define i32 @test_lea_offset_big(i32) { ; GENERIC-LABEL: test_lea_offset_big: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_offset_big: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal 1024(%rdi), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -96,43 +96,43 @@ define i32 @test_lea_offset_big(i32) { ; ; SLM-LABEL: test_lea_offset_big: ; SLM: # BB#0: -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal 1024(%rdi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_offset_big: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_offset_big: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_offset_big: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_offset_big: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_offset_big: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal 1024(%rdi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_offset_big: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal 1024(%rdi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %2 = add nsw i32 %0, 1024 @@ -143,15 +143,15 @@ define i32 @test_lea_offset_big(i32) { define i32 @test_lea_add(i32, i32) { ; GENERIC-LABEL: test_lea_add: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_add: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal (%rdi,%rsi), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -163,50 +163,50 @@ define i32 @test_lea_add(i32, i32) { ; ; SLM-LABEL: test_lea_add: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal (%rdi,%rsi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_add: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_add: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_add: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_add: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = add nsw i32 %1, %0 @@ -216,16 +216,16 @@ define i32 @test_lea_add(i32, i32) { define i32 @test_lea_add_offset(i32, i32) { ; GENERIC-LABEL: test_lea_add_offset: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $16, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_add_offset: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -237,54 +237,54 @@ define i32 @test_lea_add_offset(i32, i32) { ; ; SLM-LABEL: test_lea_add_offset: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add_offset: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $16, %eax # sched: [1:0.33] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_add_offset: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $16, %eax # sched: [1:0.25] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_add_offset: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $16, %eax # sched: [1:0.25] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_add_offset: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $16, %eax # sched: [1:0.25] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_add_offset: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add_offset: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal 16(%rdi,%rsi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = add i32 %0, 16 @@ -295,8 +295,8 @@ define i32 @test_lea_add_offset(i32, i32) { define i32 @test_lea_add_offset_big(i32, i32) { ; GENERIC-LABEL: test_lea_add_offset_big: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $-4096, %eax # imm = 0xF000 ; GENERIC-NEXT: # sched: [1:0.33] @@ -304,8 +304,8 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; ATOM-LABEL: test_lea_add_offset_big: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -317,15 +317,15 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; SLM-LABEL: test_lea_add_offset_big: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add_offset_big: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $-4096, %eax # imm = 0xF000 ; SANDY-NEXT: # sched: [1:0.33] @@ -333,8 +333,8 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; HASWELL-LABEL: test_lea_add_offset_big: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $-4096, %eax # imm = 0xF000 ; HASWELL-NEXT: # sched: [1:0.25] @@ -342,8 +342,8 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; BROADWELL-LABEL: test_lea_add_offset_big: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $-4096, %eax # imm = 0xF000 ; BROADWELL-NEXT: # sched: [1:0.25] @@ -351,8 +351,8 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; SKYLAKE-LABEL: test_lea_add_offset_big: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $-4096, %eax # imm = 0xF000 ; SKYLAKE-NEXT: # sched: [1:0.25] @@ -360,15 +360,15 @@ define i32 @test_lea_add_offset_big(i32, i32) { ; ; BTVER2-LABEL: test_lea_add_offset_big: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add_offset_big: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal -4096(%rdi,%rsi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = add i32 %0, -4096 @@ -379,13 +379,13 @@ define i32 @test_lea_add_offset_big(i32, i32) { define i32 @test_lea_mul(i32) { ; GENERIC-LABEL: test_lea_mul: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_mul: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -397,43 +397,43 @@ define i32 @test_lea_mul(i32) { ; ; SLM-LABEL: test_lea_mul: ; SLM: # BB#0: -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_mul: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_mul: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_mul: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_mul: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_mul: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_mul: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %2 = mul nsw i32 %0, 3 @@ -443,14 +443,14 @@ define i32 @test_lea_mul(i32) { define i32 @test_lea_mul_offset(i32) { ; GENERIC-LABEL: test_lea_mul_offset: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $-32, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_mul_offset: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -462,47 +462,47 @@ define i32 @test_lea_mul_offset(i32) { ; ; SLM-LABEL: test_lea_mul_offset: ; SLM: # BB#0: -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_mul_offset: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $-32, %eax # sched: [1:0.33] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_mul_offset: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $-32, %eax # sched: [1:0.25] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_mul_offset: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $-32, %eax # sched: [1:0.25] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_mul_offset: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $-32, %eax # sched: [1:0.25] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_mul_offset: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_mul_offset: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal -32(%rdi,%rdi,2), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %2 = mul nsw i32 %0, 3 @@ -513,7 +513,7 @@ define i32 @test_lea_mul_offset(i32) { define i32 @test_lea_mul_offset_big(i32) { ; GENERIC-LABEL: test_lea_mul_offset_big: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $10000, %eax # imm = 0x2710 ; GENERIC-NEXT: # sched: [1:0.33] @@ -521,7 +521,7 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; ATOM-LABEL: test_lea_mul_offset_big: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -533,13 +533,13 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; SLM-LABEL: test_lea_mul_offset_big: ; SLM: # BB#0: -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_mul_offset_big: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $10000, %eax # imm = 0x2710 ; SANDY-NEXT: # sched: [1:0.33] @@ -547,7 +547,7 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; HASWELL-LABEL: test_lea_mul_offset_big: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $10000, %eax # imm = 0x2710 ; HASWELL-NEXT: # sched: [1:0.25] @@ -555,7 +555,7 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; BROADWELL-LABEL: test_lea_mul_offset_big: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $10000, %eax # imm = 0x2710 ; BROADWELL-NEXT: # sched: [1:0.25] @@ -563,7 +563,7 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; SKYLAKE-LABEL: test_lea_mul_offset_big: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $10000, %eax # imm = 0x2710 ; SKYLAKE-NEXT: # sched: [1:0.25] @@ -571,13 +571,13 @@ define i32 @test_lea_mul_offset_big(i32) { ; ; BTVER2-LABEL: test_lea_mul_offset_big: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_mul_offset_big: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal 10000(%rdi,%rdi,8), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %2 = mul nsw i32 %0, 9 @@ -588,15 +588,15 @@ define i32 @test_lea_mul_offset_big(i32) { define i32 @test_lea_add_scale(i32, i32) { ; GENERIC-LABEL: test_lea_add_scale: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_add_scale: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -608,50 +608,50 @@ define i32 @test_lea_add_scale(i32, i32) { ; ; SLM-LABEL: test_lea_add_scale: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add_scale: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_add_scale: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_add_scale: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_add_scale: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_add_scale: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add_scale: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal (%rdi,%rsi,2), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = shl i32 %1, 1 @@ -662,16 +662,16 @@ define i32 @test_lea_add_scale(i32, i32) { define i32 @test_lea_add_scale_offset(i32, i32) { ; GENERIC-LABEL: test_lea_add_scale_offset: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $96, %eax # sched: [1:0.33] ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_lea_add_scale_offset: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -683,54 +683,54 @@ define i32 @test_lea_add_scale_offset(i32, i32) { ; ; SLM-LABEL: test_lea_add_scale_offset: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add_scale_offset: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $96, %eax # sched: [1:0.33] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_lea_add_scale_offset: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $96, %eax # sched: [1:0.25] ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_lea_add_scale_offset: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $96, %eax # sched: [1:0.25] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_lea_add_scale_offset: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi,4), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $96, %eax # sched: [1:0.25] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_lea_add_scale_offset: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add_scale_offset: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal 96(%rdi,%rsi,4), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = shl i32 %1, 2 @@ -742,8 +742,8 @@ define i32 @test_lea_add_scale_offset(i32, i32) { define i32 @test_lea_add_scale_offset_big(i32, i32) { ; GENERIC-LABEL: test_lea_add_scale_offset_big: ; GENERIC: # BB#0: -; GENERIC-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; GENERIC-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; GENERIC-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; GENERIC-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; GENERIC-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50] ; GENERIC-NEXT: addl $-1200, %eax # imm = 0xFB50 ; GENERIC-NEXT: # sched: [1:0.33] @@ -751,8 +751,8 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; ATOM-LABEL: test_lea_add_scale_offset_big: ; ATOM: # BB#0: -; ATOM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ATOM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ATOM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ATOM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ATOM-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:1.00] ; ATOM-NEXT: nop # sched: [1:0.50] ; ATOM-NEXT: nop # sched: [1:0.50] @@ -764,15 +764,15 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; SLM-LABEL: test_lea_add_scale_offset_big: ; SLM: # BB#0: -; SLM-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_lea_add_scale_offset_big: ; SANDY: # BB#0: -; SANDY-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SANDY-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SANDY-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SANDY-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SANDY-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50] ; SANDY-NEXT: addl $-1200, %eax # imm = 0xFB50 ; SANDY-NEXT: # sched: [1:0.33] @@ -780,8 +780,8 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; HASWELL-LABEL: test_lea_add_scale_offset_big: ; HASWELL: # BB#0: -; HASWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; HASWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HASWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; HASWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HASWELL-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50] ; HASWELL-NEXT: addl $-1200, %eax # imm = 0xFB50 ; HASWELL-NEXT: # sched: [1:0.25] @@ -789,8 +789,8 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; BROADWELL-LABEL: test_lea_add_scale_offset_big: ; BROADWELL: # BB#0: -; BROADWELL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BROADWELL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BROADWELL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BROADWELL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BROADWELL-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50] ; BROADWELL-NEXT: addl $-1200, %eax # imm = 0xFB50 ; BROADWELL-NEXT: # sched: [1:0.25] @@ -798,8 +798,8 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; SKYLAKE-LABEL: test_lea_add_scale_offset_big: ; SKYLAKE: # BB#0: -; SKYLAKE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SKYLAKE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SKYLAKE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SKYLAKE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SKYLAKE-NEXT: leal (%rdi,%rsi,8), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: addl $-1200, %eax # imm = 0xFB50 ; SKYLAKE-NEXT: # sched: [1:0.25] @@ -807,15 +807,15 @@ define i32 @test_lea_add_scale_offset_big(i32, i32) { ; ; BTVER2-LABEL: test_lea_add_scale_offset_big: ; BTVER2: # BB#0: -; BTVER2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; BTVER2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; BTVER2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; BTVER2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; BTVER2-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_lea_add_scale_offset_big: ; ZNVER1: # BB#0: -; ZNVER1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ZNVER1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ZNVER1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ZNVER1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ZNVER1-NEXT: leal -1200(%rdi,%rsi,8), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %3 = shl i32 %1, 3 diff --git a/test/CodeGen/X86/loop-search.ll b/test/CodeGen/X86/loop-search.ll index fda4ecec0e6..85ae7518a37 100644 --- a/test/CodeGen/X86/loop-search.ll +++ b/test/CodeGen/X86/loop-search.ll @@ -25,15 +25,15 @@ define zeroext i1 @search(i32 %needle, i32* nocapture readonly %haystack, i32 %c ; ### FIXME: BB#3 and LBB0_1 should be merged ; CHECK-NEXT: ## BB#3: ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ; CHECK-NEXT: LBB0_1: ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ; CHECK-NEXT: LBB0_6: ; CHECK-NEXT: movb $1, %al -; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %cmp5 = icmp sgt i32 %count, 0 diff --git a/test/CodeGen/X86/lzcnt-schedule.ll b/test/CodeGen/X86/lzcnt-schedule.ll index d50fad7535e..10f1935f88f 100644 --- a/test/CodeGen/X86/lzcnt-schedule.ll +++ b/test/CodeGen/X86/lzcnt-schedule.ll @@ -13,7 +13,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; GENERIC-NEXT: lzcntw (%rsi), %cx ; GENERIC-NEXT: lzcntw %di, %ax ; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_ctlz_i16: @@ -21,7 +21,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; HASWELL-NEXT: lzcntw (%rsi), %cx # sched: [3:1.00] ; HASWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00] ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_ctlz_i16: @@ -29,7 +29,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; BROADWELL-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00] ; BROADWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00] ; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_ctlz_i16: @@ -37,7 +37,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00] ; SKYLAKE-NEXT: lzcntw %di, %ax # sched: [3:1.00] ; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_ctlz_i16: @@ -45,7 +45,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; BTVER2-NEXT: lzcntw (%rsi), %cx ; BTVER2-NEXT: lzcntw %di, %ax ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_ctlz_i16: @@ -53,7 +53,7 @@ define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) { ; ZNVER1-NEXT: lzcntw (%rsi), %cx # sched: [6:0.50] ; ZNVER1-NEXT: lzcntw %di, %ax # sched: [2:0.25] ; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = load i16, i16 *%a1 %2 = tail call i16 @llvm.ctlz.i16( i16 %1, i1 false ) diff --git a/test/CodeGen/X86/lzcnt-zext-cmp.ll b/test/CodeGen/X86/lzcnt-zext-cmp.ll index 7c961a98ad5..5064579b511 100644 --- a/test/CodeGen/X86/lzcnt-zext-cmp.ll +++ b/test/CodeGen/X86/lzcnt-zext-cmp.ll @@ -84,7 +84,7 @@ define i16 @test_zext_cmp3(i16 %a, i16 %b) { ; ALL-NEXT: sete %cl ; ALL-NEXT: orb %al, %cl ; ALL-NEXT: movzbl %cl, %eax -; ALL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ALL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ALL-NEXT: retq %cmp = icmp eq i16 %a, 0 %cmp1 = icmp eq i16 %b, 0 @@ -128,7 +128,7 @@ define i32 @test_zext_cmp5(i64 %a, i64 %b) { ; FASTLZCNT-NEXT: lzcntq %rsi, %rax ; FASTLZCNT-NEXT: orl %ecx, %eax ; FASTLZCNT-NEXT: shrl $6, %eax -; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; FASTLZCNT-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; FASTLZCNT-NEXT: retq ; ; NOFASTLZCNT-LABEL: test_zext_cmp5: @@ -267,7 +267,7 @@ define i32 @test_zext_cmp9(i32 %a, i64 %b) { ; FASTLZCNT-NEXT: shrl $5, %ecx ; FASTLZCNT-NEXT: shrl $6, %eax ; FASTLZCNT-NEXT: orl %ecx, %eax -; FASTLZCNT-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; FASTLZCNT-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; FASTLZCNT-NEXT: retq ; ; NOFASTLZCNT-LABEL: test_zext_cmp9: diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll index abf39c9a058..b7441577c63 100644 --- a/test/CodeGen/X86/machine-cse.ll +++ b/test/CodeGen/X86/machine-cse.ll @@ -50,8 +50,8 @@ declare void @printf(...) nounwind define void @commute(i32 %test_case, i32 %scale) nounwind ssp { ; CHECK-LABEL: commute: ; CHECK: # BB#0: # %entry -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: cmpl $2, %eax ; CHECK-NEXT: ja .LBB1_4 @@ -64,7 +64,7 @@ define void @commute(i32 %test_case, i32 %scale) nounwind ssp { ; CHECK-NEXT: imull %edi, %esi ; CHECK-NEXT: leal (%rsi,%rsi,2), %esi ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<kill> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<kill> ; CHECK-NEXT: callq printf ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: .p2align 4, 0x90 diff --git a/test/CodeGen/X86/machine-outliner-tailcalls.ll b/test/CodeGen/X86/machine-outliner-tailcalls.ll index 020f7eeaaff..b7426a9c30c 100644 --- a/test/CodeGen/X86/machine-outliner-tailcalls.ll +++ b/test/CodeGen/X86/machine-outliner-tailcalls.ll @@ -32,4 +32,4 @@ attributes #0 = { noredzone nounwind ssp uwtable "no-frame-pointer-elim"="false" ; CHECK-LABEL: l_OUTLINED_FUNCTION_0: ; CHECK: movl $0, (%rax) ; CHECK-NEXT: movl $1, %edi -; CHECK-NEXT: jmp _ext
\ No newline at end of file +; CHECK-NEXT: jmp _ext diff --git a/test/CodeGen/X86/masked_gather_scatter.ll b/test/CodeGen/X86/masked_gather_scatter.ll index 1c678bda33e..602e3442358 100644 --- a/test/CodeGen/X86/masked_gather_scatter.ll +++ b/test/CodeGen/X86/masked_gather_scatter.ll @@ -811,26 +811,26 @@ declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*>, i32, <2 x define <4 x float> @test15(float* %base, <4 x i32> %ind, <4 x i1> %mask) { ; KNL_64-LABEL: test15: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_64-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_64-NEXT: vpmovsxdq %ymm0, %zmm2 ; KNL_64-NEXT: vpslld $31, %ymm1, %ymm0 ; KNL_64-NEXT: vptestmd %zmm0, %zmm0, %k1 ; KNL_64-NEXT: vgatherqps (%rdi,%zmm2,4), %ymm0 {%k1} -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: retq ; ; KNL_32-LABEL: test15: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_32-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vpmovsxdq %ymm0, %zmm2 ; KNL_32-NEXT: vpslld $31, %ymm1, %ymm0 ; KNL_32-NEXT: vptestmd %zmm0, %zmm0, %k1 ; KNL_32-NEXT: vgatherqps (%eax,%zmm2,4), %ymm0 {%k1} -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: retl ; @@ -861,8 +861,8 @@ define <4 x float> @test15(float* %base, <4 x i32> %ind, <4 x i1> %mask) { define <4 x double> @test16(double* %base, <4 x i32> %ind, <4 x i1> %mask, <4 x double> %src0) { ; KNL_64-LABEL: test16: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_64-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -876,8 +876,8 @@ define <4 x double> @test16(double* %base, <4 x i32> %ind, <4 x i1> %mask, <4 x ; ; KNL_32-LABEL: test16: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_32-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -916,8 +916,8 @@ define <4 x double> @test16(double* %base, <4 x i32> %ind, <4 x i1> %mask, <4 x define <2 x double> @test17(double* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x double> %src0) { ; KNL_64-LABEL: test17: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_64-NEXT: vpsllq $63, %zmm1, %zmm1 ; KNL_64-NEXT: vptestmq %zmm1, %zmm1, %k1 @@ -928,8 +928,8 @@ define <2 x double> @test17(double* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x ; ; KNL_32-LABEL: test17: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vpsllq $63, %zmm1, %zmm1 @@ -971,8 +971,8 @@ declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> , <2 x float*> , i32 define void @test18(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) { ; KNL_64-LABEL: test18: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_64-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_64-NEXT: vmovdqa %xmm2, %xmm2 ; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2 ; KNL_64-NEXT: vptestmd %zmm2, %zmm2, %k1 @@ -982,8 +982,8 @@ define void @test18(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) { ; ; KNL_32-LABEL: test18: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_32-NEXT: vmovdqa %xmm2, %xmm2 ; KNL_32-NEXT: vpmovsxdq %ymm1, %zmm1 ; KNL_32-NEXT: vpslld $31, %ymm2, %ymm2 @@ -1013,8 +1013,8 @@ define void @test18(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) { define void @test19(<4 x double>%a1, double* %ptr, <4 x i1>%mask, <4 x i64> %ind) { ; KNL_64-LABEL: test19: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; KNL_64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; KNL_64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL_64-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -1027,8 +1027,8 @@ define void @test19(<4 x double>%a1, double* %ptr, <4 x i1>%mask, <4 x i64> %ind ; ; KNL_32-LABEL: test19: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; KNL_32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; KNL_32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -1065,8 +1065,8 @@ define void @test19(<4 x double>%a1, double* %ptr, <4 x i1>%mask, <4 x i64> %ind define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) { ; KNL_64-LABEL: test20: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero ; KNL_64-NEXT: vmovaps %xmm2, %xmm2 ; KNL_64-NEXT: vpslld $31, %ymm2, %ymm2 @@ -1077,7 +1077,7 @@ define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) { ; ; KNL_32-LABEL: test20: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_32-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; KNL_32-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,2],zero,zero ; KNL_32-NEXT: vmovaps %xmm2, %xmm2 @@ -1090,7 +1090,7 @@ define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) { ; ; SKX-LABEL: test20: ; SKX: # BB#0: -; SKX-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; SKX-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; SKX-NEXT: vptestmq %xmm2, %xmm2, %k1 ; SKX-NEXT: vscatterqps %xmm0, (,%ymm1) {%k1} @@ -1112,7 +1112,7 @@ define void @test20(<2 x float>%a1, <2 x float*> %ptr, <2 x i1> %mask) { define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) { ; KNL_64-LABEL: test21: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; KNL_64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; KNL_64-NEXT: vmovdqa %xmm2, %xmm2 ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: vpsllq $63, %zmm2, %zmm2 @@ -1123,7 +1123,7 @@ define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) { ; ; KNL_32-LABEL: test21: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; KNL_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; KNL_32-NEXT: vmovdqa %xmm2, %xmm2 ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vpsllq $63, %zmm2, %zmm2 @@ -1134,7 +1134,7 @@ define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) { ; ; SKX-LABEL: test21: ; SKX: # BB#0: -; SKX-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; SKX-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; SKX-NEXT: vptestmq %xmm2, %xmm2, %k1 ; SKX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1144,7 +1144,7 @@ define void @test21(<2 x i32>%a1, <2 x i32*> %ptr, <2 x i1>%mask) { ; ; SKX_32-LABEL: test21: ; SKX_32: # BB#0: -; SKX_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; SKX_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; SKX_32-NEXT: vpsllq $63, %xmm2, %xmm2 ; SKX_32-NEXT: vptestmq %xmm2, %xmm2, %k1 ; SKX_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1161,7 +1161,7 @@ declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1 define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float> %src0) { ; KNL_64-LABEL: test22: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> +; KNL_64-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<def> ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_64-NEXT: vmovaps %xmm1, %xmm1 @@ -1175,7 +1175,7 @@ define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x fl ; ; KNL_32-LABEL: test22: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> +; KNL_32-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<def> ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_32-NEXT: vmovaps %xmm1, %xmm1 @@ -1215,8 +1215,8 @@ define <2 x float> @test22(float* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x fl define <2 x float> @test22a(float* %base, <2 x i64> %ind, <2 x i1> %mask, <2 x float> %src0) { ; KNL_64-LABEL: test22a: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_64-NEXT: vmovaps %xmm1, %xmm1 ; KNL_64-NEXT: vpslld $31, %ymm1, %ymm1 @@ -1228,8 +1228,8 @@ define <2 x float> @test22a(float* %base, <2 x i64> %ind, <2 x i1> %mask, <2 x f ; ; KNL_32-LABEL: test22a: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,2],zero,zero ; KNL_32-NEXT: vmovaps %xmm1, %xmm1 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -1267,8 +1267,8 @@ declare <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*>, i32, <2 x i1>, < define <2 x i32> @test23(i32* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> %src0) { ; KNL_64-LABEL: test23: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_64-NEXT: vpsllq $63, %zmm1, %zmm1 ; KNL_64-NEXT: vptestmq %zmm1, %zmm1, %k1 @@ -1279,8 +1279,8 @@ define <2 x i32> @test23(i32* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> % ; ; KNL_32-LABEL: test23: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vpsllq $63, %zmm1, %zmm1 @@ -1317,7 +1317,7 @@ define <2 x i32> @test23(i32* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> % define <2 x i32> @test24(i32* %base, <2 x i32> %ind) { ; KNL_64-LABEL: test24: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1} @@ -1327,7 +1327,7 @@ define <2 x i32> @test24(i32* %base, <2 x i32> %ind) { ; ; KNL_32-LABEL: test24: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vmovdqa {{.*#+}} xmm1 = [1,0,1,0] ; KNL_32-NEXT: vpsllq $63, %zmm1, %zmm1 @@ -1360,8 +1360,8 @@ define <2 x i32> @test24(i32* %base, <2 x i32> %ind) { define <2 x i64> @test25(i64* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> %src0) { ; KNL_64-LABEL: test25: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_64-NEXT: vpsllq $63, %zmm1, %zmm1 ; KNL_64-NEXT: vptestmq %zmm1, %zmm1, %k1 @@ -1372,8 +1372,8 @@ define <2 x i64> @test25(i64* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> % ; ; KNL_32-LABEL: test25: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM2<def> %XMM2<kill> %ZMM2<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm2<def> %xmm2<kill> %zmm2<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: vmovdqa %xmm1, %xmm1 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vpsllq $63, %zmm1, %zmm1 @@ -1408,8 +1408,8 @@ define <2 x i64> @test25(i64* %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> % define <2 x i64> @test26(i64* %base, <2 x i32> %ind, <2 x i64> %src0) { ; KNL_64-LABEL: test26: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: vpgatherqq (%rdi,%zmm0,8), %zmm1 {%k1} @@ -1419,8 +1419,8 @@ define <2 x i64> @test26(i64* %base, <2 x i32> %ind, <2 x i64> %src0) { ; ; KNL_32-LABEL: test26: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; KNL_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: vmovdqa {{.*#+}} xmm2 = [1,0,1,0] ; KNL_32-NEXT: vpsllq $63, %zmm2, %zmm2 @@ -1459,7 +1459,7 @@ define <2 x float> @test27(float* %base, <2 x i32> %ind) { ; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: kmovw %eax, %k1 ; KNL_64-NEXT: vgatherqps (%rdi,%zmm1,4), %ymm0 {%k1} -; KNL_64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_64-NEXT: vzeroupper ; KNL_64-NEXT: retq ; @@ -1471,7 +1471,7 @@ define <2 x float> @test27(float* %base, <2 x i32> %ind) { ; KNL_32-NEXT: movb $3, %cl ; KNL_32-NEXT: kmovw %ecx, %k1 ; KNL_32-NEXT: vgatherqps (%eax,%zmm1,4), %ymm0 {%k1} -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; KNL_32-NEXT: vzeroupper ; KNL_32-NEXT: retl ; @@ -1501,7 +1501,7 @@ define <2 x float> @test27(float* %base, <2 x i32> %ind) { define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) { ; KNL_64-LABEL: test28: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; KNL_64-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; KNL_64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_64-NEXT: movb $3, %al ; KNL_64-NEXT: kmovw %eax, %k1 @@ -1511,7 +1511,7 @@ define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) { ; ; KNL_32-LABEL: test28: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> +; KNL_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> ; KNL_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; KNL_32-NEXT: vmovdqa {{.*#+}} xmm2 = [1,0,1,0] ; KNL_32-NEXT: vpsllq $63, %zmm2, %zmm2 @@ -1522,7 +1522,7 @@ define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) { ; ; SKX-LABEL: test28: ; SKX: # BB#0: -; SKX-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; SKX-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; SKX-NEXT: movb $3, %al ; SKX-NEXT: kmovw %eax, %k1 ; SKX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1532,7 +1532,7 @@ define void @test28(<2 x i32>%a1, <2 x i32*> %ptr) { ; ; SKX_32-LABEL: test28: ; SKX_32: # BB#0: -; SKX_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; SKX_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; SKX_32-NEXT: movb $3, %al ; SKX_32-NEXT: kmovw %eax, %k1 ; SKX_32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] @@ -1606,7 +1606,7 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x ; KNL_64-NEXT: vpsllq $2, %ymm1, %ymm1 ; KNL_64-NEXT: vpaddq %ymm1, %ymm0, %ymm1 ; KNL_64-NEXT: testb $1, %dil -; KNL_64-NEXT: # implicit-def: %XMM0 +; KNL_64-NEXT: # implicit-def: %xmm0 ; KNL_64-NEXT: je .LBB30_2 ; KNL_64-NEXT: # BB#1: # %cond.load ; KNL_64-NEXT: vmovq %xmm1, %rax @@ -1655,7 +1655,7 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x ; KNL_32-NEXT: vpslld $2, %xmm1, %xmm1 ; KNL_32-NEXT: vpaddd %xmm1, %xmm0, %xmm1 ; KNL_32-NEXT: testb $1, %al -; KNL_32-NEXT: # implicit-def: %XMM0 +; KNL_32-NEXT: # implicit-def: %xmm0 ; KNL_32-NEXT: je .LBB30_2 ; KNL_32-NEXT: # BB#1: # %cond.load ; KNL_32-NEXT: vmovd %xmm1, %ecx @@ -1703,7 +1703,7 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x ; SKX-NEXT: vpsllq $2, %ymm1, %ymm1 ; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm1 ; SKX-NEXT: testb $1, %al -; SKX-NEXT: # implicit-def: %XMM0 +; SKX-NEXT: # implicit-def: %xmm0 ; SKX-NEXT: je .LBB30_2 ; SKX-NEXT: # BB#1: # %cond.load ; SKX-NEXT: vmovq %xmm1, %rax @@ -1745,7 +1745,7 @@ define <3 x i32> @test30(<3 x i32*> %base, <3 x i32> %ind, <3 x i1> %mask, <3 x ; SKX_32-NEXT: vpslld $2, %xmm1, %xmm1 ; SKX_32-NEXT: vpaddd %xmm1, %xmm0, %xmm2 ; SKX_32-NEXT: testb $1, %al -; SKX_32-NEXT: # implicit-def: %XMM1 +; SKX_32-NEXT: # implicit-def: %xmm1 ; SKX_32-NEXT: je .LBB30_2 ; SKX_32-NEXT: # BB#1: # %cond.load ; SKX_32-NEXT: vmovd %xmm2, %eax @@ -2289,7 +2289,7 @@ declare void @llvm.masked.scatter.v16f64.v16p0f64(<16 x double> %src0, <16 x dou define <4 x i64> @test_pr28312(<4 x i64*> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64> %d) { ; KNL_64-LABEL: test_pr28312: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL_64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL_64-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_64-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -2310,7 +2310,7 @@ define <4 x i64> @test_pr28312(<4 x i64*> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i6 ; KNL_32-NEXT: .cfi_def_cfa_register %ebp ; KNL_32-NEXT: andl $-32, %esp ; KNL_32-NEXT: subl $32, %esp -; KNL_32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL_32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL_32-NEXT: vpslld $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpsrad $31, %xmm1, %xmm1 ; KNL_32-NEXT: vpmovsxdq %xmm1, %ymm1 @@ -2482,7 +2482,7 @@ declare <1 x i32> @llvm.masked.gather.v1i32.v1p0i32(<1 x i32*>, i32, <1 x i1>, < define <2 x float> @large_index(float* %base, <2 x i128> %ind, <2 x i1> %mask, <2 x float> %src0) { ; KNL_64-LABEL: large_index: ; KNL_64: # BB#0: -; KNL_64-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; KNL_64-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; KNL_64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero ; KNL_64-NEXT: vmovaps %xmm0, %xmm0 ; KNL_64-NEXT: vmovq %rcx, %xmm2 @@ -2497,7 +2497,7 @@ define <2 x float> @large_index(float* %base, <2 x i128> %ind, <2 x i1> %mask, < ; ; KNL_32-LABEL: large_index: ; KNL_32: # BB#0: -; KNL_32-NEXT: # kill: %XMM1<def> %XMM1<kill> %YMM1<def> +; KNL_32-NEXT: # kill: %xmm1<def> %xmm1<kill> %ymm1<def> ; KNL_32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero ; KNL_32-NEXT: vmovaps %xmm0, %xmm0 ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax diff --git a/test/CodeGen/X86/masked_memop.ll b/test/CodeGen/X86/masked_memop.ll index ef666ff1c41..495983ac573 100644 --- a/test/CodeGen/X86/masked_memop.ll +++ b/test/CodeGen/X86/masked_memop.ll @@ -12,7 +12,7 @@ define <1 x double> @loadv1(<1 x i64> %trigger, <1 x double>* %addr, <1 x double ; AVX-LABEL: loadv1: ; AVX: ## BB#0: ; AVX-NEXT: testq %rdi, %rdi -; AVX-NEXT: ## implicit-def: %XMM1 +; AVX-NEXT: ## implicit-def: %xmm1 ; AVX-NEXT: je LBB0_1 ; AVX-NEXT: ## BB#2: ## %else ; AVX-NEXT: testq %rdi, %rdi @@ -32,7 +32,7 @@ define <1 x double> @loadv1(<1 x i64> %trigger, <1 x double>* %addr, <1 x double ; AVX512F-LABEL: loadv1: ; AVX512F: ## BB#0: ; AVX512F-NEXT: testq %rdi, %rdi -; AVX512F-NEXT: ## implicit-def: %XMM1 +; AVX512F-NEXT: ## implicit-def: %xmm1 ; AVX512F-NEXT: jne LBB0_2 ; AVX512F-NEXT: ## BB#1: ## %cond.load ; AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero @@ -46,7 +46,7 @@ define <1 x double> @loadv1(<1 x i64> %trigger, <1 x double>* %addr, <1 x double ; SKX-LABEL: loadv1: ; SKX: ## BB#0: ; SKX-NEXT: testq %rdi, %rdi -; SKX-NEXT: ## implicit-def: %XMM1 +; SKX-NEXT: ## implicit-def: %xmm1 ; SKX-NEXT: jne LBB0_2 ; SKX-NEXT: ## BB#1: ## %cond.load ; SKX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero @@ -316,14 +316,14 @@ define <8 x float> @test11a(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> ; ; AVX512F-LABEL: test11a: ; AVX512F: ## BB#0: -; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0 ; AVX512F-NEXT: kshiftlw $8, %k0, %k0 ; AVX512F-NEXT: kshiftrw $8, %k0, %k1 ; AVX512F-NEXT: vblendmps (%rdi), %zmm1, %zmm0 {%k1} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: test11a: @@ -362,12 +362,12 @@ define <8 x i32> @test11b(<8 x i1> %mask, <8 x i32>* %addr, <8 x i32> %dst) { ; ; AVX512F-LABEL: test11b: ; AVX512F: ## BB#0: -; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; AVX512F-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512F-NEXT: vpmovsxwq %xmm0, %zmm0 ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vpblendmd (%rdi), %zmm1, %zmm0 {%k1} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: test11b: @@ -407,7 +407,7 @@ define <8 x float> @test11c(<8 x i1> %mask, <8 x float>* %addr) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vmovups (%rdi), %zmm0 {%k1} {z} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: test11c: @@ -447,7 +447,7 @@ define <8 x i32> @test11d(<8 x i1> %mask, <8 x i32>* %addr) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} {z} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: test11d: @@ -482,8 +482,8 @@ define void @test12(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) { ; ; AVX512F-LABEL: test12: ; AVX512F: ## BB#0: -; AVX512F-NEXT: ## kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: ## kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm0, %k0 ; AVX512F-NEXT: kshiftlw $8, %k0, %k0 @@ -816,11 +816,11 @@ define <8 x float> @mload_constmask_v8f32(<8 x float>* %addr, <8 x float> %dst) ; ; AVX512F-LABEL: mload_constmask_v8f32: ; AVX512F: ## BB#0: -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: movw $7, %ax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vmovups (%rdi), %zmm0 {%k1} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: mload_constmask_v8f32: @@ -868,11 +868,11 @@ define <8 x i32> @mload_constmask_v8i32(<8 x i32>* %addr, <8 x i32> %dst) { ; ; AVX512F-LABEL: mload_constmask_v8i32: ; AVX512F: ## BB#0: -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: movw $135, %ax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} -; AVX512F-NEXT: ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: ## kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; SKX-LABEL: mload_constmask_v8i32: diff --git a/test/CodeGen/X86/maskmovdqu.ll b/test/CodeGen/X86/maskmovdqu.ll index 54d950abad8..2f13c535e50 100644 --- a/test/CodeGen/X86/maskmovdqu.ll +++ b/test/CodeGen/X86/maskmovdqu.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=i686-- -mattr=+sse2,-avx | grep -i EDI -; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | grep -i RDI -; RUN: llc < %s -mtriple=i686-- -mattr=+avx | grep -i EDI -; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | grep -i RDI +; RUN: llc < %s -mtriple=i686-- -mattr=+sse2,-avx | grep -i edi +; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | grep -i rdi +; RUN: llc < %s -mtriple=i686-- -mattr=+avx | grep -i edi +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | grep -i rdi ; rdar://6573467 define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind { diff --git a/test/CodeGen/X86/misched-copy.ll b/test/CodeGen/X86/misched-copy.ll index f123490d124..1263bf91fa8 100644 --- a/test/CodeGen/X86/misched-copy.ll +++ b/test/CodeGen/X86/misched-copy.ll @@ -9,10 +9,10 @@ ; MUL_HiLo PhysReg def copies should be just below the mul. ; ; CHECK: *** Final schedule for BB#1 *** -; CHECK: %EAX<def> = COPY -; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; -; CHECK-NEXT: COPY %E{{[AD]}}X -; CHECK-NEXT: COPY %E{{[AD]}}X +; CHECK: %eax<def> = COPY +; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %eax<imp-def>, %edx<imp-def>, %eflags<imp-def,dead>, %eax<imp-use>; +; CHECK-NEXT: COPY %e{{[ad]}}x +; CHECK-NEXT: COPY %e{{[ad]}}x ; CHECK: DIVSSrm define i64 @mulhoist(i32 %a, i32 %b) #0 { entry: diff --git a/test/CodeGen/X86/movmsk.ll b/test/CodeGen/X86/movmsk.ll index e40f64eb39b..c2010d09d0e 100644 --- a/test/CodeGen/X86/movmsk.ll +++ b/test/CodeGen/X86/movmsk.ll @@ -102,7 +102,7 @@ define void @float_call_signbit(double %n) { ; CHECK: ## BB#0: ## %entry ; CHECK-NEXT: movq %xmm0, %rdi ; CHECK-NEXT: shrq $63, %rdi -; CHECK-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<kill> +; CHECK-NEXT: ## kill: %edi<def> %edi<kill> %rdi<kill> ; CHECK-NEXT: jmp _float_call_signbit_callee ## TAILCALL entry: %t0 = bitcast double %n to i64 diff --git a/test/CodeGen/X86/mul-constant-i16.ll b/test/CodeGen/X86/mul-constant-i16.ll index 7b39bfe1c48..c3b822ac214 100644 --- a/test/CodeGen/X86/mul-constant-i16.ll +++ b/test/CodeGen/X86/mul-constant-i16.ll @@ -21,14 +21,14 @@ define i16 @test_mul_by_2(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl %eax, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_2: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 2 ret i16 %mul @@ -39,14 +39,14 @@ define i16 @test_mul_by_3(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_3: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 3 ret i16 %mul @@ -57,14 +57,14 @@ define i16 @test_mul_by_4(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $2, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_4: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (,%rdi,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 4 ret i16 %mul @@ -75,14 +75,14 @@ define i16 @test_mul_by_5(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_5: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 5 ret i16 %mul @@ -94,15 +94,15 @@ define i16 @test_mul_by_6(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl %eax, %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_6: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: addl %edi, %edi ; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 6 ret i16 %mul @@ -114,15 +114,15 @@ define i16 @test_mul_by_7(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: leal (,%ecx,8), %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_7: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (,%rdi,8), %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 7 ret i16 %mul @@ -133,14 +133,14 @@ define i16 @test_mul_by_8(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $3, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_8: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (,%rdi,8), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 8 ret i16 %mul @@ -151,14 +151,14 @@ define i16 @test_mul_by_9(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,8), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_9: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 9 ret i16 %mul @@ -170,15 +170,15 @@ define i16 @test_mul_by_10(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl %eax, %eax ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_10: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: addl %edi, %edi ; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 10 ret i16 %mul @@ -190,15 +190,15 @@ define i16 @test_mul_by_11(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,4), %ecx ; X86-NEXT: leal (%eax,%ecx,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_11: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: leal (%rdi,%rax,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 11 ret i16 %mul @@ -210,15 +210,15 @@ define i16 @test_mul_by_12(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $2, %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_12: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shll $2, %edi ; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 12 ret i16 %mul @@ -230,15 +230,15 @@ define i16 @test_mul_by_13(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,2), %ecx ; X86-NEXT: leal (%eax,%ecx,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_13: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,2), %eax ; X64-NEXT: leal (%rdi,%rax,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 13 ret i16 %mul @@ -251,16 +251,16 @@ define i16 @test_mul_by_14(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,2), %eax ; X86-NEXT: leal (%ecx,%eax,4), %eax ; X86-NEXT: addl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_14: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,2), %eax ; X64-NEXT: leal (%rdi,%rax,4), %eax ; X64-NEXT: addl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 14 ret i16 %mul @@ -272,15 +272,15 @@ define i16 @test_mul_by_15(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_15: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: leal (%rax,%rax,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 15 ret i16 %mul @@ -291,7 +291,7 @@ define i16 @test_mul_by_16(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $4, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_16: @@ -310,16 +310,16 @@ define i16 @test_mul_by_17(i16 %x) { ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: shll $4, %eax ; X86-NEXT: addl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_17: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movl %edi, %eax ; X64-NEXT: shll $4, %eax ; X64-NEXT: leal (%rax,%rdi), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 17 ret i16 %mul @@ -331,15 +331,15 @@ define i16 @test_mul_by_18(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl %eax, %eax ; X86-NEXT: leal (%eax,%eax,8), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_18: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: addl %edi, %edi ; X64-NEXT: leal (%rdi,%rdi,8), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 18 ret i16 %mul @@ -352,16 +352,16 @@ define i16 @test_mul_by_19(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,4), %eax ; X86-NEXT: shll $2, %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_19: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: shll $2, %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 19 ret i16 %mul @@ -373,15 +373,15 @@ define i16 @test_mul_by_20(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $2, %eax ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_20: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shll $2, %edi ; X64-NEXT: leal (%rdi,%rdi,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 20 ret i16 %mul @@ -393,15 +393,15 @@ define i16 @test_mul_by_21(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,4), %ecx ; X86-NEXT: leal (%eax,%ecx,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_21: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: leal (%rdi,%rax,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 21 ret i16 %mul @@ -414,16 +414,16 @@ define i16 @test_mul_by_22(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,4), %eax ; X86-NEXT: leal (%ecx,%eax,4), %eax ; X86-NEXT: addl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_22: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: leal (%rdi,%rax,4), %eax ; X64-NEXT: addl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 22 ret i16 %mul @@ -436,16 +436,16 @@ define i16 @test_mul_by_23(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,2), %eax ; X86-NEXT: shll $3, %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_23: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,2), %eax ; X64-NEXT: shll $3, %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 23 ret i16 %mul @@ -457,15 +457,15 @@ define i16 @test_mul_by_24(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $3, %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_24: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shll $3, %edi ; X64-NEXT: leal (%rdi,%rdi,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 24 ret i16 %mul @@ -477,15 +477,15 @@ define i16 @test_mul_by_25(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_25: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,4), %eax ; X64-NEXT: leal (%rax,%rax,4), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 25 ret i16 %mul @@ -498,16 +498,16 @@ define i16 @test_mul_by_26(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,8), %eax ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_26: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,8), %eax ; X64-NEXT: leal (%rax,%rax,2), %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 26 ret i16 %mul @@ -519,15 +519,15 @@ define i16 @test_mul_by_27(i16 %x) { ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal (%eax,%eax,8), %eax ; X86-NEXT: leal (%eax,%eax,2), %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_27: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,8), %eax ; X64-NEXT: leal (%rax,%rax,2), %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 27 ret i16 %mul @@ -540,16 +540,16 @@ define i16 @test_mul_by_28(i16 %x) { ; X86-NEXT: leal (%ecx,%ecx,8), %eax ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: addl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_28: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,8), %eax ; X64-NEXT: leal (%rax,%rax,2), %eax ; X64-NEXT: addl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 28 ret i16 %mul @@ -563,17 +563,17 @@ define i16 @test_mul_by_29(i16 %x) { ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: addl %ecx, %eax ; X86-NEXT: addl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_29: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rdi,8), %eax ; X64-NEXT: leal (%rax,%rax,2), %eax ; X64-NEXT: addl %edi, %eax ; X64-NEXT: addl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 29 ret i16 %mul @@ -587,7 +587,7 @@ define i16 @test_mul_by_30(i16 %x) { ; X86-NEXT: shll $5, %eax ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_30: @@ -596,7 +596,7 @@ define i16 @test_mul_by_30(i16 %x) { ; X64-NEXT: shll $5, %eax ; X64-NEXT: subl %edi, %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 30 ret i16 %mul @@ -609,7 +609,7 @@ define i16 @test_mul_by_31(i16 %x) { ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: shll $5, %eax ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_31: @@ -617,7 +617,7 @@ define i16 @test_mul_by_31(i16 %x) { ; X64-NEXT: movl %edi, %eax ; X64-NEXT: shll $5, %eax ; X64-NEXT: subl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 31 ret i16 %mul @@ -628,7 +628,7 @@ define i16 @test_mul_by_32(i16 %x) { ; X86: # BB#0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shll $5, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_by_32: @@ -648,16 +648,16 @@ define i16 @test_mul_spec(i16 %x) nounwind { ; X86-NEXT: leal 42(%eax,%eax,8), %ecx ; X86-NEXT: leal 2(%eax,%eax,4), %eax ; X86-NEXT: imull %ecx, %eax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: test_mul_spec: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 42(%rdi,%rdi,8), %ecx ; X64-NEXT: leal 2(%rdi,%rdi,4), %eax ; X64-NEXT: imull %ecx, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %mul = mul nsw i16 %x, 9 %add = add nsw i16 %mul, 42 diff --git a/test/CodeGen/X86/mul-constant-i32.ll b/test/CodeGen/X86/mul-constant-i32.ll index 38599f6fa19..228dd5e5f37 100644 --- a/test/CodeGen/X86/mul-constant-i32.ll +++ b/test/CodeGen/X86/mul-constant-i32.ll @@ -61,13 +61,13 @@ define i32 @test_mul_by_2(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_2: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_2: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -79,25 +79,25 @@ define i32 @test_mul_by_2(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_2: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_2: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_2: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_2: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (%rdi,%rdi), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 2 @@ -112,13 +112,13 @@ define i32 @test_mul_by_3(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_3: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_3: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -129,25 +129,25 @@ define i32 @test_mul_by_3(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_3: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_3: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_3: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_3: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 3 @@ -163,13 +163,13 @@ define i32 @test_mul_by_4(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_4: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_4: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -181,25 +181,25 @@ define i32 @test_mul_by_4(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_4: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_4: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_4: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_4: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (,%rdi,4), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 4 @@ -214,13 +214,13 @@ define i32 @test_mul_by_5(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_5: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_5: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -231,25 +231,25 @@ define i32 @test_mul_by_5(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_5: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_5: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_5: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_5: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 5 @@ -266,14 +266,14 @@ define i32 @test_mul_by_6(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_6: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_6: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -295,7 +295,7 @@ define i32 @test_mul_by_6(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_6: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -318,14 +318,14 @@ define i32 @test_mul_by_7(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_7: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_7: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -347,7 +347,7 @@ define i32 @test_mul_by_7(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_7: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] ; X64-SLM-NEXT: subl %edi, %eax # sched: [1:0.50] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -369,13 +369,13 @@ define i32 @test_mul_by_8(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_8: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_8: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -387,25 +387,25 @@ define i32 @test_mul_by_8(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_8: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_8: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_8: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_8: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (,%rdi,8), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 8 @@ -420,13 +420,13 @@ define i32 @test_mul_by_9(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_9: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_9: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] ; @@ -437,25 +437,25 @@ define i32 @test_mul_by_9(i32 %x) { ; ; HSW-NOOPT-LABEL: test_mul_by_9: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; HSW-NOOPT-NEXT: retq # sched: [2:1.00] ; ; JAG-NOOPT-LABEL: test_mul_by_9: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: retq # sched: [4:1.00] ; ; X64-SLM-LABEL: test_mul_by_9: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] ; ; SLM-NOOPT-LABEL: test_mul_by_9: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: retq # sched: [4:1.00] %mul = mul nsw i32 %x, 9 @@ -472,14 +472,14 @@ define i32 @test_mul_by_10(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_10: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_10: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -501,7 +501,7 @@ define i32 @test_mul_by_10(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_10: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -524,14 +524,14 @@ define i32 @test_mul_by_11(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_11: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_11: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -574,14 +574,14 @@ define i32 @test_mul_by_12(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_12: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: shll $2, %edi # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_12: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: shll $2, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -603,7 +603,7 @@ define i32 @test_mul_by_12(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_12: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: shll $2, %edi # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -626,14 +626,14 @@ define i32 @test_mul_by_13(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_13: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_13: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -677,7 +677,7 @@ define i32 @test_mul_by_14(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_14: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] @@ -685,7 +685,7 @@ define i32 @test_mul_by_14(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_14: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] @@ -729,14 +729,14 @@ define i32 @test_mul_by_15(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_15: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_15: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -758,7 +758,7 @@ define i32 @test_mul_by_15(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_15: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rax,%rax,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -834,7 +834,7 @@ define i32 @test_mul_by_17(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_17: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: movl %edi, %eax # sched: [1:0.25] ; X64-HSW-NEXT: shll $4, %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rdi), %eax # sched: [1:0.50] @@ -842,7 +842,7 @@ define i32 @test_mul_by_17(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_17: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: movl %edi, %eax # sched: [1:0.17] ; X64-JAG-NEXT: shll $4, %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rdi), %eax # sched: [1:0.50] @@ -865,7 +865,7 @@ define i32 @test_mul_by_17(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_17: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: movl %edi, %eax # sched: [1:0.50] ; X64-SLM-NEXT: shll $4, %eax # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rax,%rdi), %eax # sched: [1:1.00] @@ -889,14 +889,14 @@ define i32 @test_mul_by_18(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_18: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: addl %edi, %edi # sched: [1:0.25] ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_18: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -918,7 +918,7 @@ define i32 @test_mul_by_18(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_18: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: addl %edi, %edi # sched: [1:0.50] ; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -942,7 +942,7 @@ define i32 @test_mul_by_19(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_19: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: shll $2, %eax # sched: [1:0.50] ; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] @@ -950,7 +950,7 @@ define i32 @test_mul_by_19(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_19: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: shll $2, %eax # sched: [1:0.50] ; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] @@ -994,14 +994,14 @@ define i32 @test_mul_by_20(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_20: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: shll $2, %edi # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_20: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: shll $2, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -1023,7 +1023,7 @@ define i32 @test_mul_by_20(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_20: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: shll $2, %edi # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -1046,14 +1046,14 @@ define i32 @test_mul_by_21(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_21: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_21: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -1097,7 +1097,7 @@ define i32 @test_mul_by_22(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_22: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] @@ -1105,7 +1105,7 @@ define i32 @test_mul_by_22(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_22: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rax,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] @@ -1150,7 +1150,7 @@ define i32 @test_mul_by_23(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_23: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: shll $3, %eax # sched: [1:0.50] ; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] @@ -1158,7 +1158,7 @@ define i32 @test_mul_by_23(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_23: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: shll $3, %eax # sched: [1:0.50] ; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] @@ -1202,14 +1202,14 @@ define i32 @test_mul_by_24(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_24: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: shll $3, %edi # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_24: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: shll $3, %edi # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -1231,7 +1231,7 @@ define i32 @test_mul_by_24(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_24: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: shll $3, %edi # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rdi,%rdi,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -1254,14 +1254,14 @@ define i32 @test_mul_by_25(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_25: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_25: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -1283,7 +1283,7 @@ define i32 @test_mul_by_25(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_25: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rax,%rax,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -1307,7 +1307,7 @@ define i32 @test_mul_by_26(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_26: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: subl %edi, %eax # sched: [1:0.25] @@ -1315,7 +1315,7 @@ define i32 @test_mul_by_26(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_26: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: subl %edi, %eax # sched: [1:0.50] @@ -1359,14 +1359,14 @@ define i32 @test_mul_by_27(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_27: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: retq # sched: [2:1.00] ; ; X64-JAG-LABEL: test_mul_by_27: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: retq # sched: [4:1.00] @@ -1388,7 +1388,7 @@ define i32 @test_mul_by_27(i32 %x) { ; ; X64-SLM-LABEL: test_mul_by_27: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:1.00] ; X64-SLM-NEXT: leal (%rax,%rax,2), %eax # sched: [1:1.00] ; X64-SLM-NEXT: retq # sched: [4:1.00] @@ -1412,7 +1412,7 @@ define i32 @test_mul_by_28(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_28: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] @@ -1420,7 +1420,7 @@ define i32 @test_mul_by_28(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_28: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] @@ -1466,7 +1466,7 @@ define i32 @test_mul_by_29(i32 %x) { ; ; X64-HSW-LABEL: test_mul_by_29: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-HSW-NEXT: addl %edi, %eax # sched: [1:0.25] @@ -1475,7 +1475,7 @@ define i32 @test_mul_by_29(i32 %x) { ; ; X64-JAG-LABEL: test_mul_by_29: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal (%rdi,%rdi,8), %eax # sched: [1:0.50] ; X64-JAG-NEXT: leal (%rax,%rax,2), %eax # sched: [1:0.50] ; X64-JAG-NEXT: addl %edi, %eax # sched: [1:0.50] @@ -1681,7 +1681,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; X64-HSW-LABEL: test_mul_spec: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: leal (%rdi,%rdi,8), %ecx # sched: [1:0.50] ; X64-HSW-NEXT: addl $42, %ecx # sched: [1:0.25] ; X64-HSW-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] @@ -1691,7 +1691,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; X64-JAG-LABEL: test_mul_spec: ; X64-JAG: # BB#0: -; X64-JAG-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-JAG-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-JAG-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:0.50] ; X64-JAG-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:0.50] ; X64-JAG-NEXT: imull %ecx, %eax # sched: [3:1.00] @@ -1707,7 +1707,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; HSW-NOOPT-LABEL: test_mul_spec: ; HSW-NOOPT: # BB#0: -; HSW-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; HSW-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; HSW-NOOPT-NEXT: leal (%rdi,%rdi,8), %ecx # sched: [1:0.50] ; HSW-NOOPT-NEXT: addl $42, %ecx # sched: [1:0.25] ; HSW-NOOPT-NEXT: leal (%rdi,%rdi,4), %eax # sched: [1:0.50] @@ -1717,7 +1717,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; JAG-NOOPT-LABEL: test_mul_spec: ; JAG-NOOPT: # BB#0: -; JAG-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; JAG-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; JAG-NOOPT-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:0.50] ; JAG-NOOPT-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:0.50] ; JAG-NOOPT-NEXT: imull %ecx, %eax # sched: [3:1.00] @@ -1725,7 +1725,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; X64-SLM-LABEL: test_mul_spec: ; X64-SLM: # BB#0: -; X64-SLM-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SLM-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SLM-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:1.00] ; X64-SLM-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:1.00] ; X64-SLM-NEXT: imull %ecx, %eax # sched: [3:1.00] @@ -1733,7 +1733,7 @@ define i32 @test_mul_spec(i32 %x) nounwind { ; ; SLM-NOOPT-LABEL: test_mul_spec: ; SLM-NOOPT: # BB#0: -; SLM-NOOPT-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SLM-NOOPT-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SLM-NOOPT-NEXT: leal 42(%rdi,%rdi,8), %ecx # sched: [1:1.00] ; SLM-NOOPT-NEXT: leal 2(%rdi,%rdi,4), %eax # sched: [1:1.00] ; SLM-NOOPT-NEXT: imull %ecx, %eax # sched: [3:1.00] diff --git a/test/CodeGen/X86/mul-constant-result.ll b/test/CodeGen/X86/mul-constant-result.ll index 011b63ce726..6e74c1d4e9e 100644 --- a/test/CodeGen/X86/mul-constant-result.ll +++ b/test/CodeGen/X86/mul-constant-result.ll @@ -188,7 +188,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; ; X64-HSW-LABEL: mult: ; X64-HSW: # BB#0: -; X64-HSW-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-HSW-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-HSW-NEXT: cmpl $1, %esi ; X64-HSW-NEXT: movl $1, %ecx ; X64-HSW-NEXT: movl %esi, %eax @@ -202,60 +202,60 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: jmpq *.LJTI0_0(,%rdi,8) ; X64-HSW-NEXT: .LBB0_2: ; X64-HSW-NEXT: addl %eax, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_36: ; X64-HSW-NEXT: xorl %eax, %eax ; X64-HSW-NEXT: .LBB0_37: -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_3: ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_4: ; X64-HSW-NEXT: shll $2, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_5: ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_6: ; X64-HSW-NEXT: addl %eax, %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_7: ; X64-HSW-NEXT: leal (,%rax,8), %ecx ; X64-HSW-NEXT: jmp .LBB0_8 ; X64-HSW-NEXT: .LBB0_9: ; X64-HSW-NEXT: shll $3, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_10: ; X64-HSW-NEXT: leal (%rax,%rax,8), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_11: ; X64-HSW-NEXT: addl %eax, %eax ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_12: ; X64-HSW-NEXT: leal (%rax,%rax,4), %ecx ; X64-HSW-NEXT: leal (%rax,%rcx,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_13: ; X64-HSW-NEXT: shll $2, %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_14: ; X64-HSW-NEXT: leal (%rax,%rax,2), %ecx ; X64-HSW-NEXT: leal (%rax,%rcx,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_15: ; X64-HSW-NEXT: leal (%rax,%rax,2), %ecx @@ -263,11 +263,11 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_18: ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_19: ; X64-HSW-NEXT: shll $4, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_20: ; X64-HSW-NEXT: movl %eax, %ecx @@ -276,7 +276,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_21: ; X64-HSW-NEXT: addl %eax, %eax ; X64-HSW-NEXT: leal (%rax,%rax,8), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_22: ; X64-HSW-NEXT: leal (%rax,%rax,4), %ecx @@ -285,12 +285,12 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_23: ; X64-HSW-NEXT: shll $2, %eax ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_24: ; X64-HSW-NEXT: leal (%rax,%rax,4), %ecx ; X64-HSW-NEXT: leal (%rax,%rcx,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_25: ; X64-HSW-NEXT: leal (%rax,%rax,4), %ecx @@ -304,12 +304,12 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_27: ; X64-HSW-NEXT: shll $3, %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_28: ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_29: ; X64-HSW-NEXT: leal (%rax,%rax,8), %ecx @@ -318,7 +318,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_30: ; X64-HSW-NEXT: leal (%rax,%rax,8), %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_31: ; X64-HSW-NEXT: leal (%rax,%rax,8), %ecx @@ -331,7 +331,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_17: ; X64-HSW-NEXT: addl %eax, %ecx ; X64-HSW-NEXT: movl %ecx, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_33: ; X64-HSW-NEXT: movl %eax, %ecx @@ -344,11 +344,11 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: .LBB0_8: ; X64-HSW-NEXT: subl %eax, %ecx ; X64-HSW-NEXT: movl %ecx, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq ; X64-HSW-NEXT: .LBB0_35: ; X64-HSW-NEXT: shll $5, %eax -; X64-HSW-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; X64-HSW-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; X64-HSW-NEXT: retq %3 = icmp eq i32 %1, 0 %4 = icmp sgt i32 %1, 1 diff --git a/test/CodeGen/X86/negate-i1.ll b/test/CodeGen/X86/negate-i1.ll index 3736f4df5ec..0050fdc773f 100644 --- a/test/CodeGen/X86/negate-i1.ll +++ b/test/CodeGen/X86/negate-i1.ll @@ -49,7 +49,7 @@ define i16 @select_i16_neg1_or_0(i1 %a) { ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: andl $1, %eax ; X32-NEXT: negl %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl %b = sext i1 %a to i16 ret i16 %b @@ -66,7 +66,7 @@ define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) { ; X32: # BB#0: ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: negl %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl %b = sext i1 %a to i16 ret i16 %b @@ -109,7 +109,7 @@ define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { define i64 @select_i64_neg1_or_0(i1 %a) { ; X64-LABEL: select_i64_neg1_or_0: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: andl $1, %edi ; X64-NEXT: negq %rdi ; X64-NEXT: movq %rdi, %rax diff --git a/test/CodeGen/X86/norex-subreg.ll b/test/CodeGen/X86/norex-subreg.ll index dd47af9ae9a..9efafe42718 100644 --- a/test/CodeGen/X86/norex-subreg.ll +++ b/test/CodeGen/X86/norex-subreg.ll @@ -4,10 +4,10 @@ target triple = "x86_64-apple-macosx10.7" ; This test case extracts a sub_8bit_hi sub-register: ; -; %R8B<def> = COPY %BH, %EBX<imp-use,kill> -; %ESI<def> = MOVZX32_NOREXrr8 %R8B<kill> +; %r8b<def> = COPY %bh, %ebx<imp-use,kill> +; %esi<def> = MOVZX32_NOREXrr8 %r8b<kill> ; -; The register allocation above is invalid, %BH can only be encoded without an +; The register allocation above is invalid, %bh can only be encoded without an ; REX prefix, so the destination register must be GR8_NOREX. The code above ; triggers an assertion in copyPhysReg. ; @@ -42,7 +42,7 @@ entry: ; This test case extracts a sub_8bit_hi sub-register: ; ; %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8:%vreg2 GR64_ABCD:%vreg1 -; TEST8ri %vreg2, 1, %EFLAGS<imp-def>; GR8:%vreg2 +; TEST8ri %vreg2, 1, %eflags<imp-def>; GR8:%vreg2 ; ; %vreg2 must be constrained to GR8_NOREX, or the COPY could become impossible. ; diff --git a/test/CodeGen/X86/oddshuffles.ll b/test/CodeGen/X86/oddshuffles.ll index 02a399b4898..5f9979dbcb9 100644 --- a/test/CodeGen/X86/oddshuffles.ll +++ b/test/CodeGen/X86/oddshuffles.ll @@ -30,7 +30,7 @@ define void @v3i64(<2 x i64> %a, <2 x i64> %b, <3 x i64>* %p) nounwind { ; ; AVX2-LABEL: v3i64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,1,3] ; AVX2-NEXT: vpextrq $1, %xmm0, 16(%rdi) @@ -65,7 +65,7 @@ define void @v3f64(<2 x double> %a, <2 x double> %b, <3 x double>* %p) nounwind ; ; AVX2-LABEL: v3f64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 ; AVX2-NEXT: vpermpd {{.*#+}} ymm1 = ymm1[0,2,1,3] ; AVX2-NEXT: vmovhpd %xmm0, 16(%rdi) @@ -205,7 +205,7 @@ define void @v5i32(<4 x i32> %a, <4 x i32> %b, <5 x i32>* %p) nounwind { ; ; AVX2-LABEL: v5i32: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 ; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,5,1,6,3,u,u,u> ; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1 @@ -255,7 +255,7 @@ define void @v5f32(<4 x float> %a, <4 x float> %b, <5 x float>* %p) nounwind { ; ; AVX2-LABEL: v5f32: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1 ; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,5,1,6,3,u,u,u> ; AVX2-NEXT: vpermps %ymm1, %ymm2, %ymm1 @@ -421,7 +421,7 @@ define void @v7i32(<4 x i32> %a, <4 x i32> %b, <7 x i32>* %p) nounwind { ; ; AVX2-LABEL: v7i32: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vmovaps {{.*#+}} ymm2 = <0,6,3,6,1,7,4,u> ; AVX2-NEXT: vpermps %ymm0, %ymm2, %ymm0 @@ -1697,7 +1697,7 @@ define <2 x double> @wrongorder(<4 x double> %A, <8 x double>* %P) #0 { ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 ; AVX1-NEXT: vmovaps %ymm1, 32(%rdi) ; AVX1-NEXT: vmovaps %ymm1, (%rdi) -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -1716,7 +1716,7 @@ define <2 x double> @wrongorder(<4 x double> %A, <8 x double>* %P) #0 { ; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 ; XOP-NEXT: vmovaps %ymm1, 32(%rdi) ; XOP-NEXT: vmovaps %ymm1, (%rdi) -; XOP-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; XOP-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; XOP-NEXT: vzeroupper ; XOP-NEXT: retq %shuffle = shufflevector <4 x double> %A, <4 x double> %A, <8 x i32> zeroinitializer diff --git a/test/CodeGen/X86/or-lea.ll b/test/CodeGen/X86/or-lea.ll index e65056a91c4..709f29bf9e0 100644 --- a/test/CodeGen/X86/or-lea.ll +++ b/test/CodeGen/X86/or-lea.ll @@ -9,8 +9,8 @@ define i32 @or_shift1_and1(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift1_and1: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %esi ; CHECK-NEXT: leal (%rsi,%rdi,2), %eax ; CHECK-NEXT: retq @@ -24,8 +24,8 @@ define i32 @or_shift1_and1(i32 %x, i32 %y) { define i32 @or_shift1_and1_swapped(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift1_and1_swapped: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %esi ; CHECK-NEXT: leal (%rsi,%rdi,2), %eax ; CHECK-NEXT: retq @@ -39,8 +39,8 @@ define i32 @or_shift1_and1_swapped(i32 %x, i32 %y) { define i32 @or_shift2_and1(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift2_and1: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %esi ; CHECK-NEXT: leal (%rsi,%rdi,4), %eax ; CHECK-NEXT: retq @@ -54,8 +54,8 @@ define i32 @or_shift2_and1(i32 %x, i32 %y) { define i32 @or_shift3_and1(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift3_and1: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %esi ; CHECK-NEXT: leal (%rsi,%rdi,8), %eax ; CHECK-NEXT: retq @@ -69,8 +69,8 @@ define i32 @or_shift3_and1(i32 %x, i32 %y) { define i32 @or_shift3_and7(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift3_and7: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $7, %esi ; CHECK-NEXT: leal (%rsi,%rdi,8), %eax ; CHECK-NEXT: retq @@ -86,8 +86,8 @@ define i32 @or_shift3_and7(i32 %x, i32 %y) { define i32 @or_shift4_and1(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift4_and1: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: shll $4, %edi ; CHECK-NEXT: andl $1, %esi ; CHECK-NEXT: leal (%rsi,%rdi), %eax @@ -104,7 +104,7 @@ define i32 @or_shift4_and1(i32 %x, i32 %y) { define i32 @or_shift3_and8(i32 %x, i32 %y) { ; CHECK-LABEL: or_shift3_and8: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal (,%rdi,8), %eax ; CHECK-NEXT: andl $8, %esi ; CHECK-NEXT: orl %esi, %eax diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll index 74e3d1291c0..720ed69ba26 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll @@ -2,9 +2,9 @@ ; rdar://5571034 ; This requires physreg joining, %vreg13 is live everywhere: -; 304L %CL<def> = COPY %vreg13:sub_8bit; GR32_ABCD:%vreg13 +; 304L %cl<def> = COPY %vreg13:sub_8bit; GR32_ABCD:%vreg13 ; 320L %vreg15<def> = COPY %vreg19; GR32:%vreg15 GR32_NOSP:%vreg19 -; 336L %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15 +; 336L %vreg15<def> = SAR32rCL %vreg15, %eflags<imp-def,dead>, %cl<imp-use,kill>; GR32:%vreg15 define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp { ; CHECK-LABEL: foo: diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll index 2c170e2e711..249e20ce502 100644 --- a/test/CodeGen/X86/pmul.ll +++ b/test/CodeGen/X86/pmul.ll @@ -63,7 +63,7 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind { ; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0 ; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq entry: @@ -206,7 +206,7 @@ define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind { ; AVX512BW-NEXT: vpmovsxbw %xmm0, %ymm0 ; AVX512BW-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq entry: diff --git a/test/CodeGen/X86/popcnt-schedule.ll b/test/CodeGen/X86/popcnt-schedule.ll index 9b35da059f2..36b8e15eab6 100644 --- a/test/CodeGen/X86/popcnt-schedule.ll +++ b/test/CodeGen/X86/popcnt-schedule.ll @@ -17,7 +17,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; GENERIC-NEXT: popcntw (%rsi), %cx # sched: [9:1.00] ; GENERIC-NEXT: popcntw %di, %ax # sched: [3:1.00] ; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; SLM-LABEL: test_ctpop_i16: @@ -25,7 +25,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; SLM-NEXT: popcntw (%rsi), %cx # sched: [6:1.00] ; SLM-NEXT: popcntw %di, %ax # sched: [3:1.00] ; SLM-NEXT: orl %ecx, %eax # sched: [1:0.50] -; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SLM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_ctpop_i16: @@ -33,7 +33,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; SANDY-NEXT: popcntw (%rsi), %cx # sched: [9:1.00] ; SANDY-NEXT: popcntw %di, %ax # sched: [3:1.00] ; SANDY-NEXT: orl %ecx, %eax # sched: [1:0.33] -; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SANDY-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_ctpop_i16: @@ -41,7 +41,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; HASWELL-NEXT: popcntw (%rsi), %cx # sched: [3:1.00] ; HASWELL-NEXT: popcntw %di, %ax # sched: [3:1.00] ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_ctpop_i16: @@ -49,7 +49,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; BROADWELL-NEXT: popcntw (%rsi), %cx # sched: [8:1.00] ; BROADWELL-NEXT: popcntw %di, %ax # sched: [3:1.00] ; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_ctpop_i16: @@ -57,7 +57,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; SKYLAKE-NEXT: popcntw (%rsi), %cx # sched: [8:1.00] ; SKYLAKE-NEXT: popcntw %di, %ax # sched: [3:1.00] ; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_ctpop_i16: @@ -65,7 +65,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; BTVER2-NEXT: popcntw (%rsi), %cx # sched: [8:1.00] ; BTVER2-NEXT: popcntw %di, %ax # sched: [3:1.00] ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_ctpop_i16: @@ -73,7 +73,7 @@ define i16 @test_ctpop_i16(i16 zeroext %a0, i16 *%a1) { ; ZNVER1-NEXT: popcntw (%rsi), %cx # sched: [10:1.00] ; ZNVER1-NEXT: popcntw %di, %ax # sched: [3:1.00] ; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = load i16, i16 *%a1 %2 = tail call i16 @llvm.ctpop.i16( i16 %1 ) diff --git a/test/CodeGen/X86/popcnt.ll b/test/CodeGen/X86/popcnt.ll index b5d4ebba053..a4ed30e7bd9 100644 --- a/test/CodeGen/X86/popcnt.ll +++ b/test/CodeGen/X86/popcnt.ll @@ -44,14 +44,14 @@ define i8 @cnt8(i8 %x) nounwind readnone { ; X32-POPCNT: # BB#0: ; X32-POPCNT-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-POPCNT-NEXT: popcntw %ax, %ax -; X32-POPCNT-NEXT: # kill: %AL<def> %AL<kill> %AX<kill> +; X32-POPCNT-NEXT: # kill: %al<def> %al<kill> %ax<kill> ; X32-POPCNT-NEXT: retl ; ; X64-POPCNT-LABEL: cnt8: ; X64-POPCNT: # BB#0: ; X64-POPCNT-NEXT: movzbl %dil, %eax ; X64-POPCNT-NEXT: popcntw %ax, %ax -; X64-POPCNT-NEXT: # kill: %AL<def> %AL<kill> %AX<kill> +; X64-POPCNT-NEXT: # kill: %al<def> %al<kill> %ax<kill> ; X64-POPCNT-NEXT: retq %cnt = tail call i8 @llvm.ctpop.i8(i8 %x) ret i8 %cnt @@ -79,7 +79,7 @@ define i16 @cnt16(i16 %x) nounwind readnone { ; X32-NEXT: shll $8, %eax ; X32-NEXT: addl %ecx, %eax ; X32-NEXT: movzbl %ah, %eax -; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: cnt16: @@ -102,7 +102,7 @@ define i16 @cnt16(i16 %x) nounwind readnone { ; X64-NEXT: shll $8, %ecx ; X64-NEXT: addl %eax, %ecx ; X64-NEXT: movzbl %ch, %eax # NOREX -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32-POPCNT-LABEL: cnt16: diff --git a/test/CodeGen/X86/pr22970.ll b/test/CodeGen/X86/pr22970.ll index 38c063355f6..8de9c9e22c7 100644 --- a/test/CodeGen/X86/pr22970.ll +++ b/test/CodeGen/X86/pr22970.ll @@ -13,7 +13,7 @@ define i32 @PR22970_i32(i32* nocapture readonly, i32) { ; ; X64-LABEL: PR22970_i32: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: andl $4095, %esi # imm = 0xFFF ; X64-NEXT: movl 32(%rdi,%rsi,4), %eax ; X64-NEXT: retq diff --git a/test/CodeGen/X86/pr26870.ll b/test/CodeGen/X86/pr26870.ll index 2731ed2d012..1e8470bfba3 100644 --- a/test/CodeGen/X86/pr26870.ll +++ b/test/CodeGen/X86/pr26870.ll @@ -2,11 +2,11 @@ define x86_thiscallcc i32* @fn4(i32* %this, i8* dereferenceable(1) %p1) { entry: - %DL = getelementptr inbounds i32, i32* %this, i32 0 - %call.i = tail call x86_thiscallcc i64 @fn1(i32* %DL) + %dl = getelementptr inbounds i32, i32* %this, i32 0 + %call.i = tail call x86_thiscallcc i64 @fn1(i32* %dl) %getTypeAllocSize___trans_tmp_2.i = getelementptr inbounds i32, i32* %this, i32 0 %0 = load i32, i32* %getTypeAllocSize___trans_tmp_2.i, align 4 - %call.i8 = tail call x86_thiscallcc i64 @fn1(i32* %DL) + %call.i8 = tail call x86_thiscallcc i64 @fn1(i32* %dl) %1 = insertelement <2 x i64> undef, i64 %call.i, i32 0 %2 = insertelement <2 x i64> %1, i64 %call.i8, i32 1 %3 = add nsw <2 x i64> %2, <i64 7, i64 7> diff --git a/test/CodeGen/X86/pr28173.ll b/test/CodeGen/X86/pr28173.ll index 3279982e464..0d2edcde4b7 100644 --- a/test/CodeGen/X86/pr28173.ll +++ b/test/CodeGen/X86/pr28173.ll @@ -27,7 +27,7 @@ define i16 @foo16(i1 zeroext %i) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: orl $65534, %eax # imm = 0xFFFE -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq br label %bb @@ -45,7 +45,7 @@ define i16 @foo16_1(i1 zeroext %i, i32 %j) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: orl $2, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq br label %bb diff --git a/test/CodeGen/X86/pr28560.ll b/test/CodeGen/X86/pr28560.ll index d0061f670cf..bb95a59db82 100644 --- a/test/CodeGen/X86/pr28560.ll +++ b/test/CodeGen/X86/pr28560.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=i686-pc-linux -print-after=postrapseudos < %s 2>&1 | FileCheck %s -; CHECK: MOV8rr %{{[A-D]}}L, %E[[R:[A-D]]]X<imp-use,kill>, %E[[R]]X<imp-def> +; CHECK: MOV8rr %{{[a-d]}}l, %e[[R:[a-d]]]x<imp-use,kill>, %e[[R]]x<imp-def> define i32 @foo(i32 %i, i32 %k, i8* %p) { %f = icmp ne i32 %i, %k %s = zext i1 %f to i8 diff --git a/test/CodeGen/X86/pr29061.ll b/test/CodeGen/X86/pr29061.ll index 0cbe75f9ad5..918dfd4af01 100644 --- a/test/CodeGen/X86/pr29061.ll +++ b/test/CodeGen/X86/pr29061.ll @@ -11,7 +11,7 @@ define void @t1(i8 signext %c) { ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_offset %edi, -8 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %edi -; CHECK-NEXT: # kill: %DI<def> %DI<kill> %EDI<kill> +; CHECK-NEXT: # kill: %di<def> %di<kill> %edi<kill> ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: popl %edi @@ -28,7 +28,7 @@ define void @t2(i8 signext %c) { ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %esi -; CHECK-NEXT: # kill: %SI<def> %SI<kill> %ESI<kill> +; CHECK-NEXT: # kill: %si<def> %si<kill> %esi<kill> ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: popl %esi diff --git a/test/CodeGen/X86/pr30430.ll b/test/CodeGen/X86/pr30430.ll index 0254c0940b8..eb14503ec1e 100644 --- a/test/CodeGen/X86/pr30430.ll +++ b/test/CodeGen/X86/pr30430.ll @@ -73,7 +73,7 @@ define <16 x float> @makefloat(float %f1, float %f2, float %f3, float %f4, float ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] -; CHECK-NEXT: # implicit-def: %YMM2 +; CHECK-NEXT: # implicit-def: %ymm2 ; CHECK-NEXT: vmovaps %xmm1, %xmm2 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm2 ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -90,10 +90,10 @@ define <16 x float> @makefloat(float %f1, float %f2, float %f3, float %f4, float ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0] -; CHECK-NEXT: # implicit-def: %YMM3 +; CHECK-NEXT: # implicit-def: %ymm3 ; CHECK-NEXT: vmovaps %xmm1, %xmm3 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm3 -; CHECK-NEXT: # implicit-def: %ZMM24 +; CHECK-NEXT: # implicit-def: %zmm24 ; CHECK-NEXT: vmovaps %zmm3, %zmm24 ; CHECK-NEXT: vinsertf64x4 $1, %ymm2, %zmm24, %zmm24 ; CHECK-NEXT: vmovaps %zmm24, {{[0-9]+}}(%rsp) diff --git a/test/CodeGen/X86/pr32282.ll b/test/CodeGen/X86/pr32282.ll index d6e6f6eb107..ca4767ba73c 100644 --- a/test/CodeGen/X86/pr32282.ll +++ b/test/CodeGen/X86/pr32282.ll @@ -64,7 +64,7 @@ define void @foo() { ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: divl %ecx -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %rax<def> ; X64-NEXT: .LBB0_3: ; X64-NEXT: testq %rax, %rax ; X64-NEXT: setne -{{[0-9]+}}(%rsp) diff --git a/test/CodeGen/X86/pr32284.ll b/test/CodeGen/X86/pr32284.ll index 3caa7fde40f..99536733b41 100644 --- a/test/CodeGen/X86/pr32284.ll +++ b/test/CodeGen/X86/pr32284.ll @@ -308,7 +308,7 @@ entry: define void @f2() { ; X86-O0-LABEL: f2: ; X86-O0: # BB#0: # %entry -; X86-O0-NEXT: # implicit-def: %RAX +; X86-O0-NEXT: # implicit-def: %rax ; X86-O0-NEXT: movzbl var_7, %ecx ; X86-O0-NEXT: cmpb $0, var_7 ; X86-O0-NEXT: setne %dl @@ -361,7 +361,7 @@ define void @f2() { ; 686-O0-NEXT: .cfi_def_cfa_offset 14 ; 686-O0-NEXT: .cfi_offset %esi, -12 ; 686-O0-NEXT: .cfi_offset %edi, -8 -; 686-O0-NEXT: # implicit-def: %EAX +; 686-O0-NEXT: # implicit-def: %eax ; 686-O0-NEXT: movzbl var_7, %ecx ; 686-O0-NEXT: cmpb $0, var_7 ; 686-O0-NEXT: setne %dl diff --git a/test/CodeGen/X86/pr32329.ll b/test/CodeGen/X86/pr32329.ll index f6bdade24c6..4fea702e063 100644 --- a/test/CodeGen/X86/pr32329.ll +++ b/test/CodeGen/X86/pr32329.ll @@ -78,7 +78,7 @@ define void @foo() local_unnamed_addr { ; X64-NEXT: imull %esi, %ecx ; X64-NEXT: addl $-1437483407, %ecx # imm = 0xAA51BE71 ; X64-NEXT: movl $9, %edx -; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X64-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X64-NEXT: shlq %cl, %rdx ; X64-NEXT: movq %rdx, {{.*}}(%rip) ; X64-NEXT: cmpl %eax, %esi diff --git a/test/CodeGen/X86/pr32345.ll b/test/CodeGen/X86/pr32345.ll index c7625783907..038d5d639aa 100644 --- a/test/CodeGen/X86/pr32345.ll +++ b/test/CodeGen/X86/pr32345.ll @@ -10,7 +10,7 @@ define void @foo() { ; X640-LABEL: foo: ; X640: # BB#0: # %bb -; X640-NEXT: # implicit-def: %RAX +; X640-NEXT: # implicit-def: %rax ; X640-NEXT: movzwl var_22, %ecx ; X640-NEXT: movzwl var_27, %edx ; X640-NEXT: xorl %edx, %ecx @@ -27,8 +27,8 @@ define void @foo() { ; X640-NEXT: movzwl var_27, %ecx ; X640-NEXT: subl $16610, %ecx # imm = 0x40E2 ; X640-NEXT: movl %ecx, %ecx -; X640-NEXT: # kill: %RCX<def> %ECX<kill> -; X640-NEXT: # kill: %CL<def> %RCX<kill> +; X640-NEXT: # kill: %rcx<def> %ecx<kill> +; X640-NEXT: # kill: %cl<def> %rcx<kill> ; X640-NEXT: sarq %cl, %rsi ; X640-NEXT: movb %sil, %cl ; X640-NEXT: movb %cl, (%rax) @@ -49,12 +49,12 @@ define void @foo() { ; 6860-NEXT: .cfi_offset %esi, -20 ; 6860-NEXT: .cfi_offset %edi, -16 ; 6860-NEXT: .cfi_offset %ebx, -12 -; 6860-NEXT: # implicit-def: %EAX +; 6860-NEXT: # implicit-def: %eax ; 6860-NEXT: movw var_22, %cx ; 6860-NEXT: movzwl var_27, %edx ; 6860-NEXT: movw %dx, %si ; 6860-NEXT: xorw %si, %cx -; 6860-NEXT: # implicit-def: %EDI +; 6860-NEXT: # implicit-def: %edi ; 6860-NEXT: movw %cx, %di ; 6860-NEXT: xorl %edx, %edi ; 6860-NEXT: movw %di, %cx @@ -65,7 +65,7 @@ define void @foo() { ; 6860-NEXT: movzwl var_27, %edx ; 6860-NEXT: movw %dx, %si ; 6860-NEXT: xorw %si, %cx -; 6860-NEXT: # implicit-def: %EDI +; 6860-NEXT: # implicit-def: %edi ; 6860-NEXT: movw %cx, %di ; 6860-NEXT: xorl %edx, %edi ; 6860-NEXT: movw %di, %cx @@ -104,7 +104,7 @@ define void @foo() { ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; X64-NEXT: addl $-16610, %ecx # imm = 0xBF1E -; X64-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X64-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X64-NEXT: shrq %cl, %rax ; X64-NEXT: movb %al, (%rax) ; X64-NEXT: retq diff --git a/test/CodeGen/X86/pr32484.ll b/test/CodeGen/X86/pr32484.ll index 74857f8d006..093c9b01c55 100644 --- a/test/CodeGen/X86/pr32484.ll +++ b/test/CodeGen/X86/pr32484.ll @@ -4,10 +4,10 @@ define void @foo() { ; CHECK-LABEL: foo: ; CHECK: # BB#0: -; CHECK-NEXT: # implicit-def: %RAX +; CHECK-NEXT: # implicit-def: %rax ; CHECK-NEXT: jmpq *%rax ; CHECK-NEXT: .LBB0_1: -; CHECK-NEXT: # implicit-def: %RAX +; CHECK-NEXT: # implicit-def: %rax ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 ; CHECK-NEXT: movdqu %xmm1, (%rax) diff --git a/test/CodeGen/X86/pr34653.ll b/test/CodeGen/X86/pr34653.ll index 4b16ffd33d5..ef59282a40c 100644 --- a/test/CodeGen/X86/pr34653.ll +++ b/test/CodeGen/X86/pr34653.ll @@ -64,7 +64,7 @@ define void @pr34653() { ; CHECK-NEXT: vpermilpd {{.*#+}} xmm5 = xmm5[1,0] ; CHECK-NEXT: vpermilpd {{.*#+}} xmm11 = xmm11[1,0] ; CHECK-NEXT: vpermilpd {{.*#+}} xmm13 = xmm13[1,0] -; CHECK-NEXT: # kill: %YMM10<def> %YMM10<kill> %ZMM10<kill> +; CHECK-NEXT: # kill: %ymm10<def> %ymm10<kill> %zmm10<kill> ; CHECK-NEXT: vextractf128 $1, %ymm10, %xmm10 ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps %xmm10, %xmm0 @@ -75,7 +75,7 @@ define void @pr34653() { ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] -; CHECK-NEXT: # kill: %YMM9<def> %YMM9<kill> %ZMM9<kill> +; CHECK-NEXT: # kill: %ymm9<def> %ymm9<kill> %zmm9<kill> ; CHECK-NEXT: vextractf128 $1, %ymm9, %xmm9 ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps %xmm9, %xmm0 @@ -88,7 +88,7 @@ define void @pr34653() { ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] -; CHECK-NEXT: # kill: %YMM8<def> %YMM8<kill> %ZMM8<kill> +; CHECK-NEXT: # kill: %ymm8<def> %ymm8<kill> %zmm8<kill> ; CHECK-NEXT: vextractf128 $1, %ymm8, %xmm8 ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps %xmm8, %xmm0 @@ -101,7 +101,7 @@ define void @pr34653() { ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0] -; CHECK-NEXT: # kill: %YMM7<def> %YMM7<kill> %ZMM7<kill> +; CHECK-NEXT: # kill: %ymm7<def> %ymm7<kill> %zmm7<kill> ; CHECK-NEXT: vextractf128 $1, %ymm7, %xmm7 ; CHECK-NEXT: vmovsd %xmm0, {{[0-9]+}}(%rsp) # 8-byte Spill ; CHECK-NEXT: vmovaps %xmm7, %xmm0 diff --git a/test/CodeGen/X86/prolog-push-seq.ll b/test/CodeGen/X86/prolog-push-seq.ll index f23791aef92..99095104d0f 100644 --- a/test/CodeGen/X86/prolog-push-seq.ll +++ b/test/CodeGen/X86/prolog-push-seq.ll @@ -16,4 +16,4 @@ define fastcc void @foo(i32 %a, i32 %b) #0 { ret void } -attributes #0 = { nounwind optsize "no-frame-pointer-elim-non-leaf"}
\ No newline at end of file +attributes #0 = { nounwind optsize "no-frame-pointer-elim-non-leaf"} diff --git a/test/CodeGen/X86/promote-vec3.ll b/test/CodeGen/X86/promote-vec3.ll index 42aeeb14739..85b610cce3f 100644 --- a/test/CodeGen/X86/promote-vec3.ll +++ b/test/CodeGen/X86/promote-vec3.ll @@ -19,9 +19,9 @@ define <3 x i16> @zext_i8(<3 x i8>) { ; SSE3-NEXT: pextrw $2, %xmm0, %ecx ; SSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE3-NEXT: movd %xmm0, %eax -; SSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; SSE3-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; SSE3-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; SSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; SSE3-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; SSE3-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; SSE3-NEXT: retl ; ; SSE41-LABEL: zext_i8: @@ -33,9 +33,9 @@ define <3 x i16> @zext_i8(<3 x i8>) { ; SSE41-NEXT: movd %xmm0, %eax ; SSE41-NEXT: pextrw $2, %xmm0, %edx ; SSE41-NEXT: pextrw $4, %xmm0, %ecx -; SSE41-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; SSE41-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; SSE41-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; SSE41-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; SSE41-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; SSE41-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; SSE41-NEXT: retl ; ; AVX-32-LABEL: zext_i8: @@ -47,9 +47,9 @@ define <3 x i16> @zext_i8(<3 x i8>) { ; AVX-32-NEXT: vmovd %xmm0, %eax ; AVX-32-NEXT: vpextrw $2, %xmm0, %edx ; AVX-32-NEXT: vpextrw $4, %xmm0, %ecx -; AVX-32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; AVX-32-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; AVX-32-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; AVX-32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; AVX-32-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; AVX-32-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; AVX-32-NEXT: retl ; ; AVX-64-LABEL: zext_i8: @@ -61,9 +61,9 @@ define <3 x i16> @zext_i8(<3 x i8>) { ; AVX-64-NEXT: vmovd %xmm0, %eax ; AVX-64-NEXT: vpextrw $2, %xmm0, %edx ; AVX-64-NEXT: vpextrw $4, %xmm0, %ecx -; AVX-64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; AVX-64-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; AVX-64-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; AVX-64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; AVX-64-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; AVX-64-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; AVX-64-NEXT: retq %2 = zext <3 x i8> %0 to <3 x i16> ret <3 x i16> %2 @@ -85,9 +85,9 @@ define <3 x i16> @sext_i8(<3 x i8>) { ; SSE3-NEXT: movd %xmm0, %eax ; SSE3-NEXT: pextrw $2, %xmm0, %edx ; SSE3-NEXT: pextrw $4, %xmm0, %ecx -; SSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; SSE3-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; SSE3-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; SSE3-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; SSE3-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; SSE3-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; SSE3-NEXT: retl ; ; SSE41-LABEL: sext_i8: @@ -100,9 +100,9 @@ define <3 x i16> @sext_i8(<3 x i8>) { ; SSE41-NEXT: movd %xmm0, %eax ; SSE41-NEXT: pextrw $2, %xmm0, %edx ; SSE41-NEXT: pextrw $4, %xmm0, %ecx -; SSE41-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; SSE41-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; SSE41-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; SSE41-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; SSE41-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; SSE41-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; SSE41-NEXT: retl ; ; AVX-32-LABEL: sext_i8: @@ -115,9 +115,9 @@ define <3 x i16> @sext_i8(<3 x i8>) { ; AVX-32-NEXT: vmovd %xmm0, %eax ; AVX-32-NEXT: vpextrw $2, %xmm0, %edx ; AVX-32-NEXT: vpextrw $4, %xmm0, %ecx -; AVX-32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; AVX-32-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; AVX-32-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; AVX-32-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; AVX-32-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; AVX-32-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; AVX-32-NEXT: retl ; ; AVX-64-LABEL: sext_i8: @@ -130,9 +130,9 @@ define <3 x i16> @sext_i8(<3 x i8>) { ; AVX-64-NEXT: vmovd %xmm0, %eax ; AVX-64-NEXT: vpextrw $2, %xmm0, %edx ; AVX-64-NEXT: vpextrw $4, %xmm0, %ecx -; AVX-64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> -; AVX-64-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill> -; AVX-64-NEXT: # kill: %CX<def> %CX<kill> %ECX<kill> +; AVX-64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> +; AVX-64-NEXT: # kill: %dx<def> %dx<kill> %edx<kill> +; AVX-64-NEXT: # kill: %cx<def> %cx<kill> %ecx<kill> ; AVX-64-NEXT: retq %2 = sext <3 x i8> %0 to <3 x i16> ret <3 x i16> %2 diff --git a/test/CodeGen/X86/psubus.ll b/test/CodeGen/X86/psubus.ll index 6e38f06a0f8..899f17052cf 100644 --- a/test/CodeGen/X86/psubus.ll +++ b/test/CodeGen/X86/psubus.ll @@ -1925,7 +1925,7 @@ define <8 x i16> @psubus_8i64_max(<8 x i16> %x, <8 x i64> %y) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; diff --git a/test/CodeGen/X86/reduce-trunc-shl.ll b/test/CodeGen/X86/reduce-trunc-shl.ll index 0638e9e3f6c..9f01c9e38c9 100644 --- a/test/CodeGen/X86/reduce-trunc-shl.ll +++ b/test/CodeGen/X86/reduce-trunc-shl.ll @@ -43,7 +43,7 @@ define <8 x i16> @trunc_shl_v8i16_v8i32(<8 x i32> %a) { ; AVX2-NEXT: vpslld $17, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq %shl = shl <8 x i32> %a, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17> diff --git a/test/CodeGen/X86/remat-phys-dead.ll b/test/CodeGen/X86/remat-phys-dead.ll index 6cdcd28eacd..e057aadb907 100644 --- a/test/CodeGen/X86/remat-phys-dead.ll +++ b/test/CodeGen/X86/remat-phys-dead.ll @@ -4,12 +4,12 @@ ; We need to make sure that rematerialization into a physical register marks the ; super- or sub-register as dead after this rematerialization since only the ; original register is actually used later. Largely irrelevant for a trivial -; example like this, since EAX is never used again, but easy to test. +; example like this, since eax is never used again, but easy to test. define i8 @test_remat() { ret i8 0 ; CHECK: REGISTER COALESCING -; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def> +; CHECK: Remat: %eax<def,dead> = MOV32r0 %eflags<imp-def,dead>, %al<imp-def> } ; On the other hand, if it's already the correct width, we really shouldn't be @@ -18,6 +18,6 @@ define i8 @test_remat() { define i32 @test_remat32() { ret i32 0 ; CHECK: REGISTER COALESCING -; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead> +; CHECK: Remat: %eax<def> = MOV32r0 %eflags<imp-def,dead> } diff --git a/test/CodeGen/X86/sar_fold64.ll b/test/CodeGen/X86/sar_fold64.ll index 66ad8c3f40f..7bea518162a 100644 --- a/test/CodeGen/X86/sar_fold64.ll +++ b/test/CodeGen/X86/sar_fold64.ll @@ -6,7 +6,7 @@ define i32 @shl48sar47(i64 %a) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movswq %di, %rax ; CHECK-NEXT: addl %eax, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; CHECK-NEXT: retq %1 = shl i64 %a, 48 %2 = ashr exact i64 %1, 47 @@ -19,7 +19,7 @@ define i32 @shl48sar49(i64 %a) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movswq %di, %rax ; CHECK-NEXT: shrq %rax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; CHECK-NEXT: retq %1 = shl i64 %a, 48 %2 = ashr exact i64 %1, 49 @@ -32,7 +32,7 @@ define i32 @shl56sar55(i64 %a) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movsbq %dil, %rax ; CHECK-NEXT: addl %eax, %eax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; CHECK-NEXT: retq %1 = shl i64 %a, 56 %2 = ashr exact i64 %1, 55 @@ -45,7 +45,7 @@ define i32 @shl56sar57(i64 %a) #0 { ; CHECK: # BB#0: ; CHECK-NEXT: movsbq %dil, %rax ; CHECK-NEXT: shrq %rax -; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; CHECK-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; CHECK-NEXT: retq %1 = shl i64 %a, 56 %2 = ashr exact i64 %1, 57 diff --git a/test/CodeGen/X86/schedule-x86_64.ll b/test/CodeGen/X86/schedule-x86_64.ll index cdc06d72ca8..acc54c74927 100644 --- a/test/CodeGen/X86/schedule-x86_64.ll +++ b/test/CodeGen/X86/schedule-x86_64.ll @@ -23,7 +23,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; GENERIC-NEXT: bsfw (%rsi), %cx # sched: [8:1.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_bsf16: @@ -33,7 +33,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; ATOM-NEXT: bsfw (%rsi), %cx # sched: [16:8.00] ; ATOM-NEXT: #NO_APP ; ATOM-NEXT: orl %ecx, %eax # sched: [1:0.50] -; ATOM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ATOM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ATOM-NEXT: retq # sched: [79:39.50] ; ; SLM-LABEL: test_bsf16: @@ -43,7 +43,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; SLM-NEXT: bsfw (%rsi), %cx # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: orl %ecx, %eax # sched: [1:0.50] -; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SLM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_bsf16: @@ -53,7 +53,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; SANDY-NEXT: bsfw (%rsi), %cx # sched: [8:1.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: orl %ecx, %eax # sched: [1:0.33] -; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SANDY-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_bsf16: @@ -63,7 +63,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; HASWELL-NEXT: bsfw (%rsi), %cx # sched: [3:1.00] ; HASWELL-NEXT: #NO_APP ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_bsf16: @@ -73,7 +73,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; BROADWELL-NEXT: bsfw (%rsi), %cx # sched: [8:1.00] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_bsf16: @@ -83,7 +83,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; SKYLAKE-NEXT: bsfw (%rsi), %cx # sched: [8:1.00] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; SKX-LABEL: test_bsf16: @@ -93,7 +93,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; SKX-NEXT: bsfw (%rsi), %cx # sched: [8:1.00] ; SKX-NEXT: #NO_APP ; SKX-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_bsf16: @@ -103,7 +103,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; BTVER2-NEXT: bsfw (%rsi), %cx # sched: [4:1.00] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_bsf16: @@ -113,7 +113,7 @@ define i16 @test_bsf16(i16 %a0, i16* %a1) optsize { ; ZNVER1-NEXT: bsfw (%rsi), %cx # sched: [7:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call { i16, i16 } asm sideeffect "bsf $2, $0 \0A\09 bsf $3, $1", "=r,=r,r,*m,~{dirflag},~{fpsr},~{flags}"(i16 %a0, i16* %a1) %2 = extractvalue { i16, i16 } %1, 0 @@ -322,7 +322,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; GENERIC-NEXT: bsrw (%rsi), %cx # sched: [8:1.00] ; GENERIC-NEXT: #NO_APP ; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_bsr16: @@ -332,7 +332,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; ATOM-NEXT: bsrw (%rsi), %cx # sched: [16:8.00] ; ATOM-NEXT: #NO_APP ; ATOM-NEXT: orl %ecx, %eax # sched: [1:0.50] -; ATOM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ATOM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ATOM-NEXT: retq # sched: [79:39.50] ; ; SLM-LABEL: test_bsr16: @@ -342,7 +342,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; SLM-NEXT: bsrw (%rsi), %cx # sched: [4:1.00] ; SLM-NEXT: #NO_APP ; SLM-NEXT: orl %ecx, %eax # sched: [1:0.50] -; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SLM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_bsr16: @@ -352,7 +352,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; SANDY-NEXT: bsrw (%rsi), %cx # sched: [8:1.00] ; SANDY-NEXT: #NO_APP ; SANDY-NEXT: orl %ecx, %eax # sched: [1:0.33] -; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SANDY-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_bsr16: @@ -362,7 +362,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; HASWELL-NEXT: bsrw (%rsi), %cx # sched: [3:1.00] ; HASWELL-NEXT: #NO_APP ; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_bsr16: @@ -372,7 +372,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; BROADWELL-NEXT: bsrw (%rsi), %cx # sched: [8:1.00] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_bsr16: @@ -382,7 +382,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; SKYLAKE-NEXT: bsrw (%rsi), %cx # sched: [8:1.00] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; SKX-LABEL: test_bsr16: @@ -392,7 +392,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; SKX-NEXT: bsrw (%rsi), %cx # sched: [8:1.00] ; SKX-NEXT: #NO_APP ; SKX-NEXT: orl %ecx, %eax # sched: [1:0.25] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_bsr16: @@ -402,7 +402,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; BTVER2-NEXT: bsrw (%rsi), %cx # sched: [4:1.00] ; BTVER2-NEXT: #NO_APP ; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_bsr16: @@ -412,7 +412,7 @@ define i16 @test_bsr16(i16 %a0, i16* %a1) optsize { ; ZNVER1-NEXT: bsrw (%rsi), %cx # sched: [7:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call { i16, i16 } asm sideeffect "bsr $2, $0 \0A\09 bsr $3, $1", "=r,=r,r,*m,~{dirflag},~{fpsr},~{flags}"(i16 %a0, i16* %a1) %2 = extractvalue { i16, i16 } %1, 0 diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll index c3674639eab..535d914a008 100644 --- a/test/CodeGen/X86/select.ll +++ b/test/CodeGen/X86/select.ll @@ -145,7 +145,7 @@ define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly { ; MCU-NEXT: fucompp ; MCU-NEXT: fnstsw %ax ; MCU-NEXT: xorl %edx, %edx -; MCU-NEXT: # kill: %AH<def> %AH<kill> %AX<kill> +; MCU-NEXT: # kill: %ah<def> %ah<kill> %ax<kill> ; MCU-NEXT: sahf ; MCU-NEXT: seta %dl ; MCU-NEXT: movb (%ecx,%edx,4), %al @@ -798,14 +798,14 @@ define i16 @test17(i16 %x) nounwind { ; GENERIC: ## BB#0: ## %entry ; GENERIC-NEXT: negw %di ; GENERIC-NEXT: sbbl %eax, %eax -; GENERIC-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq ; ; ATOM-LABEL: test17: ; ATOM: ## BB#0: ## %entry ; ATOM-NEXT: negw %di ; ATOM-NEXT: sbbl %eax, %eax -; ATOM-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; ATOM-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; ATOM-NEXT: nop ; ATOM-NEXT: nop ; ATOM-NEXT: nop @@ -816,7 +816,7 @@ define i16 @test17(i16 %x) nounwind { ; MCU: # BB#0: # %entry ; MCU-NEXT: negw %ax ; MCU-NEXT: sbbl %eax, %eax -; MCU-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; MCU-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; MCU-NEXT: retl entry: %cmp = icmp ne i16 %x, 0 @@ -1027,7 +1027,7 @@ define void @test19() { ; MCU-NEXT: cmpl %eax, %ecx ; MCU-NEXT: fucom %st(0) ; MCU-NEXT: fnstsw %ax -; MCU-NEXT: # kill: %AH<def> %AH<kill> %AX<kill> +; MCU-NEXT: # kill: %ah<def> %ah<kill> %ax<kill> ; MCU-NEXT: sahf ; MCU-NEXT: jp .LBB24_4 ; MCU-NEXT: # BB#5: # %CF244 @@ -1073,7 +1073,7 @@ define i16 @select_xor_1(i16 %A, i8 %cond) { ; MCU-NEXT: negl %edx ; MCU-NEXT: andl $43, %edx ; MCU-NEXT: xorl %edx, %eax -; MCU-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; MCU-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; MCU-NEXT: retl entry: %and = and i8 %cond, 1 diff --git a/test/CodeGen/X86/select_const.ll b/test/CodeGen/X86/select_const.ll index 6454c284ae8..264cc8175b7 100644 --- a/test/CodeGen/X86/select_const.ll +++ b/test/CodeGen/X86/select_const.ll @@ -74,7 +74,7 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { define i32 @select_0_or_neg1(i1 %cond) { ; CHECK-LABEL: select_0_or_neg1: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: retq @@ -85,7 +85,7 @@ define i32 @select_0_or_neg1(i1 %cond) { define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_neg1_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 0, i32 -1 @@ -139,7 +139,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { define i32 @select_Cplus1_C(i1 %cond) { ; CHECK-LABEL: select_Cplus1_C: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: leal 41(%rdi), %eax ; CHECK-NEXT: retq @@ -150,7 +150,7 @@ define i32 @select_Cplus1_C(i1 %cond) { define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_Cplus1_C_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal 41(%rdi), %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 42, i32 41 @@ -287,7 +287,7 @@ define i16 @sel_neg1_1(i32 %x) { ; CHECK-NEXT: cmpl $43, %edi ; CHECK-NEXT: setl %al ; CHECK-NEXT: leal -1(,%rax,4), %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %cmp = icmp sgt i32 %x, 42 %sel = select i1 %cmp, i16 -1, i16 3 @@ -344,7 +344,7 @@ define i16 @select_pow2_diff_invert(i1 zeroext %cond) { ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: shll $6, %eax ; CHECK-NEXT: orl $7, %eax -; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %sel = select i1 %cond, i16 7, i16 71 ret i16 %sel diff --git a/test/CodeGen/X86/setcc-lowering.ll b/test/CodeGen/X86/setcc-lowering.ll index a4db6b4b729..f9222c4dec5 100644 --- a/test/CodeGen/X86/setcc-lowering.ll +++ b/test/CodeGen/X86/setcc-lowering.ll @@ -23,7 +23,7 @@ define <8 x i16> @pr25080(<8 x i32> %a) { ; ; KNL-32-LABEL: pr25080: ; KNL-32: # BB#0: # %entry -; KNL-32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL-32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL-32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [8388607,8388607,8388607,8388607,8388607,8388607,8388607,8388607] ; KNL-32-NEXT: vptestnmd %zmm1, %zmm0, %k0 ; KNL-32-NEXT: movb $15, %al diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll index ce997f599c1..5aa51bcd721 100644 --- a/test/CodeGen/X86/sext-i1.ll +++ b/test/CodeGen/X86/sext-i1.ll @@ -124,7 +124,7 @@ define i32 @select_0_or_1s(i1 %cond) { ; ; X64-LABEL: select_0_or_1s: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: andl $1, %edi ; X64-NEXT: leal -1(%rdi), %eax ; X64-NEXT: retq @@ -144,7 +144,7 @@ define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) { ; ; X64-LABEL: select_0_or_1s_zeroext: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal -1(%rdi), %eax ; X64-NEXT: retq %not = xor i1 %cond, 1 diff --git a/test/CodeGen/X86/sha.ll b/test/CodeGen/X86/sha.ll index eb196647049..cf428b2a7e8 100644 --- a/test/CodeGen/X86/sha.ll +++ b/test/CodeGen/X86/sha.ll @@ -84,9 +84,9 @@ entry: %0 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) ret <4 x i32> %0 ; CHECK: test_sha256rnds2rr - ; CHECK: movaps %xmm0, [[XMM_TMP1:%xmm[1-9][0-9]?]] + ; CHECK: movaps %xmm0, [[xmm_TMP1:%xmm[1-9][0-9]?]] ; CHECK: movaps %xmm2, %xmm0 - ; CHECK: sha256rnds2 %xmm0, %xmm1, [[XMM_TMP1]] + ; CHECK: sha256rnds2 %xmm0, %xmm1, [[xmm_TMP1]] } define <4 x i32> @test_sha256rnds2rm(<4 x i32> %a, <4 x i32>* %b, <4 x i32> %c) nounwind uwtable { @@ -95,9 +95,9 @@ entry: %1 = tail call <4 x i32> @llvm.x86.sha256rnds2(<4 x i32> %a, <4 x i32> %0, <4 x i32> %c) ret <4 x i32> %1 ; CHECK: test_sha256rnds2rm - ; CHECK: movaps %xmm0, [[XMM_TMP2:%xmm[1-9][0-9]?]] + ; CHECK: movaps %xmm0, [[xmm_TMP2:%xmm[1-9][0-9]?]] ; CHECK: movaps %xmm1, %xmm0 - ; CHECK: sha256rnds2 %xmm0, (%rdi), [[XMM_TMP2]] + ; CHECK: sha256rnds2 %xmm0, (%rdi), [[xmm_TMP2]] } declare <4 x i32> @llvm.x86.sha256msg1(<4 x i32>, <4 x i32>) nounwind readnone diff --git a/test/CodeGen/X86/shift-combine.ll b/test/CodeGen/X86/shift-combine.ll index 6e132f25bf3..7b8a1fc2dff 100644 --- a/test/CodeGen/X86/shift-combine.ll +++ b/test/CodeGen/X86/shift-combine.ll @@ -14,7 +14,7 @@ define i32 @test_lshr_and(i32 %x) { ; ; X64-LABEL: test_lshr_and: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shrl $2, %edi ; X64-NEXT: andl $3, %edi ; X64-NEXT: movl array(,%rdi,4), %eax @@ -102,7 +102,7 @@ define i32* @test_exact4(i32 %a, i32 %b, i32* %x) { ; ; X64-LABEL: test_exact4: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: subl %edi, %esi ; X64-NEXT: shrl $3, %esi ; X64-NEXT: leaq (%rdx,%rsi,4), %rax @@ -124,7 +124,7 @@ define i32* @test_exact5(i32 %a, i32 %b, i32* %x) { ; ; X64-LABEL: test_exact5: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: subl %edi, %esi ; X64-NEXT: shrl $3, %esi ; X64-NEXT: leaq (%rdx,%rsi,4), %rax @@ -145,7 +145,7 @@ define i32* @test_exact6(i32 %a, i32 %b, i32* %x) { ; ; X64-LABEL: test_exact6: ; X64: # BB#0: -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: subl %edi, %esi ; X64-NEXT: leaq (%rsi,%rdx), %rax ; X64-NEXT: retq diff --git a/test/CodeGen/X86/shift-double.ll b/test/CodeGen/X86/shift-double.ll index cabf4d8660d..3d0b755d56f 100644 --- a/test/CodeGen/X86/shift-double.ll +++ b/test/CodeGen/X86/shift-double.ll @@ -278,7 +278,7 @@ define i32 @test11(i32 %hi, i32 %lo, i32 %bits) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: andl $31, %ecx -; X86-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X86-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X86-NEXT: shldl %cl, %edx, %eax ; X86-NEXT: retl ; @@ -304,7 +304,7 @@ define i32 @test12(i32 %hi, i32 %lo, i32 %bits) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: andl $31, %ecx -; X86-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X86-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X86-NEXT: shrdl %cl, %edx, %eax ; X86-NEXT: retl ; diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll index 7f35258377e..0cecf9c0d1d 100644 --- a/test/CodeGen/X86/shrink-compare.ll +++ b/test/CodeGen/X86/shrink-compare.ll @@ -72,11 +72,11 @@ define i1 @test4(i64 %a, i32 %b) { ; CHECK-NEXT: testl %esi, %esi ; CHECK-NEXT: je .LBB3_1 ; CHECK-NEXT: # BB#2: # %lor.end -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB3_1: # %lor.rhs ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: retq entry: %tobool = icmp ne i32 %b, 0 diff --git a/test/CodeGen/X86/shuffle-vs-trunc-256.ll b/test/CodeGen/X86/shuffle-vs-trunc-256.ll index c8c2abc570c..e986e1af2fb 100644 --- a/test/CodeGen/X86/shuffle-vs-trunc-256.ll +++ b/test/CodeGen/X86/shuffle-vs-trunc-256.ll @@ -760,7 +760,7 @@ define <16 x i8> @negative(<32 x i8> %v, <32 x i8> %w) nounwind { ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -770,7 +770,7 @@ define <16 x i8> @negative(<32 x i8> %v, <32 x i8> %w) nounwind { ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512F-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -780,7 +780,7 @@ define <16 x i8> @negative(<32 x i8> %v, <32 x i8> %w) nounwind { ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512VL-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -790,7 +790,7 @@ define <16 x i8> @negative(<32 x i8> %v, <32 x i8> %w) nounwind { ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; AVX512BW-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0 ; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -801,7 +801,7 @@ define <16 x i8> @negative(<32 x i8> %v, <32 x i8> %w) nounwind { ; AVX512BWVL-NEXT: kmovd %eax, %k1 ; AVX512BWVL-NEXT: vmovdqu8 %ymm1, %ymm0 {%k1} ; AVX512BWVL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,3,2,3] -; AVX512BWVL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BWVL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: retq %strided.vec = shufflevector <32 x i8> %v, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> diff --git a/test/CodeGen/X86/sjlj-eh.ll b/test/CodeGen/X86/sjlj-eh.ll index a4d638c798a..9a40b5932d4 100644 --- a/test/CodeGen/X86/sjlj-eh.ll +++ b/test/CodeGen/X86/sjlj-eh.ll @@ -41,9 +41,9 @@ try.cont: ; CHECK: movl $___gxx_personality_sj0, -40(%ebp) ; UFC.__lsda = $LSDA ; CHECK: movl $[[LSDA:GCC_except_table[0-9]+]], -36(%ebp) -; UFC.__jbuf[0] = $EBP +; UFC.__jbuf[0] = $ebp ; CHECK: movl %ebp, -32(%ebp) -; UFC.__jbuf[2] = $ESP +; UFC.__jbuf[2] = $esp ; CHECK: movl %esp, -24(%ebp) ; UFC.__jbuf[1] = $EIP ; CHECK: movl $[[RESUME:LBB[0-9]+_[0-9]+]], -28(%ebp) @@ -91,9 +91,9 @@ try.cont: ; UFC.__lsda = $LSDA ; CHECK-X64: leaq [[LSDA:GCC_except_table[0-9]+]](%rip), %rax ; CHECK-X64: movq %rax, -272(%rbp) -; UFC.__jbuf[0] = $RBP +; UFC.__jbuf[0] = $rbp ; CHECK-X64: movq %rbp, -264(%rbp) -; UFC.__jbuf[2] = $RSP +; UFC.__jbuf[2] = $rsp ; CHECK-X64: movq %rsp, -248(%rbp) ; UFC.__jbuf[1] = $RIP ; CHECK-X64: leaq .[[RESUME:LBB[0-9]+_[0-9]+]](%rip), %rax diff --git a/test/CodeGen/X86/sse-regcall.ll b/test/CodeGen/X86/sse-regcall.ll index 862b9cc92f6..e7a4c686f87 100644 --- a/test/CodeGen/X86/sse-regcall.ll +++ b/test/CodeGen/X86/sse-regcall.ll @@ -75,7 +75,7 @@ define x86_regcallcc i1 @test_CallargReti1(i1 %a) { ; LINUXOSX: movaps {{.*(%r(b|s)p).*}}, {{%xmm(1[2-5])}} {{#+}} 16-byte Reload ; LINUXOSX: retq -;test calling conventions - input parameters, callee saved XMMs +;test calling conventions - input parameters, callee saved xmms define x86_regcallcc <16 x float> @testf32_inp(<16 x float> %a, <16 x float> %b, <16 x float> %c) nounwind { %x1 = fadd <16 x float> %a, %b %x2 = fmul <16 x float> %a, %b diff --git a/test/CodeGen/X86/sse2-schedule.ll b/test/CodeGen/X86/sse2-schedule.ll index a03ea00cbbc..b7a4d7be2cd 100644 --- a/test/CodeGen/X86/sse2-schedule.ll +++ b/test/CodeGen/X86/sse2-schedule.ll @@ -5485,61 +5485,61 @@ define i16 @test_pextrw(<8 x i16> %a0) { ; GENERIC-LABEL: test_pextrw: ; GENERIC: # BB#0: ; GENERIC-NEXT: pextrw $6, %xmm0, %eax # sched: [3:1.00] -; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; GENERIC-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; GENERIC-NEXT: retq # sched: [1:1.00] ; ; ATOM-LABEL: test_pextrw: ; ATOM: # BB#0: ; ATOM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:2.00] -; ATOM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ATOM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ATOM-NEXT: retq # sched: [79:39.50] ; ; SLM-LABEL: test_pextrw: ; SLM: # BB#0: ; SLM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:1.00] -; SLM-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SLM-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SLM-NEXT: retq # sched: [4:1.00] ; ; SANDY-LABEL: test_pextrw: ; SANDY: # BB#0: ; SANDY-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00] -; SANDY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SANDY-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_pextrw: ; HASWELL: # BB#0: ; HASWELL-NEXT: vpextrw $6, %xmm0, %eax # sched: [2:1.00] -; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; HASWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; HASWELL-NEXT: retq # sched: [2:1.00] ; ; BROADWELL-LABEL: test_pextrw: ; BROADWELL: # BB#0: ; BROADWELL-NEXT: vpextrw $6, %xmm0, %eax # sched: [2:1.00] -; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BROADWELL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BROADWELL-NEXT: retq # sched: [7:1.00] ; ; SKYLAKE-LABEL: test_pextrw: ; SKYLAKE: # BB#0: ; SKYLAKE-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00] -; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKYLAKE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; SKX-LABEL: test_pextrw: ; SKX: # BB#0: ; SKX-NEXT: vpextrw $6, %xmm0, %eax # sched: [3:1.00] -; SKX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SKX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SKX-NEXT: retq # sched: [7:1.00] ; ; BTVER2-LABEL: test_pextrw: ; BTVER2: # BB#0: ; BTVER2-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.50] -; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; BTVER2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; BTVER2-NEXT: retq # sched: [4:1.00] ; ; ZNVER1-LABEL: test_pextrw: ; ZNVER1: # BB#0: ; ZNVER1-NEXT: vpextrw $6, %xmm0, %eax # sched: [1:0.25] -; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ZNVER1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = extractelement <8 x i16> %a0, i32 6 ret i16 %1 diff --git a/test/CodeGen/X86/sse42-schedule.ll b/test/CodeGen/X86/sse42-schedule.ll index d966ee66c5c..4af89595cad 100644 --- a/test/CodeGen/X86/sse42-schedule.ll +++ b/test/CodeGen/X86/sse42-schedule.ll @@ -370,7 +370,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; GENERIC-NEXT: movl $7, %eax # sched: [1:0.33] ; GENERIC-NEXT: movl $7, %edx # sched: [1:0.33] ; GENERIC-NEXT: pcmpestri $7, (%rdi), %xmm0 # sched: [4:2.33] -; GENERIC-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; GENERIC-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; GENERIC-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -383,7 +383,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SLM-NEXT: movl $7, %edx # sched: [1:0.50] ; SLM-NEXT: movl %ecx, %esi # sched: [1:0.50] ; SLM-NEXT: pcmpestri $7, (%rdi), %xmm0 # sched: [21:21.00] -; SLM-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SLM-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SLM-NEXT: leal (%rcx,%rsi), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -396,7 +396,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SANDY-NEXT: movl $7, %eax # sched: [1:0.33] ; SANDY-NEXT: movl $7, %edx # sched: [1:0.33] ; SANDY-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [4:2.33] -; SANDY-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SANDY-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SANDY-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -409,7 +409,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; HASWELL-NEXT: movl $7, %eax # sched: [1:0.25] ; HASWELL-NEXT: movl $7, %edx # sched: [1:0.25] ; HASWELL-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [18:4.00] -; HASWELL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; HASWELL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; HASWELL-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; @@ -422,7 +422,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; BROADWELL-NEXT: movl $7, %eax # sched: [1:0.25] ; BROADWELL-NEXT: movl $7, %edx # sched: [1:0.25] ; BROADWELL-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [23:4.00] -; BROADWELL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; BROADWELL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; BROADWELL-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -435,7 +435,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SKYLAKE-NEXT: movl $7, %eax # sched: [1:0.25] ; SKYLAKE-NEXT: movl $7, %edx # sched: [1:0.25] ; SKYLAKE-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [24:4.00] -; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SKYLAKE-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SKYLAKE-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -448,7 +448,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SKX-NEXT: movl $7, %eax # sched: [1:0.25] ; SKX-NEXT: movl $7, %edx # sched: [1:0.25] ; SKX-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [24:4.00] -; SKX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SKX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SKX-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; SKX-NEXT: retq # sched: [7:1.00] ; @@ -461,7 +461,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; BTVER2-NEXT: movl $7, %edx # sched: [1:0.17] ; BTVER2-NEXT: movl %ecx, %esi # sched: [1:0.17] ; BTVER2-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [19:10.00] -; BTVER2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; BTVER2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; BTVER2-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -474,7 +474,7 @@ define i32 @test_pcmpestri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; ZNVER1-NEXT: movl $7, %edx # sched: [1:0.25] ; ZNVER1-NEXT: movl %ecx, %esi # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpestri $7, (%rdi), %xmm0 # sched: [100:?] -; ZNVER1-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; ZNVER1-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; ZNVER1-NEXT: leal (%rcx,%rsi), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call i32 @llvm.x86.sse42.pcmpestri128(<16 x i8> %a0, i32 7, <16 x i8> %a1, i32 7, i8 7) @@ -588,7 +588,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; GENERIC-NEXT: pcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00] ; GENERIC-NEXT: movl %ecx, %eax # sched: [1:0.33] ; GENERIC-NEXT: pcmpistri $7, (%rdi), %xmm0 # sched: [17:3.00] -; GENERIC-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; GENERIC-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; GENERIC-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; GENERIC-NEXT: retq # sched: [1:1.00] ; @@ -597,7 +597,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SLM-NEXT: pcmpistri $7, %xmm1, %xmm0 # sched: [17:17.00] ; SLM-NEXT: movl %ecx, %eax # sched: [1:0.50] ; SLM-NEXT: pcmpistri $7, (%rdi), %xmm0 # sched: [17:17.00] -; SLM-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SLM-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SLM-NEXT: leal (%rcx,%rax), %eax # sched: [1:1.00] ; SLM-NEXT: retq # sched: [4:1.00] ; @@ -606,7 +606,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SANDY-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00] ; SANDY-NEXT: movl %ecx, %eax # sched: [1:0.33] ; SANDY-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [17:3.00] -; SANDY-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SANDY-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SANDY-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; SANDY-NEXT: retq # sched: [1:1.00] ; @@ -615,7 +615,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; HASWELL-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00] ; HASWELL-NEXT: movl %ecx, %eax # sched: [1:0.25] ; HASWELL-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [11:3.00] -; HASWELL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; HASWELL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; HASWELL-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; HASWELL-NEXT: retq # sched: [2:1.00] ; @@ -624,7 +624,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; BROADWELL-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [11:3.00] ; BROADWELL-NEXT: movl %ecx, %eax # sched: [1:0.25] ; BROADWELL-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00] -; BROADWELL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; BROADWELL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; BROADWELL-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -633,7 +633,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SKYLAKE-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [10:3.00] ; SKYLAKE-NEXT: movl %ecx, %eax # sched: [1:0.25] ; SKYLAKE-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00] -; SKYLAKE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SKYLAKE-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SKYLAKE-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -642,7 +642,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; SKX-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [10:3.00] ; SKX-NEXT: movl %ecx, %eax # sched: [1:0.25] ; SKX-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [16:3.00] -; SKX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; SKX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; SKX-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; SKX-NEXT: retq # sched: [7:1.00] ; @@ -651,7 +651,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; BTVER2-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [7:2.00] ; BTVER2-NEXT: movl %ecx, %eax # sched: [1:0.17] ; BTVER2-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [12:2.00] -; BTVER2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; BTVER2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; BTVER2-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; @@ -660,7 +660,7 @@ define i32 @test_pcmpistri(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> *%a2) { ; ZNVER1-NEXT: vpcmpistri $7, %xmm1, %xmm0 # sched: [100:?] ; ZNVER1-NEXT: movl %ecx, %eax # sched: [1:0.25] ; ZNVER1-NEXT: vpcmpistri $7, (%rdi), %xmm0 # sched: [100:?] -; ZNVER1-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> +; ZNVER1-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> ; ZNVER1-NEXT: leal (%rcx,%rax), %eax # sched: [1:0.25] ; ZNVER1-NEXT: retq # sched: [1:0.50] %1 = call i32 @llvm.x86.sse42.pcmpistri128(<16 x i8> %a0, <16 x i8> %a1, i8 7) diff --git a/test/CodeGen/X86/stackmap-fast-isel.ll b/test/CodeGen/X86/stackmap-fast-isel.ll index ae10a37756b..dd25065f306 100644 --- a/test/CodeGen/X86/stackmap-fast-isel.ll +++ b/test/CodeGen/X86/stackmap-fast-isel.ll @@ -157,7 +157,7 @@ define void @liveConstant() { ; CHECK-NEXT: .short 0 ; 1 location ; CHECK-NEXT: .short 1 -; Loc 0: Direct RBP - ofs +; Loc 0: Direct rbp - ofs ; CHECK-NEXT: .byte 2 ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .short 8 diff --git a/test/CodeGen/X86/stackmap-liveness.ll b/test/CodeGen/X86/stackmap-liveness.ll index eb95b9c8df4..4cbfe234ff4 100644 --- a/test/CodeGen/X86/stackmap-liveness.ll +++ b/test/CodeGen/X86/stackmap-liveness.ll @@ -48,7 +48,7 @@ entry: ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 1 ; PATCH-NEXT: .short 1 -; LiveOut Entry 1: %YMM2 (16 bytes) --> %XMM2 +; LiveOut Entry 1: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -81,23 +81,23 @@ entry: ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 5 ; PATCH-NEXT: .short 5 -; LiveOut Entry 1: %RAX (1 bytes) --> %AL or %AH +; LiveOut Entry 1: %rax (1 bytes) --> %al or %ah ; PATCH-NEXT: .short 0 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 1 -; LiveOut Entry 2: %R8 (8 bytes) +; LiveOut Entry 2: %r8 (8 bytes) ; PATCH-NEXT: .short 8 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 3: %YMM0 (32 bytes) +; LiveOut Entry 3: %ymm0 (32 bytes) ; PATCH-NEXT: .short 17 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 32 -; LiveOut Entry 4: %YMM1 (32 bytes) +; LiveOut Entry 4: %ymm1 (32 bytes) ; PATCH-NEXT: .short 18 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 32 -; LiveOut Entry 5: %YMM2 (16 bytes) --> %XMM2 +; LiveOut Entry 5: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -127,11 +127,11 @@ entry: ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 2 ; PATCH-NEXT: .short 2 -; LiveOut Entry 1: %RSP (8 bytes) +; LiveOut Entry 1: %rsp (8 bytes) ; PATCH-NEXT: .short 7 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2 +; LiveOut Entry 2: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 @@ -166,11 +166,11 @@ entry: ; PATCH-NEXT: .short 0 ; Num LiveOut Entries: 2 ; PATCH-NEXT: .short 2 -; LiveOut Entry 1: %RSP (8 bytes) +; LiveOut Entry 1: %rsp (8 bytes) ; PATCH-NEXT: .short 7 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 8 -; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2 +; LiveOut Entry 2: %ymm2 (16 bytes) --> %xmm2 ; PATCH-NEXT: .short 19 ; PATCH-NEXT: .byte 0 ; PATCH-NEXT: .byte 16 diff --git a/test/CodeGen/X86/statepoint-allocas.ll b/test/CodeGen/X86/statepoint-allocas.ll index b8e5c82913a..bd820e0b83d 100644 --- a/test/CodeGen/X86/statepoint-allocas.ll +++ b/test/CodeGen/X86/statepoint-allocas.ll @@ -96,7 +96,7 @@ declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i3 ; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 0 -; Direct Spill Slot [RSP+0] +; Direct Spill Slot [rsp+0] ; CHECK: .byte 2 ; CHECK: .byte 0 ; CHECK: .short 8 @@ -133,7 +133,7 @@ declare token @llvm.experimental.gc.statepoint.p0f_i1f(i64, i32, i1 ()*, i32, i3 ; CHECK: .short 0 ; CHECK: .short 0 ; CHECK: .long 1 -; Direct Spill Slot [RSP+0] +; Direct Spill Slot [rsp+0] ; CHECK: .byte 2 ; CHECK: .byte 0 ; CHECK: .short 8 diff --git a/test/CodeGen/X86/subvector-broadcast.ll b/test/CodeGen/X86/subvector-broadcast.ll index 2756e42573c..3f6d25bd2fc 100644 --- a/test/CodeGen/X86/subvector-broadcast.ll +++ b/test/CodeGen/X86/subvector-broadcast.ll @@ -1145,13 +1145,13 @@ entry: define <4 x double> @reg_broadcast_2f64_4f64(<2 x double> %a0) nounwind { ; X32-LABEL: reg_broadcast_2f64_4f64: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_2f64_4f64: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <2 x double> %a0, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> @@ -1161,28 +1161,28 @@ define <4 x double> @reg_broadcast_2f64_4f64(<2 x double> %a0) nounwind { define <8 x double> @reg_broadcast_2f64_8f64(<2 x double> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_2f64_8f64: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512-LABEL: reg_broadcast_2f64_8f64: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_2f64_8f64: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512-LABEL: reg_broadcast_2f64_8f64: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq @@ -1198,7 +1198,7 @@ define <8 x double> @reg_broadcast_4f64_8f64(<4 x double> %a0) nounwind { ; ; X32-AVX512-LABEL: reg_broadcast_4f64_8f64: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; @@ -1209,7 +1209,7 @@ define <8 x double> @reg_broadcast_4f64_8f64(<4 x double> %a0) nounwind { ; ; X64-AVX512-LABEL: reg_broadcast_4f64_8f64: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq %1 = shufflevector <4 x double> %a0, <4 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> @@ -1219,13 +1219,13 @@ define <8 x double> @reg_broadcast_4f64_8f64(<4 x double> %a0) nounwind { define <4 x i64> @reg_broadcast_2i64_4i64(<2 x i64> %a0) nounwind { ; X32-LABEL: reg_broadcast_2i64_4i64: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_2i64_4i64: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <2 x i64> %a0, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> @@ -1235,28 +1235,28 @@ define <4 x i64> @reg_broadcast_2i64_4i64(<2 x i64> %a0) nounwind { define <8 x i64> @reg_broadcast_2i64_8i64(<2 x i64> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_2i64_8i64: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512-LABEL: reg_broadcast_2i64_8i64: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_2i64_8i64: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512-LABEL: reg_broadcast_2i64_8i64: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq @@ -1272,7 +1272,7 @@ define <8 x i64> @reg_broadcast_4i64_8i64(<4 x i64> %a0) nounwind { ; ; X32-AVX512-LABEL: reg_broadcast_4i64_8i64: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; @@ -1283,7 +1283,7 @@ define <8 x i64> @reg_broadcast_4i64_8i64(<4 x i64> %a0) nounwind { ; ; X64-AVX512-LABEL: reg_broadcast_4i64_8i64: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq %1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> @@ -1293,13 +1293,13 @@ define <8 x i64> @reg_broadcast_4i64_8i64(<4 x i64> %a0) nounwind { define <8 x float> @reg_broadcast_4f32_8f32(<4 x float> %a0) nounwind { ; X32-LABEL: reg_broadcast_4f32_8f32: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_4f32_8f32: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <4 x float> %a0, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> @@ -1309,28 +1309,28 @@ define <8 x float> @reg_broadcast_4f32_8f32(<4 x float> %a0) nounwind { define <16 x float> @reg_broadcast_4f32_16f32(<4 x float> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_4f32_16f32: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512-LABEL: reg_broadcast_4f32_16f32: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_4f32_16f32: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512-LABEL: reg_broadcast_4f32_16f32: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq @@ -1346,7 +1346,7 @@ define <16 x float> @reg_broadcast_8f32_16f32(<8 x float> %a0) nounwind { ; ; X32-AVX512-LABEL: reg_broadcast_8f32_16f32: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; @@ -1357,7 +1357,7 @@ define <16 x float> @reg_broadcast_8f32_16f32(<8 x float> %a0) nounwind { ; ; X64-AVX512-LABEL: reg_broadcast_8f32_16f32: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq %1 = shufflevector <8 x float> %a0, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -1367,13 +1367,13 @@ define <16 x float> @reg_broadcast_8f32_16f32(<8 x float> %a0) nounwind { define <8 x i32> @reg_broadcast_4i32_8i32(<4 x i32> %a0) nounwind { ; X32-LABEL: reg_broadcast_4i32_8i32: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_4i32_8i32: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> @@ -1383,28 +1383,28 @@ define <8 x i32> @reg_broadcast_4i32_8i32(<4 x i32> %a0) nounwind { define <16 x i32> @reg_broadcast_4i32_16i32(<4 x i32> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_4i32_16i32: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512-LABEL: reg_broadcast_4i32_16i32: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_4i32_16i32: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512-LABEL: reg_broadcast_4i32_16i32: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq @@ -1420,7 +1420,7 @@ define <16 x i32> @reg_broadcast_8i32_16i32(<8 x i32> %a0) nounwind { ; ; X32-AVX512-LABEL: reg_broadcast_8i32_16i32: ; X32-AVX512: # BB#0: -; X32-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512-NEXT: retl ; @@ -1431,7 +1431,7 @@ define <16 x i32> @reg_broadcast_8i32_16i32(<8 x i32> %a0) nounwind { ; ; X64-AVX512-LABEL: reg_broadcast_8i32_16i32: ; X64-AVX512: # BB#0: -; X64-AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512-NEXT: retq %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -1441,13 +1441,13 @@ define <16 x i32> @reg_broadcast_8i32_16i32(<8 x i32> %a0) nounwind { define <16 x i16> @reg_broadcast_8i16_16i16(<8 x i16> %a0) nounwind { ; X32-LABEL: reg_broadcast_8i16_16i16: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_8i16_16i16: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -1457,56 +1457,56 @@ define <16 x i16> @reg_broadcast_8i16_16i16(<8 x i16> %a0) nounwind { define <32 x i16> @reg_broadcast_8i16_32i16(<8 x i16> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_8i16_32i16: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512F-LABEL: reg_broadcast_8i16_32i16: ; X32-AVX512F: # BB#0: -; X32-AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512F-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX512F-NEXT: retl ; ; X32-AVX512BW-LABEL: reg_broadcast_8i16_32i16: ; X32-AVX512BW: # BB#0: -; X32-AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512BW-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512BW-NEXT: retl ; ; X32-AVX512DQ-LABEL: reg_broadcast_8i16_32i16: ; X32-AVX512DQ: # BB#0: -; X32-AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512DQ-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512DQ-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX512DQ-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_8i16_32i16: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512F-LABEL: reg_broadcast_8i16_32i16: ; X64-AVX512F: # BB#0: -; X64-AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512F-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX512F-NEXT: retq ; ; X64-AVX512BW-LABEL: reg_broadcast_8i16_32i16: ; X64-AVX512BW: # BB#0: -; X64-AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512BW-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512BW-NEXT: retq ; ; X64-AVX512DQ-LABEL: reg_broadcast_8i16_32i16: ; X64-AVX512DQ: # BB#0: -; X64-AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512DQ-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512DQ-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX512DQ-NEXT: retq @@ -1527,7 +1527,7 @@ define <32 x i16> @reg_broadcast_16i16_32i16(<16 x i16> %a0) nounwind { ; ; X32-AVX512BW-LABEL: reg_broadcast_16i16_32i16: ; X32-AVX512BW: # BB#0: -; X32-AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512BW-NEXT: retl ; @@ -1548,7 +1548,7 @@ define <32 x i16> @reg_broadcast_16i16_32i16(<16 x i16> %a0) nounwind { ; ; X64-AVX512BW-LABEL: reg_broadcast_16i16_32i16: ; X64-AVX512BW: # BB#0: -; X64-AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512BW-NEXT: retq ; @@ -1563,13 +1563,13 @@ define <32 x i16> @reg_broadcast_16i16_32i16(<16 x i16> %a0) nounwind { define <32 x i8> @reg_broadcast_16i8_32i8(<16 x i8> %a0) nounwind { ; X32-LABEL: reg_broadcast_16i8_32i8: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: reg_broadcast_16i8_32i8: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -1579,56 +1579,56 @@ define <32 x i8> @reg_broadcast_16i8_32i8(<16 x i8> %a0) nounwind { define <64 x i8> @reg_broadcast_16i8_64i8(<16 x i8> %a0) nounwind { ; X32-AVX-LABEL: reg_broadcast_16i8_64i8: ; X32-AVX: # BB#0: -; X32-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX-NEXT: retl ; ; X32-AVX512F-LABEL: reg_broadcast_16i8_64i8: ; X32-AVX512F: # BB#0: -; X32-AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512F-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX512F-NEXT: retl ; ; X32-AVX512BW-LABEL: reg_broadcast_16i8_64i8: ; X32-AVX512BW: # BB#0: -; X32-AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512BW-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512BW-NEXT: retl ; ; X32-AVX512DQ-LABEL: reg_broadcast_16i8_64i8: ; X32-AVX512DQ: # BB#0: -; X32-AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-AVX512DQ-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X32-AVX512DQ-NEXT: vmovaps %ymm0, %ymm1 ; X32-AVX512DQ-NEXT: retl ; ; X64-AVX-LABEL: reg_broadcast_16i8_64i8: ; X64-AVX: # BB#0: -; X64-AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX-NEXT: retq ; ; X64-AVX512F-LABEL: reg_broadcast_16i8_64i8: ; X64-AVX512F: # BB#0: -; X64-AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512F-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX512F-NEXT: retq ; ; X64-AVX512BW-LABEL: reg_broadcast_16i8_64i8: ; X64-AVX512BW: # BB#0: -; X64-AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512BW-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512BW-NEXT: retq ; ; X64-AVX512DQ-LABEL: reg_broadcast_16i8_64i8: ; X64-AVX512DQ: # BB#0: -; X64-AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-AVX512DQ-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; X64-AVX512DQ-NEXT: vmovaps %ymm0, %ymm1 ; X64-AVX512DQ-NEXT: retq @@ -1649,7 +1649,7 @@ define <64 x i8> @reg_broadcast_32i8_64i8(<32 x i8> %a0) nounwind { ; ; X32-AVX512BW-LABEL: reg_broadcast_32i8_64i8: ; X32-AVX512BW: # BB#0: -; X32-AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X32-AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X32-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X32-AVX512BW-NEXT: retl ; @@ -1670,7 +1670,7 @@ define <64 x i8> @reg_broadcast_32i8_64i8(<32 x i8> %a0) nounwind { ; ; X64-AVX512BW-LABEL: reg_broadcast_32i8_64i8: ; X64-AVX512BW: # BB#0: -; X64-AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; X64-AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; X64-AVX512BW-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; X64-AVX512BW-NEXT: retq ; diff --git a/test/CodeGen/X86/tailcall-64.ll b/test/CodeGen/X86/tailcall-64.ll index 9e054fea5b3..65395a0947a 100644 --- a/test/CodeGen/X86/tailcall-64.ll +++ b/test/CodeGen/X86/tailcall-64.ll @@ -181,8 +181,8 @@ define { i64, i64 } @crash(i8* %this) { ; Check that we can fold an indexed load into a tail call instruction. ; CHECK: fold_indexed_load -; CHECK: leaq (%rsi,%rsi,4), %[[RAX:r..]] -; CHECK: jmpq *16(%{{r..}},%[[RAX]],8) ## TAILCALL +; CHECK: leaq (%rsi,%rsi,4), %[[rax:r..]] +; CHECK: jmpq *16(%{{r..}},%[[rax]],8) ## TAILCALL %struct.funcs = type { i32 (i8*, i32*, i32)*, i32 (i8*)*, i32 (i8*)*, i32 (i8*, i32)*, i32 } @func_table = external global [0 x %struct.funcs] define void @fold_indexed_load(i8* %mbstr, i64 %idxprom) nounwind uwtable ssp { diff --git a/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll b/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll index a264adffe79..7a90ba3f5ec 100644 --- a/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll +++ b/test/CodeGen/X86/tbm-intrinsics-fast-isel.ll @@ -28,7 +28,7 @@ define i32 @test__blcfill_u32(i32 %a0) { ; ; X64-LABEL: test__blcfill_u32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 1(%rdi), %eax ; X64-NEXT: andl %edi, %eax ; X64-NEXT: retq @@ -48,7 +48,7 @@ define i32 @test__blci_u32(i32 %a0) { ; ; X64-LABEL: test__blci_u32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 1(%rdi), %eax ; X64-NEXT: xorl $-1, %eax ; X64-NEXT: orl %edi, %eax @@ -93,7 +93,7 @@ define i32 @test__blcmsk_u32(i32 %a0) { ; ; X64-LABEL: test__blcmsk_u32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 1(%rdi), %eax ; X64-NEXT: xorl %edi, %eax ; X64-NEXT: retq @@ -112,7 +112,7 @@ define i32 @test__blcs_u32(i32 %a0) { ; ; X64-LABEL: test__blcs_u32: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal 1(%rdi), %eax ; X64-NEXT: orl %edi, %eax ; X64-NEXT: retq diff --git a/test/CodeGen/X86/tbm_patterns.ll b/test/CodeGen/X86/tbm_patterns.ll index e459e173eda..b78f19fa101 100644 --- a/test/CodeGen/X86/tbm_patterns.ll +++ b/test/CodeGen/X86/tbm_patterns.ll @@ -151,7 +151,7 @@ define i32 @test_x86_tbm_blcfill_u32_z(i32 %a, i32 %b) nounwind { define i32 @test_x86_tbm_blcfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK-LABEL: test_x86_tbm_blcfill_u32_z2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal 1(%rdi), %eax ; CHECK-NEXT: testl %edi, %eax ; CHECK-NEXT: cmovnel %edx, %esi @@ -230,7 +230,7 @@ define i32 @test_x86_tbm_blci_u32_z(i32 %a, i32 %b) nounwind { define i32 @test_x86_tbm_blci_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK-LABEL: test_x86_tbm_blci_u32_z2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal 1(%rdi), %eax ; CHECK-NEXT: notl %eax ; CHECK-NEXT: orl %edi, %eax @@ -419,7 +419,7 @@ define i32 @test_x86_tbm_blcmsk_u32_z(i32 %a, i32 %b) nounwind { define i32 @test_x86_tbm_blcmsk_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK-LABEL: test_x86_tbm_blcmsk_u32_z2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal 1(%rdi), %eax ; CHECK-NEXT: xorl %edi, %eax ; CHECK-NEXT: cmovnel %edx, %esi @@ -496,7 +496,7 @@ define i32 @test_x86_tbm_blcs_u32_z(i32 %a, i32 %b) nounwind { define i32 @test_x86_tbm_blcs_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK-LABEL: test_x86_tbm_blcs_u32_z2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal 1(%rdi), %eax ; CHECK-NEXT: orl %edi, %eax ; CHECK-NEXT: cmovnel %edx, %esi @@ -573,7 +573,7 @@ define i32 @test_x86_tbm_blsfill_u32_z(i32 %a, i32 %b) nounwind { define i32 @test_x86_tbm_blsfill_u32_z2(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK-LABEL: test_x86_tbm_blsfill_u32_z2: ; CHECK: # BB#0: -; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; CHECK-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: orl %edi, %eax ; CHECK-NEXT: cmovnel %edx, %esi diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll index e198a15d526..2e877a0b6e0 100644 --- a/test/CodeGen/X86/umul-with-overflow.ll +++ b/test/CodeGen/X86/umul-with-overflow.ll @@ -35,7 +35,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind readnone { ; ; X64-LABEL: test2: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: addl %esi, %edi ; X64-NEXT: leal (%rdi,%rdi), %eax ; X64-NEXT: retq @@ -57,8 +57,8 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone { ; ; X64-LABEL: test3: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: leal (%rdi,%rsi), %eax ; X64-NEXT: movl $4, %ecx ; X64-NEXT: mull %ecx diff --git a/test/CodeGen/X86/urem-i8-constant.ll b/test/CodeGen/X86/urem-i8-constant.ll index e2ddd7ee068..a9cb99c0d35 100644 --- a/test/CodeGen/X86/urem-i8-constant.ll +++ b/test/CodeGen/X86/urem-i8-constant.ll @@ -11,7 +11,7 @@ define i8 @foo(i8 %tmp325) { ; CHECK-NEXT: shrl $12, %eax ; CHECK-NEXT: movzwl %ax, %eax ; CHECK-NEXT: movb $37, %dl -; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; CHECK-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; CHECK-NEXT: mulb %dl ; CHECK-NEXT: subb %al, %cl ; CHECK-NEXT: movl %ecx, %eax diff --git a/test/CodeGen/X86/urem-power-of-two.ll b/test/CodeGen/X86/urem-power-of-two.ll index 72f96776bab..9509cfe1231 100644 --- a/test/CodeGen/X86/urem-power-of-two.ll +++ b/test/CodeGen/X86/urem-power-of-two.ll @@ -56,7 +56,7 @@ define i16 @shift_right_pow_2(i16 %x, i16 %y) { ; X86-NEXT: shrl %cl, %eax ; X86-NEXT: decl %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax -; X86-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X86-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: shift_right_pow_2: @@ -66,7 +66,7 @@ define i16 @shift_right_pow_2(i16 %x, i16 %y) { ; X64-NEXT: shrl %cl, %eax ; X64-NEXT: decl %eax ; X64-NEXT: andl %edi, %eax -; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq %shr = lshr i16 -32768, %y %urem = urem i16 %x, %shr @@ -81,20 +81,20 @@ define i8 @and_pow_2(i8 %x, i8 %y) { ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: andb $4, %cl ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X86-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X86-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X86-NEXT: divb %cl ; X86-NEXT: movzbl %ah, %eax # NOREX -; X86-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X86-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X86-NEXT: retl ; ; X64-LABEL: and_pow_2: ; X64: # BB#0: ; X64-NEXT: andb $4, %sil ; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def> +; X64-NEXT: # kill: %eax<def> %eax<kill> %ax<def> ; X64-NEXT: divb %sil ; X64-NEXT: movzbl %ah, %eax # NOREX -; X64-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; X64-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; X64-NEXT: retq %and = and i8 %y, 4 %urem = urem i8 %x, %and diff --git a/test/CodeGen/X86/vec_fp_to_int.ll b/test/CodeGen/X86/vec_fp_to_int.ll index 2f52bab2803..1a6512d2f36 100644 --- a/test/CodeGen/X86/vec_fp_to_int.ll +++ b/test/CodeGen/X86/vec_fp_to_int.ll @@ -60,9 +60,9 @@ define <2 x i64> @fptosi_2f64_to_2i64(<2 x double> %a) { ; ; AVX512DQ-LABEL: fptosi_2f64_to_2i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -115,7 +115,7 @@ define <4 x i32> @fptosi_4f64_to_2i32(<2 x double> %a) { ; ; AVX-LABEL: fptosi_4f64_to_2i32: ; AVX: # BB#0: -; AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq @@ -217,9 +217,9 @@ define <4 x i64> @fptosi_4f64_to_4i64(<4 x double> %a) { ; ; AVX512DQ-LABEL: fptosi_4f64_to_4i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2qq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptosi_4f64_to_4i64: @@ -321,9 +321,9 @@ define <2 x i64> @fptoui_2f64_to_2i64(<2 x double> %a) { ; ; AVX512DQ-LABEL: fptoui_2f64_to_2i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2uqq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -388,7 +388,7 @@ define <4 x i32> @fptoui_2f64_to_4i32(<2 x double> %a) { ; ; AVX512F-LABEL: fptoui_2f64_to_4i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm0 ; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX512F-NEXT: vzeroupper @@ -401,7 +401,7 @@ define <4 x i32> @fptoui_2f64_to_4i32(<2 x double> %a) { ; ; AVX512DQ-LABEL: fptoui_2f64_to_4i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm0 ; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX512DQ-NEXT: vzeroupper @@ -467,9 +467,9 @@ define <4 x i32> @fptoui_2f64_to_2i32(<2 x double> %a) { ; ; AVX512F-LABEL: fptoui_2f64_to_2i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -480,9 +480,9 @@ define <4 x i32> @fptoui_2f64_to_2i32(<2 x double> %a) { ; ; AVX512DQ-LABEL: fptoui_2f64_to_2i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -542,30 +542,30 @@ define <4 x i32> @fptoui_4f64_to_2i32(<2 x double> %a) { ; ; AVX512F-LABEL: fptoui_4f64_to_2i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: fptoui_4f64_to_2i32: ; AVX512VL: # BB#0: -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512VL-NEXT: vcvttpd2udq %ymm0, %xmm0 ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: fptoui_4f64_to_2i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_4f64_to_2i32: ; AVX512VLDQ: # BB#0: -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512VLDQ-NEXT: vcvttpd2udq %ymm0, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -736,9 +736,9 @@ define <4 x i64> @fptoui_4f64_to_4i64(<4 x double> %a) { ; ; AVX512DQ-LABEL: fptoui_4f64_to_4i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2uqq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_4f64_to_4i64: @@ -812,9 +812,9 @@ define <4 x i32> @fptoui_4f64_to_4i32(<4 x double> %a) { ; ; AVX512F-LABEL: fptoui_4f64_to_4i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -826,9 +826,9 @@ define <4 x i32> @fptoui_4f64_to_4i32(<4 x double> %a) { ; ; AVX512DQ-LABEL: fptoui_4f64_to_4i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttpd2udq %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -980,16 +980,16 @@ define <2 x i64> @fptosi_4f32_to_2i64(<4 x float> %a) { ; ; AVX512DQ-LABEL: fptosi_4f32_to_2i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptosi_4f32_to_2i64: ; AVX512VLDQ: # BB#0: ; AVX512VLDQ-NEXT: vcvttps2qq %xmm0, %ymm0 -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq %cvt = fptosi <4 x float> %a to <4 x i64> @@ -1108,7 +1108,7 @@ define <4 x i64> @fptosi_4f32_to_4i64(<8 x float> %a) { ; AVX512DQ-LABEL: fptosi_4f32_to_4i64: ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptosi_4f32_to_4i64: @@ -1216,13 +1216,13 @@ define <4 x i64> @fptosi_8f32_to_4i64(<8 x float> %a) { ; AVX512DQ-LABEL: fptosi_8f32_to_4i64: ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptosi_8f32_to_4i64: ; AVX512VLDQ: # BB#0: ; AVX512VLDQ-NEXT: vcvttps2qq %ymm0, %zmm0 -; AVX512VLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VLDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VLDQ-NEXT: retq %cvt = fptosi <8 x float> %a to <8 x i64> %shuf = shufflevector <8 x i64> %cvt, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -1283,7 +1283,7 @@ define <2 x i32> @fptoui_2f32_to_2i32(<2 x float> %a) { ; ; AVX512F-LABEL: fptoui_2f32_to_2i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttps2udq %zmm0, %zmm0 ; AVX512F-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX512F-NEXT: vzeroupper @@ -1297,7 +1297,7 @@ define <2 x i32> @fptoui_2f32_to_2i32(<2 x float> %a) { ; ; AVX512DQ-LABEL: fptoui_2f32_to_2i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm0 ; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vzeroupper @@ -1351,9 +1351,9 @@ define <4 x i32> @fptoui_4f32_to_4i32(<4 x float> %a) { ; ; AVX512F-LABEL: fptoui_4f32_to_4i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1364,9 +1364,9 @@ define <4 x i32> @fptoui_4f32_to_4i32(<4 x float> %a) { ; ; AVX512DQ-LABEL: fptoui_4f32_to_4i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -1535,16 +1535,16 @@ define <2 x i64> @fptoui_4f32_to_2i64(<4 x float> %a) { ; ; AVX512DQ-LABEL: fptoui_4f32_to_2i64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_4f32_to_2i64: ; AVX512VLDQ: # BB#0: ; AVX512VLDQ-NEXT: vcvttps2uqq %xmm0, %ymm0 -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq %cvt = fptoui <4 x float> %a to <4 x i64> @@ -1648,9 +1648,9 @@ define <8 x i32> @fptoui_8f32_to_8i32(<8 x float> %a) { ; ; AVX512F-LABEL: fptoui_8f32_to_8i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: fptoui_8f32_to_8i32: @@ -1660,9 +1660,9 @@ define <8 x i32> @fptoui_8f32_to_8i32(<8 x float> %a) { ; ; AVX512DQ-LABEL: fptoui_8f32_to_8i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvttps2udq %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_8f32_to_8i32: @@ -1839,7 +1839,7 @@ define <4 x i64> @fptoui_4f32_to_4i64(<8 x float> %a) { ; AVX512DQ-LABEL: fptoui_4f32_to_4i64: ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_4f32_to_4i64: @@ -2017,13 +2017,13 @@ define <4 x i64> @fptoui_8f32_to_4i64(<8 x float> %a) { ; AVX512DQ-LABEL: fptoui_8f32_to_4i64: ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vcvttps2uqq %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: fptoui_8f32_to_4i64: ; AVX512VLDQ: # BB#0: ; AVX512VLDQ-NEXT: vcvttps2uqq %ymm0, %zmm0 -; AVX512VLDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VLDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VLDQ-NEXT: retq %cvt = fptoui <8 x float> %a to <8 x i64> %shuf = shufflevector <8 x i64> %cvt, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> diff --git a/test/CodeGen/X86/vec_ins_extract-1.ll b/test/CodeGen/X86/vec_ins_extract-1.ll index 1dc8b7abd20..6b930649d15 100644 --- a/test/CodeGen/X86/vec_ins_extract-1.ll +++ b/test/CodeGen/X86/vec_ins_extract-1.ll @@ -22,7 +22,7 @@ define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; ; X64-LABEL: t0: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: andl $3, %edi ; X64-NEXT: movl $76, -24(%rsp,%rdi,4) @@ -51,7 +51,7 @@ define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; ; X64-LABEL: t1: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movl $76, %eax ; X64-NEXT: pinsrd $0, %eax, %xmm0 ; X64-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) @@ -79,7 +79,7 @@ define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; ; X64-LABEL: t2: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: andl $3, %edi ; X64-NEXT: pinsrd $0, -24(%rsp,%rdi,4), %xmm0 @@ -106,7 +106,7 @@ define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind { ; ; X64-LABEL: t3: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: andl $3, %edi ; X64-NEXT: movss %xmm0, -24(%rsp,%rdi,4) diff --git a/test/CodeGen/X86/vec_insert-4.ll b/test/CodeGen/X86/vec_insert-4.ll index 82627c54e66..aebac7f9d44 100644 --- a/test/CodeGen/X86/vec_insert-4.ll +++ b/test/CodeGen/X86/vec_insert-4.ll @@ -26,7 +26,7 @@ define <8 x float> @f(<8 x float> %a, i32 %b) nounwind { ; X64-NEXT: movq %rsp, %rbp ; X64-NEXT: andq $-32, %rsp ; X64-NEXT: subq $64, %rsp -; X64-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) ; X64-NEXT: movaps %xmm0, (%rsp) ; X64-NEXT: andl $7, %edi diff --git a/test/CodeGen/X86/vec_insert-5.ll b/test/CodeGen/X86/vec_insert-5.ll index e7c06a99df9..64e8bbf5456 100644 --- a/test/CodeGen/X86/vec_insert-5.ll +++ b/test/CodeGen/X86/vec_insert-5.ll @@ -17,7 +17,7 @@ define void @t1(i32 %a, x86_mmx* %P) nounwind { ; ; X64-LABEL: t1: ; X64: # BB#0: -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: shll $12, %edi ; X64-NEXT: movq %rdi, %xmm0 ; X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] diff --git a/test/CodeGen/X86/vec_insert-7.ll b/test/CodeGen/X86/vec_insert-7.ll index 02db6e6d875..a600d20902d 100644 --- a/test/CodeGen/X86/vec_insert-7.ll +++ b/test/CodeGen/X86/vec_insert-7.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64 -; MMX insertelement is not available; these are promoted to XMM. +; MMX insertelement is not available; these are promoted to xmm. ; (Without SSE they are split to two ints, and the code is much better.) define x86_mmx @mmx_movzl(x86_mmx %x) nounwind { diff --git a/test/CodeGen/X86/vec_insert-8.ll b/test/CodeGen/X86/vec_insert-8.ll index 4074b6d3235..5f80225a24d 100644 --- a/test/CodeGen/X86/vec_insert-8.ll +++ b/test/CodeGen/X86/vec_insert-8.ll @@ -23,7 +23,7 @@ define <4 x i32> @var_insert(<4 x i32> %x, i32 %val, i32 %idx) nounwind { ; ; X64-LABEL: var_insert: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; X64-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: andl $3, %esi ; X64-NEXT: movl %edi, -24(%rsp,%rsi,4) @@ -51,7 +51,7 @@ define i32 @var_extract(<4 x i32> %x, i32 %idx) nounwind { ; ; X64-LABEL: var_extract: ; X64: # BB#0: # %entry -; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; X64-NEXT: andl $3, %edi ; X64-NEXT: movl -24(%rsp,%rdi,4), %eax diff --git a/test/CodeGen/X86/vec_insert-mmx.ll b/test/CodeGen/X86/vec_insert-mmx.ll index fffafe7697d..ad857636ebb 100644 --- a/test/CodeGen/X86/vec_insert-mmx.ll +++ b/test/CodeGen/X86/vec_insert-mmx.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse4.1 | FileCheck %s --check-prefix=X64 -; This is not an MMX operation; promoted to XMM. +; This is not an MMX operation; promoted to xmm. define x86_mmx @t0(i32 %A) nounwind { ; X32-LABEL: t0: ; X32: ## BB#0: @@ -16,7 +16,7 @@ define x86_mmx @t0(i32 %A) nounwind { ; ; X64-LABEL: t0: ; X64: ## BB#0: -; X64-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-NEXT: ## kill: %edi<def> %edi<kill> %rdi<def> ; X64-NEXT: movq %rdi, %xmm0 ; X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] diff --git a/test/CodeGen/X86/vec_int_to_fp.ll b/test/CodeGen/X86/vec_int_to_fp.ll index 52bad6456f5..afcbc9a9d17 100644 --- a/test/CodeGen/X86/vec_int_to_fp.ll +++ b/test/CodeGen/X86/vec_int_to_fp.ll @@ -58,9 +58,9 @@ define <2 x double> @sitofp_2i64_to_2f64(<2 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_2i64_to_2f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -96,7 +96,7 @@ define <2 x double> @sitofp_4i32_to_2f64(<4 x i32> %a) { ; AVX-LABEL: sitofp_4i32_to_2f64: ; AVX: # BB#0: ; AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq %cvt = sitofp <4 x i32> %a to <4 x double> @@ -134,7 +134,7 @@ define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX1: # BB#0: ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -142,7 +142,7 @@ define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -150,7 +150,7 @@ define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = sitofp <8 x i16> %a to <8 x double> @@ -190,7 +190,7 @@ define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX1: # BB#0: ; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -198,7 +198,7 @@ define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -206,7 +206,7 @@ define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = sitofp <16 x i8> %a to <16 x double> @@ -301,9 +301,9 @@ define <4 x double> @sitofp_4i64_to_4f64(<4 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_4i64_to_4f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: sitofp_4i64_to_4f64: @@ -377,7 +377,7 @@ define <4 x double> @sitofp_8i16_to_4f64(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = sitofp <8 x i16> %a to <8 x double> %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -432,7 +432,7 @@ define <4 x double> @sitofp_16i8_to_4f64(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = sitofp <16 x i8> %a to <16 x double> %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -492,9 +492,9 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_2i64_to_2f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -531,9 +531,9 @@ define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) { ; ; AVX512F-LABEL: uitofp_2i32_to_2f64: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -544,9 +544,9 @@ define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) { ; ; AVX512DQ-LABEL: uitofp_2i32_to_2f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -580,7 +580,7 @@ define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) { ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -594,37 +594,37 @@ define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) { ; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7] ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX2-NEXT: vaddpd %ymm0, %ymm1, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; ; AVX512F-LABEL: uitofp_4i32_to_2f64: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_4i32_to_2f64: ; AVX512VL: # BB#0: ; AVX512VL-NEXT: vcvtudq2pd %xmm0, %ymm0 -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; ; AVX512DQ-LABEL: uitofp_4i32_to_2f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_4i32_to_2f64: ; AVX512VLDQ: # BB#0: ; AVX512VLDQ-NEXT: vcvtudq2pd %xmm0, %ymm0 -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq %cvt = uitofp <4 x i32> %a to <4 x double> @@ -662,7 +662,7 @@ define <2 x double> @uitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX1: # BB#0: ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -670,7 +670,7 @@ define <2 x double> @uitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -678,7 +678,7 @@ define <2 x double> @uitofp_8i16_to_2f64(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = uitofp <8 x i16> %a to <8 x double> @@ -718,7 +718,7 @@ define <2 x double> @uitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX1: # BB#0: ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -726,7 +726,7 @@ define <2 x double> @uitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -734,7 +734,7 @@ define <2 x double> @uitofp_16i8_to_2f64(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = uitofp <16 x i8> %a to <16 x double> @@ -823,9 +823,9 @@ define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_4i64_to_4f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_4i64_to_4f64: @@ -883,9 +883,9 @@ define <4 x double> @uitofp_4i32_to_4f64(<4 x i32> %a) { ; ; AVX512F-LABEL: uitofp_4i32_to_4f64: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_4i32_to_4f64: @@ -895,9 +895,9 @@ define <4 x double> @uitofp_4i32_to_4f64(<4 x i32> %a) { ; ; AVX512DQ-LABEL: uitofp_4i32_to_4f64: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_4i32_to_4f64: @@ -956,7 +956,7 @@ define <4 x double> @uitofp_8i16_to_4f64(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = uitofp <8 x i16> %a to <8 x double> %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -1013,7 +1013,7 @@ define <4 x double> @uitofp_16i8_to_4f64(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512-NEXT: vcvtdq2pd %ymm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = uitofp <16 x i8> %a to <16 x double> %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -1072,9 +1072,9 @@ define <4 x float> @sitofp_2i64_to_4f32(<2 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_2i64_to_4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -1131,7 +1131,7 @@ define <4 x float> @sitofp_2i64_to_4f32_zero(<2 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_2i64_to_4f32_zero: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 ; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX512DQ-NEXT: vzeroupper @@ -1197,15 +1197,15 @@ define <4 x float> @sitofp_4i64_to_4f32_undef(<2 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_4i64_to_4f32_undef: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: sitofp_4i64_to_4f32_undef: ; AVX512VLDQ: # BB#0: -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -1261,7 +1261,7 @@ define <4 x float> @sitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -1269,7 +1269,7 @@ define <4 x float> @sitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1277,7 +1277,7 @@ define <4 x float> @sitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = sitofp <8 x i16> %a to <8 x float> @@ -1320,7 +1320,7 @@ define <4 x float> @sitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX1-NEXT: vpmovsxbd %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -1328,7 +1328,7 @@ define <4 x float> @sitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovsxbd %xmm0, %ymm0 ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1336,7 +1336,7 @@ define <4 x float> @sitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = sitofp <16 x i8> %a to <16 x float> @@ -1436,9 +1436,9 @@ define <4 x float> @sitofp_4i64_to_4f32(<4 x i64> %a) { ; ; AVX512DQ-LABEL: sitofp_4i64_to_4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -1576,7 +1576,7 @@ define <8 x float> @sitofp_16i8_to_8f32(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = sitofp <16 x i8> %a to <16 x float> %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -1691,9 +1691,9 @@ define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_2i64_to_4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -1800,7 +1800,7 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_2i64_to_2f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; AVX512DQ-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX512DQ-NEXT: vzeroupper @@ -1927,15 +1927,15 @@ define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_4i64_to_4f32_undef: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_4i64_to_4f32_undef: ; AVX512VLDQ: # BB#0: -; AVX512VLDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512VLDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -1979,9 +1979,9 @@ define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) { ; ; AVX512F-LABEL: uitofp_4i32_to_4f32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1992,9 +1992,9 @@ define <4 x float> @uitofp_4i32_to_4f32(<4 x i32> %a) { ; ; AVX512DQ-LABEL: uitofp_4i32_to_4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -2039,7 +2039,7 @@ define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -2047,7 +2047,7 @@ define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -2055,7 +2055,7 @@ define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = uitofp <8 x i16> %a to <8 x float> @@ -2098,7 +2098,7 @@ define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -2106,7 +2106,7 @@ define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX2: # BB#0: ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-NEXT: vcvtdq2ps %ymm0, %ymm0 -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -2114,7 +2114,7 @@ define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = uitofp <16 x i8> %a to <16 x float> @@ -2361,9 +2361,9 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { ; ; AVX512DQ-LABEL: uitofp_4i64_to_4f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -2425,9 +2425,9 @@ define <8 x float> @uitofp_8i32_to_8f32(<8 x i32> %a) { ; ; AVX512F-LABEL: uitofp_8i32_to_8f32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_8i32_to_8f32: @@ -2437,9 +2437,9 @@ define <8 x float> @uitofp_8i32_to_8f32(<8 x i32> %a) { ; ; AVX512DQ-LABEL: uitofp_8i32_to_8f32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_8i32_to_8f32: @@ -2556,7 +2556,7 @@ define <8 x float> @uitofp_16i8_to_8f32(<16 x i8> %a) { ; AVX512: # BB#0: ; AVX512-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512-NEXT: vcvtdq2ps %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %cvt = uitofp <16 x i8> %a to <16 x float> %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -2614,7 +2614,7 @@ define <2 x double> @sitofp_load_2i64_to_2f64(<2 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -2778,7 +2778,7 @@ define <4 x double> @sitofp_load_4i64_to_4f64(<4 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: sitofp_load_4i64_to_4f64: @@ -2910,7 +2910,7 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 ; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -2952,7 +2952,7 @@ define <2 x double> @uitofp_load_2i32_to_2f64(<2 x i32> *%a) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -2965,7 +2965,7 @@ define <2 x double> @uitofp_load_2i32_to_2f64(<2 x i32> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -3108,7 +3108,7 @@ define <4 x double> @uitofp_load_4i64_to_4f64(<4 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtuqq2pd %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_load_4i64_to_4f64: @@ -3172,7 +3172,7 @@ define <4 x double> @uitofp_load_4i32_to_4f64(<4 x i32> *%a) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_load_4i32_to_4f64: @@ -3184,7 +3184,7 @@ define <4 x double> @uitofp_load_4i32_to_4f64(<4 x i32> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 ; AVX512DQ-NEXT: vcvtudq2pd %ymm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_load_4i32_to_4f64: @@ -3342,7 +3342,7 @@ define <4 x float> @sitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -3933,7 +3933,7 @@ define <4 x float> @uitofp_load_4i64_to_4f32(<4 x i64> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -3986,7 +3986,7 @@ define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -3999,7 +3999,7 @@ define <4 x float> @uitofp_load_4i32_to_4f32(<4 x i32> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %xmm0 ; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -4575,7 +4575,7 @@ define <8 x float> @uitofp_load_8i32_to_8f32(<8 x i32> *%a) { ; AVX512F: # BB#0: ; AVX512F-NEXT: vmovaps (%rdi), %ymm0 ; AVX512F-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: uitofp_load_8i32_to_8f32: @@ -4587,7 +4587,7 @@ define <8 x float> @uitofp_load_8i32_to_8f32(<8 x i32> *%a) { ; AVX512DQ: # BB#0: ; AVX512DQ-NEXT: vmovaps (%rdi), %ymm0 ; AVX512DQ-NEXT: vcvtudq2ps %zmm0, %zmm0 -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512DQ-NEXT: retq ; ; AVX512VLDQ-LABEL: uitofp_load_8i32_to_8f32: diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll index f8221fda52b..f861391f166 100644 --- a/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/test/CodeGen/X86/vec_ss_load_fold.ll @@ -17,7 +17,7 @@ define i16 @test1(float %f) nounwind { ; X32-NEXT: minss LCPI0_2, %xmm0 ; X32-NEXT: maxss %xmm1, %xmm0 ; X32-NEXT: cvttss2si %xmm0, %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test1: @@ -29,7 +29,7 @@ define i16 @test1(float %f) nounwind { ; X64-NEXT: minss {{.*}}(%rip), %xmm0 ; X64-NEXT: maxss %xmm1, %xmm0 ; X64-NEXT: cvttss2si %xmm0, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32_AVX1-LABEL: test1: @@ -42,7 +42,7 @@ define i16 @test1(float %f) nounwind { ; X32_AVX1-NEXT: vminss LCPI0_2, %xmm0, %xmm0 ; X32_AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X32_AVX1-NEXT: vcvttss2si %xmm0, %eax -; X32_AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32_AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32_AVX1-NEXT: retl ; ; X64_AVX1-LABEL: test1: @@ -54,7 +54,7 @@ define i16 @test1(float %f) nounwind { ; X64_AVX1-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0 ; X64_AVX1-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X64_AVX1-NEXT: vcvttss2si %xmm0, %eax -; X64_AVX1-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64_AVX1-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64_AVX1-NEXT: retq ; ; X32_AVX512-LABEL: test1: @@ -67,7 +67,7 @@ define i16 @test1(float %f) nounwind { ; X32_AVX512-NEXT: vminss LCPI0_2, %xmm0, %xmm0 ; X32_AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X32_AVX512-NEXT: vcvttss2si %xmm0, %eax -; X32_AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32_AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32_AVX512-NEXT: retl ; ; X64_AVX512-LABEL: test1: @@ -79,7 +79,7 @@ define i16 @test1(float %f) nounwind { ; X64_AVX512-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0 ; X64_AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X64_AVX512-NEXT: vcvttss2si %xmm0, %eax -; X64_AVX512-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64_AVX512-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64_AVX512-NEXT: retq %tmp = insertelement <4 x float> undef, float %f, i32 0 ; <<4 x float>> [#uses=1] %tmp10 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1] @@ -104,7 +104,7 @@ define i16 @test2(float %f) nounwind { ; X32-NEXT: xorps %xmm1, %xmm1 ; X32-NEXT: maxss %xmm1, %xmm0 ; X32-NEXT: cvttss2si %xmm0, %eax -; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32-NEXT: retl ; ; X64-LABEL: test2: @@ -115,7 +115,7 @@ define i16 @test2(float %f) nounwind { ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: maxss %xmm1, %xmm0 ; X64-NEXT: cvttss2si %xmm0, %eax -; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64-NEXT: retq ; ; X32_AVX-LABEL: test2: @@ -127,7 +127,7 @@ define i16 @test2(float %f) nounwind { ; X32_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; X32_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X32_AVX-NEXT: vcvttss2si %xmm0, %eax -; X32_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X32_AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X32_AVX-NEXT: retl ; ; X64_AVX-LABEL: test2: @@ -138,7 +138,7 @@ define i16 @test2(float %f) nounwind { ; X64_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; X64_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0 ; X64_AVX-NEXT: vcvttss2si %xmm0, %eax -; X64_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; X64_AVX-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; X64_AVX-NEXT: retq %tmp28 = fsub float %f, 1.000000e+00 ; <float> [#uses=1] %tmp37 = fmul float %tmp28, 5.000000e-01 ; <float> [#uses=1] diff --git a/test/CodeGen/X86/vector-bitreverse.ll b/test/CodeGen/X86/vector-bitreverse.ll index 485911280c6..646e5c3c306 100644 --- a/test/CodeGen/X86/vector-bitreverse.ll +++ b/test/CodeGen/X86/vector-bitreverse.ll @@ -50,7 +50,7 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { ; XOP-NEXT: vmovd %edi, %xmm0 ; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0 ; XOP-NEXT: vpextrb $0, %xmm0, %eax -; XOP-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; XOP-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; XOP-NEXT: retq %b = call i8 @llvm.bitreverse.i8(i8 %a) ret i8 %b @@ -59,7 +59,7 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { define i16 @test_bitreverse_i16(i16 %a) nounwind { ; SSE-LABEL: test_bitreverse_i16: ; SSE: # BB#0: -; SSE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE-NEXT: rolw $8, %di ; SSE-NEXT: movl %edi, %eax ; SSE-NEXT: andl $3855, %eax # imm = 0xF0F @@ -77,12 +77,12 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; SSE-NEXT: andl $43690, %eax # imm = 0xAAAA ; SSE-NEXT: shrl %eax ; SSE-NEXT: leal (%rax,%rcx,2), %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: test_bitreverse_i16: ; AVX: # BB#0: -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: rolw $8, %di ; AVX-NEXT: movl %edi, %eax ; AVX-NEXT: andl $3855, %eax # imm = 0xF0F @@ -100,7 +100,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; AVX-NEXT: andl $43690, %eax # imm = 0xAAAA ; AVX-NEXT: shrl %eax ; AVX-NEXT: leal (%rax,%rcx,2), %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: retq ; ; XOP-LABEL: test_bitreverse_i16: @@ -108,7 +108,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; XOP-NEXT: vmovd %edi, %xmm0 ; XOP-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0 ; XOP-NEXT: vmovd %xmm0, %eax -; XOP-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; XOP-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; XOP-NEXT: retq %b = call i16 @llvm.bitreverse.i16(i16 %a) ret i16 %b @@ -117,7 +117,7 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { define i32 @test_bitreverse_i32(i32 %a) nounwind { ; SSE-LABEL: test_bitreverse_i32: ; SSE: # BB#0: -; SSE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE-NEXT: bswapl %edi ; SSE-NEXT: movl %edi, %eax ; SSE-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F @@ -139,7 +139,7 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; ; AVX-LABEL: test_bitreverse_i32: ; AVX: # BB#0: -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: bswapl %edi ; AVX-NEXT: movl %edi, %eax ; AVX-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F diff --git a/test/CodeGen/X86/vector-compare-all_of.ll b/test/CodeGen/X86/vector-compare-all_of.ll index f3646e1346c..d9339299ea1 100644 --- a/test/CodeGen/X86/vector-compare-all_of.ll +++ b/test/CodeGen/X86/vector-compare-all_of.ll @@ -624,7 +624,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; SSE-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; SSE-NEXT: movl $-1, %eax ; SSE-NEXT: cmovnel %ecx, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: test_v8i16_sext: @@ -635,7 +635,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; AVX-NEXT: movl $-1, %eax ; AVX-NEXT: cmovnel %ecx, %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: retq ; ; AVX512-LABEL: test_v8i16_sext: @@ -649,7 +649,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: retq %c = icmp sgt <8 x i16> %a0, %a1 %s = sext <8 x i1> %c to <8 x i16> @@ -674,7 +674,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; SSE-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; SSE-NEXT: movl $-1, %eax ; SSE-NEXT: cmovnel %ecx, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v16i16_sext: @@ -692,7 +692,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmovd %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -703,7 +703,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX2-NEXT: xorl %eax, %eax ; AVX2-NEXT: cmpl $-1, %ecx ; AVX2-NEXT: cmovel %ecx, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -720,7 +720,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <16 x i16> %a0, %a1 @@ -748,7 +748,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; SSE-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; SSE-NEXT: movl $-1, %eax ; SSE-NEXT: cmovnel %ecx, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v16i16_legal_sext: @@ -763,7 +763,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX1-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: movl $-1, %eax ; AVX1-NEXT: cmovnel %ecx, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -777,7 +777,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; AVX2-NEXT: movl $-1, %eax ; AVX2-NEXT: cmovnel %ecx, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -795,7 +795,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax ; AVX512-NEXT: movsbl %al, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <16 x i16> %a0, %a1 @@ -822,7 +822,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; SSE-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; SSE-NEXT: movl $-1, %eax ; SSE-NEXT: cmovnel %ecx, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: test_v16i8_sext: @@ -833,7 +833,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; AVX-NEXT: movl $-1, %eax ; AVX-NEXT: cmovnel %ecx, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: retq ; ; AVX512-LABEL: test_v16i8_sext: @@ -849,7 +849,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512-NEXT: retq %c = icmp sgt <16 x i8> %a0, %a1 %s = sext <16 x i1> %c to <16 x i8> @@ -876,7 +876,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; SSE-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; SSE-NEXT: movl $-1, %eax ; SSE-NEXT: cmovnel %ecx, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v32i8_sext: @@ -896,7 +896,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpextrb $0, %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -907,7 +907,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX2-NEXT: xorl %eax, %eax ; AVX2-NEXT: cmpl $-1, %ecx ; AVX2-NEXT: cmovel %ecx, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -926,7 +926,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <32 x i8> %a0, %a1 diff --git a/test/CodeGen/X86/vector-compare-any_of.ll b/test/CodeGen/X86/vector-compare-any_of.ll index e746c7e9adc..1a6a1c17bc0 100644 --- a/test/CodeGen/X86/vector-compare-any_of.ll +++ b/test/CodeGen/X86/vector-compare-any_of.ll @@ -578,7 +578,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: negl %eax ; SSE-NEXT: sbbl %eax, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: test_v8i16_sext: @@ -587,7 +587,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX-NEXT: vpmovmskb %xmm0, %eax ; AVX-NEXT: negl %eax ; AVX-NEXT: sbbl %eax, %eax -; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX-NEXT: retq ; ; AVX512-LABEL: test_v8i16_sext: @@ -601,7 +601,7 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: retq %c = icmp sgt <8 x i16> %a0, %a1 %s = sext <8 x i1> %c to <8 x i16> @@ -624,7 +624,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: negl %eax ; SSE-NEXT: sbbl %eax, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v16i16_sext: @@ -642,7 +642,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmovd %xmm0, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -652,7 +652,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: negl %eax ; AVX2-NEXT: sbbl %eax, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -669,7 +669,7 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <16 x i16> %a0, %a1 @@ -695,7 +695,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: negl %eax ; SSE-NEXT: sbbl %eax, %eax -; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; SSE-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v16i16_legal_sext: @@ -708,7 +708,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: negl %eax ; AVX1-NEXT: sbbl %eax, %eax -; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX1-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -720,7 +720,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX2-NEXT: vpmovmskb %xmm0, %eax ; AVX2-NEXT: negl %eax ; AVX2-NEXT: sbbl %eax, %eax -; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX2-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -738,7 +738,7 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax ; AVX512-NEXT: movsbl %al, %eax -; AVX512-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <16 x i16> %a0, %a1 @@ -763,7 +763,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: negl %eax ; SSE-NEXT: sbbl %eax, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX-LABEL: test_v16i8_sext: @@ -772,7 +772,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX-NEXT: vpmovmskb %xmm0, %eax ; AVX-NEXT: negl %eax ; AVX-NEXT: sbbl %eax, %eax -; AVX-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX-NEXT: retq ; ; AVX512-LABEL: test_v16i8_sext: @@ -788,7 +788,7 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512-NEXT: retq %c = icmp sgt <16 x i8> %a0, %a1 %s = sext <16 x i1> %c to <16 x i8> @@ -813,7 +813,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: negl %eax ; SSE-NEXT: sbbl %eax, %eax -; SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; SSE-NEXT: retq ; ; AVX1-LABEL: test_v32i8_sext: @@ -833,7 +833,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpextrb $0, %xmm0, %eax -; AVX1-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX1-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; @@ -843,7 +843,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: negl %eax ; AVX2-NEXT: sbbl %eax, %eax -; AVX2-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX2-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -862,7 +862,7 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <32 x i8> %a0, %a1 diff --git a/test/CodeGen/X86/vector-compare-results.ll b/test/CodeGen/X86/vector-compare-results.ll index b2dfaaa6a4c..3ceef9e8a2c 100644 --- a/test/CodeGen/X86/vector-compare-results.ll +++ b/test/CodeGen/X86/vector-compare-results.ll @@ -145,7 +145,7 @@ define <4 x i1> @test_cmp_v4f64(<4 x double> %a0, <4 x double> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = fcmp ogt <4 x double> %a0, %a1 @@ -181,7 +181,7 @@ define <8 x i1> @test_cmp_v8f32(<8 x float> %a0, <8 x float> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = fcmp ogt <8 x float> %a0, %a1 @@ -244,7 +244,7 @@ define <4 x i1> @test_cmp_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = icmp sgt <4 x i64> %a0, %a1 @@ -281,7 +281,7 @@ define <8 x i1> @test_cmp_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = icmp sgt <8 x i32> %a0, %a1 @@ -334,7 +334,7 @@ define <16 x i1> @test_cmp_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = icmp sgt <16 x i16> %a0, %a1 @@ -632,7 +632,7 @@ define <8 x i1> @test_cmp_v8f64(<8 x double> %a0, <8 x double> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vcmpltpd %zmm0, %zmm1, %k0 ; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = fcmp ogt <8 x double> %a0, %a1 @@ -695,7 +695,7 @@ define <16 x i1> @test_cmp_v16f32(<16 x float> %a0, <16 x float> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vcmpltps %zmm0, %zmm1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = fcmp ogt <16 x float> %a0, %a1 @@ -809,7 +809,7 @@ define <8 x i1> @test_cmp_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = icmp sgt <8 x i64> %a0, %a1 @@ -875,7 +875,7 @@ define <16 x i1> @test_cmp_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = icmp sgt <16 x i32> %a0, %a1 @@ -1146,7 +1146,7 @@ define <32 x i1> @test_cmp_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpgtw %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq %1 = icmp sgt <32 x i16> %a0, %a1 ret <32 x i1> %1 @@ -1973,7 +1973,7 @@ define <64 x i1> @test_cmp_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512F-NEXT: vextracti128 $1, %ymm4, %xmm3 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vmovdqa %xmm4, %xmm2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1984,7 +1984,7 @@ define <64 x i1> @test_cmp_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; AVX512DQ-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm0 ; AVX512DQ-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512DQ-NEXT: vextracti128 $1, %ymm4, %xmm3 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vmovdqa %xmm4, %xmm2 ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq @@ -2094,7 +2094,7 @@ define <16 x i1> @test_cmp_v16f64(<16 x double> %a0, <16 x double> %a1) nounwind ; AVX512BW-NEXT: vcmpltpd %zmm1, %zmm3, %k1 ; AVX512BW-NEXT: kunpckbw %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = fcmp ogt <16 x double> %a0, %a1 @@ -2657,7 +2657,7 @@ define <32 x i1> @test_cmp_v32f32(<32 x float> %a0, <32 x float> %a1) nounwind { ; AVX512BW-NEXT: vcmpltps %zmm1, %zmm3, %k1 ; AVX512BW-NEXT: kunpckwd %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq %1 = fcmp ogt <32 x float> %a0, %a1 ret <32 x i1> %1 @@ -2853,7 +2853,7 @@ define <16 x i1> @test_cmp_v16i64(<16 x i64> %a0, <16 x i64> %a1) nounwind { ; AVX512BW-NEXT: vpcmpgtq %zmm3, %zmm1, %k1 ; AVX512BW-NEXT: kunpckbw %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq %1 = icmp sgt <16 x i64> %a0, %a1 @@ -3408,7 +3408,7 @@ define <32 x i1> @test_cmp_v32i32(<32 x i32> %a0, <32 x i32> %a1) nounwind { ; AVX512BW-NEXT: vpcmpgtd %zmm3, %zmm1, %k1 ; AVX512BW-NEXT: kunpckwd %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq %1 = icmp sgt <32 x i32> %a0, %a1 ret <32 x i1> %1 @@ -4535,8 +4535,8 @@ define <64 x i1> @test_cmp_v64i16(<64 x i16> %a0, <64 x i16> %a1) nounwind { ; AVX512F-NEXT: vpcmpgtb %ymm0, %ymm6, %ymm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512F-NEXT: vextracti128 $1, %ymm2, %xmm3 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> -; AVX512F-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> +; AVX512F-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -4822,8 +4822,8 @@ define <64 x i1> @test_cmp_v64i16(<64 x i16> %a0, <64 x i16> %a1) nounwind { ; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm6, %ymm0 ; AVX512DQ-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512DQ-NEXT: vextracti128 $1, %ymm2, %xmm3 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> -; AVX512DQ-NEXT: # kill: %XMM2<def> %XMM2<kill> %YMM2<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> +; AVX512DQ-NEXT: # kill: %xmm2<def> %xmm2<kill> %ymm2<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -7280,7 +7280,7 @@ define <32 x i1> @test_cmp_v32f64(<32 x double> %a0, <32 x double> %a1) nounwind ; AVX512BW-NEXT: kunpckbw %k1, %k2, %k1 ; AVX512BW-NEXT: kunpckwd %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq %1 = fcmp ogt <32 x double> %a0, %a1 ret <32 x i1> %1 @@ -8165,7 +8165,7 @@ define <32 x i1> @test_cmp_v32i64(<32 x i64> %a0, <32 x i64> %a1) nounwind { ; AVX512BW-NEXT: kunpckbw %k1, %k2, %k1 ; AVX512BW-NEXT: kunpckwd %k0, %k1, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq %1 = icmp sgt <32 x i64> %a0, %a1 ret <32 x i1> %1 diff --git a/test/CodeGen/X86/vector-extend-inreg.ll b/test/CodeGen/X86/vector-extend-inreg.ll index 91806a41eb7..e111dcb4102 100644 --- a/test/CodeGen/X86/vector-extend-inreg.ll +++ b/test/CodeGen/X86/vector-extend-inreg.ll @@ -47,7 +47,7 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) noun ; X64-SSE-NEXT: movq %rsp, %rbp ; X64-SSE-NEXT: andq $-128, %rsp ; X64-SSE-NEXT: subq $256, %rsp # imm = 0x100 -; X64-SSE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-SSE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-SSE-NEXT: psrldq {{.*#+}} xmm7 = xmm7[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero ; X64-SSE-NEXT: xorps %xmm0, %xmm0 ; X64-SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) @@ -99,7 +99,7 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) noun ; X64-AVX-NEXT: movq %rsp, %rbp ; X64-AVX-NEXT: andq $-128, %rsp ; X64-AVX-NEXT: subq $256, %rsp # imm = 0x100 -; X64-AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; X64-AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; X64-AVX-NEXT: vpermpd {{.*#+}} ymm0 = ymm3[3,1,2,3] ; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; X64-AVX-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] diff --git a/test/CodeGen/X86/vector-half-conversions.ll b/test/CodeGen/X86/vector-half-conversions.ll index 9feff88a576..dba0b084629 100644 --- a/test/CodeGen/X86/vector-half-conversions.ll +++ b/test/CodeGen/X86/vector-half-conversions.ll @@ -28,7 +28,7 @@ define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind { ; AVX1-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rdx ; AVX1-NEXT: movswl %ax, %esi -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $48, %rdx @@ -55,7 +55,7 @@ define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind { ; AVX2-NEXT: movq %rax, %rcx ; AVX2-NEXT: movq %rax, %rdx ; AVX2-NEXT: movswl %ax, %esi -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: shrq $32, %rcx ; AVX2-NEXT: shrq $48, %rdx @@ -82,7 +82,7 @@ define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind { ; AVX512F-NEXT: movq %rax, %rcx ; AVX512F-NEXT: movq %rax, %rdx ; AVX512F-NEXT: movswl %ax, %esi -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: shrq $32, %rcx ; AVX512F-NEXT: shrq $48, %rdx @@ -109,7 +109,7 @@ define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind { ; AVX512VL-NEXT: movq %rax, %rcx ; AVX512VL-NEXT: movq %rax, %rdx ; AVX512VL-NEXT: movswl %ax, %esi -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: shrq $32, %rcx ; AVX512VL-NEXT: shrq $48, %rdx @@ -140,7 +140,7 @@ define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind { ; AVX1-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rdx ; AVX1-NEXT: movswl %ax, %esi -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $48, %rdx @@ -166,7 +166,7 @@ define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind { ; AVX2-NEXT: movq %rax, %rcx ; AVX2-NEXT: movq %rax, %rdx ; AVX2-NEXT: movswl %ax, %esi -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: shrq $32, %rcx ; AVX2-NEXT: shrq $48, %rdx @@ -192,7 +192,7 @@ define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind { ; AVX512F-NEXT: movq %rax, %rcx ; AVX512F-NEXT: movq %rax, %rdx ; AVX512F-NEXT: movswl %ax, %esi -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: shrq $32, %rcx ; AVX512F-NEXT: shrq $48, %rdx @@ -220,7 +220,7 @@ define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind { ; AVX512VL-NEXT: movq %rax, %rcx ; AVX512VL-NEXT: movq %rax, %rdx ; AVX512VL-NEXT: movswl %ax, %esi -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: shrq $32, %rcx ; AVX512VL-NEXT: shrq $48, %rdx @@ -252,7 +252,7 @@ define <8 x float> @cvt_8i16_to_8f32(<8 x i16> %a0) nounwind { ; ALL-NEXT: movq %rdx, %r8 ; ALL-NEXT: movq %rdx, %r10 ; ALL-NEXT: movswl %dx, %r9d -; ALL-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> +; ALL-NEXT: # kill: %edx<def> %edx<kill> %rdx<kill> ; ALL-NEXT: shrl $16, %edx ; ALL-NEXT: shrq $32, %r8 ; ALL-NEXT: shrq $48, %r10 @@ -260,7 +260,7 @@ define <8 x float> @cvt_8i16_to_8f32(<8 x i16> %a0) nounwind { ; ALL-NEXT: movq %rdi, %rax ; ALL-NEXT: movq %rdi, %rsi ; ALL-NEXT: movswl %di, %ecx -; ALL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<kill> +; ALL-NEXT: # kill: %edi<def> %edi<kill> %rdi<kill> ; ALL-NEXT: shrl $16, %edi ; ALL-NEXT: shrq $32, %rax ; ALL-NEXT: shrq $48, %rsi @@ -313,7 +313,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX1-NEXT: movswl %cx, %ecx ; AVX1-NEXT: vmovd %ecx, %xmm9 ; AVX1-NEXT: movswl %ax, %ecx -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: cwtl ; AVX1-NEXT: vmovd %eax, %xmm10 @@ -328,7 +328,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX1-NEXT: movswl %cx, %ecx ; AVX1-NEXT: vmovd %ecx, %xmm13 ; AVX1-NEXT: movswl %ax, %ecx -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: cwtl ; AVX1-NEXT: vmovd %eax, %xmm14 @@ -343,7 +343,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX1-NEXT: movswl %cx, %ecx ; AVX1-NEXT: vmovd %ecx, %xmm3 ; AVX1-NEXT: movswl %ax, %ecx -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: cwtl ; AVX1-NEXT: vmovd %eax, %xmm4 @@ -408,7 +408,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX2-NEXT: movswl %cx, %ecx ; AVX2-NEXT: vmovd %ecx, %xmm9 ; AVX2-NEXT: movswl %ax, %ecx -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: cwtl ; AVX2-NEXT: vmovd %eax, %xmm10 @@ -423,7 +423,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX2-NEXT: movswl %cx, %ecx ; AVX2-NEXT: vmovd %ecx, %xmm13 ; AVX2-NEXT: movswl %ax, %ecx -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: cwtl ; AVX2-NEXT: vmovd %eax, %xmm14 @@ -438,7 +438,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX2-NEXT: movswl %cx, %ecx ; AVX2-NEXT: vmovd %ecx, %xmm3 ; AVX2-NEXT: movswl %ax, %ecx -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: cwtl ; AVX2-NEXT: vmovd %eax, %xmm4 @@ -503,7 +503,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: movswl %cx, %ecx ; AVX512F-NEXT: vmovd %ecx, %xmm9 ; AVX512F-NEXT: movswl %ax, %ecx -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: cwtl ; AVX512F-NEXT: vmovd %eax, %xmm11 @@ -518,7 +518,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: movswl %cx, %ecx ; AVX512F-NEXT: vmovd %ecx, %xmm14 ; AVX512F-NEXT: movswl %ax, %ecx -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: cwtl ; AVX512F-NEXT: vmovd %eax, %xmm15 @@ -533,7 +533,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512F-NEXT: movswl %cx, %ecx ; AVX512F-NEXT: vmovd %ecx, %xmm1 ; AVX512F-NEXT: movswl %ax, %ecx -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: cwtl ; AVX512F-NEXT: vmovd %eax, %xmm4 @@ -599,7 +599,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512VL-NEXT: movswl %cx, %ecx ; AVX512VL-NEXT: vmovd %ecx, %xmm9 ; AVX512VL-NEXT: movswl %ax, %ecx -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: cwtl ; AVX512VL-NEXT: vmovd %eax, %xmm11 @@ -614,7 +614,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512VL-NEXT: movswl %cx, %ecx ; AVX512VL-NEXT: vmovd %ecx, %xmm14 ; AVX512VL-NEXT: movswl %ax, %ecx -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: cwtl ; AVX512VL-NEXT: vmovd %eax, %xmm15 @@ -629,7 +629,7 @@ define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { ; AVX512VL-NEXT: movswl %cx, %ecx ; AVX512VL-NEXT: vmovd %ecx, %xmm18 ; AVX512VL-NEXT: movswl %ax, %ecx -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: cwtl ; AVX512VL-NEXT: vmovd %eax, %xmm19 @@ -735,7 +735,7 @@ define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind { ; AVX1-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rdx ; AVX1-NEXT: movswl %ax, %esi -; AVX1-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX1-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX1-NEXT: shrl $16, %eax ; AVX1-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $48, %rdx @@ -761,7 +761,7 @@ define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind { ; AVX2-NEXT: movq %rax, %rcx ; AVX2-NEXT: movq %rax, %rdx ; AVX2-NEXT: movswl %ax, %esi -; AVX2-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX2-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX2-NEXT: shrl $16, %eax ; AVX2-NEXT: shrq $32, %rcx ; AVX2-NEXT: shrq $48, %rdx @@ -787,7 +787,7 @@ define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind { ; AVX512F-NEXT: movq %rax, %rcx ; AVX512F-NEXT: movq %rax, %rdx ; AVX512F-NEXT: movswl %ax, %esi -; AVX512F-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512F-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512F-NEXT: shrl $16, %eax ; AVX512F-NEXT: shrq $32, %rcx ; AVX512F-NEXT: shrq $48, %rdx @@ -815,7 +815,7 @@ define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind { ; AVX512VL-NEXT: movq %rax, %rcx ; AVX512VL-NEXT: movq %rax, %rdx ; AVX512VL-NEXT: movswl %ax, %esi -; AVX512VL-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> +; AVX512VL-NEXT: # kill: %eax<def> %eax<kill> %rax<kill> ; AVX512VL-NEXT: shrl $16, %eax ; AVX512VL-NEXT: shrq $32, %rcx ; AVX512VL-NEXT: shrq $48, %rdx @@ -2061,7 +2061,7 @@ define i16 @cvt_f32_to_i16(float %a0) nounwind { ; ALL: # BB#0: ; ALL-NEXT: vcvtps2ph $4, %xmm0, %xmm0 ; ALL-NEXT: vmovd %xmm0, %eax -; ALL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; ALL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; ALL-NEXT: retq %1 = fptrunc float %a0 to half %2 = bitcast half %1 to i16 @@ -3139,7 +3139,7 @@ define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind { ; AVX1-NEXT: movl %eax, %ebx ; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %r14d @@ -3176,7 +3176,7 @@ define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind { ; AVX2-NEXT: movl %eax, %ebx ; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %r14d @@ -3213,7 +3213,7 @@ define <4 x i16> @cvt_4f64_to_4i16(<4 x double> %a0) nounwind { ; AVX512-NEXT: movl %eax, %ebx ; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movzwl %ax, %r14d @@ -3255,7 +3255,7 @@ define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind { ; AVX1-NEXT: movl %eax, %ebx ; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %r14d @@ -3293,7 +3293,7 @@ define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind { ; AVX2-NEXT: movl %eax, %ebx ; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %r14d @@ -3331,7 +3331,7 @@ define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind { ; AVX512F-NEXT: movl %eax, %ebx ; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: movzwl %ax, %r14d @@ -3369,7 +3369,7 @@ define <8 x i16> @cvt_4f64_to_8i16_undef(<4 x double> %a0) nounwind { ; AVX512VL-NEXT: movl %eax, %ebx ; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: movzwl %ax, %r14d @@ -3414,7 +3414,7 @@ define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind { ; AVX1-NEXT: movl %eax, %ebx ; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %r14d @@ -3452,7 +3452,7 @@ define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind { ; AVX2-NEXT: movl %eax, %ebx ; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %r14d @@ -3490,7 +3490,7 @@ define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind { ; AVX512F-NEXT: movl %eax, %ebx ; AVX512F-NEXT: shll $16, %ebx ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: movzwl %ax, %r14d @@ -3528,7 +3528,7 @@ define <8 x i16> @cvt_4f64_to_8i16_zero(<4 x double> %a0) nounwind { ; AVX512VL-NEXT: movl %eax, %ebx ; AVX512VL-NEXT: shll $16, %ebx ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: movzwl %ax, %r14d @@ -3577,7 +3577,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX1-NEXT: movl %eax, %ebx ; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %r15d @@ -3602,7 +3602,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX1-NEXT: movl %eax, %ebx ; AVX1-NEXT: shll $16, %ebx ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %r15d @@ -3644,7 +3644,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX2-NEXT: movl %eax, %ebx ; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %r15d @@ -3669,7 +3669,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX2-NEXT: movl %eax, %ebx ; AVX2-NEXT: shll $16, %ebx ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %r15d @@ -3710,7 +3710,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX512-NEXT: movl %eax, %ebx ; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: vmovups (%rsp), %zmm0 # 64-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movzwl %ax, %r15d @@ -3738,7 +3738,7 @@ define <8 x i16> @cvt_8f64_to_8i16(<8 x double> %a0) nounwind { ; AVX512-NEXT: movl %eax, %ebx ; AVX512-NEXT: shll $16, %ebx ; AVX512-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movzwl %ax, %r15d @@ -3836,7 +3836,7 @@ define void @store_cvt_4f64_to_4i16(<4 x double> %a0, <4 x i16>* %a1) nounwind { ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %r15d ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %ebp @@ -3874,7 +3874,7 @@ define void @store_cvt_4f64_to_4i16(<4 x double> %a0, <4 x i16>* %a1) nounwind { ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %r15d ; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %ebp @@ -3912,7 +3912,7 @@ define void @store_cvt_4f64_to_4i16(<4 x double> %a0, <4 x i16>* %a1) nounwind { ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %r15d ; AVX512-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %ebp @@ -3949,7 +3949,7 @@ define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) noun ; AVX1-NEXT: movl %eax, %ebp ; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %ebx @@ -3991,7 +3991,7 @@ define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) noun ; AVX2-NEXT: movl %eax, %ebp ; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %ebx @@ -4033,7 +4033,7 @@ define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) noun ; AVX512F-NEXT: movl %eax, %ebp ; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: movzwl %ax, %ebx @@ -4075,7 +4075,7 @@ define void @store_cvt_4f64_to_8i16_undef(<4 x double> %a0, <8 x i16>* %a1) noun ; AVX512VL-NEXT: movl %eax, %ebp ; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: movzwl %ax, %ebx @@ -4125,7 +4125,7 @@ define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounw ; AVX1-NEXT: movl %eax, %ebp ; AVX1-NEXT: shll $16, %ebp ; AVX1-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movzwl %ax, %ebx @@ -4167,7 +4167,7 @@ define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounw ; AVX2-NEXT: movl %eax, %ebp ; AVX2-NEXT: shll $16, %ebp ; AVX2-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movzwl %ax, %ebx @@ -4209,7 +4209,7 @@ define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounw ; AVX512F-NEXT: movl %eax, %ebp ; AVX512F-NEXT: shll $16, %ebp ; AVX512F-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: callq __truncdfhf2 ; AVX512F-NEXT: movzwl %ax, %ebx @@ -4251,7 +4251,7 @@ define void @store_cvt_4f64_to_8i16_zero(<4 x double> %a0, <8 x i16>* %a1) nounw ; AVX512VL-NEXT: movl %eax, %ebp ; AVX512VL-NEXT: shll $16, %ebp ; AVX512VL-NEXT: vmovups (%rsp), %ymm0 # 32-byte Reload -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: callq __truncdfhf2 ; AVX512VL-NEXT: movzwl %ax, %ebx @@ -4324,7 +4324,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %r13d ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %ebp @@ -4332,7 +4332,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %r14d ; AVX1-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: callq __truncdfhf2 ; AVX1-NEXT: movl %eax, %r15d @@ -4392,7 +4392,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %r13d ; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %ebp @@ -4400,7 +4400,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %r14d ; AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: callq __truncdfhf2 ; AVX2-NEXT: movl %eax, %r15d @@ -4462,7 +4462,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %r13d ; AVX512-NEXT: vmovups {{[0-9]+}}(%rsp), %zmm0 # 64-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %ebp @@ -4470,7 +4470,7 @@ define void @store_cvt_8f64_to_8i16(<8 x double> %a0, <8 x i16>* %a1) nounwind { ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %r14d ; AVX512-NEXT: vmovups {{[0-9]+}}(%rsp), %ymm0 # 32-byte Reload -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: callq __truncdfhf2 ; AVX512-NEXT: movl %eax, %r15d diff --git a/test/CodeGen/X86/vector-lzcnt-128.ll b/test/CodeGen/X86/vector-lzcnt-128.ll index ee666168295..b23730f57ff 100644 --- a/test/CodeGen/X86/vector-lzcnt-128.ll +++ b/test/CodeGen/X86/vector-lzcnt-128.ll @@ -233,9 +233,9 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; ; AVX512CD-LABEL: testv2i64: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; @@ -499,9 +499,9 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind { ; ; AVX512CD-LABEL: testv2i64u: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; @@ -747,9 +747,9 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; ; AVX512CD-LABEL: testv4i32: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; @@ -989,9 +989,9 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind { ; ; AVX512CD-LABEL: testv4i32u: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512CD-NEXT: vzeroupper ; AVX512CD-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-lzcnt-256.ll b/test/CodeGen/X86/vector-lzcnt-256.ll index 97dac558ebe..54b53272288 100644 --- a/test/CodeGen/X86/vector-lzcnt-256.ll +++ b/test/CodeGen/X86/vector-lzcnt-256.ll @@ -162,9 +162,9 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; ; AVX512CD-LABEL: testv4i64: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512CD-NEXT: retq ; ; X32-AVX-LABEL: testv4i64: @@ -354,9 +354,9 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; ; AVX512CD-LABEL: testv4i64u: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntq %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512CD-NEXT: retq ; ; X32-AVX-LABEL: testv4i64u: @@ -521,9 +521,9 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; ; AVX512CD-LABEL: testv8i32: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512CD-NEXT: retq ; ; X32-AVX-LABEL: testv8i32: @@ -683,9 +683,9 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; ; AVX512CD-LABEL: testv8i32u: ; AVX512CD: # BB#0: -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512CD-NEXT: vplzcntd %zmm0, %zmm0 -; AVX512CD-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512CD-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512CD-NEXT: retq ; ; X32-AVX-LABEL: testv8i32u: diff --git a/test/CodeGen/X86/vector-popcnt-128.ll b/test/CodeGen/X86/vector-popcnt-128.ll index 8f5755cea46..86a3c6e6856 100644 --- a/test/CodeGen/X86/vector-popcnt-128.ll +++ b/test/CodeGen/X86/vector-popcnt-128.ll @@ -114,9 +114,9 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; ; AVX512VPOPCNTDQ-LABEL: testv2i64: ; AVX512VPOPCNTDQ: # BB#0: -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -284,9 +284,9 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; ; AVX512VPOPCNTDQ-LABEL: testv4i32: ; AVX512VPOPCNTDQ: # BB#0: -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -450,9 +450,9 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind { ; ; BITALG_NOVLX-LABEL: testv8i16: ; BITALG_NOVLX: # BB#0: -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; @@ -567,9 +567,9 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { ; ; BITALG_NOVLX-LABEL: testv16i8: ; BITALG_NOVLX: # BB#0: -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-popcnt-256.ll b/test/CodeGen/X86/vector-popcnt-256.ll index 48c02572cf1..a4d101f4fd3 100644 --- a/test/CodeGen/X86/vector-popcnt-256.ll +++ b/test/CodeGen/X86/vector-popcnt-256.ll @@ -45,9 +45,9 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; ; AVX512VPOPCNTDQ-LABEL: testv4i64: ; AVX512VPOPCNTDQ: # BB#0: -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv4i64: @@ -133,9 +133,9 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; ; AVX512VPOPCNTDQ-LABEL: testv8i32: ; AVX512VPOPCNTDQ: # BB#0: -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv8i32: @@ -228,9 +228,9 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; ; BITALG_NOVLX-LABEL: testv16i16: ; BITALG_NOVLX: # BB#0: -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv16i16: @@ -288,9 +288,9 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; ; BITALG_NOVLX-LABEL: testv32i8: ; BITALG_NOVLX: # BB#0: -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv32i8: diff --git a/test/CodeGen/X86/vector-rotate-128.ll b/test/CodeGen/X86/vector-rotate-128.ll index afcc053bb6a..fcdb6cb61f6 100644 --- a/test/CodeGen/X86/vector-rotate-128.ll +++ b/test/CodeGen/X86/vector-rotate-128.ll @@ -78,10 +78,10 @@ define <2 x i64> @var_rotate_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v2i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolvq %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -219,10 +219,10 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v4i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolvd %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -462,8 +462,8 @@ define <8 x i16> @var_rotate_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16] ; AVX512BW-NEXT: vpsubw %xmm1, %xmm2, %xmm2 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm1 @@ -838,10 +838,10 @@ define <2 x i64> @constant_rotate_v2i64(<2 x i64> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v2i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [4,14] ; AVX512BW-NEXT: vprolvq %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -940,10 +940,10 @@ define <4 x i32> @constant_rotate_v4i32(<4 x i32> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v4i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [4,5,6,7] ; AVX512BW-NEXT: vprolvd %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1067,7 +1067,7 @@ define <8 x i16> @constant_rotate_v8i16(<8 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7] ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm1 ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = [16,15,14,13,12,11,10,9] @@ -1350,9 +1350,9 @@ define <2 x i64> @splatconstant_rotate_v2i64(<2 x i64> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_v2i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolq $14, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1397,9 +1397,9 @@ define <4 x i32> @splatconstant_rotate_v4i32(<4 x i32> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_v4i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprold $4, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1535,7 +1535,7 @@ define <2 x i64> @splatconstant_rotate_mask_v2i64(<2 x i64> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_mask_v2i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolq $15, %zmm0, %zmm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper @@ -1587,7 +1587,7 @@ define <4 x i32> @splatconstant_rotate_mask_v4i32(<4 x i32> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_mask_v4i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprold $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper diff --git a/test/CodeGen/X86/vector-rotate-256.ll b/test/CodeGen/X86/vector-rotate-256.ll index 3f67ea65b00..1af190f1665 100644 --- a/test/CodeGen/X86/vector-rotate-256.ll +++ b/test/CodeGen/X86/vector-rotate-256.ll @@ -50,10 +50,10 @@ define <4 x i64> @var_rotate_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v4i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolvq %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: var_rotate_v4i64: @@ -141,10 +141,10 @@ define <8 x i32> @var_rotate_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v8i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolvd %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: var_rotate_v8i32: @@ -271,8 +271,8 @@ define <16 x i16> @var_rotate_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; ; AVX512BW-LABEL: var_rotate_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX512BW-NEXT: vpsubw %ymm1, %ymm2, %ymm2 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm1 @@ -479,10 +479,10 @@ define <4 x i64> @constant_rotate_v4i64(<4 x i64> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v4i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [4,14,50,60] ; AVX512BW-NEXT: vprolvq %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: constant_rotate_v4i64: @@ -545,10 +545,10 @@ define <8 x i32> @constant_rotate_v8i32(<8 x i32> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v8i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [4,5,6,7,8,9,10,11] ; AVX512BW-NEXT: vprolvd %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: constant_rotate_v8i32: @@ -623,7 +623,7 @@ define <16 x i16> @constant_rotate_v16i16(<16 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_rotate_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm1 ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1] @@ -800,9 +800,9 @@ define <4 x i64> @splatconstant_rotate_v4i64(<4 x i64> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_v4i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolq $14, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_rotate_v4i64: @@ -853,9 +853,9 @@ define <8 x i32> @splatconstant_rotate_v8i32(<8 x i32> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_v8i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprold $4, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_rotate_v8i32: @@ -1012,7 +1012,7 @@ define <4 x i64> @splatconstant_rotate_mask_v4i64(<4 x i64> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_mask_v4i64: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprolq $15, %zmm0, %zmm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: retq @@ -1074,7 +1074,7 @@ define <8 x i32> @splatconstant_rotate_mask_v8i32(<8 x i32> %a) nounwind { ; ; AVX512BW-LABEL: splatconstant_rotate_mask_v8i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vprold $4, %zmm0, %zmm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: retq diff --git a/test/CodeGen/X86/vector-sext.ll b/test/CodeGen/X86/vector-sext.ll index cd4b237735f..009a4cf501a 100644 --- a/test/CodeGen/X86/vector-sext.ll +++ b/test/CodeGen/X86/vector-sext.ll @@ -1245,7 +1245,7 @@ define <2 x i64> @load_sext_2i1_to_2i64(<2 x i1> *%ptr) { ; AVX512F-NEXT: movzbl (%rdi), %eax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1254,7 +1254,7 @@ define <2 x i64> @load_sext_2i1_to_2i64(<2 x i1> *%ptr) { ; AVX512BW-NEXT: movzbl (%rdi), %eax ; AVX512BW-NEXT: kmovd %eax, %k1 ; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1437,7 +1437,7 @@ define <4 x i32> @load_sext_4i1_to_4i32(<4 x i1> *%ptr) { ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -1447,7 +1447,7 @@ define <4 x i32> @load_sext_4i1_to_4i32(<4 x i1> *%ptr) { ; AVX512BW-NEXT: kmovd %eax, %k1 ; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1643,7 +1643,7 @@ define <4 x i64> @load_sext_4i1_to_4i64(<4 x i1> *%ptr) { ; AVX512F-NEXT: movzbl (%rdi), %eax ; AVX512F-NEXT: kmovw %eax, %k1 ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: load_sext_4i1_to_4i64: @@ -1651,7 +1651,7 @@ define <4 x i64> @load_sext_4i1_to_4i64(<4 x i1> *%ptr) { ; AVX512BW-NEXT: movzbl (%rdi), %eax ; AVX512BW-NEXT: kmovd %eax, %k1 ; AVX512BW-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; X32-SSE41-LABEL: load_sext_4i1_to_4i64: @@ -2009,7 +2009,7 @@ define <8 x i16> @load_sext_8i1_to_8i16(<8 x i1> *%ptr) { ; AVX512BW-NEXT: movzbl (%rdi), %eax ; AVX512BW-NEXT: kmovd %eax, %k0 ; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -2921,7 +2921,7 @@ define <16 x i8> @load_sext_16i1_to_16i8(<16 x i1> *%ptr) nounwind readnone { ; AVX512BW: # BB#0: # %entry ; AVX512BW-NEXT: kmovw (%rdi), %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -3442,7 +3442,7 @@ define <16 x i16> @load_sext_16i1_to_16i16(<16 x i1> *%ptr) { ; AVX512BW: # BB#0: # %entry ; AVX512BW-NEXT: kmovw (%rdi), %k0 ; AVX512BW-NEXT: vpmovm2w %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; X32-SSE41-LABEL: load_sext_16i1_to_16i16: @@ -4297,7 +4297,7 @@ define <32 x i8> @load_sext_32i1_to_32i8(<32 x i1> *%ptr) nounwind readnone { ; AVX512BW: # BB#0: # %entry ; AVX512BW-NEXT: kmovd (%rdi), %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; X32-SSE41-LABEL: load_sext_32i1_to_32i8: @@ -5030,7 +5030,7 @@ define <32 x i8> @sext_32xi1_to_32xi8(<32 x i16> %c1, <32 x i16> %c2)nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpcmpeqw %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; X32-SSE41-LABEL: sext_32xi1_to_32xi8: diff --git a/test/CodeGen/X86/vector-shift-ashr-128.ll b/test/CodeGen/X86/vector-shift-ashr-128.ll index 53a8961a2dd..3cfe0003807 100644 --- a/test/CodeGen/X86/vector-shift-ashr-128.ll +++ b/test/CodeGen/X86/vector-shift-ashr-128.ll @@ -82,10 +82,10 @@ define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; AVX512-LABEL: var_shift_v2i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; @@ -336,16 +336,16 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; AVX512DQ-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512DQ-NEXT: vpsravd %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: var_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -651,9 +651,9 @@ define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind { ; ; AVX512-LABEL: splatvar_shift_v2i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpsraq %xmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; @@ -1087,10 +1087,10 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; ; AVX512-LABEL: constant_shift_v2i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vmovdqa {{.*#+}} xmm1 = [1,7] ; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; @@ -1265,16 +1265,16 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; AVX512DQ-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512DQ-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: constant_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7] ; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1564,9 +1564,9 @@ define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind { ; ; AVX512-LABEL: splatconstant_shift_v2i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512-NEXT: vpsraq $7, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-shift-ashr-256.ll b/test/CodeGen/X86/vector-shift-ashr-256.ll index 5c728f27294..d29518d3640 100644 --- a/test/CodeGen/X86/vector-shift-ashr-256.ll +++ b/test/CodeGen/X86/vector-shift-ashr-256.ll @@ -75,10 +75,10 @@ define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; ; AVX512-LABEL: var_shift_v4i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: var_shift_v4i64: @@ -309,10 +309,10 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; ; AVX512BW-LABEL: var_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: var_shift_v16i16: @@ -696,9 +696,9 @@ define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwind { ; ; AVX512-LABEL: splatvar_shift_v4i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpsraq %xmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatvar_shift_v4i64: @@ -1170,10 +1170,10 @@ define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) nounwind { ; ; AVX512-LABEL: constant_shift_v4i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vmovdqa {{.*#+}} ymm1 = [1,7,31,62] ; AVX512-NEXT: vpsravq %zmm1, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: constant_shift_v4i64: @@ -1360,10 +1360,10 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: constant_shift_v16i16: @@ -1702,9 +1702,9 @@ define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) nounwind { ; ; AVX512-LABEL: splatconstant_shift_v4i64: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpsraq $7, %zmm0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq ; ; AVX512VL-LABEL: splatconstant_shift_v4i64: diff --git a/test/CodeGen/X86/vector-shift-lshr-128.ll b/test/CodeGen/X86/vector-shift-lshr-128.ll index 0734b984737..2511cfedf7e 100644 --- a/test/CodeGen/X86/vector-shift-lshr-128.ll +++ b/test/CodeGen/X86/vector-shift-lshr-128.ll @@ -290,7 +290,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -307,16 +307,16 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQ-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: var_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1010,7 +1010,7 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1026,16 +1026,16 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQ-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: constant_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7] ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-shift-lshr-256.ll b/test/CodeGen/X86/vector-shift-lshr-256.ll index 0b563e8f3e5..1d84a1f500e 100644 --- a/test/CodeGen/X86/vector-shift-lshr-256.ll +++ b/test/CodeGen/X86/vector-shift-lshr-256.ll @@ -272,10 +272,10 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; ; AVX512BW-LABEL: var_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: var_shift_v16i16: @@ -1091,10 +1091,10 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: constant_shift_v16i16: diff --git a/test/CodeGen/X86/vector-shift-shl-128.ll b/test/CodeGen/X86/vector-shift-shl-128.ll index 252c4d03b68..33b479f96ee 100644 --- a/test/CodeGen/X86/vector-shift-shl-128.ll +++ b/test/CodeGen/X86/vector-shift-shl-128.ll @@ -247,7 +247,7 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -262,16 +262,16 @@ define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind { ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQ-NEXT: vpsllvd %ymm1, %ymm0, %ymm0 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; ; AVX512BW-LABEL: var_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM1<def> %XMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm1<def> %xmm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -902,10 +902,10 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_shift_v8i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7] ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-shift-shl-256.ll b/test/CodeGen/X86/vector-shift-shl-256.ll index 4e6964c3d4a..a2cb3621d7b 100644 --- a/test/CodeGen/X86/vector-shift-shl-256.ll +++ b/test/CodeGen/X86/vector-shift-shl-256.ll @@ -232,10 +232,10 @@ define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) nounwind { ; ; AVX512BW-LABEL: var_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: var_shift_v16i16: @@ -966,10 +966,10 @@ define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { ; ; AVX512BW-LABEL: constant_shift_v16i16: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0 -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512BW-NEXT: retq ; ; AVX512DQVL-LABEL: constant_shift_v16i16: diff --git a/test/CodeGen/X86/vector-shuffle-256-v4.ll b/test/CodeGen/X86/vector-shuffle-256-v4.ll index 56567c7e794..1cc2a8385f0 100644 --- a/test/CodeGen/X86/vector-shuffle-256-v4.ll +++ b/test/CodeGen/X86/vector-shuffle-256-v4.ll @@ -1295,21 +1295,21 @@ define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) { define <4 x double> @insert_reg_and_zero_v4f64(double %a) { ; AVX1-LABEL: insert_reg_and_zero_v4f64: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX1-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; AVX1-NEXT: retq ; ; AVX2-LABEL: insert_reg_and_zero_v4f64: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] ; AVX2-NEXT: retq ; ; AVX512VL-LABEL: insert_reg_and_zero_v4f64: ; AVX512VL: # BB#0: -; AVX512VL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512VL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512VL-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX512VL-NEXT: retq diff --git a/test/CodeGen/X86/vector-shuffle-512-v16.ll b/test/CodeGen/X86/vector-shuffle-512-v16.ll index 13cde3321d9..d1b6d6c2c64 100644 --- a/test/CodeGen/X86/vector-shuffle-512-v16.ll +++ b/test/CodeGen/X86/vector-shuffle-512-v16.ll @@ -689,7 +689,7 @@ define <16 x i32> @mask_shuffle_v16i32_00_01_02_03_16_17_18_19_08_09_10_11_12_13 define <16 x i32> @mask_shuffle_v4i32_v16i32_00_01_02_03_00_01_02_03_00_01_02_03_00_01_02_03(<4 x i32> %a) { ; ALL-LABEL: mask_shuffle_v4i32_v16i32_00_01_02_03_00_01_02_03_00_01_02_03_00_01_02_03: ; ALL: # BB#0: -; ALL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; ALL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; ALL-NEXT: retq @@ -700,7 +700,7 @@ define <16 x i32> @mask_shuffle_v4i32_v16i32_00_01_02_03_00_01_02_03_00_01_02_03 define <16 x float> @mask_shuffle_v4f32_v16f32_00_01_02_03_00_01_02_03_00_01_02_03_00_01_02_03(<4 x float> %a) { ; ALL-LABEL: mask_shuffle_v4f32_v16f32_00_01_02_03_00_01_02_03_00_01_02_03_00_01_02_03: ; ALL: # BB#0: -; ALL-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; ALL-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; ALL-NEXT: retq diff --git a/test/CodeGen/X86/vector-shuffle-512-v8.ll b/test/CodeGen/X86/vector-shuffle-512-v8.ll index 1d17ef109d2..a4f67195f72 100644 --- a/test/CodeGen/X86/vector-shuffle-512-v8.ll +++ b/test/CodeGen/X86/vector-shuffle-512-v8.ll @@ -2644,14 +2644,14 @@ define <8 x double> @shuffle_v4f64_v8f64_22222222(<4 x double> %a) { define <8 x i64> @shuffle_v2i64_v8i64_01010101(<2 x i64> %a) { ; AVX512F-LABEL: shuffle_v2i64_v8i64_01010101: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; AVX512F-NEXT: retq ; ; AVX512F-32-LABEL: shuffle_v2i64_v8i64_01010101: ; AVX512F-32: # BB#0: -; AVX512F-32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX512F-32-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; AVX512F-32-NEXT: retl @@ -2662,14 +2662,14 @@ define <8 x i64> @shuffle_v2i64_v8i64_01010101(<2 x i64> %a) { define <8 x double> @shuffle_v2f64_v8f64_01010101(<2 x double> %a) { ; AVX512F-LABEL: shuffle_v2f64_v8f64_01010101: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; AVX512F-NEXT: retq ; ; AVX512F-32-LABEL: shuffle_v2f64_v8f64_01010101: ; AVX512F-32: # BB#0: -; AVX512F-32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; AVX512F-32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; AVX512F-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX512F-32-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; AVX512F-32-NEXT: retl diff --git a/test/CodeGen/X86/vector-shuffle-avx512.ll b/test/CodeGen/X86/vector-shuffle-avx512.ll index efbe5586747..5a7207952be 100644 --- a/test/CodeGen/X86/vector-shuffle-avx512.ll +++ b/test/CodeGen/X86/vector-shuffle-avx512.ll @@ -8,7 +8,7 @@ define <8 x float> @expand(<4 x float> %a) { ; SKX64-LABEL: expand: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $5, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} @@ -23,7 +23,7 @@ define <8 x float> @expand(<4 x float> %a) { ; ; SKX32-LABEL: expand: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $5, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} @@ -42,7 +42,7 @@ define <8 x float> @expand(<4 x float> %a) { define <8 x float> @expand1(<4 x float> %a ) { ; SKX64-LABEL: expand1: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $-86, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} @@ -50,7 +50,7 @@ define <8 x float> @expand1(<4 x float> %a ) { ; ; KNL64-LABEL: expand1: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL64-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3> ; KNL64-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -59,7 +59,7 @@ define <8 x float> @expand1(<4 x float> %a ) { ; ; SKX32-LABEL: expand1: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $-86, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} @@ -67,7 +67,7 @@ define <8 x float> @expand1(<4 x float> %a ) { ; ; KNL32-LABEL: expand1: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL32-NEXT: vmovaps {{.*#+}} ymm1 = <u,0,u,1,u,2,u,3> ; KNL32-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1 @@ -81,7 +81,7 @@ define <8 x float> @expand1(<4 x float> %a ) { define <4 x double> @expand2(<2 x double> %a) { ; SKX64-LABEL: expand2: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $9, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z} @@ -89,7 +89,7 @@ define <4 x double> @expand2(<2 x double> %a) { ; ; KNL64-LABEL: expand2: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL64-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; KNL64-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] @@ -97,7 +97,7 @@ define <4 x double> @expand2(<2 x double> %a) { ; ; SKX32-LABEL: expand2: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $9, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandpd %ymm0, %ymm0 {%k1} {z} @@ -105,7 +105,7 @@ define <4 x double> @expand2(<2 x double> %a) { ; ; KNL32-LABEL: expand2: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL32-NEXT: vxorpd %xmm1, %xmm1, %xmm1 ; KNL32-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2],ymm0[3] @@ -118,7 +118,7 @@ define <4 x double> @expand2(<2 x double> %a) { define <8 x i32> @expand3(<4 x i32> %a ) { ; SKX64-LABEL: expand3: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $-127, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} @@ -133,7 +133,7 @@ define <8 x i32> @expand3(<4 x i32> %a ) { ; ; SKX32-LABEL: expand3: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $-127, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vpexpandd %ymm0, %ymm0 {%k1} {z} @@ -153,7 +153,7 @@ define <8 x i32> @expand3(<4 x i32> %a ) { define <4 x i64> @expand4(<2 x i64> %a ) { ; SKX64-LABEL: expand4: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $9, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z} @@ -161,7 +161,7 @@ define <4 x i64> @expand4(<2 x i64> %a ) { ; ; KNL64-LABEL: expand4: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; KNL64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7] @@ -169,7 +169,7 @@ define <4 x i64> @expand4(<2 x i64> %a ) { ; ; SKX32-LABEL: expand4: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $9, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vpexpandq %ymm0, %ymm0 {%k1} {z} @@ -177,7 +177,7 @@ define <4 x i64> @expand4(<2 x i64> %a ) { ; ; KNL32-LABEL: expand4: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; KNL32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; KNL32-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,1,2,1] ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; KNL32-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7] @@ -251,7 +251,7 @@ define <8 x float> @expand6(<4 x float> %a ) { define <16 x float> @expand7(<8 x float> %a) { ; SKX64-LABEL: expand7: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: movw $1285, %ax # imm = 0x505 ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -259,7 +259,7 @@ define <16 x float> @expand7(<8 x float> %a) { ; ; KNL64-LABEL: expand7: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: movw $1285, %ax # imm = 0x505 ; KNL64-NEXT: kmovw %eax, %k1 ; KNL64-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -267,7 +267,7 @@ define <16 x float> @expand7(<8 x float> %a) { ; ; SKX32-LABEL: expand7: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: movw $1285, %ax # imm = 0x505 ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -275,7 +275,7 @@ define <16 x float> @expand7(<8 x float> %a) { ; ; KNL32-LABEL: expand7: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: movw $1285, %ax # imm = 0x505 ; KNL32-NEXT: kmovw %eax, %k1 ; KNL32-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -287,7 +287,7 @@ define <16 x float> @expand7(<8 x float> %a) { define <16 x float> @expand8(<8 x float> %a ) { ; SKX64-LABEL: expand8: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: movw $-21846, %ax # imm = 0xAAAA ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -295,7 +295,7 @@ define <16 x float> @expand8(<8 x float> %a ) { ; ; KNL64-LABEL: expand8: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: movw $-21846, %ax # imm = 0xAAAA ; KNL64-NEXT: kmovw %eax, %k1 ; KNL64-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -303,7 +303,7 @@ define <16 x float> @expand8(<8 x float> %a ) { ; ; SKX32-LABEL: expand8: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: movw $-21846, %ax # imm = 0xAAAA ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -311,7 +311,7 @@ define <16 x float> @expand8(<8 x float> %a ) { ; ; KNL32-LABEL: expand8: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: movw $-21846, %ax # imm = 0xAAAA ; KNL32-NEXT: kmovw %eax, %k1 ; KNL32-NEXT: vexpandps %zmm0, %zmm0 {%k1} {z} @@ -324,7 +324,7 @@ define <16 x float> @expand8(<8 x float> %a ) { define <8 x double> @expand9(<4 x double> %a) { ; SKX64-LABEL: expand9: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: movb $-127, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandpd %zmm0, %zmm0 {%k1} {z} @@ -332,7 +332,7 @@ define <8 x double> @expand9(<4 x double> %a) { ; ; KNL64-LABEL: expand9: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: movb $-127, %al ; KNL64-NEXT: kmovw %eax, %k1 ; KNL64-NEXT: vexpandpd %zmm0, %zmm0 {%k1} {z} @@ -340,7 +340,7 @@ define <8 x double> @expand9(<4 x double> %a) { ; ; SKX32-LABEL: expand9: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: movb $-127, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandpd %zmm0, %zmm0 {%k1} {z} @@ -348,7 +348,7 @@ define <8 x double> @expand9(<4 x double> %a) { ; ; KNL32-LABEL: expand9: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: movb $-127, %al ; KNL32-NEXT: kmovw %eax, %k1 ; KNL32-NEXT: vexpandpd %zmm0, %zmm0 {%k1} {z} @@ -360,7 +360,7 @@ define <8 x double> @expand9(<4 x double> %a) { define <16 x i32> @expand10(<8 x i32> %a ) { ; SKX64-LABEL: expand10: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: movw $-21846, %ax # imm = 0xAAAA ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} @@ -368,7 +368,7 @@ define <16 x i32> @expand10(<8 x i32> %a ) { ; ; KNL64-LABEL: expand10: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: movw $-21846, %ax # imm = 0xAAAA ; KNL64-NEXT: kmovw %eax, %k1 ; KNL64-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} @@ -376,7 +376,7 @@ define <16 x i32> @expand10(<8 x i32> %a ) { ; ; SKX32-LABEL: expand10: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: movw $-21846, %ax # imm = 0xAAAA ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} @@ -384,7 +384,7 @@ define <16 x i32> @expand10(<8 x i32> %a ) { ; ; KNL32-LABEL: expand10: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: movw $-21846, %ax # imm = 0xAAAA ; KNL32-NEXT: kmovw %eax, %k1 ; KNL32-NEXT: vpexpandd %zmm0, %zmm0 {%k1} {z} @@ -396,7 +396,7 @@ define <16 x i32> @expand10(<8 x i32> %a ) { define <8 x i64> @expand11(<4 x i64> %a) { ; SKX64-LABEL: expand11: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: movb $-127, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} @@ -404,7 +404,7 @@ define <8 x i64> @expand11(<4 x i64> %a) { ; ; KNL64-LABEL: expand11: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: movb $-127, %al ; KNL64-NEXT: kmovw %eax, %k1 ; KNL64-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} @@ -412,7 +412,7 @@ define <8 x i64> @expand11(<4 x i64> %a) { ; ; SKX32-LABEL: expand11: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: movb $-127, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} @@ -420,7 +420,7 @@ define <8 x i64> @expand11(<4 x i64> %a) { ; ; KNL32-LABEL: expand11: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: movb $-127, %al ; KNL32-NEXT: kmovw %eax, %k1 ; KNL32-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} @@ -433,7 +433,7 @@ define <8 x i64> @expand11(<4 x i64> %a) { define <16 x float> @expand12(<8 x float> %a) { ; SKX64-LABEL: expand12: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX64-NEXT: vmovaps {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16] ; SKX64-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; SKX64-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1 @@ -442,7 +442,7 @@ define <16 x float> @expand12(<8 x float> %a) { ; ; KNL64-LABEL: expand12: ; KNL64: # BB#0: -; KNL64-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL64-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL64-NEXT: vmovaps {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16] ; KNL64-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; KNL64-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1 @@ -451,7 +451,7 @@ define <16 x float> @expand12(<8 x float> %a) { ; ; SKX32-LABEL: expand12: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; SKX32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; SKX32-NEXT: vmovaps {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16] ; SKX32-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; SKX32-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1 @@ -460,7 +460,7 @@ define <16 x float> @expand12(<8 x float> %a) { ; ; KNL32-LABEL: expand12: ; KNL32: # BB#0: -; KNL32-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; KNL32-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; KNL32-NEXT: vmovaps {{.*#+}} zmm2 = [0,16,2,16,4,16,6,16,0,16,1,16,2,16,3,16] ; KNL32-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; KNL32-NEXT: vpermt2ps %zmm0, %zmm2, %zmm1 @@ -503,7 +503,7 @@ define <16 x float> @expand13(<8 x float> %a ) { define <8 x float> @expand14(<4 x float> %a) { ; SKX64-LABEL: expand14: ; SKX64: # BB#0: -; SKX64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX64-NEXT: movb $20, %al ; SKX64-NEXT: kmovd %eax, %k1 ; SKX64-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} @@ -520,7 +520,7 @@ define <8 x float> @expand14(<4 x float> %a) { ; ; SKX32-LABEL: expand14: ; SKX32: # BB#0: -; SKX32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; SKX32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; SKX32-NEXT: movb $20, %al ; SKX32-NEXT: kmovd %eax, %k1 ; SKX32-NEXT: vexpandps %ymm0, %ymm0 {%k1} {z} diff --git a/test/CodeGen/X86/vector-shuffle-combining-avx2.ll b/test/CodeGen/X86/vector-shuffle-combining-avx2.ll index e7ad4aca204..9c6bebdd78b 100644 --- a/test/CodeGen/X86/vector-shuffle-combining-avx2.ll +++ b/test/CodeGen/X86/vector-shuffle-combining-avx2.ll @@ -196,13 +196,13 @@ define <16 x i8> @combine_pshufb_as_vpbroadcastb128(<16 x i8> %a) { define <32 x i8> @combine_pshufb_as_vpbroadcastb256(<2 x i64> %a) { ; X32-LABEL: combine_pshufb_as_vpbroadcastb256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vpbroadcastb %xmm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_pshufb_as_vpbroadcastb256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vpbroadcastb %xmm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> @@ -231,13 +231,13 @@ define <16 x i8> @combine_pshufb_as_vpbroadcastw128(<16 x i8> %a) { define <32 x i8> @combine_pshufb_as_vpbroadcastw256(<2 x i64> %a) { ; X32-LABEL: combine_pshufb_as_vpbroadcastw256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vpbroadcastw %xmm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_pshufb_as_vpbroadcastw256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vpbroadcastw %xmm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> @@ -269,14 +269,14 @@ define <16 x i8> @combine_pshufb_as_vpbroadcastd128(<16 x i8> %a) { define <8 x i32> @combine_permd_as_vpbroadcastd256(<4 x i32> %a) { ; X32-LABEL: combine_permd_as_vpbroadcastd256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vpbroadcastd %xmm0, %ymm0 ; X32-NEXT: vpaddd {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_permd_as_vpbroadcastd256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vpbroadcastd %xmm0, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: retq @@ -303,14 +303,14 @@ define <16 x i8> @combine_pshufb_as_vpbroadcastq128(<16 x i8> %a) { define <8 x i32> @combine_permd_as_vpbroadcastq256(<4 x i32> %a) { ; X32-LABEL: combine_permd_as_vpbroadcastq256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vpbroadcastq %xmm0, %ymm0 ; X32-NEXT: vpaddd {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_permd_as_vpbroadcastq256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vpbroadcastq %xmm0, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: retq @@ -339,13 +339,13 @@ define <4 x float> @combine_pshufb_as_vpbroadcastss128(<4 x float> %a) { define <8 x float> @combine_permps_as_vpbroadcastss256(<4 x float> %a) { ; X32-LABEL: combine_permps_as_vpbroadcastss256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vbroadcastss %xmm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_permps_as_vpbroadcastss256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vbroadcastss %xmm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <4 x float> %a, <4 x float> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> @@ -356,13 +356,13 @@ define <8 x float> @combine_permps_as_vpbroadcastss256(<4 x float> %a) { define <4 x double> @combine_permps_as_vpbroadcastsd256(<2 x double> %a) { ; X32-LABEL: combine_permps_as_vpbroadcastsd256: ; X32: # BB#0: -; X32-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X32-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X32-NEXT: vbroadcastsd %xmm0, %ymm0 ; X32-NEXT: retl ; ; X64-LABEL: combine_permps_as_vpbroadcastsd256: ; X64: # BB#0: -; X64-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; X64-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; X64-NEXT: vbroadcastsd %xmm0, %ymm0 ; X64-NEXT: retq %1 = shufflevector <2 x double> %a, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> diff --git a/test/CodeGen/X86/vector-shuffle-v1.ll b/test/CodeGen/X86/vector-shuffle-v1.ll index 8d057290085..1a408fe1d59 100644 --- a/test/CodeGen/X86/vector-shuffle-v1.ll +++ b/test/CodeGen/X86/vector-shuffle-v1.ll @@ -285,7 +285,7 @@ define i8 @shuf8i1_10_2_9_u_3_u_2_u(i8 %a) { ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -299,7 +299,7 @@ define i8 @shuf8i1_10_2_9_u_3_u_2_u(i8 %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -312,7 +312,7 @@ define i8 @shuf8i1_10_2_9_u_3_u_2_u(i8 %a) { ; VL_BW_DQ-NEXT: vpermi2q %zmm1, %zmm0, %zmm2 ; VL_BW_DQ-NEXT: vpmovq2m %zmm2, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i8 %a to <8 x i1> @@ -330,7 +330,7 @@ define i8 @shuf8i1_0_1_4_5_u_u_u_u(i8 %a) { ; AVX512F-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -342,7 +342,7 @@ define i8 @shuf8i1_0_1_4_5_u_u_u_u(i8 %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm0, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -353,7 +353,7 @@ define i8 @shuf8i1_0_1_4_5_u_u_u_u(i8 %a) { ; VL_BW_DQ-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5,0,1,0,1] ; VL_BW_DQ-NEXT: vpmovq2m %zmm0, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i8 %a to <8 x i1> @@ -373,7 +373,7 @@ define i8 @shuf8i1_9_6_1_0_3_7_7_0(i8 %a) { ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -387,7 +387,7 @@ define i8 @shuf8i1_9_6_1_0_3_7_7_0(i8 %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -400,7 +400,7 @@ define i8 @shuf8i1_9_6_1_0_3_7_7_0(i8 %a) { ; VL_BW_DQ-NEXT: vpermi2q %zmm1, %zmm0, %zmm2 ; VL_BW_DQ-NEXT: vpmovq2m %zmm2, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i8 %a to <8 x i1> @@ -420,7 +420,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0(i8 %a) { ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -434,7 +434,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0(i8 %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -447,7 +447,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0(i8 %a) { ; VL_BW_DQ-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 ; VL_BW_DQ-NEXT: vpmovq2m %zmm2, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i8 %a to <8 x i1> @@ -469,7 +469,7 @@ define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) { ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -485,7 +485,7 @@ define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -498,7 +498,7 @@ define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) { ; VL_BW_DQ-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 ; VL_BW_DQ-NEXT: vpmovq2m %zmm2, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i8 %a to <8 x i1> @@ -520,7 +520,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0_all_ones(<8 x i1> %a) { ; AVX512F-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -536,7 +536,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0_all_ones(<8 x i1> %a) { ; AVX512VL-NEXT: vpsllq $63, %zmm2, %zmm0 ; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -550,7 +550,7 @@ define i8 @shuf8i1_9_6_1_10_3_7_7_0_all_ones(<8 x i1> %a) { ; VL_BW_DQ-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 ; VL_BW_DQ-NEXT: vpmovq2m %zmm2, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %al<def> %al<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %c = shufflevector <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i1> %a, <8 x i32> <i32 9, i32 6, i32 1, i32 0, i32 3, i32 7, i32 7, i32 0> @@ -568,7 +568,7 @@ define i16 @shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0(i16 %a) { ; AVX512F-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax -; AVX512F-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512F-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -580,7 +580,7 @@ define i16 @shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0(i16 %a) { ; AVX512VL-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512VL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512VL-NEXT: kmovw %k0, %eax -; AVX512VL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; AVX512VL-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq ; @@ -591,7 +591,7 @@ define i16 @shuf16i1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0(i16 %a) { ; VL_BW_DQ-NEXT: vpbroadcastd %xmm0, %zmm0 ; VL_BW_DQ-NEXT: vpmovd2m %zmm0, %k0 ; VL_BW_DQ-NEXT: kmovd %k0, %eax -; VL_BW_DQ-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> +; VL_BW_DQ-NEXT: # kill: %ax<def> %ax<kill> %eax<kill> ; VL_BW_DQ-NEXT: vzeroupper ; VL_BW_DQ-NEXT: retq %b = bitcast i16 %a to <16 x i1> diff --git a/test/CodeGen/X86/vector-shuffle-variable-128.ll b/test/CodeGen/X86/vector-shuffle-variable-128.ll index 6a72e1834d0..c0a58640b56 100644 --- a/test/CodeGen/X86/vector-shuffle-variable-128.ll +++ b/test/CodeGen/X86/vector-shuffle-variable-128.ll @@ -37,8 +37,8 @@ define <2 x double> @var_shuffle_v2f64_v2f64_xx_i64(<2 x double> %x, i64 %i0, i6 define <2 x i64> @var_shuffle_v2i64_v2i64_xx_i64(<2 x i64> %x, i32 %i0, i32 %i1) nounwind { ; SSE-LABEL: var_shuffle_v2i64_v2i64_xx_i64: ; SSE: # BB#0: -; SSE-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE-NEXT: andl $1, %edi ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: andl $1, %esi @@ -49,8 +49,8 @@ define <2 x i64> @var_shuffle_v2i64_v2i64_xx_i64(<2 x i64> %x, i32 %i0, i32 %i1) ; ; AVX-LABEL: var_shuffle_v2i64_v2i64_xx_i64: ; AVX: # BB#0: -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $1, %edi ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: andl $1, %esi @@ -68,10 +68,10 @@ define <2 x i64> @var_shuffle_v2i64_v2i64_xx_i64(<2 x i64> %x, i32 %i0, i32 %i1) define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { ; SSE2-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: ; SSE2: # BB#0: -; SSE2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-NEXT: andl $3, %edi ; SSE2-NEXT: andl $3, %esi ; SSE2-NEXT: andl $3, %edx @@ -88,10 +88,10 @@ define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i3 ; ; SSSE3-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: ; SSSE3: # BB#0: -; SSSE3-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSSE3-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSSE3-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSSE3-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSSE3-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSSE3-NEXT: andl $3, %edi ; SSSE3-NEXT: andl $3, %esi ; SSSE3-NEXT: andl $3, %edx @@ -108,10 +108,10 @@ define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i3 ; ; SSE41-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: ; SSE41: # BB#0: -; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE41-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE41-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE41-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE41-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE41-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE41-NEXT: andl $3, %edi ; SSE41-NEXT: andl $3, %esi ; SSE41-NEXT: andl $3, %edx @@ -125,10 +125,10 @@ define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i3 ; ; AVX-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: ; AVX: # BB#0: -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $3, %edi ; AVX-NEXT: andl $3, %esi ; AVX-NEXT: andl $3, %edx @@ -153,10 +153,10 @@ define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i3 define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { ; SSE2-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: ; SSE2: # BB#0: -; SSE2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-NEXT: andl $3, %edi ; SSE2-NEXT: andl $3, %esi ; SSE2-NEXT: andl $3, %edx @@ -173,10 +173,10 @@ define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i ; ; SSSE3-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: ; SSSE3: # BB#0: -; SSSE3-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSSE3-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSSE3-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSSE3-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSSE3-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSSE3-NEXT: andl $3, %edi ; SSSE3-NEXT: andl $3, %esi ; SSSE3-NEXT: andl $3, %edx @@ -193,10 +193,10 @@ define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i ; ; SSE41-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: ; SSE41: # BB#0: -; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE41-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE41-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE41-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE41-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE41-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE41-NEXT: andl $3, %edi ; SSE41-NEXT: andl $3, %esi ; SSE41-NEXT: andl $3, %edx @@ -210,10 +210,10 @@ define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i ; ; AVX-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: ; AVX: # BB#0: -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $3, %edi ; AVX-NEXT: andl $3, %esi ; AVX-NEXT: andl $3, %edx @@ -238,12 +238,12 @@ define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i16 %i1, i16 %i2, i16 %i3, i16 %i4, i16 %i5, i16 %i6, i16 %i7) nounwind { ; SSE2-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: ; SSE2: # BB#0: -; SSE2-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE2-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE2-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-NEXT: andl $7, %edi ; SSE2-NEXT: andl $7, %esi ; SSE2-NEXT: andl $7, %edx @@ -282,12 +282,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1 ; ; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: ; SSSE3: # BB#0: -; SSSE3-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSSE3-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSSE3-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSSE3-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSSE3-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSSE3-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSSE3-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSSE3-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSSE3-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSSE3-NEXT: andl $7, %edi ; SSSE3-NEXT: andl $7, %esi ; SSSE3-NEXT: andl $7, %edx @@ -326,12 +326,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1 ; ; SSE41-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: ; SSE41: # BB#0: -; SSE41-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE41-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE41-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE41-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE41-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE41-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE41-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE41-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE41-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE41-NEXT: andl $7, %edi ; SSE41-NEXT: andl $7, %esi ; SSE41-NEXT: andl $7, %edx @@ -356,12 +356,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1 ; ; AVX-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: ; AVX: # BB#0: -; AVX-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $7, %edi ; AVX-NEXT: andl $7, %esi ; AVX-NEXT: andl $7, %edx @@ -405,12 +405,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1 define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 %i0, i8 %i1, i8 %i2, i8 %i3, i8 %i4, i8 %i5, i8 %i6, i8 %i7, i8 %i8, i8 %i9, i8 %i10, i8 %i11, i8 %i12, i8 %i13, i8 %i14, i8 %i15) nounwind { ; SSE2-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: ; SSE2: # BB#0: -; SSE2-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE2-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE2-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: andl $15, %eax @@ -490,12 +490,12 @@ define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 % ; ; SSSE3-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: ; SSSE3: # BB#0: -; SSSE3-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSSE3-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSSE3-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSSE3-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSSE3-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSSE3-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSSE3-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSSE3-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSSE3-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax ; SSSE3-NEXT: andl $15, %eax @@ -575,12 +575,12 @@ define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 % ; ; SSE41-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: ; SSE41: # BB#0: -; SSE41-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE41-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE41-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE41-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE41-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE41-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE41-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE41-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE41-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE41-NEXT: andl $15, %edi ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rax @@ -630,12 +630,12 @@ define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 % ; ; AVX-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: ; AVX: # BB#0: -; AVX-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $15, %edi ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rax @@ -1168,9 +1168,9 @@ define <16 x i8> @mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8* define <4 x float> @var_shuffle_v4f32_v4f32_x0yx_i32(<4 x float> %x, <4 x float> %y, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { ; SSE-LABEL: var_shuffle_v4f32_v4f32_x0yx_i32: ; SSE: # BB#0: -; SSE-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE-NEXT: andl $3, %edi ; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) ; SSE-NEXT: andl $3, %edx @@ -1185,9 +1185,9 @@ define <4 x float> @var_shuffle_v4f32_v4f32_x0yx_i32(<4 x float> %x, <4 x float> ; ; AVX-LABEL: var_shuffle_v4f32_v4f32_x0yx_i32: ; AVX: # BB#0: -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $3, %edi ; AVX-NEXT: vmovaps %xmm1, -{{[0-9]+}}(%rsp) ; AVX-NEXT: andl $3, %edx @@ -1213,12 +1213,12 @@ define <4 x float> @var_shuffle_v4f32_v4f32_x0yx_i32(<4 x float> %x, <4 x float> define <8 x i16> @var_shuffle_v8i16_v8i16_xyxyxy00_i16(<8 x i16> %x, <8 x i16> %y, i16 %i0, i16 %i1, i16 %i2, i16 %i3, i16 %i4, i16 %i5, i16 %i6, i16 %i7) nounwind { ; SSE2-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; SSE2: # BB#0: -; SSE2-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE2-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE2-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE2-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE2-NEXT: andl $7, %edi ; SSE2-NEXT: andl $7, %esi ; SSE2-NEXT: andl $7, %edx @@ -1250,12 +1250,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xyxyxy00_i16(<8 x i16> %x, <8 x i16> % ; ; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; SSSE3: # BB#0: -; SSSE3-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSSE3-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSSE3-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSSE3-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSSE3-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSSE3-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSSE3-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSSE3-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSSE3-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSSE3-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSSE3-NEXT: andl $7, %edi ; SSSE3-NEXT: andl $7, %esi ; SSSE3-NEXT: andl $7, %edx @@ -1287,12 +1287,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xyxyxy00_i16(<8 x i16> %x, <8 x i16> % ; ; SSE41-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; SSE41: # BB#0: -; SSE41-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; SSE41-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; SSE41-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; SSE41-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; SSE41-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; SSE41-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; SSE41-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; SSE41-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; SSE41-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; SSE41-NEXT: andl $7, %edi ; SSE41-NEXT: andl $7, %esi ; SSE41-NEXT: andl $7, %edx @@ -1312,12 +1312,12 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xyxyxy00_i16(<8 x i16> %x, <8 x i16> % ; ; AVX-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; AVX: # BB#0: -; AVX-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX-NEXT: andl $7, %edi ; AVX-NEXT: andl $7, %esi ; AVX-NEXT: andl $7, %edx diff --git a/test/CodeGen/X86/vector-shuffle-variable-256.ll b/test/CodeGen/X86/vector-shuffle-variable-256.ll index f1ab54467a4..aa60e774232 100644 --- a/test/CodeGen/X86/vector-shuffle-variable-256.ll +++ b/test/CodeGen/X86/vector-shuffle-variable-256.ll @@ -185,12 +185,12 @@ define <8 x float> @var_shuffle_v8f32_v8f32_xxxxxxxx_i32(<8 x float> %x, i32 %i0 ; ALL-NEXT: movq %rsp, %rbp ; ALL-NEXT: andq $-32, %rsp ; ALL-NEXT: subq $64, %rsp -; ALL-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; ALL-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; ALL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; ALL-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; ALL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ALL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ALL-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; ALL-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; ALL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; ALL-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; ALL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ALL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ALL-NEXT: andl $7, %edi ; ALL-NEXT: andl $7, %esi ; ALL-NEXT: andl $7, %edx @@ -236,12 +236,12 @@ define <8 x float> @var_shuffle_v8f32_v8f32_xxxxxxxx_i32(<8 x float> %x, i32 %i0 define <8 x float> @var_shuffle_v8f32_v4f32_xxxxxxxx_i32(<4 x float> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7) nounwind { ; ALL-LABEL: var_shuffle_v8f32_v4f32_xxxxxxxx_i32: ; ALL: # BB#0: -; ALL-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; ALL-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; ALL-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; ALL-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; ALL-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; ALL-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; ALL-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; ALL-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; ALL-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; ALL-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; ALL-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; ALL-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; ALL-NEXT: andl $3, %edi ; ALL-NEXT: andl $3, %esi ; ALL-NEXT: andl $3, %edx @@ -289,12 +289,12 @@ define <16 x i16> @var_shuffle_v16i16_v16i16_xxxxxxxxxxxxxxxx_i16(<16 x i16> %x, ; AVX1-NEXT: movq %rsp, %rbp ; AVX1-NEXT: andq $-32, %rsp ; AVX1-NEXT: subq $64, %rsp -; AVX1-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX1-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX1-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX1-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX1-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX1-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX1-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: andl $15, %edi ; AVX1-NEXT: vmovaps %ymm0, (%rsp) ; AVX1-NEXT: movzwl (%rsp,%rdi,2), %eax @@ -351,12 +351,12 @@ define <16 x i16> @var_shuffle_v16i16_v16i16_xxxxxxxxxxxxxxxx_i16(<16 x i16> %x, ; AVX2-NEXT: movq %rsp, %rbp ; AVX2-NEXT: andq $-32, %rsp ; AVX2-NEXT: subq $64, %rsp -; AVX2-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX2-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX2-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: andl $15, %edi ; AVX2-NEXT: vmovaps %ymm0, (%rsp) ; AVX2-NEXT: movzwl (%rsp,%rdi,2), %eax @@ -444,12 +444,12 @@ define <16 x i16> @var_shuffle_v16i16_v16i16_xxxxxxxxxxxxxxxx_i16(<16 x i16> %x, define <16 x i16> @var_shuffle_v16i16_v8i16_xxxxxxxxxxxxxxxx_i16(<8 x i16> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, i32 %i11, i32 %i12, i32 %i13, i32 %i14, i32 %i15) nounwind { ; AVX1-LABEL: var_shuffle_v16i16_v8i16_xxxxxxxxxxxxxxxx_i16: ; AVX1: # BB#0: -; AVX1-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX1-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX1-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX1-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX1-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX1-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX1-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX1-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX1-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX1-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX1-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX1-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX1-NEXT: andl $7, %edi ; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX1-NEXT: movzwl -24(%rsp,%rdi,2), %eax @@ -500,12 +500,12 @@ define <16 x i16> @var_shuffle_v16i16_v8i16_xxxxxxxxxxxxxxxx_i16(<8 x i16> %x, i ; ; AVX2-LABEL: var_shuffle_v16i16_v8i16_xxxxxxxxxxxxxxxx_i16: ; AVX2: # BB#0: -; AVX2-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def> -; AVX2-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def> -; AVX2-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def> -; AVX2-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<def> -; AVX2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> -; AVX2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def> +; AVX2-NEXT: # kill: %r9d<def> %r9d<kill> %r9<def> +; AVX2-NEXT: # kill: %r8d<def> %r8d<kill> %r8<def> +; AVX2-NEXT: # kill: %ecx<def> %ecx<kill> %rcx<def> +; AVX2-NEXT: # kill: %edx<def> %edx<kill> %rdx<def> +; AVX2-NEXT: # kill: %esi<def> %esi<kill> %rsi<def> +; AVX2-NEXT: # kill: %edi<def> %edi<kill> %rdi<def> ; AVX2-NEXT: andl $7, %edi ; AVX2-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX2-NEXT: movzwl -24(%rsp,%rdi,2), %eax diff --git a/test/CodeGen/X86/vector-trunc-math.ll b/test/CodeGen/X86/vector-trunc-math.ll index a3044b65ce4..c399ea077cc 100644 --- a/test/CodeGen/X86/vector-trunc-math.ll +++ b/test/CodeGen/X86/vector-trunc-math.ll @@ -33,7 +33,7 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -41,7 +41,7 @@ define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = add <4 x i64> %a0, %a1 @@ -101,7 +101,7 @@ define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -146,7 +146,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -154,7 +154,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = add <8 x i32> %a0, %a1 @@ -383,7 +383,7 @@ define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -435,7 +435,7 @@ define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; ; AVX512-LABEL: trunc_add_v8i32_v8i16_sext_8i8: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512-NEXT: vpmovsxbw %xmm0, %xmm0 ; AVX512-NEXT: vpaddw %xmm1, %xmm0, %xmm0 @@ -477,7 +477,7 @@ define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; ; AVX512-LABEL: trunc_add_const_v4i64_v4i32: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -576,7 +576,7 @@ define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; ; AVX512-LABEL: trunc_add_const_v8i32_v8i16: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -771,7 +771,7 @@ define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; ; AVX512BW-LABEL: trunc_add_const_v16i16_v16i8: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper @@ -816,7 +816,7 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -824,7 +824,7 @@ define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = sub <4 x i64> %a0, %a1 @@ -884,7 +884,7 @@ define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -929,7 +929,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -937,7 +937,7 @@ define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = sub <8 x i32> %a0, %a1 @@ -1166,7 +1166,7 @@ define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpsubw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1214,7 +1214,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1222,7 +1222,7 @@ define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = sub <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3> @@ -1287,7 +1287,7 @@ define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1331,7 +1331,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1339,7 +1339,7 @@ define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = sub <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -1567,7 +1567,7 @@ define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1635,8 +1635,8 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; ; AVX512F-LABEL: trunc_mul_v4i64_v4i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512F-NEXT: vpmulld %xmm1, %xmm0, %xmm0 @@ -1645,8 +1645,8 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; ; AVX512BW-LABEL: trunc_mul_v4i64_v4i32: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512BW-NEXT: vpmulld %xmm1, %xmm0, %xmm0 @@ -1655,11 +1655,11 @@ define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; ; AVX512DQ-LABEL: trunc_mul_v4i64_v4i32: ; AVX512DQ: # BB#0: -; AVX512DQ-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512DQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512DQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq %1 = mul <4 x i64> %a0, %a1 @@ -1810,7 +1810,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -1818,7 +1818,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpmulld %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = mul <8 x i32> %a0, %a1 @@ -2241,7 +2241,7 @@ define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -2293,7 +2293,7 @@ define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) { ; ; AVX512-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> +; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> ; AVX512-NEXT: vpmovdw %zmm1, %ymm1 ; AVX512-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512-NEXT: vpmullw %xmm1, %xmm0, %xmm0 @@ -2350,7 +2350,7 @@ define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; ; AVX512-LABEL: trunc_mul_const_v4i64_v4i32: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2449,7 +2449,7 @@ define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; ; AVX512-LABEL: trunc_mul_const_v8i32_v8i16: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -2793,7 +2793,7 @@ define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -2834,7 +2834,7 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -2842,7 +2842,7 @@ define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = and <4 x i64> %a0, %a1 @@ -2898,7 +2898,7 @@ define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -2941,7 +2941,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -2949,7 +2949,7 @@ define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = and <8 x i32> %a0, %a1 @@ -3164,7 +3164,7 @@ define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -3209,7 +3209,7 @@ define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; ; AVX512-LABEL: trunc_and_const_v4i64_v4i32: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3308,7 +3308,7 @@ define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; ; AVX512-LABEL: trunc_and_const_v8i32_v8i16: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -3503,7 +3503,7 @@ define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; ; AVX512BW-LABEL: trunc_and_const_v16i16_v16i8: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper @@ -3546,7 +3546,7 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -3554,7 +3554,7 @@ define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = xor <4 x i64> %a0, %a1 @@ -3610,7 +3610,7 @@ define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -3653,7 +3653,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -3661,7 +3661,7 @@ define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = xor <8 x i32> %a0, %a1 @@ -3876,7 +3876,7 @@ define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwin ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -3921,7 +3921,7 @@ define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; ; AVX512-LABEL: trunc_xor_const_v4i64_v4i32: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4020,7 +4020,7 @@ define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; ; AVX512-LABEL: trunc_xor_const_v8i32_v8i16: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4215,7 +4215,7 @@ define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; ; AVX512BW-LABEL: trunc_xor_const_v16i16_v16i8: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper @@ -4258,7 +4258,7 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -4266,7 +4266,7 @@ define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = or <4 x i64> %a0, %a1 @@ -4322,7 +4322,7 @@ define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -4365,7 +4365,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -4373,7 +4373,7 @@ define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; AVX512: # BB#0: ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = or <8 x i32> %a0, %a1 @@ -4588,7 +4588,7 @@ define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind ; AVX512BW: # BB#0: ; AVX512BW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -4633,7 +4633,7 @@ define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind { ; ; AVX512-LABEL: trunc_or_const_v4i64_v4i32: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4732,7 +4732,7 @@ define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind { ; ; AVX512-LABEL: trunc_or_const_v8i32_v8i16: ; AVX512: # BB#0: -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper @@ -4927,7 +4927,7 @@ define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind { ; ; AVX512BW-LABEL: trunc_or_const_v16i16_v16i8: ; AVX512BW: # BB#0: -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-NEXT: vzeroupper diff --git a/test/CodeGen/X86/vector-trunc.ll b/test/CodeGen/X86/vector-trunc.ll index ac1083ad447..b5ba1ff24da 100644 --- a/test/CodeGen/X86/vector-trunc.ll +++ b/test/CodeGen/X86/vector-trunc.ll @@ -237,7 +237,7 @@ define <8 x i16> @trunc8i64_8i16(<8 x i64> %a) { ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; @@ -348,15 +348,15 @@ define <8 x i16> @trunc8i32_8i16(<8 x i32> %a) { ; AVX2: # BB#0: # %entry ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; ; AVX512F-LABEL: trunc8i32_8i16: ; AVX512F: # BB#0: # %entry -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -368,9 +368,9 @@ define <8 x i16> @trunc8i32_8i16(<8 x i32> %a) { ; ; AVX512BW-LABEL: trunc8i32_8i16: ; AVX512BW: # BB#0: # %entry -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -413,7 +413,7 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8 x i32> %a) { ; AVX512F: # BB#0: # %entry ; AVX512F-NEXT: vpsrad $16, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -428,7 +428,7 @@ define <8 x i16> @trunc8i32_8i16_ashr(<8 x i32> %a) { ; AVX512BW: # BB#0: # %entry ; AVX512BW-NEXT: vpsrad $16, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -492,7 +492,7 @@ define <8 x i16> @trunc8i32_8i16_lshr(<8 x i32> %a) { ; AVX512F: # BB#0: # %entry ; AVX512F-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512F-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512F-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq ; @@ -507,7 +507,7 @@ define <8 x i16> @trunc8i32_8i16_lshr(<8 x i32> %a) { ; AVX512BW: # BB#0: # %entry ; AVX512BW-NEXT: vpsrld $16, %ymm0, %ymm0 ; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0 -; AVX512BW-NEXT: # kill: %XMM0<def> %XMM0<kill> %YMM0<kill> +; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill> ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -574,7 +574,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) { ; ; AVX512F-LABEL: trunc8i32_8i8: ; AVX512F: # BB#0: # %entry -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX512F-NEXT: vmovq %xmm0, (%rax) @@ -589,7 +589,7 @@ define void @trunc8i32_8i8(<8 x i32> %a) { ; ; AVX512BW-LABEL: trunc8i32_8i8: ; AVX512BW: # BB#0: # %entry -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX512BW-NEXT: vmovq %xmm0, (%rax) @@ -1089,7 +1089,7 @@ define void @trunc16i16_16i8(<16 x i16> %a) { ; ; AVX512BW-LABEL: trunc16i16_16i8: ; AVX512BW: # BB#0: # %entry -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512BW-NEXT: vmovdqu %xmm0, (%rax) ; AVX512BW-NEXT: vzeroupper @@ -1379,8 +1379,8 @@ define <8 x i32> @trunc2x4i64_8i32(<4 x i64> %a, <4 x i64> %b) { ; ; AVX512F-LABEL: trunc2x4i64_8i32: ; AVX512F: # BB#0: # %entry -; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 @@ -1395,8 +1395,8 @@ define <8 x i32> @trunc2x4i64_8i32(<4 x i64> %a, <4 x i64> %b) { ; ; AVX512BW-LABEL: trunc2x4i64_8i32: ; AVX512BW: # BB#0: # %entry -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 @@ -1489,8 +1489,8 @@ define <8 x i16> @trunc2x4i64_8i16(<4 x i64> %a, <4 x i64> %b) { ; ; AVX512F-LABEL: trunc2x4i64_8i16: ; AVX512F: # BB#0: # %entry -; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512F-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] @@ -1516,8 +1516,8 @@ define <8 x i16> @trunc2x4i64_8i16(<4 x i64> %a, <4 x i64> %b) { ; ; AVX512BW-LABEL: trunc2x4i64_8i16: ; AVX512BW: # BB#0: # %entry -; AVX512BW-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512BW-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1 ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] diff --git a/test/CodeGen/X86/vector-tzcnt-128.ll b/test/CodeGen/X86/vector-tzcnt-128.ll index e8d81173615..8a3f9621b33 100644 --- a/test/CodeGen/X86/vector-tzcnt-128.ll +++ b/test/CodeGen/X86/vector-tzcnt-128.ll @@ -133,7 +133,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; AVX512VPOPCNTDQ-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -354,7 +354,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; AVX512VPOPCNTDQ-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -625,7 +625,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; AVX512VPOPCNTDQ-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -886,7 +886,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; AVX512VPOPCNTDQ-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: vzeroupper ; AVX512VPOPCNTDQ-NEXT: retq ; @@ -1104,7 +1104,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; BITALG_NOVLX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; @@ -1286,7 +1286,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; BITALG_NOVLX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; @@ -1449,7 +1449,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; BITALG_NOVLX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; @@ -1608,7 +1608,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 ; BITALG_NOVLX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: vzeroupper ; BITALG_NOVLX-NEXT: retq ; diff --git a/test/CodeGen/X86/vector-tzcnt-256.ll b/test/CodeGen/X86/vector-tzcnt-256.ll index 6e197139709..6de28399a2f 100644 --- a/test/CodeGen/X86/vector-tzcnt-256.ll +++ b/test/CodeGen/X86/vector-tzcnt-256.ll @@ -103,7 +103,7 @@ define <4 x i64> @testv4i64(<4 x i64> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv4i64: @@ -239,7 +239,7 @@ define <4 x i64> @testv4i64u(<4 x i64> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntq %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv4i64u: @@ -411,7 +411,7 @@ define <8 x i32> @testv8i32(<8 x i32> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv8i32: @@ -572,7 +572,7 @@ define <8 x i32> @testv8i32u(<8 x i32> %in) nounwind { ; AVX512VPOPCNTDQ-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; AVX512VPOPCNTDQ-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512VPOPCNTDQ-NEXT: vpopcntd %zmm0, %zmm0 -; AVX512VPOPCNTDQ-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512VPOPCNTDQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512VPOPCNTDQ-NEXT: retq ; ; BITALG_NOVLX-LABEL: testv8i32u: @@ -759,7 +759,7 @@ define <16 x i16> @testv16i16(<16 x i16> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; BITALG_NOVLX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv16i16: @@ -910,7 +910,7 @@ define <16 x i16> @testv16i16u(<16 x i16> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; BITALG_NOVLX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; BITALG_NOVLX-NEXT: vpopcntw %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv16i16u: @@ -1051,7 +1051,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; BITALG_NOVLX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv32i8: @@ -1189,7 +1189,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; BITALG_NOVLX-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 ; BITALG_NOVLX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; BITALG_NOVLX-NEXT: vpopcntb %zmm0, %zmm0 -; BITALG_NOVLX-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; BITALG_NOVLX-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; BITALG_NOVLX-NEXT: retq ; ; BITALG-LABEL: testv32i8u: diff --git a/test/CodeGen/X86/vpshufbitqbm-intrinsics.ll b/test/CodeGen/X86/vpshufbitqbm-intrinsics.ll index fc96a161ead..e490798bfd5 100644 --- a/test/CodeGen/X86/vpshufbitqbm-intrinsics.ll +++ b/test/CodeGen/X86/vpshufbitqbm-intrinsics.ll @@ -8,7 +8,7 @@ define i16 @test_vpshufbitqmb_128(<16 x i8> %a, <16 x i8> %b, i16 %mask) { ; CHECK-NEXT: kmovd %edi, %k1 ; CHECK-NEXT: vpshufbitqmb %xmm1, %xmm0, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill> +; CHECK-NEXT: ## kill: %ax<def> %ax<kill> %eax<kill> ; CHECK-NEXT: retq %res = call i16 @llvm.x86.avx512.mask.vpshufbitqmb.128(<16 x i8> %a, <16 x i8> %b, i16 %mask) ret i16 %res diff --git a/test/CodeGen/X86/vselect-pcmp.ll b/test/CodeGen/X86/vselect-pcmp.ll index a9ee1bcc32f..d162e342e5c 100644 --- a/test/CodeGen/X86/vselect-pcmp.ll +++ b/test/CodeGen/X86/vselect-pcmp.ll @@ -182,13 +182,13 @@ define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) ; ; AVX512F-LABEL: signbit_sel_v8i32: ; AVX512F: # BB#0: -; AVX512F-NEXT: # kill: %YMM2<def> %YMM2<kill> %ZMM2<def> -; AVX512F-NEXT: # kill: %YMM1<def> %YMM1<kill> %ZMM1<def> -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<def> +; AVX512F-NEXT: # kill: %ymm2<def> %ymm2<kill> %zmm2<def> +; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def> ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1 ; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} -; AVX512F-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512F-NEXT: retq ; ; AVX512VL-LABEL: signbit_sel_v8i32: diff --git a/test/CodeGen/X86/widen_bitops-0.ll b/test/CodeGen/X86/widen_bitops-0.ll index 132a2fd928f..ab27d497ebb 100644 --- a/test/CodeGen/X86/widen_bitops-0.ll +++ b/test/CodeGen/X86/widen_bitops-0.ll @@ -141,9 +141,9 @@ define <3 x i8> @and_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X32-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X32-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X32-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X32-SSE-NEXT: retl ; ; X64-SSE-LABEL: and_v3i8_as_i24: @@ -158,9 +158,9 @@ define <3 x i8> @and_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X64-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X64-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X64-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X64-SSE-NEXT: retq %1 = bitcast <3 x i8> %a to i24 %2 = bitcast <3 x i8> %b to i24 @@ -182,9 +182,9 @@ define <3 x i8> @xor_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X32-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X32-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X32-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X32-SSE-NEXT: retl ; ; X64-SSE-LABEL: xor_v3i8_as_i24: @@ -199,9 +199,9 @@ define <3 x i8> @xor_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X64-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X64-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X64-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X64-SSE-NEXT: retq %1 = bitcast <3 x i8> %a to i24 %2 = bitcast <3 x i8> %b to i24 @@ -223,9 +223,9 @@ define <3 x i8> @or_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X32-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X32-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X32-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X32-SSE-NEXT: retl ; ; X64-SSE-LABEL: or_v3i8_as_i24: @@ -240,9 +240,9 @@ define <3 x i8> @or_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx -; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> -; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill> -; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill> +; X64-SSE-NEXT: # kill: %al<def> %al<kill> %eax<kill> +; X64-SSE-NEXT: # kill: %dl<def> %dl<kill> %edx<kill> +; X64-SSE-NEXT: # kill: %cl<def> %cl<kill> %ecx<kill> ; X64-SSE-NEXT: retq %1 = bitcast <3 x i8> %a to i24 %2 = bitcast <3 x i8> %b to i24 diff --git a/test/CodeGen/X86/x86-interleaved-access.ll b/test/CodeGen/X86/x86-interleaved-access.ll index acad9f771fc..2b2ef74a682 100644 --- a/test/CodeGen/X86/x86-interleaved-access.ll +++ b/test/CodeGen/X86/x86-interleaved-access.ll @@ -651,7 +651,7 @@ define <16 x i1> @interleaved_load_vf16_i8_stride4(<64 x i8>* %ptr) { ; AVX512-NEXT: vpmovb2m %zmm0, %k1 ; AVX512-NEXT: kxnorw %k1, %k0, %k0 ; AVX512-NEXT: vpmovm2b %k0, %zmm0 -; AVX512-NEXT: # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %zmm0<kill> ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %wide.vec = load <64 x i8>, <64 x i8>* %ptr @@ -964,7 +964,7 @@ define <32 x i1> @interleaved_load_vf32_i8_stride4(<128 x i8>* %ptr) { ; AVX512-NEXT: vpmovb2m %zmm0, %k1 ; AVX512-NEXT: kxnord %k1, %k0, %k0 ; AVX512-NEXT: vpmovm2b %k0, %zmm0 -; AVX512-NEXT: # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill> +; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<kill> ; AVX512-NEXT: retq %wide.vec = load <128 x i8>, <128 x i8>* %ptr %v1 = shufflevector <128 x i8> %wide.vec, <128 x i8> undef, <32 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28, i32 32, i32 36, i32 40, i32 44, i32 48, i32 52, i32 56, i32 60, i32 64, i32 68, i32 72, i32 76, i32 80, i32 84, i32 88, i32 92, i32 96, i32 100, i32 104, i32 108, i32 112, i32 116, i32 120, i32 124> diff --git a/test/CodeGen/X86/x86-interrupt_cc.ll b/test/CodeGen/X86/x86-interrupt_cc.ll index b91b8fbfb76..3251d731468 100644 --- a/test/CodeGen/X86/x86-interrupt_cc.ll +++ b/test/CodeGen/X86/x86-interrupt_cc.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx -show-mc-encoding -mattr=+avx512f < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64 ; RUN: llc -verify-machineinstrs -mtriple=i386-apple-macosx -show-mc-encoding -mattr=+avx512f < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK32 -; Make sure we spill the high numbered ZMM registers and K registers with the right encoding. +; Make sure we spill the high numbered zmm registers and K registers with the right encoding. ; CHECK-LABEL: foo ; CHECK: kmovq %k7, {{.+}} ; CHECK64: encoding: [0xc4,0xe1,0xf8,0x91,0xbc,0x24,0x68,0x08,0x00,0x00] diff --git a/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll b/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll index 763d764698d..8eb299d9360 100644 --- a/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll +++ b/test/CodeGen/X86/x86-no_caller_saved_registers-preserve.ll @@ -3,10 +3,10 @@ ;; In functions with 'no_caller_saved_registers' attribute, all registers should ;; be preserved except for registers used for passing/returning arguments. -;; In the following function registers %RDI, %RSI and %XMM0 are used to store -;; arguments %a0, %a1 and %b0 accordingally. The value is returned in %RAX. +;; In the following function registers %rdi, %rsi and %xmm0 are used to store +;; arguments %a0, %a1 and %b0 accordingally. The value is returned in %rax. ;; The above registers should not be preserved, however other registers -;; (that are modified by the function) should be preserved (%RDX and %XMM1). +;; (that are modified by the function) should be preserved (%rdx and %xmm1). define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 { ; CHECK-LABEL: bar: ; CHECK: # BB#0: @@ -27,7 +27,7 @@ define x86_64_sysvcc i32 @bar(i32 %a0, i32 %a1, float %b0) #0 { ;; Because "bar" has 'no_caller_saved_registers' attribute, function "foo" ;; doesn't need to preserve registers except for the arguments passed -;; to "bar" (%ESI, %EDI and %XMM0). +;; to "bar" (%esi, %edi and %xmm0). define x86_64_sysvcc float @foo(i32 %a0, i32 %a1, float %b0) { ; CHECK-LABEL: foo ; CHECK: movaps %xmm0, %xmm1 diff --git a/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll b/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll index 8e081b9e410..9dc0d9f7113 100644 --- a/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll +++ b/test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll @@ -8,7 +8,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" define <4 x i64> @broadcast128(<2 x i64> %src) { ; CHECK-LABEL: broadcast128: ; CHECK: ## BB#0: -; CHECK-NEXT: ## kill: %XMM0<def> %XMM0<kill> %YMM0<def> +; CHECK-NEXT: ## kill: %xmm0<def> %xmm0<kill> %ymm0<def> ; CHECK-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; CHECK-NEXT: retq diff --git a/test/DebugInfo/ARM/PR16736.ll b/test/DebugInfo/ARM/PR16736.ll index 3369a90e1d9..65caba85864 100644 --- a/test/DebugInfo/ARM/PR16736.ll +++ b/test/DebugInfo/ARM/PR16736.ll @@ -2,7 +2,7 @@ ; RUN: llc -filetype=obj < %s \ ; RUN: | llvm-dwarfdump -debug-info - | FileCheck %s --check-prefix=DWARF ; -; CHECK: @DEBUG_VALUE: h:x <- [DW_OP_plus_uconst {{.*}}] [%R{{.*}}+0] +; CHECK: @DEBUG_VALUE: h:x <- [DW_OP_plus_uconst {{.*}}] [%r{{.*}}+0] ; DWARF: DW_TAG_formal_parameter ; DWARF: DW_AT_location ; DWARF-NEXT: DW_OP_reg0 R0 diff --git a/test/DebugInfo/ARM/sdag-split-arg.ll b/test/DebugInfo/ARM/sdag-split-arg.ll index 9f13d4f8486..af16f953241 100644 --- a/test/DebugInfo/ARM/sdag-split-arg.ll +++ b/test/DebugInfo/ARM/sdag-split-arg.ll @@ -19,8 +19,8 @@ target triple = "thumbv7k-apple-watchos2.0.0" ; Function Attrs: optsize ssp define i64 @_Z3foox(i64 returned) local_unnamed_addr #0 !dbg !13 { tail call void @llvm.dbg.value(metadata i64 %0, metadata !17, metadata !DIExpression()), !dbg !18 - ; CHECK: @DEBUG_VALUE: foo:offset <- [DW_OP_LLVM_fragment 0 32] %R5 - ; CHECK: @DEBUG_VALUE: foo:offset <- [DW_OP_LLVM_fragment 32 32] %R4 + ; CHECK: @DEBUG_VALUE: foo:offset <- [DW_OP_LLVM_fragment 0 32] %r5 + ; CHECK: @DEBUG_VALUE: foo:offset <- [DW_OP_LLVM_fragment 32 32] %r4 %2 = load i64, i64* @g, align 8, !dbg !19, !tbaa !21 %3 = icmp eq i64 %2, %0, !dbg !19 diff --git a/test/DebugInfo/COFF/fpo-csrs.ll b/test/DebugInfo/COFF/fpo-csrs.ll index 5c5ca888d14..92a0cc07c79 100644 --- a/test/DebugInfo/COFF/fpo-csrs.ll +++ b/test/DebugInfo/COFF/fpo-csrs.ll @@ -65,7 +65,7 @@ entry: ; ASM: pushl %esi ; ASM: .cv_fpo_pushreg %esi ; ASM: .cv_fpo_endprologue -; ASM: #DEBUG_VALUE: csr1:a <- %ESI +; ASM: #DEBUG_VALUE: csr1:a <- %esi ; ASM: retl ; ASM: .cv_fpo_endproc @@ -122,8 +122,8 @@ entry: ; ASM: pushl %esi ; ASM: .cv_fpo_pushreg %esi ; ASM: .cv_fpo_endprologue -; ASM: #DEBUG_VALUE: csr2:a <- %ESI -; ASM: #DEBUG_VALUE: csr2:b <- %EDI +; ASM: #DEBUG_VALUE: csr2:a <- %esi +; ASM: #DEBUG_VALUE: csr2:b <- %edi ; ASM: retl ; ASM: .cv_fpo_endproc @@ -192,9 +192,9 @@ entry: ; ASM: pushl %esi ; ASM: .cv_fpo_pushreg %esi ; ASM: .cv_fpo_endprologue -; ASM: #DEBUG_VALUE: csr3:a <- %ESI -; ASM: #DEBUG_VALUE: csr3:b <- %EDI -; ASM: #DEBUG_VALUE: csr3:c <- %EBX +; ASM: #DEBUG_VALUE: csr3:a <- %esi +; ASM: #DEBUG_VALUE: csr3:b <- %edi +; ASM: #DEBUG_VALUE: csr3:c <- %ebx ; ASM: retl ; ASM: .cv_fpo_endproc @@ -279,10 +279,10 @@ entry: ; ASM: pushl %esi ; ASM: .cv_fpo_pushreg %esi ; ASM: .cv_fpo_endprologue -; ASM: #DEBUG_VALUE: csr4:a <- %ESI -; ASM: #DEBUG_VALUE: csr4:b <- %EDI -; ASM: #DEBUG_VALUE: csr4:c <- %EBX -; ASM: #DEBUG_VALUE: csr4:d <- %EBP +; ASM: #DEBUG_VALUE: csr4:a <- %esi +; ASM: #DEBUG_VALUE: csr4:b <- %edi +; ASM: #DEBUG_VALUE: csr4:c <- %ebx +; ASM: #DEBUG_VALUE: csr4:d <- %ebp ; ASM: retl ; ASM: .cv_fpo_endproc diff --git a/test/DebugInfo/COFF/local-variable-gap.ll b/test/DebugInfo/COFF/local-variable-gap.ll index 1fc56bf1e14..d0e2188098f 100644 --- a/test/DebugInfo/COFF/local-variable-gap.ll +++ b/test/DebugInfo/COFF/local-variable-gap.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=x86_64-windows-msvc < %s -filetype=obj | llvm-readobj -codeview - | FileCheck %s --check-prefix=OBJ ; This test attempts to exercise gaps in local variables. The local variable 'p' -; will end up in some CSR (ESI), which will be used in both the BB scheduled +; will end up in some CSR (esi), which will be used in both the BB scheduled ; discontiguously out of line and the normal return BB. The best way to encode ; this is to use a LocalVariableAddrGap. If the gap is too large, multiple ; ranges should be emitted. @@ -33,13 +33,13 @@ ; ASM: callq vardef ; ASM: movl %eax, %esi ; ASM: [[p_b1:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: p <- %ESI +; ASM: #DEBUG_VALUE: p <- %esi ; ASM: callq barrier ; ASM: movl %esi, %ecx ; ASM: testl %eax, %eax ; ASM: jne .LBB0_5 ; ASM: # BB#2: # %if.end -; ASM: #DEBUG_VALUE: p <- %ESI +; ASM: #DEBUG_VALUE: p <- %esi ; ASM: callq use ; ASM: jmp .LBB0_4 ; ASM: [[p_e1:\.Ltmp[0-9]+]]: @@ -52,7 +52,7 @@ ; ASM: retq ; ASM: .LBB0_5: # %if.then4 ; ASM: [[p_b2:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: p <- %ESI +; ASM: #DEBUG_VALUE: p <- %esi ; ASM: callq call_noreturn ; ASM: ud2 ; ASM: .Lfunc_end0: diff --git a/test/DebugInfo/COFF/pieces.ll b/test/DebugInfo/COFF/pieces.ll index 9e1d7408b84..5c5b5a1da37 100644 --- a/test/DebugInfo/COFF/pieces.ll +++ b/test/DebugInfo/COFF/pieces.ll @@ -43,19 +43,19 @@ ; ASM: .p2align 4, 0x90 ; ASM: .LBB0_3: # %for.body ; ASM: [[ox_start:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] %EDI +; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] %edi ; ASM: .cv_loc 0 1 13 11 # t.c:13:11 ; ASM: movl %edi, %ecx ; ASM: callq g ; ASM: movl %eax, %edi ; ASM: [[oy_start:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] %EDI -; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] %ESI +; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] %edi +; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] %esi ; ASM: .cv_loc 0 1 14 11 # t.c:14:11 ; ASM: movl %esi, %ecx ; ASM: callq g ; ASM: movl %eax, %esi -; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] %ESI +; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] %esi ; ASM: cmpl n(%rip), %eax ; ASM: jl .LBB0_3 ; ASM: [[oy_end:\.Ltmp[0-9]+]]: @@ -64,23 +64,23 @@ ; ASM-LABEL: pad_right: # @pad_right -; ASM: #DEBUG_VALUE: pad_right:o <- [DW_OP_LLVM_fragment 32 32] %ECX +; ASM: #DEBUG_VALUE: pad_right:o <- [DW_OP_LLVM_fragment 32 32] %ecx ; ASM: movl %ecx, %eax ; ASM: retq ; ASM-LABEL: pad_left: # @pad_left -; ASM: #DEBUG_VALUE: pad_left:o <- [DW_OP_LLVM_fragment 0 32] %ECX +; ASM: #DEBUG_VALUE: pad_left:o <- [DW_OP_LLVM_fragment 0 32] %ecx ; ASM: .cv_loc 2 1 24 3 # t.c:24:3 ; ASM: movl %ecx, %eax ; ASM: retq ; ASM-LABEL: nested: # @nested -; ASM: #DEBUG_VALUE: nested:o <- [DW_OP_deref] [%RCX+0] +; ASM: #DEBUG_VALUE: nested:o <- [DW_OP_deref] [%rcx+0] ; ASM: movl 12(%rcx), %eax ; ASM: [[p_start:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: nested:p <- [DW_OP_LLVM_fragment 32 32] %EAX +; ASM: #DEBUG_VALUE: nested:p <- [DW_OP_LLVM_fragment 32 32] %eax ; ASM: retq ; ASM-LABEL: bitpiece_spill: # @bitpiece_spill @@ -89,7 +89,7 @@ ; ASM: callq g ; ASM: movl %eax, [[offset_o_x:[0-9]+]](%rsp) # 4-byte Spill ; ASM: [[spill_o_x_start:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_LLVM_fragment 32 32] [%RSP+0] +; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_LLVM_fragment 32 32] [%rsp+0] ; ASM: #APP ; ASM: #NO_APP ; ASM: movl [[offset_o_x]](%rsp), %eax # 4-byte Reload diff --git a/test/DebugInfo/COFF/register-variables.ll b/test/DebugInfo/COFF/register-variables.ll index 52c447d7723..c00d3d3b62e 100644 --- a/test/DebugInfo/COFF/register-variables.ll +++ b/test/DebugInfo/COFF/register-variables.ll @@ -26,30 +26,30 @@ ; ASM: # BB#0: # %entry ; ASM: pushq %rsi ; ASM: subq $32, %rsp -; ASM: #DEBUG_VALUE: f:p <- %ECX +; ASM: #DEBUG_VALUE: f:p <- %ecx ; ASM: movl %ecx, %esi ; ASM: [[p_ecx_esi:\.Ltmp.*]]: -; ASM: #DEBUG_VALUE: f:p <- %ESI +; ASM: #DEBUG_VALUE: f:p <- %esi ; ASM: callq getint ; ASM: [[after_getint:\.Ltmp.*]]: -; ASM: #DEBUG_VALUE: a <- %EAX -; ASM: #DEBUG_VALUE: inlineinc:a <- %EAX -; ASM: #DEBUG_VALUE: c <- %EAX +; ASM: #DEBUG_VALUE: a <- %eax +; ASM: #DEBUG_VALUE: inlineinc:a <- %eax +; ASM: #DEBUG_VALUE: c <- %eax ; ASM: testl %esi, %esi ; ASM: je .LBB0_2 ; ASM: [[after_je:\.Ltmp.*]]: ; ASM: # BB#1: # %if.then -; ASM-DAG: #DEBUG_VALUE: inlineinc:a <- %EAX -; ASM-DAG: #DEBUG_VALUE: a <- %EAX -; ASM-DAG: #DEBUG_VALUE: f:p <- %ESI +; ASM-DAG: #DEBUG_VALUE: inlineinc:a <- %eax +; ASM-DAG: #DEBUG_VALUE: a <- %eax +; ASM-DAG: #DEBUG_VALUE: f:p <- %esi ; ASM: addl $1, %eax ; ASM: [[after_inc_eax:\.Ltmp.*]]: -; ASM: #DEBUG_VALUE: inlineinc:b <- %EAX -; ASM: #DEBUG_VALUE: b <- %EAX +; ASM: #DEBUG_VALUE: inlineinc:b <- %eax +; ASM: #DEBUG_VALUE: b <- %eax ; ASM: addl $1, x(%rip) ; ASM: [[after_if:\.Ltmp.*]]: ; ASM: .LBB0_2: # %if.else -; ASM: #DEBUG_VALUE: f:p <- %ESI +; ASM: #DEBUG_VALUE: f:p <- %esi ; ASM: movl %eax, %ecx ; ASM: addq $32, %rsp ; ASM: popq %rsi diff --git a/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir b/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir index fdb8660dc06..a703f5f8f14 100644 --- a/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir +++ b/test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir @@ -147,15 +147,15 @@ body: | ... # Let's verify that the slot index ranges for the unused variables argc/argv, -# connected to physical regs %EDI and %RSI, does not overlap with the ranges +# connected to physical regs %edi and %rsi, does not overlap with the ranges # for %vreg2 and %vreg3. The register allocator is actually allocating the -# virtual registers # to %EDI and %ESI, so the ranges for argc/argv should +# virtual registers # to %edi and %esi, so the ranges for argc/argv should # not cover the whole BB. # # CHECKDBG-LABEL: ********** EMITTING LIVE DEBUG VARIABLES ********** -# CHECKDBG-NEXT: !"argc,5" [0B;0e):0 Loc0=%EDI +# CHECKDBG-NEXT: !"argc,5" [0B;0e):0 Loc0=%edi # CHECKDBG-NEXT: [0B;0e):0 BB#0-160B -# CHECKDBG-NEXT: !"argv,5" [0B;0e):0 Loc0=%RSI +# CHECKDBG-NEXT: !"argv,5" [0B;0e):0 Loc0=%rsi # CHECKDBG-NEXT: [0B;0e):0 BB#0-160B # CHECKDBG-NEXT: !"a0,7" [16r;64r):0 Loc0=%vreg2 # CHECKDBG-NEXT: [16r;64r):0 BB#0-160B diff --git a/test/DebugInfo/X86/dbg-addr-dse.ll b/test/DebugInfo/X86/dbg-addr-dse.ll index 9d5d69dc66b..3fc66d9d109 100644 --- a/test/DebugInfo/X86/dbg-addr-dse.ll +++ b/test/DebugInfo/X86/dbg-addr-dse.ll @@ -47,12 +47,12 @@ entry: ; ASM-LABEL: f: # @f ; ASM: movl %ecx, [[OFF_X:[0-9]+]](%rsp) -; ASM: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] +; ASM: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%rsp+0] ; ASM: callq escape ; ASM: #DEBUG_VALUE: f:x <- 1 ; ASM: movl $1, global(%rip) ; FIXME: Needs a fix to LiveDebugVariables -; ASMX: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] +; ASMX: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%rsp+0] ; ASM: movl $2, [[OFF_X]](%rsp) ; ASM: callq escape ; ASM: retq diff --git a/test/DebugInfo/X86/dbg-addr.ll b/test/DebugInfo/X86/dbg-addr.ll index ffd0f77ebb7..7229849c3cd 100644 --- a/test/DebugInfo/X86/dbg-addr.ll +++ b/test/DebugInfo/X86/dbg-addr.ll @@ -7,7 +7,7 @@ ; is control-dependent. ; CHECK-LABEL: use_dbg_addr: -; CHECK: #DEBUG_VALUE: use_dbg_addr:o <- [%RSP+0] +; CHECK: #DEBUG_VALUE: use_dbg_addr:o <- [%rsp+0] ; FIXME: Avoid the use of a single-location location list and use ; DW_AT_start_offset instead. diff --git a/test/DebugInfo/X86/dbg-value-dag-combine.ll b/test/DebugInfo/X86/dbg-value-dag-combine.ll index 67e90e6f9cc..52237976f03 100644 --- a/test/DebugInfo/X86/dbg-value-dag-combine.ll +++ b/test/DebugInfo/X86/dbg-value-dag-combine.ll @@ -8,8 +8,8 @@ target triple = "i686-apple-darwin" ; CHECK-LABEL: __OpenCL_test_kernel: ; CHECK-DAG: ##DEBUG_VALUE: __OpenCL_test_kernel:ip <- ; CHECK-DAG: ##DEBUG_VALUE: xxx <- 0 -; CHECK-DAG: ##DEBUG_VALUE: gid <- %E{{..$}} -; CHECK-DAG: ##DEBUG_VALUE: idx <- %E{{..$}} +; CHECK-DAG: ##DEBUG_VALUE: gid <- %e{{..$}} +; CHECK-DAG: ##DEBUG_VALUE: idx <- %e{{..$}} ; CHECK-NOT: ##DEBUG_VALUE: declare <4 x i32> @__amdil_get_global_id_int() diff --git a/test/DebugInfo/X86/dbg-value-frame-index.ll b/test/DebugInfo/X86/dbg-value-frame-index.ll index a6a54613302..3d3a284a3cf 100644 --- a/test/DebugInfo/X86/dbg-value-frame-index.ll +++ b/test/DebugInfo/X86/dbg-value-frame-index.ll @@ -20,7 +20,7 @@ while.end: } ; CHECK-LABEL: test -; CHECK: #DEBUG_VALUE: test:w <- [DW_OP_plus_uconst 8] [%RSP+0] +; CHECK: #DEBUG_VALUE: test:w <- [DW_OP_plus_uconst 8] [%rsp+0] ; DWARF: DW_AT_location [DW_FORM_sec_offset] ( ; DWARF-NEXT: {{.*}} - {{.*}}: DW_OP_breg7 RSP+8) diff --git a/test/DebugInfo/X86/dbg-value-regmask-clobber.ll b/test/DebugInfo/X86/dbg-value-regmask-clobber.ll index 043d82df28f..53fdeecd146 100644 --- a/test/DebugInfo/X86/dbg-value-regmask-clobber.ll +++ b/test/DebugInfo/X86/dbg-value-regmask-clobber.ll @@ -5,11 +5,11 @@ ; of individual register def operands. ; ASM: main: # @main -; ASM: #DEBUG_VALUE: main:argc <- %ECX +; ASM: #DEBUG_VALUE: main:argc <- %ecx ; ASM: movl $1, x(%rip) ; ASM: callq clobber ; ASM-NEXT: [[argc_range_end:.Ltmp[0-9]+]]: -; Previously LiveDebugValues would claim argc was still in ECX after the call. +; Previously LiveDebugValues would claim argc was still in ecx after the call. ; ASM-NOT: #DEBUG_VALUE: main:argc ; argc is the first debug location. diff --git a/test/DebugInfo/X86/dbg-value-transfer-order.ll b/test/DebugInfo/X86/dbg-value-transfer-order.ll index 68ca4058283..6c55da986ff 100644 --- a/test/DebugInfo/X86/dbg-value-transfer-order.ll +++ b/test/DebugInfo/X86/dbg-value-transfer-order.ll @@ -33,7 +33,7 @@ ; CHECK: movl %eax, %ecx ; CHECK: .LBB0_3: # %if.end ; Check that this DEBUG_VALUE comes before the left shift. -; CHECK: #DEBUG_VALUE: bit_offset <- %ECX +; CHECK: #DEBUG_VALUE: bit_offset <- %ecx ; CHECK: .cv_loc 0 1 8 28 # t.c:8:28 ; CHECK: movl $1, %[[reg:[^ ]*]] ; CHECK: shll %cl, %[[reg]] diff --git a/test/DebugInfo/X86/debug-loc-asan.ll b/test/DebugInfo/X86/debug-loc-asan.ll index f6d1939d6fb..c95681af54a 100644 --- a/test/DebugInfo/X86/debug-loc-asan.ll +++ b/test/DebugInfo/X86/debug-loc-asan.ll @@ -12,9 +12,9 @@ ; with "clang++ -S -emit-llvm -mllvm -asan-skip-promotable-allocas=0 -fsanitize=address -O0 -g test.cc" ; The address of the (potentially now malloc'ed) alloca ends up -; in RDI, after which it is spilled to the stack. We record the +; in rdi, after which it is spilled to the stack. We record the ; spill OFFSET on the stack for checking the debug info below. -; CHECK: #DEBUG_VALUE: bar:y <- [DW_OP_deref] [%RDI+0] +; CHECK: #DEBUG_VALUE: bar:y <- [DW_OP_deref] [%rdi+0] ; CHECK: movq %rdi, [[OFFSET:[0-9]+]](%rsp) ; CHECK-NEXT: [[START_LABEL:.Ltmp[0-9]+]] ; CHECK-NEXT: #DEBUG_VALUE: bar:y <- [DW_OP_plus_uconst [[OFFSET]], DW_OP_deref, DW_OP_deref] diff --git a/test/DebugInfo/X86/live-debug-values.ll b/test/DebugInfo/X86/live-debug-values.ll index 1e5b01151a4..206b2d62f27 100644 --- a/test/DebugInfo/X86/live-debug-values.ll +++ b/test/DebugInfo/X86/live-debug-values.ll @@ -30,7 +30,7 @@ ; DBG_VALUE for variable "n" is extended into BB#5 from its predecessors BB#3 ; and BB#4. ; CHECK: .LBB0_5: -; CHECK-NEXT: #DEBUG_VALUE: main:n <- %EBX +; CHECK-NEXT: #DEBUG_VALUE: main:n <- %ebx ; Other register values have been clobbered. ; CHECK-NOT: #DEBUG_VALUE: ; CHECK: movl %ecx, m(%rip) diff --git a/test/DebugInfo/X86/live-debug-vars-dse.mir b/test/DebugInfo/X86/live-debug-vars-dse.mir index 18f706982d4..b4a79c87e82 100644 --- a/test/DebugInfo/X86/live-debug-vars-dse.mir +++ b/test/DebugInfo/X86/live-debug-vars-dse.mir @@ -13,12 +13,12 @@ # CHECK-LABEL: f: # @f # CHECK: movl %ecx, [[OFF_X:[0-9]+]](%rsp) -# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] +# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%rsp+0] # CHECK: leaq [[OFF_X]](%rsp), %rsi # CHECK: callq escape # CHECK: #DEBUG_VALUE: f:x <- 1 # CHECK: movl $1, global(%rip) -# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] +# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%rsp+0] # CHECK: movl $2, [[OFF_X]](%rsp) # CHECK: callq escape # CHECK: retq diff --git a/test/DebugInfo/X86/op_deref.ll b/test/DebugInfo/X86/op_deref.ll index 80894c18a8a..c2a42f49603 100644 --- a/test/DebugInfo/X86/op_deref.ll +++ b/test/DebugInfo/X86/op_deref.ll @@ -17,7 +17,7 @@ ; Check the DEBUG_VALUE comments for good measure. ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK ; vla should have a register-indirect address at one point. -; ASM-CHECK: DEBUG_VALUE: vla <- [DW_OP_deref] [%RCX+0] +; ASM-CHECK: DEBUG_VALUE: vla <- [DW_OP_deref] [%rcx+0] ; ASM-CHECK: DW_OP_breg2 ; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s --check-prefix=PRETTY-PRINT diff --git a/test/DebugInfo/X86/pieces-4.ll b/test/DebugInfo/X86/pieces-4.ll index 495449c90e2..1840e667570 100644 --- a/test/DebugInfo/X86/pieces-4.ll +++ b/test/DebugInfo/X86/pieces-4.ll @@ -17,7 +17,7 @@ ; CHECK: callq g ; CHECK: movl %eax, [[offs:[0-9]+]](%rsp) # 4-byte Spill ; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 32 32] 0 -; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offs]], DW_OP_LLVM_fragment 0 32] [%RSP+0] +; CHECK: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offs]], DW_OP_LLVM_fragment 0 32] [%rsp+0] ; CHECK: #APP ; CHECK: #NO_APP ; CHECK: movl [[offs]](%rsp), %eax # 4-byte Reload diff --git a/test/DebugInfo/X86/sdag-split-arg.ll b/test/DebugInfo/X86/sdag-split-arg.ll index 8807cffe27a..790b48236c2 100644 --- a/test/DebugInfo/X86/sdag-split-arg.ll +++ b/test/DebugInfo/X86/sdag-split-arg.ll @@ -1,10 +1,10 @@ ; RUN: llc -O0 -filetype=asm %s -o - | FileCheck %s ; Test large integral function arguments passed in multiple registers. -; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 64 16] %AX -; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 48 16] %R9W -; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 32 16] %R10W -; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 16 16] %R11W -; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 0 16] %BX +; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 64 16] %ax +; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 48 16] %r9w +; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 32 16] %r10w +; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 16 16] %r11w +; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 0 16] %bx target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-unknown" diff --git a/test/DebugInfo/X86/spill-indirect-nrvo.ll b/test/DebugInfo/X86/spill-indirect-nrvo.ll index ec2959701e4..939045c3478 100644 --- a/test/DebugInfo/X86/spill-indirect-nrvo.ll +++ b/test/DebugInfo/X86/spill-indirect-nrvo.ll @@ -21,9 +21,9 @@ ; } ; CHECK-LABEL: _Z10get_stringv: -; CHECK: #DEBUG_VALUE: get_string:result <- [%RDI+0] +; CHECK: #DEBUG_VALUE: get_string:result <- [%rdi+0] ; CHECK: movq %rdi, [[OFFS:[0-9]+]](%rsp) # 8-byte Spill -; CHECK: #DEBUG_VALUE: get_string:result <- [DW_OP_plus_uconst [[OFFS]], DW_OP_deref] [%RSP+0] +; CHECK: #DEBUG_VALUE: get_string:result <- [DW_OP_plus_uconst [[OFFS]], DW_OP_deref] [%rsp+0] ; CHECK: callq _ZN6stringC1Ei ; CHECK: #APP ; CHECK: #NO_APP diff --git a/test/DebugInfo/X86/spill-nontrivial-param.ll b/test/DebugInfo/X86/spill-nontrivial-param.ll index 9ac82374a0e..223da4fb906 100644 --- a/test/DebugInfo/X86/spill-nontrivial-param.ll +++ b/test/DebugInfo/X86/spill-nontrivial-param.ll @@ -20,9 +20,9 @@ ; } ; CHECK-LABEL: _Z3foo10NonTrivial: -; CHECK: #DEBUG_VALUE: foo:nt <- [%RDI+0] +; CHECK: #DEBUG_VALUE: foo:nt <- [%rdi+0] ; CHECK: movq %rdi, -8(%rsp) # 8-byte Spill -; CHECK: #DEBUG_VALUE: foo:nt <- [DW_OP_constu 8, DW_OP_minus, DW_OP_deref] [%RSP+0] +; CHECK: #DEBUG_VALUE: foo:nt <- [DW_OP_constu 8, DW_OP_minus, DW_OP_deref] [%rsp+0] ; CHECK: #APP ; CHECK: #NO_APP ; CHECK: movq -8(%rsp), %rax # 8-byte Reload diff --git a/test/DebugInfo/X86/spill-nospill.ll b/test/DebugInfo/X86/spill-nospill.ll index f5d6d372037..84ba8b6b8e2 100644 --- a/test/DebugInfo/X86/spill-nospill.ll +++ b/test/DebugInfo/X86/spill-nospill.ll @@ -24,12 +24,12 @@ ; CHECK-LABEL: f: # @f ; CHECK: callq g ; CHECK: movl %eax, [[X_OFFS:[0-9]+]](%rsp) # 4-byte Spill -; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]]] [%RSP+0] +; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]]] [%rsp+0] ; CHECK: #APP ; CHECK: #NO_APP ; CHECK: callq g ; CHECK: movl %eax, %[[CSR:[^ ]*]] -; CHECK: #DEBUG_VALUE: f:y <- %ESI +; CHECK: #DEBUG_VALUE: f:y <- %esi ; CHECK: movl %[[CSR]], %ecx ; CHECK: callq g ; CHECK: movl %[[CSR]], %ecx @@ -37,7 +37,7 @@ ; CHECK: movl %[[CSR]], %ecx ; CHECK: callq g ; CHECK: movl [[X_OFFS]](%rsp), %eax # 4-byte Reload -; CHECK: #DEBUG_VALUE: f:x <- %EAX +; CHECK: #DEBUG_VALUE: f:x <- %eax ; CHECK: addl %[[CSR]], %eax ; DWARF: DW_TAG_variable diff --git a/test/DebugInfo/X86/vla.ll b/test/DebugInfo/X86/vla.ll index 17f1c48b6eb..b86b172a37a 100644 --- a/test/DebugInfo/X86/vla.ll +++ b/test/DebugInfo/X86/vla.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s ; Ensure that we generate an indirect location for the variable length array a. -; CHECK: ##DEBUG_VALUE: vla:a <- [DW_OP_deref] [%RCX+0] +; CHECK: ##DEBUG_VALUE: vla:a <- [DW_OP_deref] [%rcx+0] ; CHECK: DW_OP_breg2 ; rdar://problem/13658587 ; diff --git a/test/MC/COFF/cv-def-range.s b/test/MC/COFF/cv-def-range.s index 7a90ec26368..2b0d4b754d4 100644 --- a/test/MC/COFF/cv-def-range.s +++ b/test/MC/COFF/cv-def-range.s @@ -23,7 +23,7 @@ Lfunc_begin0: subl $8, %esp leal -4(%ebp), %eax Lvar_begin0: - #DEBUG_VALUE: g:x <- %EAX + #DEBUG_VALUE: g:x <- %eax .cv_loc 0 1 4 7 # <stdin>:4:7 movl $0, -4(%ebp) .cv_loc 0 1 5 3 # <stdin>:5:3 diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index aca0445f7ac..8d930f677f9 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -417,7 +417,7 @@ enter $0x7ace,$0x7f // rdar://8456364 // CHECK: movw %cs, %ax -mov %CS, %ax +mov %cs, %ax // rdar://8456391 fcmovb %st(1), %st(0) // CHECK: fcmovb %st(1), %st(0) @@ -583,8 +583,8 @@ movmskpd %xmm6, %eax fdivrp %st(0), %st(1) // CHECK: encoding: [0xde,0xf9] fdivrp %st(1), %st(0) // CHECK: encoding: [0xde,0xf9] -fsubrp %ST(0), %ST(1) // CHECK: encoding: [0xde,0xe9] -fsubrp %ST(1), %ST(0) // CHECK: encoding: [0xde,0xe9] +fsubrp %st(0), %st(1) // CHECK: encoding: [0xde,0xe9] +fsubrp %st(1), %st(0) // CHECK: encoding: [0xde,0xe9] // also PR8861 fdivp %st(0), %st(1) // CHECK: encoding: [0xde,0xf1] |