diff options
64 files changed, 420 insertions, 468 deletions
diff --git a/include/llvm/CodeGen/CommandFlags.h b/include/llvm/CodeGen/CommandFlags.h index 0d898827efc..f7ac27f8870 100644 --- a/include/llvm/CodeGen/CommandFlags.h +++ b/include/llvm/CodeGen/CommandFlags.h @@ -77,20 +77,20 @@ TMModel("thread-model", clEnumValN(ThreadModel::Single, "single", "Single thread model"))); -cl::opt<llvm::CodeModel::Model> -CMModel("code-model", - cl::desc("Choose code model"), - cl::init(CodeModel::Default), - cl::values(clEnumValN(CodeModel::Default, "default", - "Target default code model"), - clEnumValN(CodeModel::Small, "small", - "Small code model"), - clEnumValN(CodeModel::Kernel, "kernel", - "Kernel code model"), - clEnumValN(CodeModel::Medium, "medium", - "Medium code model"), - clEnumValN(CodeModel::Large, "large", - "Large code model"))); +cl::opt<llvm::CodeModel::Model> CMModel( + "code-model", cl::desc("Choose code model"), + cl::values(clEnumValN(CodeModel::Small, "small", "Small code model"), + clEnumValN(CodeModel::Kernel, "kernel", "Kernel code model"), + clEnumValN(CodeModel::Medium, "medium", "Medium code model"), + clEnumValN(CodeModel::Large, "large", "Large code model"))); + +static inline Optional<CodeModel::Model> getCodeModel() { + if (CMModel.getNumOccurrences()) { + CodeModel::Model M = CMModel; + return M; + } + return None; +} cl::opt<llvm::ExceptionHandling> ExceptionModel("exception-model", diff --git a/include/llvm/ExecutionEngine/ExecutionEngine.h b/include/llvm/ExecutionEngine/ExecutionEngine.h index 2830a262875..70ee843095f 100644 --- a/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -535,7 +535,7 @@ private: std::shared_ptr<JITSymbolResolver> Resolver; TargetOptions Options; Optional<Reloc::Model> RelocModel; - CodeModel::Model CMModel; + Optional<CodeModel::Model> CMModel; std::string MArch; std::string MCPU; SmallVector<std::string, 4> MAttrs; diff --git a/include/llvm/LTO/Config.h b/include/llvm/LTO/Config.h index 8e9d0c76e7c..60a5fa6eb36 100644 --- a/include/llvm/LTO/Config.h +++ b/include/llvm/LTO/Config.h @@ -40,7 +40,7 @@ struct Config { TargetOptions Options; std::vector<std::string> MAttrs; Optional<Reloc::Model> RelocModel = Reloc::PIC_; - CodeModel::Model CodeModel = CodeModel::Default; + Optional<CodeModel::Model> CodeModel = None; CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default; TargetMachine::CodeGenFileType CGFileType = TargetMachine::CGFT_ObjectFile; unsigned OptLevel = 2; diff --git a/include/llvm/Support/CodeGen.h b/include/llvm/Support/CodeGen.h index 941c112b0dd..5f9e3312958 100644 --- a/include/llvm/Support/CodeGen.h +++ b/include/llvm/Support/CodeGen.h @@ -25,7 +25,7 @@ namespace llvm { // Code model types. namespace CodeModel { // Sync changes with CodeGenCWrappers.h. - enum Model { Default, JITDefault, Small, Kernel, Medium, Large }; + enum Model { Small, Kernel, Medium, Large }; } namespace PICLevel { diff --git a/include/llvm/Support/CodeGenCWrappers.h b/include/llvm/Support/CodeGenCWrappers.h index 6db4433a435..d7414107478 100644 --- a/include/llvm/Support/CodeGenCWrappers.h +++ b/include/llvm/Support/CodeGenCWrappers.h @@ -22,12 +22,13 @@ namespace llvm { -inline CodeModel::Model unwrap(LLVMCodeModel Model) { +inline Optional<CodeModel::Model> unwrap(LLVMCodeModel Model, bool &JIT) { + JIT = false; switch (Model) { - case LLVMCodeModelDefault: - return CodeModel::Default; case LLVMCodeModelJITDefault: - return CodeModel::JITDefault; + JIT = true; + case LLVMCodeModelDefault: + return None; case LLVMCodeModelSmall: return CodeModel::Small; case LLVMCodeModelKernel: @@ -37,15 +38,11 @@ inline CodeModel::Model unwrap(LLVMCodeModel Model) { case LLVMCodeModelLarge: return CodeModel::Large; } - return CodeModel::Default; + return CodeModel::Small; } inline LLVMCodeModel wrap(CodeModel::Model Model) { switch (Model) { - case CodeModel::Default: - return LLVMCodeModelDefault; - case CodeModel::JITDefault: - return LLVMCodeModelJITDefault; case CodeModel::Small: return LLVMCodeModelSmall; case CodeModel::Kernel: diff --git a/include/llvm/Support/TargetRegistry.h b/include/llvm/Support/TargetRegistry.h index 90d6c084ee9..9106e0856b1 100644 --- a/include/llvm/Support/TargetRegistry.h +++ b/include/llvm/Support/TargetRegistry.h @@ -101,19 +101,16 @@ public: using MCAsmInfoCtorFnTy = MCAsmInfo *(*)(const MCRegisterInfo &MRI, const Triple &TT); - using MCAdjustCodeGenOptsFnTy = void (*)(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM); - using MCInstrInfoCtorFnTy = MCInstrInfo *(*)(); using MCInstrAnalysisCtorFnTy = MCInstrAnalysis *(*)(const MCInstrInfo *Info); using MCRegInfoCtorFnTy = MCRegisterInfo *(*)(const Triple &TT); using MCSubtargetInfoCtorFnTy = MCSubtargetInfo *(*)(const Triple &TT, StringRef CPU, StringRef Features); - using TargetMachineCtorTy = TargetMachine *(*)( - const Target &T, const Triple &TT, StringRef CPU, StringRef Features, - const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL); + using TargetMachineCtorTy = TargetMachine + *(*)(const Target &T, const Triple &TT, StringRef CPU, StringRef Features, + const TargetOptions &Options, Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT); // If it weren't for layering issues (this header is in llvm/Support, but // depends on MC?) this should take the Streamer by value rather than rvalue // reference. @@ -191,8 +188,6 @@ private: /// registered. MCAsmInfoCtorFnTy MCAsmInfoCtorFn; - MCAdjustCodeGenOptsFnTy MCAdjustCodeGenOptsFn; - /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// if registered. MCInstrInfoCtorFnTy MCInstrInfoCtorFn; @@ -312,12 +307,6 @@ public: return MCAsmInfoCtorFn(MRI, Triple(TheTriple)); } - void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) const { - if (MCAdjustCodeGenOptsFn) - MCAdjustCodeGenOptsFn(TT, RM, CM); - } - /// createMCInstrInfo - Create a MCInstrInfo implementation. /// MCInstrInfo *createMCInstrInfo() const { @@ -365,15 +354,17 @@ public: /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - TargetMachine * - createTargetMachine(StringRef TT, StringRef CPU, StringRef Features, - const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM = CodeModel::Default, - CodeGenOpt::Level OL = CodeGenOpt::Default) const { + TargetMachine *createTargetMachine(StringRef TT, StringRef CPU, + StringRef Features, + const TargetOptions &Options, + Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM = None, + CodeGenOpt::Level OL = CodeGenOpt::Default, + bool JIT = false) const { if (!TargetMachineCtorFn) return nullptr; return TargetMachineCtorFn(*this, Triple(TT), CPU, Features, Options, RM, - CM, OL); + CM, OL, JIT); } /// createMCAsmBackend - Create a target specific assembly parser. @@ -663,11 +654,6 @@ struct TargetRegistry { T.MCAsmInfoCtorFn = Fn; } - static void registerMCAdjustCodeGenOpts(Target &T, - Target::MCAdjustCodeGenOptsFnTy Fn) { - T.MCAdjustCodeGenOptsFn = Fn; - } - /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the /// given target. /// @@ -929,12 +915,6 @@ struct RegisterMCAsmInfoFn { } }; -struct RegisterMCAdjustCodeGenOptsFn { - RegisterMCAdjustCodeGenOptsFn(Target &T, Target::MCAdjustCodeGenOptsFnTy Fn) { - TargetRegistry::registerMCAdjustCodeGenOpts(T, Fn); - } -}; - /// RegisterMCInstrInfo - Helper template for registering a target instruction /// info implementation. This invokes the static "Create" method on the class /// to actually do the construction. Usage: @@ -1080,12 +1060,11 @@ template <class TargetMachineImpl> struct RegisterTargetMachine { } private: - static TargetMachine *Allocator(const Target &T, const Triple &TT, - StringRef CPU, StringRef FS, - const TargetOptions &Options, - Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) { - return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL); + static TargetMachine * + Allocator(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, + const TargetOptions &Options, Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) { + return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL, JIT); } }; diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index a44ac31ff69..14c7a635a7c 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -78,7 +78,7 @@ protected: // Can only create subclasses. std::string TargetFS; Reloc::Model RM = Reloc::Static; - CodeModel::Model CMModel = CodeModel::Default; + CodeModel::Model CMModel = CodeModel::Small; CodeGenOpt::Level OptLevel = CodeGenOpt::Default; /// Contains target specific asm information. diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index ad105429bfe..753db852263 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -77,7 +77,6 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { - T.adjustCodeGenOpts(TT, RM, CM); this->RM = RM; this->CMModel = CM; this->OptLevel = OL; diff --git a/lib/ExecutionEngine/ExecutionEngine.cpp b/lib/ExecutionEngine/ExecutionEngine.cpp index 2ee72f9a8c1..c59885753a8 100644 --- a/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/lib/ExecutionEngine/ExecutionEngine.cpp @@ -476,7 +476,7 @@ EngineBuilder::EngineBuilder() : EngineBuilder(nullptr) {} EngineBuilder::EngineBuilder(std::unique_ptr<Module> M) : M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr), OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr), - CMModel(CodeModel::JITDefault), UseOrcMCJITReplacement(false) { + UseOrcMCJITReplacement(false) { // IR module verification is enabled by default in debug builds, and disabled // by default in release builds. #ifndef NDEBUG diff --git a/lib/ExecutionEngine/ExecutionEngineBindings.cpp b/lib/ExecutionEngine/ExecutionEngineBindings.cpp index e956dbebaff..20251c23b17 100644 --- a/lib/ExecutionEngine/ExecutionEngineBindings.cpp +++ b/lib/ExecutionEngine/ExecutionEngineBindings.cpp @@ -198,8 +198,10 @@ LLVMBool LLVMCreateMCJITCompilerForModule( builder.setEngineKind(EngineKind::JIT) .setErrorStr(&Error) .setOptLevel((CodeGenOpt::Level)options.OptLevel) - .setCodeModel(unwrap(options.CodeModel)) .setTargetOptions(targetOptions); + bool JIT; + if (Optional<CodeModel::Model> CM = unwrap(options.CodeModel, JIT)) + builder.setCodeModel(*CM); if (options.MCJMM) builder.setMCJITMemoryManager( std::unique_ptr<RTDyldMemoryManager>(unwrap(options.MCJMM))); diff --git a/lib/ExecutionEngine/TargetSelect.cpp b/lib/ExecutionEngine/TargetSelect.cpp index 6e2973c04e5..5df5e1eabec 100644 --- a/lib/ExecutionEngine/TargetSelect.cpp +++ b/lib/ExecutionEngine/TargetSelect.cpp @@ -92,11 +92,10 @@ TargetMachine *EngineBuilder::selectTarget(const Triple &TargetTriple, } // Allocate a target... - TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(), - MCPU, FeaturesStr, - Options, - RelocModel, CMModel, - OptLevel); + TargetMachine *Target = + TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr, + Options, RelocModel, CMModel, OptLevel, + /*JIT*/ true); assert(Target && "Could not allocate target machine!"); return Target; } diff --git a/lib/LTO/LTO.cpp b/lib/LTO/LTO.cpp index 958151ad91b..e28b3744d20 100644 --- a/lib/LTO/LTO.cpp +++ b/lib/LTO/LTO.cpp @@ -118,7 +118,10 @@ static void computeCacheKey( AddUnsigned(*Conf.RelocModel); else AddUnsigned(-1); - AddUnsigned(Conf.CodeModel); + if (Conf.CodeModel) + AddUnsigned(*Conf.CodeModel); + else + AddUnsigned(-1); AddUnsigned(Conf.CGOptLevel); AddUnsigned(Conf.CGFileType); AddUnsigned(Conf.OptLevel); diff --git a/lib/LTO/LTOCodeGenerator.cpp b/lib/LTO/LTOCodeGenerator.cpp index 6a275560dc9..8ad3cccf8d4 100644 --- a/lib/LTO/LTOCodeGenerator.cpp +++ b/lib/LTO/LTOCodeGenerator.cpp @@ -368,9 +368,8 @@ bool LTOCodeGenerator::determineTarget() { } std::unique_ptr<TargetMachine> LTOCodeGenerator::createTargetMachine() { - return std::unique_ptr<TargetMachine>( - MArch->createTargetMachine(TripleStr, MCpu, FeatureStr, Options, - RelocModel, CodeModel::Default, CGOptLevel)); + return std::unique_ptr<TargetMachine>(MArch->createTargetMachine( + TripleStr, MCpu, FeatureStr, Options, RelocModel, None, CGOptLevel)); } // If a linkonce global is present in the MustPreserveSymbols, we need to make diff --git a/lib/LTO/ThinLTOCodeGenerator.cpp b/lib/LTO/ThinLTOCodeGenerator.cpp index 1efd481b246..ffd78dad922 100644 --- a/lib/LTO/ThinLTOCodeGenerator.cpp +++ b/lib/LTO/ThinLTOCodeGenerator.cpp @@ -583,9 +583,9 @@ std::unique_ptr<TargetMachine> TargetMachineBuilder::create() const { Features.getDefaultSubtargetFeatures(TheTriple); std::string FeatureStr = Features.getString(); - return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine( - TheTriple.str(), MCpu, FeatureStr, Options, RelocModel, - CodeModel::Default, CGOptLevel)); + return std::unique_ptr<TargetMachine>( + TheTarget->createTargetMachine(TheTriple.str(), MCpu, FeatureStr, Options, + RelocModel, None, CGOptLevel)); } /** diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index 9837685de0a..14263d47b1a 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -206,18 +206,42 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, return *RM; } +static CodeModel::Model getEffectiveCodeModel(const Triple &TT, + Optional<CodeModel::Model> CM, + bool JIT) { + if (CM) { + if (*CM != CodeModel::Small && *CM != CodeModel::Large) { + if (!TT.isOSFuchsia()) + report_fatal_error( + "Only small and large code models are allowed on AArch64"); + else if (CM != CodeModel::Kernel) + report_fatal_error( + "Only small, kernel, and large code models are allowed on AArch64"); + } + return *CM; + } + // The default MCJIT memory managers make no guarantees about where they can + // find an executable page; JITed code needs to be able to refer to globals + // no matter how far away they are. + if (JIT) + return CodeModel::Large; + return CodeModel::Small; +} + /// Create an AArch64 architecture model. /// -AArch64TargetMachine::AArch64TargetMachine( - const Target &T, const Triple &TT, StringRef CPU, StringRef FS, - const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian) - : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions, - LittleEndian), - TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), CM, OL), - TLOF(createTLOF(getTargetTriple())), - isLittle(LittleEndian) { +AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, + bool LittleEndian) + : LLVMTargetMachine(T, + computeDataLayout(TT, Options.MCOptions, LittleEndian), + TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(TT, CM, JIT), OL), + TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) { initAsmInfo(); } @@ -252,16 +276,16 @@ void AArch64leTargetMachine::anchor() { } AArch64leTargetMachine::AArch64leTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} void AArch64beTargetMachine::anchor() { } AArch64beTargetMachine::AArch64beTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) + : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} namespace { diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index a2a0a7a82fc..2bbfb2da3db 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -31,8 +31,8 @@ protected: public: AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool IsLittleEndian); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian); ~AArch64TargetMachine() override; const AArch64Subtarget *getSubtargetImpl(const Function &F) const override; @@ -62,8 +62,9 @@ class AArch64leTargetMachine : public AArch64TargetMachine { public: AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, + bool JIT); }; // AArch64 big endian target machine. @@ -73,8 +74,9 @@ class AArch64beTargetMachine : public AArch64TargetMachine { public: AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, + bool JIT); }; } // end namespace llvm diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp index d3c7dc60c4d..3141f259ac2 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -84,28 +84,6 @@ static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - assert((TT.isOSBinFormatELF() || TT.isOSBinFormatMachO() || - TT.isOSBinFormatCOFF()) && "Invalid target"); - - if (CM == CodeModel::Default) - CM = CodeModel::Small; - // The default MCJIT memory managers make no guarantees about where they can - // find an executable page; JITed code needs to be able to refer to globals - // no matter how far away they are. - else if (CM == CodeModel::JITDefault) - CM = CodeModel::Large; - else if (CM != CodeModel::Small && CM != CodeModel::Large) { - if (!TT.isOSFuchsia()) - report_fatal_error( - "Only small and large code models are allowed on AArch64"); - else if (CM != CodeModel::Kernel) - report_fatal_error( - "Only small, kernel, and large code models are allowed on AArch64"); - } -} - static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -153,9 +131,6 @@ extern "C" void LLVMInitializeAArch64TargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); - // Register the MC codegen info. - TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo); diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index de3f405b24f..e3f8dc15bd2 100644 --- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -266,15 +266,22 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return Reloc::PIC_; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OptLevel) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), - FS, Options, getEffectiveRelocModel(RM), CM, OptLevel), - TLOF(createTLOF(getTargetTriple())) { + : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU), + FS, Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), OptLevel), + TLOF(createTLOF(getTargetTriple())) { AS = AMDGPU::getAMDGPUAS(TT); initAsmInfo(); } @@ -378,8 +385,9 @@ R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { setRequiresStructuredCFG(true); } @@ -411,8 +419,9 @@ GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} const SISubtarget *GCNTargetMachine::getSubtargetImpl(const Function &F) const { StringRef GPU = getGPUName(F); diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/lib/Target/AMDGPU/AMDGPUTargetMachine.h index f388d8d5ba6..0b1fd5e9cfa 100644 --- a/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -43,7 +43,7 @@ protected: public: AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL); ~AMDGPUTargetMachine() override; @@ -85,8 +85,8 @@ private: public: R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; @@ -108,8 +108,8 @@ private: public: GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/lib/Target/ARM/ARMFrameLowering.cpp b/lib/Target/ARM/ARMFrameLowering.cpp index 12e6e329a92..f5a745f1d43 100644 --- a/lib/Target/ARM/ARMFrameLowering.cpp +++ b/lib/Target/ARM/ARMFrameLowering.cpp @@ -512,7 +512,6 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF, switch (TM.getCodeModel()) { case CodeModel::Small: case CodeModel::Medium: - case CodeModel::Default: case CodeModel::Kernel: BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) .add(predOps(ARMCC::AL)) @@ -521,7 +520,6 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF, .setMIFlags(MachineInstr::FrameSetup); break; case CodeModel::Large: - case CodeModel::JITDefault: BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) .addExternalSymbol("__chkstk") .setMIFlags(MachineInstr::FrameSetup); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 73ba1671df4..9746490988e 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -8783,7 +8783,6 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, switch (TM.getCodeModel()) { case CodeModel::Small: case CodeModel::Medium: - case CodeModel::Default: case CodeModel::Kernel: BuildMI(*MBB, MI, DL, TII.get(ARM::tBL)) .add(predOps(ARMCC::AL)) @@ -8793,8 +8792,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead); break; - case CodeModel::Large: - case CodeModel::JITDefault: { + case CodeModel::Large: { MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass); diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index c323a1d368d..eaab7331e34 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -190,17 +190,23 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + /// Create an ARM architecture model. /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM, - OL), + CPU, FS, Options, getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM), OL), TargetABI(computeTargetABI(TT, CPU, Options)), TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { @@ -276,21 +282,20 @@ TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() { }); } - ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} namespace { diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index bc4c751b255..9311073333a 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -42,7 +42,7 @@ protected: public: ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool isLittle); ~ARMBaseTargetMachine() override; @@ -74,8 +74,8 @@ class ARMLETargetMachine : public ARMBaseTargetMachine { public: ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; /// ARM/Thumb big endian target machine. @@ -84,8 +84,8 @@ class ARMBETargetMachine : public ARMBaseTargetMachine { public: ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm diff --git a/lib/Target/BPF/BPFTargetMachine.cpp b/lib/Target/BPF/BPFTargetMachine.cpp index d84b0a80fc0..60672fa2684 100644 --- a/lib/Target/BPF/BPFTargetMachine.cpp +++ b/lib/Target/BPF/BPFTargetMachine.cpp @@ -43,13 +43,21 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), CM, OL), + getEffectiveRelocModel(RM), getEffectiveCodeModel(CM), + OL), TLOF(make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/lib/Target/BPF/BPFTargetMachine.h b/lib/Target/BPF/BPFTargetMachine.h index 64448144688..a560dd27335 100644 --- a/lib/Target/BPF/BPFTargetMachine.h +++ b/lib/Target/BPF/BPFTargetMachine.h @@ -25,8 +25,8 @@ class BPFTargetMachine : public LLVMTargetMachine { public: BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; } const BPFSubtarget *getSubtargetImpl(const Function &) const override { diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 7d88b51f32d..543318c7a14 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -152,6 +152,12 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + extern "C" void LLVMInitializeHexagonTarget() { // Register the target. RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget()); @@ -168,17 +174,18 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) // Specify the vector alignment explicitly. For v512x1, the calculated // alignment would be 512*alignment(i1), which is 512 bytes, instead of // the required minimum of 64 bytes. : LLVMTargetMachine( - T, "e-m:e-p:32:32:32-a:0-n16:32-" - "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" - "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", - TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, - (HexagonNoOpt ? CodeGenOpt::None : OL)), + T, + "e-m:e-p:32:32:32-a:0-n16:32-" + "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" + "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048", + TT, CPU, FS, Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)), TLOF(make_unique<HexagonTargetObjectFile>()) { initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); initAsmInfo(); diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index 3d01929fbfb..acd41f920b5 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -30,8 +30,8 @@ class HexagonTargetMachine : public LLVMTargetMachine { public: HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~HexagonTargetMachine() override; const HexagonSubtarget *getSubtargetImpl(const Function &F) const override; diff --git a/lib/Target/Lanai/LanaiTargetMachine.cpp b/lib/Target/Lanai/LanaiTargetMachine.cpp index a2f005ce445..9a73c95d651 100644 --- a/lib/Target/Lanai/LanaiTargetMachine.cpp +++ b/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -53,15 +53,23 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Medium; +} + LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, StringRef Cpu, StringRef FeatureString, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CodeModel, - CodeGenOpt::Level OptLevel) + Optional<CodeModel::Model> CodeModel, + CodeGenOpt::Level OptLevel, bool JIT) : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, - getEffectiveRelocModel(RM), CodeModel, OptLevel), - Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CodeModel), OptLevel), + Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(), + OptLevel), TLOF(new LanaiTargetObjectFile()) { initAsmInfo(); } diff --git a/lib/Target/Lanai/LanaiTargetMachine.h b/lib/Target/Lanai/LanaiTargetMachine.h index 083ba6fdf84..ce1271d9dea 100644 --- a/lib/Target/Lanai/LanaiTargetMachine.h +++ b/lib/Target/Lanai/LanaiTargetMachine.h @@ -34,7 +34,8 @@ public: StringRef Cpu, StringRef FeatureString, const TargetOptions &Options, Optional<Reloc::Model> RelocationModel, - CodeModel::Model CodeModel, CodeGenOpt::Level OptLevel); + Optional<CodeModel::Model> CodeModel, + CodeGenOpt::Level OptLevel, bool JIT); const LanaiSubtarget * getSubtargetImpl(const llvm::Function & /*Fn*/) const override { diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp index 982c6fea62d..01f44e266d7 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -32,6 +32,12 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options) { return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"; @@ -41,10 +47,11 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, - Options, getEffectiveRelocModel(RM), CM, OL), + Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), OL), TLOF(make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index de8f06e71de..97b5e810a1d 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -30,8 +30,8 @@ class MSP430TargetMachine : public LLVMTargetMachine { public: MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~MSP430TargetMachine() override; const MSP430Subtarget *getSubtargetImpl(const Function &F) const override { diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 330ae19ecd0..4ed06471dd9 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -84,13 +84,19 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, return Ret; } -static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM, +static Reloc::Model getEffectiveRelocModel(bool JIT, Optional<Reloc::Model> RM) { - if (!RM.hasValue() || CM == CodeModel::JITDefault) + if (!RM.hasValue() || JIT) return Reloc::Static; return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + // On function prologue, the stack is created by decrementing // its pointer. Once decremented, all references are done with positive // offset from the stack/frame pointer, using StackGrowsUp enables @@ -100,11 +106,12 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL, + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, bool isLittle) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM, - OL), + CPU, FS, Options, getEffectiveRelocModel(JIT, RM), + getEffectiveCodeModel(CM), OL), isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()), ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), @@ -124,9 +131,9 @@ MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} void MipselTargetMachine::anchor() {} @@ -134,9 +141,9 @@ MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} const MipsSubtarget * MipsTargetMachine::getSubtargetImpl(const Function &F) const { diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index a3462868cb1..ccfc9a938d9 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -40,8 +40,8 @@ class MipsTargetMachine : public LLVMTargetMachine { public: MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool isLittle); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, bool isLittle); ~MipsTargetMachine() override; TargetIRAnalysis getTargetIRAnalysis() override; @@ -80,8 +80,8 @@ class MipsebTargetMachine : public MipsTargetMachine { public: MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; /// Mips32/64 little endian target machine. @@ -92,8 +92,8 @@ class MipselTargetMachine : public MipsTargetMachine { public: MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/lib/Target/NVPTX/NVPTXTargetMachine.cpp index ac21563ee9a..85f757878f9 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -86,18 +86,23 @@ static std::string computeDataLayout(bool is64Bit) { return Ret; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool is64bit) // The pic relocation model is used regardless of what the client has // specified, as it is the only relocation model currently supported. : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, - Reloc::PIC_, CM, OL), - is64bit(is64bit), - TLOF(llvm::make_unique<NVPTXTargetObjectFile>()), + Reloc::PIC_, getEffectiveCodeModel(CM), OL), + is64bit(is64bit), TLOF(llvm::make_unique<NVPTXTargetObjectFile>()), Subtarget(TT, CPU, FS, *this) { if (TT.getOS() == Triple::NVCL) drvInterface = NVPTX::NVCL; @@ -114,8 +119,8 @@ NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} void NVPTXTargetMachine64::anchor() {} @@ -124,8 +129,8 @@ NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} namespace { diff --git a/lib/Target/NVPTX/NVPTXTargetMachine.h b/lib/Target/NVPTX/NVPTXTargetMachine.h index 2f3981be22f..7674135f0a7 100644 --- a/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -36,7 +36,7 @@ class NVPTXTargetMachine : public LLVMTargetMachine { public: NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OP, bool is64bit); ~NVPTXTargetMachine() override; @@ -75,8 +75,8 @@ class NVPTXTargetMachine32 : public NVPTXTargetMachine { public: NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; class NVPTXTargetMachine64 : public NVPTXTargetMachine { @@ -84,8 +84,8 @@ class NVPTXTargetMachine64 : public NVPTXTargetMachine { public: NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index e8f220ea545..7044835cb8a 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -94,15 +94,6 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - if (CM == CodeModel::Default) { - if (!TT.isOSDarwin() && - (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)) - CM = CodeModel::Medium; - } -} - namespace { class PPCTargetAsmStreamer : public PPCTargetStreamer { @@ -257,9 +248,6 @@ extern "C" void LLVMInitializePowerPCTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); - // Register the MC codegen info. - TargetRegistry::registerMCAdjustCodeGenOpts(*T, adjustCodeGenOpts); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createPPCMCInstrInfo); diff --git a/lib/Target/PowerPC/PPCFastISel.cpp b/lib/Target/PowerPC/PPCFastISel.cpp index bc9957194f6..f42f15ad223 100644 --- a/lib/Target/PowerPC/PPCFastISel.cpp +++ b/lib/Target/PowerPC/PPCFastISel.cpp @@ -1930,7 +1930,7 @@ unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { PPCFuncInfo->setUsesTOCBasePtr(); // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)). - if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) { + if (CModel == CodeModel::Small) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT), TmpReg) .addConstantPoolIndex(Idx).addReg(PPC::X2); @@ -1981,7 +1981,7 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { PPCFuncInfo->setUsesTOCBasePtr(); // For small code model, generate a simple TOC load. - if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) + if (CModel == CodeModel::Small) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc), DestReg) .addGlobalAddress(GV) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index ff88b388fb9..2c0936b1c64 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2476,7 +2476,6 @@ SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table, return TargetLowering::getPICJumpTableRelocBase(Table, DAG); switch (getTargetMachine().getCodeModel()) { - case CodeModel::Default: case CodeModel::Small: case CodeModel::Medium: return TargetLowering::getPICJumpTableRelocBase(Table, DAG); @@ -2494,7 +2493,6 @@ PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); switch (getTargetMachine().getCodeModel()) { - case CodeModel::Default: case CodeModel::Small: case CodeModel::Medium: return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index fe092cc3b85..c3744092afb 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -208,6 +208,16 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, return Reloc::Static; } +static CodeModel::Model getEffectiveCodeModel(const Triple &TT, + Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + if (!TT.isOSDarwin() && + (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)) + return CodeModel::Medium; + return CodeModel::Small; +} + // The FeatureString here is a little subtle. We are modifying the feature // string with what are (currently) non-function specific overrides as it goes // into the LLVMTargetMachine constructor and then using the stored value in the @@ -216,10 +226,12 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU, computeFSAdditions(FS, OL, TT), Options, - getEffectiveRelocModel(TT, RM), CM, OL), + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(TT, CM), OL), TLOF(createTLOF(getTargetTriple())), TargetABI(computeTargetABI(TT, Options)) { initAsmInfo(); diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 81b5ef21b7e..102bf7ca59c 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -35,8 +35,8 @@ private: public: PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~PPCTargetMachine() override; diff --git a/lib/Target/RISCV/RISCVTargetMachine.cpp b/lib/Target/RISCV/RISCVTargetMachine.cpp index 744d7b8aaa3..78d9cf53b5d 100644 --- a/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -43,14 +43,21 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), CM, OL), + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM), OL), TLOF(make_unique<TargetLoweringObjectFileELF>()) { initAsmInfo(); } diff --git a/lib/Target/RISCV/RISCVTargetMachine.h b/lib/Target/RISCV/RISCVTargetMachine.h index d13e574c9bf..5c2ec956ee2 100644 --- a/lib/Target/RISCV/RISCVTargetMachine.h +++ b/lib/Target/RISCV/RISCVTargetMachine.h @@ -26,8 +26,8 @@ class RISCVTargetMachine : public LLVMTargetMachine { public: RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 889e2fd19ba..bd6596faee5 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -69,43 +69,6 @@ createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createSparcMCSubtargetInfoImpl(TT, CPU, FS); } -// Code models. Some only make sense for 64-bit code. -// -// SunCC Reloc CodeModel Constraints -// abs32 Static Small text+data+bss linked below 2^32 bytes -// abs44 Static Medium text+data+bss linked below 2^44 bytes -// abs64 Static Large text smaller than 2^31 bytes -// pic13 PIC_ Small GOT < 2^13 bytes -// pic32 PIC_ Medium GOT < 2^32 bytes -// -// All code models require that the text segment is smaller than 2GB. - -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - // The default 32-bit code model is abs32/pic32 and the default 32-bit - // code model for JIT is abs32. - switch (CM) { - default: break; - case CodeModel::Default: - case CodeModel::JITDefault: CM = CodeModel::Small; break; - } -} - -static void adjustCodeGenOptsV9(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - // The default 64-bit code model is abs44/pic32 and the default 64-bit - // code model for JIT is abs64. - switch (CM) { - default: break; - case CodeModel::Default: - CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; - break; - case CodeModel::JITDefault: - CM = CodeModel::Large; - break; - } -} - static MCTargetStreamer * createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { return new SparcTargetELFStreamer(S); @@ -159,12 +122,4 @@ extern "C" void LLVMInitializeSparcTargetMC() { // Register the MCInstPrinter TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); } - - // Register the MC codegen info. - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcTarget(), - adjustCodeGenOpts); - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcV9Target(), - adjustCodeGenOptsV9); - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSparcelTarget(), - adjustCodeGenOpts); } diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index a07bca1bd26..a0d40653fd9 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -60,15 +60,39 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +// Code models. Some only make sense for 64-bit code. +// +// SunCC Reloc CodeModel Constraints +// abs32 Static Small text+data+bss linked below 2^32 bytes +// abs44 Static Medium text+data+bss linked below 2^44 bytes +// abs64 Static Large text smaller than 2^31 bytes +// pic13 PIC_ Small GOT < 2^13 bytes +// pic32 PIC_ Medium GOT < 2^32 bytes +// +// All code models require that the text segment is smaller than 2GB. +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM, + Reloc::Model RM, bool Is64Bit, + bool JIT) { + if (CM) + return *CM; + if (Is64Bit) { + if (JIT) + return CodeModel::Large; + return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; + } + return CodeModel::Small; +} + /// Create an ILP32 architecture model -SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, - StringRef CPU, StringRef FS, - const TargetOptions &Options, - Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL, bool is64bit) - : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), CM, OL), +SparcTargetMachine::SparcTargetMachine( + const Target &T, const Triple &TT, StringRef CPU, StringRef FS, + const TargetOptions &Options, Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) + : LLVMTargetMachine( + T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), is64bit, JIT), + OL), TLOF(make_unique<SparcELFTargetObjectFile>()), Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { initAsmInfo(); @@ -164,9 +188,9 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} void SparcV9TargetMachine::anchor() { } @@ -174,9 +198,9 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} void SparcelTargetMachine::anchor() {} @@ -184,6 +208,6 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index faf714cbe2c..b0d76abeba7 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -28,8 +28,8 @@ class SparcTargetMachine : public LLVMTargetMachine { public: SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL, bool is64bit); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT, bool is64bit); ~SparcTargetMachine() override; const SparcSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -53,8 +53,8 @@ class SparcV8TargetMachine : public SparcTargetMachine { public: SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; /// Sparc 64-bit target machine @@ -64,8 +64,8 @@ class SparcV9TargetMachine : public SparcTargetMachine { public: SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; class SparcelTargetMachine : public SparcTargetMachine { @@ -74,8 +74,8 @@ class SparcelTargetMachine : public SparcTargetMachine { public: SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 727ab921daf..05688ed8efb 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -173,43 +173,6 @@ createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createSystemZMCSubtargetInfoImpl(TT, CPU, FS); } -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - // For SystemZ we define the models as follows: - // - // Small: BRASL can call any function and will use a stub if necessary. - // Locally-binding symbols will always be in range of LARL. - // - // Medium: BRASL can call any function and will use a stub if necessary. - // GOT slots and locally-defined text will always be in range - // of LARL, but other symbols might not be. - // - // Large: Equivalent to Medium for now. - // - // Kernel: Equivalent to Medium for now. - // - // This means that any PIC module smaller than 4GB meets the - // requirements of Small, so Small seems like the best default there. - // - // All symbols bind locally in a non-PIC module, so the choice is less - // obvious. There are two cases: - // - // - When creating an executable, PLTs and copy relocations allow - // us to treat external symbols as part of the executable. - // Any executable smaller than 4GB meets the requirements of Small, - // so that seems like the best default. - // - // - When creating JIT code, stubs will be in range of BRASL if the - // image is less than 4GB in size. GOT entries will likewise be - // in range of LARL. However, the JIT environment has no equivalent - // of copy relocs, so locally-binding data symbols might not be in - // the range of LARL. We need the Medium model in that case. - if (CM == CodeModel::Default) - CM = CodeModel::Small; - else if (CM == CodeModel::JITDefault) - CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; -} - static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -223,10 +186,6 @@ extern "C" void LLVMInitializeSystemZTargetMC() { TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(), createSystemZMCAsmInfo); - // Register the adjustCodeGenOpts. - TargetRegistry::registerMCAdjustCodeGenOpts(getTheSystemZTarget(), - adjustCodeGenOpts); - // Register the MCCodeEmitter. TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(), createSystemZMCCodeEmitter); diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index 025bf73d2df..aa76a96413b 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -99,14 +99,54 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +// For SystemZ we define the models as follows: +// +// Small: BRASL can call any function and will use a stub if necessary. +// Locally-binding symbols will always be in range of LARL. +// +// Medium: BRASL can call any function and will use a stub if necessary. +// GOT slots and locally-defined text will always be in range +// of LARL, but other symbols might not be. +// +// Large: Equivalent to Medium for now. +// +// Kernel: Equivalent to Medium for now. +// +// This means that any PIC module smaller than 4GB meets the +// requirements of Small, so Small seems like the best default there. +// +// All symbols bind locally in a non-PIC module, so the choice is less +// obvious. There are two cases: +// +// - When creating an executable, PLTs and copy relocations allow +// us to treat external symbols as part of the executable. +// Any executable smaller than 4GB meets the requirements of Small, +// so that seems like the best default. +// +// - When creating JIT code, stubs will be in range of BRASL if the +// image is less than 4GB in size. GOT entries will likewise be +// in range of LARL. However, the JIT environment has no equivalent +// of copy relocs, so locally-binding data symbols might not be in +// the range of LARL. We need the Medium model in that case. +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM, + Reloc::Model RM, bool JIT) { + if (CM) + return *CM; + if (JIT) + return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; + return CodeModel::Small; +} + SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) - : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, - getEffectiveRelocModel(RM), CM, OL), + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : LLVMTargetMachine( + T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, + getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL), TLOF(llvm::make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h index a10ca64fa63..95ad5e339e0 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/lib/Target/SystemZ/SystemZTargetMachine.h @@ -32,8 +32,8 @@ class SystemZTargetMachine : public LLVMTargetMachine { public: SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~SystemZTargetMachine() override; const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } diff --git a/lib/Target/TargetMachineC.cpp b/lib/Target/TargetMachineC.cpp index 01f14939864..210375ff828 100644 --- a/lib/Target/TargetMachineC.cpp +++ b/lib/Target/TargetMachineC.cpp @@ -119,7 +119,8 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, break; } - CodeModel::Model CM = unwrap(CodeModel); + bool JIT; + Optional<CodeModel::Model> CM = unwrap(CodeModel, JIT); CodeGenOpt::Level OL; switch (Level) { @@ -138,8 +139,8 @@ LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, } TargetOptions opt; - return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, - CM, OL)); + return wrap(unwrap(T)->createTargetMachine(Triple, CPU, Features, opt, RM, CM, + OL, JIT)); } void LLVMDisposeTargetMachine(LLVMTargetMachineRef T) { delete unwrap(T); } diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 22cb0fac33c..b33d895520b 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -198,18 +198,6 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - bool is64Bit = TT.getArch() == Triple::x86_64; - - // For static codegen, if we're not already set, use Small codegen. - if (CM == CodeModel::Default) - CM = CodeModel::Small; - else if (CM == CodeModel::JITDefault) - // 64-bit JIT places everything in the same buffer except external funcs. - CM = is64Bit ? CodeModel::Large : CodeModel::Small; -} - static MCInstPrinter *createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -238,9 +226,6 @@ extern "C" void LLVMInitializeX86TargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); - // Register the MC codegen info. - RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 08c2cdaefe7..e40481dad34 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -181,15 +181,27 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM, + bool JIT, bool Is64Bit) { + if (CM) + return *CM; + if (JIT) + return Is64Bit ? CodeModel::Large : CodeModel::Small; + return CodeModel::Small; +} + /// Create an X86 target. /// X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, - getEffectiveRelocModel(TT, RM), CM, OL), + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : LLVMTargetMachine( + T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(TT, RM), + getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL), TLOF(createTLOF(getTargetTriple())) { // Windows stack unwinder gets confused when execution flow "falls through" // after a call to 'noreturn' function. diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 617cec26567..952bd1321ff 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -35,8 +35,8 @@ class X86TargetMachine final : public LLVMTargetMachine { public: X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~X86TargetMachine() override; const X86Subtarget *getSubtargetImpl(const Function &F) const override; diff --git a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index dd27e7ca30a..805f1c18b60 100644 --- a/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -65,15 +65,6 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, - CodeModel::Model &CM) { - if (CM == CodeModel::Default) { - CM = CodeModel::Small; - } - if (CM != CodeModel::Small && CM != CodeModel::Large) - report_fatal_error("Target only supports CodeModel Small or Large"); -} - static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, @@ -134,10 +125,6 @@ extern "C" void LLVMInitializeXCoreTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(getTheXCoreTarget(), createXCoreMCAsmInfo); - // Register the MC codegen info. - TargetRegistry::registerMCAdjustCodeGenOpts(getTheXCoreTarget(), - adjustCodeGenOpts); - // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(getTheXCoreTarget(), createXCoreMCInstrInfo); diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index cb23399995d..3aa7187e0cd 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -31,17 +31,27 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) { + if (*CM != CodeModel::Small && *CM != CodeModel::Large) + report_fatal_error("Target only supports CodeModel Small or Large"); + return *CM; + } + return CodeModel::Small; +} + /// Create an ILP32 architecture model /// XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) : LLVMTargetMachine( T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32", - TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), + TT, CPU, FS, Options, getEffectiveRelocModel(RM), + getEffectiveCodeModel(CM), OL), TLOF(llvm::make_unique<XCoreTargetObjectFile>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index a047b3c9d9f..5baa3524d2a 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -31,8 +31,8 @@ class XCoreTargetMachine : public LLVMTargetMachine { public: XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, - Optional<Reloc::Model> RM, CodeModel::Model CM, - CodeGenOpt::Level OL); + Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT); ~XCoreTargetMachine() override; const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } diff --git a/test/CodeGen/ARM/legalize-unaligned-load.ll b/test/CodeGen/ARM/legalize-unaligned-load.ll index ccf93c3ef55..3defd7623e9 100644 --- a/test/CodeGen/ARM/legalize-unaligned-load.ll +++ b/test/CodeGen/ARM/legalize-unaligned-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -code-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s +; RUN: llc -O3 -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s ; Check that we respect the existing chain between loads and stores when we ; legalize unaligned loads. ; Test case from PR24669. diff --git a/test/CodeGen/XCore/codemodel.ll b/test/CodeGen/XCore/codemodel.ll index 4e637995c5a..d18525f3a9b 100644 --- a/test/CodeGen/XCore/codemodel.ll +++ b/test/CodeGen/XCore/codemodel.ll @@ -4,7 +4,7 @@ ; BAD_CM: Target only supports CodeModel Small or Large -; RUN: llc < %s -march=xcore -code-model=default | FileCheck %s +; RUN: llc < %s -march=xcore | FileCheck %s ; RUN: llc < %s -march=xcore -code-model=small | FileCheck %s ; RUN: llc < %s -march=xcore -code-model=large | FileCheck %s -check-prefix=LARGE diff --git a/tools/llc/llc.cpp b/tools/llc/llc.cpp index 648f74be4ba..aad237c42dc 100644 --- a/tools/llc/llc.cpp +++ b/tools/llc/llc.cpp @@ -448,9 +448,9 @@ static int compileModule(char **argv, LLVMContext &Context) { Options.MCOptions.IASSearchPaths = IncludeDirs; Options.MCOptions.SplitDwarfFile = SplitDwarfFile; - std::unique_ptr<TargetMachine> Target( - TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr, FeaturesStr, - Options, getRelocModel(), CMModel, OLvl)); + std::unique_ptr<TargetMachine> Target(TheTarget->createTargetMachine( + TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(), + getCodeModel(), OLvl)); assert(Target && "Could not allocate target machine!"); diff --git a/tools/lli/lli.cpp b/tools/lli/lli.cpp index 091ca22b4e8..cce549d0a25 100644 --- a/tools/lli/lli.cpp +++ b/tools/lli/lli.cpp @@ -15,20 +15,21 @@ #include "OrcLazyJIT.h" #include "RemoteJITUtils.h" -#include "llvm/IR/LLVMContext.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Triple.h" #include "llvm/Bitcode/BitcodeReader.h" +#include "llvm/CodeGen/CommandFlags.h" #include "llvm/CodeGen/LinkAllCodegenComponents.h" #include "llvm/ExecutionEngine/GenericValue.h" #include "llvm/ExecutionEngine/Interpreter.h" #include "llvm/ExecutionEngine/JITEventListener.h" #include "llvm/ExecutionEngine/MCJIT.h" #include "llvm/ExecutionEngine/ObjectCache.h" +#include "llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h" #include "llvm/ExecutionEngine/OrcMCJITReplacement.h" #include "llvm/ExecutionEngine/SectionMemoryManager.h" -#include "llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/LLVMContext.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/TypeBuilder.h" @@ -124,22 +125,6 @@ namespace { TargetTriple("mtriple", cl::desc("Override target triple for module")); cl::opt<std::string> - MArch("march", - cl::desc("Architecture to generate assembly for (see --version)")); - - cl::opt<std::string> - MCPU("mcpu", - cl::desc("Target a specific cpu type (-mcpu=help for details)"), - cl::value_desc("cpu-name"), - cl::init("")); - - cl::list<std::string> - MAttrs("mattr", - cl::CommaSeparated, - cl::desc("Target specific attributes (-mattr=help for details)"), - cl::value_desc("a1,+a2,-a3,...")); - - cl::opt<std::string> EntryFunc("entry-function", cl::desc("Specify the entry function (default = 'main') " "of the executable"), @@ -186,47 +171,11 @@ namespace { cl::desc("Disable JIT lazy compilation"), cl::init(false)); - cl::opt<Reloc::Model> RelocModel( - "relocation-model", cl::desc("Choose relocation model"), - cl::values( - clEnumValN(Reloc::Static, "static", "Non-relocatable code"), - clEnumValN(Reloc::PIC_, "pic", - "Fully relocatable, position independent code"), - clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic", - "Relocatable external references, non-relocatable code"))); - - cl::opt<llvm::CodeModel::Model> - CMModel("code-model", - cl::desc("Choose code model"), - cl::init(CodeModel::JITDefault), - cl::values(clEnumValN(CodeModel::JITDefault, "default", - "Target default JIT code model"), - clEnumValN(CodeModel::Small, "small", - "Small code model"), - clEnumValN(CodeModel::Kernel, "kernel", - "Kernel code model"), - clEnumValN(CodeModel::Medium, "medium", - "Medium code model"), - clEnumValN(CodeModel::Large, "large", - "Large code model"))); - cl::opt<bool> GenerateSoftFloatCalls("soft-float", cl::desc("Generate software floating point library calls"), cl::init(false)); - cl::opt<llvm::FloatABI::ABIType> - FloatABIForCalls("float-abi", - cl::desc("Choose float ABI type"), - cl::init(FloatABI::Default), - cl::values( - clEnumValN(FloatABI::Default, "default", - "Target default float ABI type"), - clEnumValN(FloatABI::Soft, "soft", - "Soft float ABI (implied by -soft-float)"), - clEnumValN(FloatABI::Hard, "hard", - "Hard float ABI (uses FP registers)"))); - ExitOnError ExitOnErr; } @@ -433,7 +382,8 @@ int main(int argc, char **argv, char * const *envp) { builder.setMAttrs(MAttrs); if (RelocModel.getNumOccurrences()) builder.setRelocationModel(RelocModel); - builder.setCodeModel(CMModel); + if (CMModel.getNumOccurrences()) + builder.setCodeModel(CMModel); builder.setErrorStr(&ErrorMsg); builder.setEngineKind(ForceInterpreter ? EngineKind::Interpreter diff --git a/tools/llvm-lto2/llvm-lto2.cpp b/tools/llvm-lto2/llvm-lto2.cpp index 5db441fff25..1c7038e6a2e 100644 --- a/tools/llvm-lto2/llvm-lto2.cpp +++ b/tools/llvm-lto2/llvm-lto2.cpp @@ -197,7 +197,7 @@ static int run(int argc, char **argv) { Conf.MAttrs = MAttrs; if (auto RM = getRelocModel()) Conf.RelocModel = *RM; - Conf.CodeModel = CMModel; + Conf.CodeModel = getCodeModel(); Conf.DebugPassManager = DebugPassManager; diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp index 24cce58047f..7bbdb7ebb23 100644 --- a/tools/opt/opt.cpp +++ b/tools/opt/opt.cpp @@ -349,7 +349,7 @@ static TargetMachine* GetTargetMachine(Triple TheTriple, StringRef CPUStr, return TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(), - CMModel, GetCodeGenOptLevel()); + getCodeModel(), GetCodeGenOptLevel()); } #ifdef LINK_POLLY_INTO_TOOLS diff --git a/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h b/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h index e14201c2d78..a768920ff47 100644 --- a/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h +++ b/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h @@ -278,14 +278,9 @@ protected: class MCJITTestBase : public MCJITTestAPICommon, public TrivialModuleBuilder { protected: - MCJITTestBase() - : TrivialModuleBuilder(HostTriple) - , OptLevel(CodeGenOpt::None) - , CodeModel(CodeModel::Default) - , MArch("") - , MM(new SectionMemoryManager) - { + : TrivialModuleBuilder(HostTriple), OptLevel(CodeGenOpt::None), + CodeModel(CodeModel::Small), MArch(""), MM(new SectionMemoryManager) { // The architectures below are known to be compatible with MCJIT as they // are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be // kept in sync. @@ -320,7 +315,6 @@ protected: .setMCJITMemoryManager(std::move(MM)) .setErrorStr(&Error) .setOptLevel(CodeGenOpt::None) - .setCodeModel(CodeModel::JITDefault) .setMArch(MArch) .setMCPU(sys::getHostCPUName()) //.setMAttrs(MAttrs) diff --git a/unittests/MI/LiveIntervalTest.cpp b/unittests/MI/LiveIntervalTest.cpp index 01dce37d9c6..9d1d864eccd 100644 --- a/unittests/MI/LiveIntervalTest.cpp +++ b/unittests/MI/LiveIntervalTest.cpp @@ -45,9 +45,8 @@ std::unique_ptr<TargetMachine> createTargetMachine() { return nullptr; TargetOptions Options; - return std::unique_ptr<TargetMachine>( - T->createTargetMachine("AMDGPU", "", "", Options, None, - CodeModel::Default, CodeGenOpt::Aggressive)); + return std::unique_ptr<TargetMachine>(T->createTargetMachine( + "AMDGPU", "", "", Options, None, None, CodeGenOpt::Aggressive)); } std::unique_ptr<Module> parseMIR(LLVMContext &Context, diff --git a/unittests/Target/AArch64/InstSizes.cpp b/unittests/Target/AArch64/InstSizes.cpp index f5a6d4fa67d..e58df0a45cc 100644 --- a/unittests/Target/AArch64/InstSizes.cpp +++ b/unittests/Target/AArch64/InstSizes.cpp @@ -22,9 +22,8 @@ std::unique_ptr<TargetMachine> createTargetMachine() { std::string Error; const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); - return std::unique_ptr<TargetMachine>( - TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), None, - CodeModel::Default, CodeGenOpt::Default)); + return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine( + TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default)); } std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) { |