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-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp23
-rw-r--r--lib/Target/PowerPC/PPCVSXSwapRemoval.cpp1
-rw-r--r--test/CodeGen/PowerPC/vsx.ll294
3 files changed, 299 insertions, 19 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index de7761c7db9..c85c2610d2f 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -2773,18 +2773,6 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
else
DM[i] = 1;
- // For little endian, we must swap the input operands and adjust
- // the mask elements (reverse and invert them).
- if (PPCSubTarget->isLittleEndian()) {
- std::swap(Op1, Op2);
- unsigned tmp = DM[0];
- DM[0] = 1 - DM[1];
- DM[1] = 1 - tmp;
- }
-
- SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
- MVT::i32);
-
if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
isa<LoadSDNode>(Op1.getOperand(0))) {
@@ -2800,6 +2788,17 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
}
}
+ // For little endian, we must swap the input operands and adjust
+ // the mask elements (reverse and invert them).
+ if (PPCSubTarget->isLittleEndian()) {
+ std::swap(Op1, Op2);
+ unsigned tmp = DM[0];
+ DM[0] = 1 - DM[1];
+ DM[1] = 1 - tmp;
+ }
+
+ SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), dl,
+ MVT::i32);
SDValue Ops[] = { Op1, Op2, DMV };
return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
}
diff --git a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index e238669145a..6f75ff1dbf4 100644
--- a/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -349,7 +349,6 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
case PPC::LVSL:
case PPC::LVSR:
case PPC::LVXL:
- case PPC::LXVDSX:
case PPC::STVEBX:
case PPC::STVEHX:
case PPC::STVEWX:
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index b185fed4cd5..f85acebeea6 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -1,9 +1,8 @@
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
-; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s
define double @test1(double %a, double %b) {
entry:
@@ -13,6 +12,10 @@ entry:
; CHECK-LABEL: @test1
; CHECK: xsmuldp 1, 1, 2
; CHECK: blr
+
+; CHECK-LE-LABEL: @test1
+; CHECK-LE: xsmuldp 1, 1, 2
+; CHECK-LE: blr
}
define double @test2(double %a, double %b) {
@@ -23,6 +26,10 @@ entry:
; CHECK-LABEL: @test2
; CHECK: xsdivdp 1, 1, 2
; CHECK: blr
+
+; CHECK-LE-LABEL: @test2
+; CHECK-LE: xsdivdp 1, 1, 2
+; CHECK-LE: blr
}
define double @test3(double %a, double %b) {
@@ -33,6 +40,10 @@ entry:
; CHECK-LABEL: @test3
; CHECK: xsadddp 1, 1, 2
; CHECK: blr
+
+; CHECK-LE-LABEL: @test3
+; CHECK-LE: xsadddp 1, 1, 2
+; CHECK-LE: blr
}
define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
@@ -43,6 +54,10 @@ entry:
; CHECK-LABEL: @test4
; CHECK: xvadddp 34, 34, 35
; CHECK: blr
+
+; CHECK-LE-LABEL: @test4
+; CHECK-LE: xvadddp 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
@@ -60,6 +75,10 @@ entry:
; CHECK-FISL: xxlxor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test5
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
}
define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
@@ -77,6 +96,10 @@ entry:
; CHECK-FISL: xxlxor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test6
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
}
define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
@@ -94,6 +117,10 @@ entry:
; CHECK-FISL: xxlxor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test7
+; CHECK-LE: xxlxor 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
@@ -111,6 +138,10 @@ entry:
; CHECK-FISL: xxlor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test8
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
}
define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
@@ -128,6 +159,10 @@ entry:
; CHECK-FISL: xxlor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test9
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
}
define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
@@ -145,6 +180,10 @@ entry:
; CHECK-FISL: xxlor 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test10
+; CHECK-LE: xxlor 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
@@ -162,6 +201,10 @@ entry:
; CHECK-FISL: xxland 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test11
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
}
define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
@@ -179,6 +222,10 @@ entry:
; CHECK-FISL: xxland 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test12
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
}
define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
@@ -196,6 +243,10 @@ entry:
; CHECK-FISL: xxland 36, 36, 37
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test13
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
@@ -221,6 +272,10 @@ entry:
; CHECK-FISL: ori 0, 0, 65520
; CHECK-FISL: stvx 0, 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test14
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
}
define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
@@ -246,6 +301,10 @@ entry:
; CHECK-FISL: ori 0, 0, 65520
; CHECK-FISL: stvx 0, 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test15
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
}
define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
@@ -271,6 +330,10 @@ entry:
; CHECK-FISL: ori 0, 0, 65520
; CHECK-FISL: stvx 0, 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test16
+; CHECK-LE: xxlnor 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
@@ -294,6 +357,10 @@ entry:
; CHECK-FISL: xxland 37, 37, 32
; CHECK-FISL: vor 2, 5, 5
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test17
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
}
define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
@@ -320,6 +387,10 @@ entry:
; CHECK-FISL: ori 0, 0, 65520
; CHECK-FISL: stvx 4, 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test18
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
}
define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
@@ -346,6 +417,10 @@ entry:
; CHECK-FISL: ori 0, 0, 65520
; CHECK-FISL: stvx 4, 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test19
+; CHECK-LE: xxlandc 34, 34, 35
+; CHECK-LE: blr
}
define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
@@ -367,6 +442,11 @@ entry:
; CHECK-FISL: xxsel 32, 32, 33, 38
; CHECK-FISL: vor 2, 0, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test20
+; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
}
define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
@@ -389,6 +469,11 @@ entry:
; CHECK-FISL: xxsel 32, 38, 39, 32
; CHECK-FISL: vor 2, 0, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test21
+; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
+; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: blr
}
define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
@@ -418,6 +503,17 @@ entry:
; CHECK-FISL-DAG: xxlor
; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test22
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
+; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
+; CHECK-LE-DAG: xxlnor
+; CHECK-LE-DAG: xxlnor
+; CHECK-LE-DAG: xxlor
+; CHECK-LE-DAG: xxlor
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
}
define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
@@ -439,6 +535,11 @@ entry:
; CHECK-FISL: xxsel 32, 32, 33, 38
; CHECK-FISL: vor 2, 0,
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test23
+; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
}
define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
@@ -460,6 +561,11 @@ entry:
; CHECK-FISL: xxsel 32, 32, 33, 38
; CHECK-FISL: vor 2, 0, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test24
+; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
+; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
+; CHECK-LE: blr
}
define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
@@ -472,6 +578,11 @@ entry:
; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
; CHECK: xxsel 34, 35, 34, [[V1]]
; CHECK: blr
+
+; CHECK-LE-LABEL: @test25
+; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
+; CHECK-LE: xxsel 34, 35, 34, [[V1]]
+; CHECK-LE: blr
}
define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
@@ -489,6 +600,9 @@ define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
; CHECK: add
; CHECK: add
; CHECK: blr
+
+; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: blr
}
define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
@@ -498,6 +612,10 @@ define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: @test27
; CHECK: xxland 34, 34, 35
; CHECK: blr
+
+; CHECK-LE-LABEL: @test27
+; CHECK-LE: xxland 34, 34, 35
+; CHECK-LE: blr
}
define <2 x double> @test28(<2 x double>* %a) {
@@ -507,6 +625,11 @@ define <2 x double> @test28(<2 x double>* %a) {
; CHECK-LABEL: @test28
; CHECK: lxvd2x 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test28
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test29(<2 x double>* %a, <2 x double> %b) {
@@ -516,6 +639,11 @@ define void @test29(<2 x double>* %a, <2 x double> %b) {
; CHECK-LABEL: @test29
; CHECK: stxvd2x 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test29
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <2 x double> @test28u(<2 x double>* %a) {
@@ -525,6 +653,11 @@ define <2 x double> @test28u(<2 x double>* %a) {
; CHECK-LABEL: @test28u
; CHECK: lxvd2x 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test28u
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test29u(<2 x double>* %a, <2 x double> %b) {
@@ -534,6 +667,11 @@ define void @test29u(<2 x double>* %a, <2 x double> %b) {
; CHECK-LABEL: @test29u
; CHECK: stxvd2x 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test29u
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <2 x i64> @test30(<2 x i64>* %a) {
@@ -550,6 +688,11 @@ define <2 x i64> @test30(<2 x i64>* %a) {
; CHECK-FISL: vor 3, 2, 2
; CHECK-FISL: vor 2, 3, 3
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test30
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test31(<2 x i64>* %a, <2 x i64> %b) {
@@ -559,6 +702,11 @@ define void @test31(<2 x i64>* %a, <2 x i64> %b) {
; CHECK-LABEL: @test31
; CHECK: stxvd2x 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test31
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <4 x float> @test32(<4 x float>* %a) {
@@ -573,6 +721,11 @@ define <4 x float> @test32(<4 x float>* %a) {
; CHECK-FISL: lxvw4x 0, 0, 3
; CHECK-FISL: xxlor 34, 0, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test32
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test33(<4 x float>* %a, <4 x float> %b) {
@@ -587,6 +740,11 @@ define void @test33(<4 x float>* %a, <4 x float> %b) {
; CHECK-FISL: vor 3, 2, 2
; CHECK-FISL: stxvw4x 35, 0, 3
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test33
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <4 x float> @test32u(<4 x float>* %a) {
@@ -599,6 +757,11 @@ define <4 x float> @test32u(<4 x float>* %a) {
; CHECK-DAG: lvx
; CHECK: vperm 2,
; CHECK: blr
+
+; CHECK-LE-LABEL: @test32u
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test33u(<4 x float>* %a, <4 x float> %b) {
@@ -613,6 +776,11 @@ define void @test33u(<4 x float>* %a, <4 x float> %b) {
; CHECK-FISL: vor 3, 2, 2
; CHECK-FISL: stxvw4x 35, 0, 3
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test33u
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <4 x i32> @test34(<4 x i32>* %a) {
@@ -629,6 +797,11 @@ define <4 x i32> @test34(<4 x i32>* %a) {
; CHECK-FISL: vor 3, 2, 2
; CHECK-FISL: vor 2, 3, 3
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test34
+; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
+; CHECK-LE: xxswapd 34, [[V1]]
+; CHECK-LE: blr
}
define void @test35(<4 x i32>* %a, <4 x i32> %b) {
@@ -643,6 +816,11 @@ define void @test35(<4 x i32>* %a, <4 x i32> %b) {
; CHECK-FISL: vor 3, 2, 2
; CHECK-FISL: stxvw4x 35, 0, 3
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test35
+; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
+; CHECK-LE: stxvd2x [[V1]], 0, 3
+; CHECK-LE: blr
}
define <2 x double> @test40(<2 x i64> %a) {
@@ -652,6 +830,10 @@ define <2 x double> @test40(<2 x i64> %a) {
; CHECK-LABEL: @test40
; CHECK: xvcvuxddp 34, 34
; CHECK: blr
+
+; CHECK-LE-LABEL: @test40
+; CHECK-LE: xvcvuxddp 34, 34
+; CHECK-LE: blr
}
define <2 x double> @test41(<2 x i64> %a) {
@@ -661,6 +843,10 @@ define <2 x double> @test41(<2 x i64> %a) {
; CHECK-LABEL: @test41
; CHECK: xvcvsxddp 34, 34
; CHECK: blr
+
+; CHECK-LE-LABEL: @test41
+; CHECK-LE: xvcvsxddp 34, 34
+; CHECK-LE: blr
}
define <2 x i64> @test42(<2 x double> %a) {
@@ -670,6 +856,10 @@ define <2 x i64> @test42(<2 x double> %a) {
; CHECK-LABEL: @test42
; CHECK: xvcvdpuxds 34, 34
; CHECK: blr
+
+; CHECK-LE-LABEL: @test42
+; CHECK-LE: xvcvdpuxds 34, 34
+; CHECK-LE: blr
}
define <2 x i64> @test43(<2 x double> %a) {
@@ -679,6 +869,10 @@ define <2 x i64> @test43(<2 x double> %a) {
; CHECK-LABEL: @test43
; CHECK: xvcvdpsxds 34, 34
; CHECK: blr
+
+; CHECK-LE-LABEL: @test43
+; CHECK-LE: xvcvdpsxds 34, 34
+; CHECK-LE: blr
}
define <2 x float> @test44(<2 x i64> %a) {
@@ -726,6 +920,10 @@ define <2 x double> @test50(double* %a) {
; CHECK-LABEL: @test50
; CHECK: lxvdsx 34, 0, 3
; CHECK: blr
+
+; CHECK-LE-LABEL: @test50
+; CHECK-LE: lxvdsx 34, 0, 3
+; CHECK-LE: blr
}
define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
@@ -735,6 +933,10 @@ define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test51
; CHECK: xxspltd 34, 34, 0
; CHECK: blr
+
+; CHECK-LE-LABEL: @test51
+; CHECK-LE: xxspltd 34, 34, 1
+; CHECK-LE: blr
}
define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
@@ -744,6 +946,10 @@ define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test52
; CHECK: xxmrghd 34, 34, 35
; CHECK: blr
+
+; CHECK-LE-LABEL: @test52
+; CHECK-LE: xxmrgld 34, 35, 34
+; CHECK-LE: blr
}
define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
@@ -753,6 +959,10 @@ define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test53
; CHECK: xxmrghd 34, 35, 34
; CHECK: blr
+
+; CHECK-LE-LABEL: @test53
+; CHECK-LE: xxmrgld 34, 34, 35
+; CHECK-LE: blr
}
define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
@@ -762,6 +972,10 @@ define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test54
; CHECK: xxpermdi 34, 34, 35, 2
; CHECK: blr
+
+; CHECK-LE-LABEL: @test54
+; CHECK-LE: xxpermdi 34, 35, 34, 2
+; CHECK-LE: blr
}
define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
@@ -771,6 +985,10 @@ define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
; CHECK-LABEL: @test55
; CHECK: xxmrgld 34, 34, 35
; CHECK: blr
+
+; CHECK-LE-LABEL: @test55
+; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: blr
}
define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
@@ -780,6 +998,10 @@ define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: @test56
; CHECK: xxmrgld 34, 34, 35
; CHECK: blr
+
+; CHECK-LE-LABEL: @test56
+; CHECK-LE: xxmrghd 34, 35, 34
+; CHECK-LE: blr
}
define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
@@ -836,6 +1058,10 @@ define double @test63(<2 x double> %a) {
; CHECK-FISL: xxlor 0, 34, 34
; CHECK-FISL: fmr 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test63
+; CHECK-LE: xxswapd 1, 34
+; CHECK-LE: blr
}
define double @test64(<2 x double> %a) {
@@ -851,6 +1077,9 @@ define double @test64(<2 x double> %a) {
; CHECK-FISL: xxlor 0, 34, 34
; CHECK-FISL: fmr 1, 0
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test64
+; CHECK-LE: xxlor 1, 34, 34
}
define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
@@ -867,6 +1096,10 @@ define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
; CHECK-FISL: vcmpequw 4, 5, 4
; CHECK-FISL: vor 2, 4, 4
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test65
+; CHECK-LE: vcmpequd 2, 2, 3
+; CHECK-LE: blr
}
define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
@@ -882,6 +1115,11 @@ define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test66
+; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
+; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
+; CHECK-LE: blr
}
define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
@@ -896,6 +1134,10 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
; CHECK: cmpld
; CHECK: lxvd2x
; CHECK: blr
+
+; CHECK-LE-LABEL: @test67
+; CHECK-LE: vcmpgtud 2, 3, 2
+; CHECK-LE: blr
}
define <2 x double> @test68(<2 x i32> %a) {
@@ -906,6 +1148,11 @@ define <2 x double> @test68(<2 x i32> %a) {
; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
; CHECK: xvcvsxwdp 34, [[V1]]
; CHECK: blr
+
+; CHECK-LE-LABEL: @test68
+; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1
+; CHECK-LE: xvcvsxwdp 34, [[V1]]
+; CHECK-LE: blr
}
define <2 x double> @test69(<2 x i16> %a) {
@@ -920,6 +1167,15 @@ define <2 x double> @test69(<2 x i16> %a) {
; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
; CHECK: xvcvsxwdp 34, [[V4]]
; CHECK: blr
+
+; CHECK-LE-LABEL: @test69
+; CHECK-LE: vspltisw [[V1:[0-9]+]], 8
+; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
+; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
+; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
+; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: blr
}
define <2 x double> @test70(<2 x i8> %a) {
@@ -934,6 +1190,15 @@ define <2 x double> @test70(<2 x i8> %a) {
; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
; CHECK: xvcvsxwdp 34, [[V4]]
; CHECK: blr
+
+; CHECK-LE-LABEL: @test70
+; CHECK-LE: vspltisw [[V1:[0-9]+]], 12
+; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
+; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
+; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
+; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
+; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: blr
}
define <2 x i32> @test80(i32 %v) {
@@ -960,6 +1225,16 @@ define <2 x i32> @test80(i32 %v) {
; CHECK-FISL-DAG: std [[R3]], -16(1)
; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
; CHECK-FISL: blr
+
+; CHECK-LE-LABEL: @test80
+; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16
+; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
+; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]]
+; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
+; CHECK-LE-DAG: xxswapd 34, [[V1]]
+; CHECK-LE-DAG: xxswapd 35, [[V2]]
+; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: blr
}
define <2 x double> @test81(<4 x float> %b) {
@@ -968,6 +1243,9 @@ define <2 x double> @test81(<4 x float> %b) {
; CHECK-LABEL: @test81
; CHECK: blr
+
+; CHECK-LE-LABEL: @test81
+; CHECK-LE: blr
}
define double @test82(double %a, double %b, double %c, double %d) {
@@ -983,4 +1261,8 @@ entry:
; CHECK-FISL-LABEL: @test82
; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
; CHECK-FISL: beq [[REG]], {{.*}}
+
+; CHECK-LE-LABEL: @test82
+; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
+; CHECK-LE: beqlr [[REG]]
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 17:00:38 +0000