diff options
26 files changed, 1121 insertions, 147 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index c9a5faa86f6..f794312e39b 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -75,8 +75,6 @@ STATISTIC(NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence."); STATISTIC(SignExtensionsAdded, "Number of sign extensions for compare inputs added."); -STATISTIC(ZeroExtensionsAdded, - "Number of zero extensions for compare inputs added."); STATISTIC(NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR."); STATISTIC(OmittedForNonExtendUses, @@ -288,13 +286,24 @@ private: // SExtInvert - invert the condition code, sign-extend value enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert }; + // Comparisons against zero to emit GPR code sequences for. Each of these + // sequences may need to be emitted for two or more equivalent patterns. + // For example (a >= 0) == (a > -1). The direction of the comparison (</>) + // matters as well as the extension type: sext (-1/0), zext (1/0). + // GEZExt - (zext (LHS >= 0)) + // GESExt - (sext (LHS >= 0)) + // LEZExt - (zext (LHS <= 0)) + // LESExt - (sext (LHS <= 0)) + enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt }; + bool trySETCC(SDNode *N); bool tryEXTEND(SDNode *N); bool tryLogicOpOfCompares(SDNode *N); SDValue computeLogicOpInGPR(SDValue LogicOp); SDValue signExtendInputIfNeeded(SDValue Input); - SDValue zeroExtendInputIfNeeded(SDValue Input); SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv); + SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, + ZeroCompare CmpTy); SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, int64_t RHSValue, SDLoc dl); SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC, @@ -2553,15 +2562,15 @@ bool PPCDAGToDAGISel::tryEXTEND(SDNode *N) { return false; SDLoc dl(N); - bool Inputs32Bit = N->getOperand(0).getOperand(0).getValueType() == MVT::i32; + bool Input32Bit = WideRes.getValueType() == MVT::i32; bool Output32Bit = N->getValueType(0) == MVT::i32; NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0; NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1; SDValue ConvOp = WideRes; - if (Inputs32Bit != Output32Bit) - ConvOp = addExtOrTrunc(WideRes, Inputs32Bit ? ExtOrTruncConversion::Ext : + if (Input32Bit != Output32Bit) + ConvOp = addExtOrTrunc(WideRes, Input32Bit ? ExtOrTruncConversion::Ext : ExtOrTruncConversion::Trunc); ReplaceNode(N, ConvOp.getNode()); @@ -2722,6 +2731,7 @@ bool PPCDAGToDAGISel::tryLogicOpOfCompares(SDNode *N) { } /// If the value isn't guaranteed to be sign-extended to 64-bits, extend it. +/// Otherwise just reinterpret it as a 64-bit value. /// Useful when emitting comparison code for 32-bit values without using /// the compare instruction (which only considers the lower 32-bits). SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) { @@ -2734,51 +2744,23 @@ SDValue PPCDAGToDAGISel::signExtendInputIfNeeded(SDValue Input) { if (Opc == ISD::TRUNCATE && (Input.getOperand(0).getOpcode() == ISD::AssertSext || Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND)) - return Input; + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input); // The input is a sign-extending load. No reason to sign-extend. if (InputLoad && InputLoad->getExtensionType() == ISD::SEXTLOAD) - return Input; + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input); // We don't sign-extend constants and already sign-extended values. if (InputConst || Opc == ISD::AssertSext || Opc == ISD::SIGN_EXTEND_INREG || Opc == ISD::SIGN_EXTEND) - return Input; + return addExtOrTrunc(Input, ExtOrTruncConversion::Ext); SDLoc dl(Input); SignExtensionsAdded++; - return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32, dl, MVT::i32, Input), 0); -} - -/// If the value isn't guaranteed to be zero-extended to 64-bits, extend it. -/// Useful when emitting comparison code for 32-bit values without using -/// the compare instruction (which only considers the lower 32-bits). -SDValue PPCDAGToDAGISel::zeroExtendInputIfNeeded(SDValue Input) { - assert(Input.getValueType() == MVT::i32 && - "Can only zero-extend 32-bit values here."); - LoadSDNode *InputLoad = dyn_cast<LoadSDNode>(Input); - unsigned Opc = Input.getOpcode(); - - // No need to zero-extend loaded values (unless they're loaded with - // a sign-extending load). - if (InputLoad && InputLoad->getExtensionType() != ISD::SEXTLOAD) - return Input; - - ConstantSDNode *InputConst = dyn_cast<ConstantSDNode>(Input); - bool InputZExtConst = InputConst && InputConst->getSExtValue() >= 0; - // An ISD::TRUNCATE will be lowered to an EXTRACT_SUBREG so we have - // to conservatively actually clear the high bits. We also don't need to - // zero-extend constants or values that are already zero-extended. - if (InputZExtConst || Opc == ISD::AssertZext || Opc == ISD::ZERO_EXTEND) - return Input; - - SDLoc dl(Input); - ZeroExtensionsAdded++; - return SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Input, - getI64Imm(0, dl), getI64Imm(32, dl)), - 0); + return SDValue(CurDAG->getMachineNode(PPC::EXTSW_32_64, dl, + MVT::i64, Input), 0); } // Handle a 32-bit value in a 64-bit register and vice-versa. These are of @@ -2809,6 +2791,73 @@ SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes, NatWidthRes, SubRegIdx), 0); } +// Produce a GPR sequence for compound comparisons (<=, >=) against zero. +// Handle both zero-extensions and sign-extensions. +SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl, + ZeroCompare CmpTy) { + EVT InVT = LHS.getValueType(); + bool Is32Bit = InVT == MVT::i32; + SDValue ToExtend; + + // Produce the value that needs to be either zero or sign extended. + switch (CmpTy) { + default: llvm_unreachable("Unknown Zero-comparison type."); + case ZeroCompare::GEZExt: + case ZeroCompare::GESExt: + ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8, + dl, InVT, LHS, LHS), 0); + case ZeroCompare::LEZExt: + case ZeroCompare::LESExt: { + if (Is32Bit) { + // Upper 32 bits cannot be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + SDValue Neg = + SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, LHS), 0); + ToExtend = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + Neg, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + } else { + SDValue Addi = + SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS, + getI64Imm(~0ULL, dl)), 0); + ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64, + Addi, LHS), 0); + } + } + } + + // For 64-bit sequences, the extensions are the same for the GE/LE cases. + if (!Is32Bit && (CmpTy == ZeroCompare::GEZExt || ZeroCompare::LEZExt)) + return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + ToExtend, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + if (!Is32Bit && (CmpTy == ZeroCompare::GESExt || ZeroCompare::LESExt)) + return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend, + getI64Imm(63, dl)), 0); + + assert(Is32Bit && "Should have handled the 32-bit sequences above."); + // For 32-bit sequences, the extensions differ between GE/LE cases. + switch (CmpTy) { + default: llvm_unreachable("Unknown Zero-comparison type."); + case ZeroCompare::GEZExt: { + SDValue ShiftOps[] = + { ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) }; + return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, + ShiftOps), 0); + } + case ZeroCompare::GESExt: + return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend, + getI32Imm(31, dl)), 0); + case ZeroCompare::LEZExt: + return SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, MVT::i64, ToExtend, + getI32Imm(1, dl)), 0); + case ZeroCompare::LESExt: + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, ToExtend, + getI32Imm(-1, dl)), 0); + } +} + /// Produces a zero-extended result of comparing two 32-bit values according to /// the passed condition code. SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS, @@ -2843,6 +2892,34 @@ SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS, return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift, getI32Imm(1, dl)), 0); } + case ISD::SETGE: { + // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1) + // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31) + if(IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt); + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1) + // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1) + if(IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt); + + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue Sub = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, LHS, RHS), 0); + SDValue Shift = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Sub, + getI64Imm(1, dl), getI64Imm(63, dl)), 0); + return + SDValue(CurDAG->getMachineNode(PPC::XORI8, dl, + MVT::i64, Shift, getI32Imm(1, dl)), 0); + } } } @@ -2863,11 +2940,11 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS, SDValue(CurDAG->getMachineNode(PPC::XOR, dl, MVT::i32, LHS, RHS), 0); SDValue Cntlzw = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, CountInput), 0); - SDValue SHLOps[] = { Cntlzw, getI32Imm(58, dl), getI32Imm(0, dl) }; - SDValue Sldi = - SDValue(CurDAG->getMachineNode(PPC::RLDICR_32, dl, MVT::i32, SHLOps), 0); - return SDValue(CurDAG->getMachineNode(PPC::SRADI_32, dl, MVT::i32, Sldi, - getI32Imm(63, dl)), 0); + SDValue SHLOps[] = { Cntlzw, getI32Imm(27, dl), + getI32Imm(5, dl), getI32Imm(31, dl) }; + SDValue Slwi = + SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, SHLOps), 0); + return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Slwi), 0); } case ISD::SETNE: { // Bitwise xor the operands, count leading zeros, shift right by 5 bits and @@ -2890,6 +2967,35 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS, getI32Imm(1, dl)), 0); return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0); } + case ISD::SETGE: { + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1) + // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt); + std::swap(LHS, RHS); + ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS); + IsRHSZero = RHSConst && RHSConst->isNullValue(); + LLVM_FALLTHROUGH; + } + case ISD::SETLE: { + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1) + // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1) + if (IsRHSZero) + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt); + + // The upper 32-bits of the register can't be undefined for this sequence. + LHS = signExtendInputIfNeeded(LHS); + RHS = signExtendInputIfNeeded(RHS); + SDValue SUBFNode = + SDValue(CurDAG->getMachineNode(PPC::SUBF8, dl, MVT::i64, MVT::Glue, + LHS, RHS), 0); + SDValue Srdi = + SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, + SUBFNode, getI64Imm(1, dl), + getI64Imm(63, dl)), 0); + return SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, Srdi, + getI32Imm(-1, dl)), 0); + } } } @@ -3020,13 +3126,6 @@ SDValue PPCDAGToDAGISel::getSETCCInGPR(SDValue Compare, CC = ISD::getSetCCInverse(CC, true); bool Inputs32Bit = InputVT == MVT::i32; - if (ISD::isSignedIntSetCC(CC) && Inputs32Bit) { - LHS = signExtendInputIfNeeded(LHS); - RHS = signExtendInputIfNeeded(RHS); - } else if (ISD::isUnsignedIntSetCC(CC) && Inputs32Bit) { - LHS = zeroExtendInputIfNeeded(LHS); - RHS = zeroExtendInputIfNeeded(RHS); - } SDLoc dl(Compare); ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS); diff --git a/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll new file mode 100644 index 00000000000..56a167d99e6 --- /dev/null +++ b/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll @@ -0,0 +1,56 @@ +; The purpose of the test case is to ensure that a spill that happens during +; intermediate calculations for a comparison performed in a GPR spills the +; full register. Some i32 comparisons performed in GPRs use code that uses +; the full 64-bits of the register in intermediate stages. Spilling such a value +; as a 32-bit value is incorrect. +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +@glob = common local_unnamed_addr global i64 0, align 8 +@.str = private unnamed_addr constant [12 x i8] c"Value = %d\0A\00", align 1 + +; Function Attrs: noinline nounwind +define void @call(i64 %a) local_unnamed_addr #0 { +entry: + store i64 %a, i64* @glob, align 8 + tail call void asm sideeffect "#Do Nothing", "~{memory}"() + ret void +} + +; Function Attrs: noinline nounwind +define signext i32 @test(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr #0 { +entry: + %add = add nsw i32 %b, %a + %sub = sub nsw i32 %add, %c + %conv = sext i32 %sub to i64 + tail call void @call(i64 %conv) + tail call void asm sideeffect "#Do Nothing", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() + %cmp = icmp sle i32 %add, %c + %conv1 = zext i1 %cmp to i32 + ret i32 %conv1 +; CHECK-LABEL: test +; CHECK: subf r3, +; CHECK: extsw r3, +; CHECK: bl call +; CHECK: sub r3, +; CHECK: rldicl r3, r3, 1, 63 +; CHECK: std r3, [[OFF:[0-9]+]](r1) +; CHECK: #APP +; CHECK: ld r3, [[OFF]](r1) +; CHECK: xori r3, r3, 1 +; CHECK: blr +} + +; Function Attrs: nounwind +define signext i32 @main() local_unnamed_addr #1 { +entry: + %call = tail call signext i32 @test(i32 signext 10, i32 signext -15, i32 signext 0) + %call1 = tail call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i64 0, i64 0), i32 signext %call) + ret i32 0 +} + +; Function Attrs: nounwind +declare signext i32 @printf(i8* nocapture readonly, ...) local_unnamed_addr #2 diff --git a/test/CodeGen/PowerPC/testComparesieqsc.ll b/test/CodeGen/PowerPC/testComparesieqsc.ll index 71ad5ed3496..832f918a690 100644 --- a/test/CodeGen/PowerPC/testComparesieqsc.ll +++ b/test/CodeGen/PowerPC/testComparesieqsc.ll @@ -29,8 +29,8 @@ define signext i32 @test_ieqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_ieqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_ieqsc_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -91,8 +91,8 @@ define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_ieqsc_sext_z_store(i8 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesieqsi.ll b/test/CodeGen/PowerPC/testComparesieqsi.ll index 16882dbd004..90664ee9910 100644 --- a/test/CodeGen/PowerPC/testComparesieqsi.ll +++ b/test/CodeGen/PowerPC/testComparesieqsi.ll @@ -29,8 +29,8 @@ define signext i32 @test_ieqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_ieqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_ieqsi_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -91,8 +91,8 @@ define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_ieqsi_sext_z_store(i32 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesieqss.ll b/test/CodeGen/PowerPC/testComparesieqss.ll index 110c5a62804..499f482c8eb 100644 --- a/test/CodeGen/PowerPC/testComparesieqss.ll +++ b/test/CodeGen/PowerPC/testComparesieqss.ll @@ -29,8 +29,8 @@ define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_ieqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_ieqss_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -91,8 +91,8 @@ define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_ieqss_sext_z_store(i16 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequc.ll b/test/CodeGen/PowerPC/testComparesiequc.ll index e2c975f2c19..54d3ebf2247 100644 --- a/test/CodeGen/PowerPC/testComparesiequc.ll +++ b/test/CodeGen/PowerPC/testComparesiequc.ll @@ -29,8 +29,8 @@ define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_iequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_iequc_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -91,8 +91,8 @@ define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_iequc_sext_z_store(i8 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequi.ll b/test/CodeGen/PowerPC/testComparesiequi.ll index 789b176a770..cef35667a2e 100644 --- a/test/CodeGen/PowerPC/testComparesiequi.ll +++ b/test/CodeGen/PowerPC/testComparesiequi.ll @@ -29,8 +29,8 @@ define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_iequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_iequi_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -91,8 +91,8 @@ define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_iequi_sext_z_store(i32 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesiequs.ll b/test/CodeGen/PowerPC/testComparesiequs.ll index b72943893e9..11c393eb363 100644 --- a/test/CodeGen/PowerPC/testComparesiequs.ll +++ b/test/CodeGen/PowerPC/testComparesiequs.ll @@ -29,8 +29,8 @@ define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -56,8 +56,8 @@ define signext i32 @test_iequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_iequs_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -91,8 +91,8 @@ define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_iequs_sext_z_store(i16 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesigesc.ll b/test/CodeGen/PowerPC/testComparesigesc.ll new file mode 100644 index 00000000000..cd3c99fdcc0 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesc.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i8 0, align 1 + +define signext i32 @test_igesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_igesc_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigesi.ll b/test/CodeGen/PowerPC/testComparesigesi.ll new file mode 100644 index 00000000000..57f4c0f33ea --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define signext i32 @test_igesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_igesi_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesigess.ll b/test/CodeGen/PowerPC/testComparesigess.ll new file mode 100644 index 00000000000..91594a0430c --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesigess.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i16 0, align 2 + +define signext i32 @test_igess(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_igess_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_igess_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesilesc.ll b/test/CodeGen/PowerPC/testComparesilesc.ll new file mode 100644 index 00000000000..802424802bc --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesilesc.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i8 0, align 1 + +define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_ilesc_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesilesi.ll b/test/CodeGen/PowerPC/testComparesilesi.ll new file mode 100644 index 00000000000..163a31330b4 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesilesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_ilesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_ilesi_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesiless.ll b/test/CodeGen/PowerPC/testComparesiless.ll new file mode 100644 index 00000000000..61e3b37d8c4 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesiless.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i16 0, align 2 + +define signext i32 @test_iless(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv2 = zext i1 %cmp to i32 + ret i32 %conv2 +} + +define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %sub = sext i1 %cmp to i32 + ret i32 %sub +} + +define void @test_iless_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_iless_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testCompareslleqsc.ll b/test/CodeGen/PowerPC/testCompareslleqsc.ll index 56af1282793..96665e6201c 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsc.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsc.ll @@ -29,8 +29,8 @@ define i64 @test_lleqsc_sext(i8 signext %a, i8 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -56,8 +56,8 @@ define i64 @test_lleqsc_sext_z(i8 signext %a) { ; CHECK-LABEL: test_lleqsc_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -91,8 +91,8 @@ define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_lleqsc_sext_z_store(i8 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testCompareslleqsi.ll b/test/CodeGen/PowerPC/testCompareslleqsi.ll index 90cf2c85888..8bec2a0f5e9 100644 --- a/test/CodeGen/PowerPC/testCompareslleqsi.ll +++ b/test/CodeGen/PowerPC/testCompareslleqsi.ll @@ -28,8 +28,8 @@ define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -55,8 +55,8 @@ define i64 @test_lleqsi_sext_z(i32 signext %a) { ; CHECK-LABEL: test_lleqsi_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -90,8 +90,8 @@ define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -126,8 +126,8 @@ define void @test_lleqsi_sext_z_store(i32 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testCompareslleqss.ll b/test/CodeGen/PowerPC/testCompareslleqss.ll index df60a6ccc00..34c6e014bc5 100644 --- a/test/CodeGen/PowerPC/testCompareslleqss.ll +++ b/test/CodeGen/PowerPC/testCompareslleqss.ll @@ -28,8 +28,8 @@ define i64 @test_lleqss_sext(i16 signext %a, i16 signext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -55,8 +55,8 @@ define i64 @test_lleqss_sext_z(i16 signext %a) { ; CHECK-LABEL: test_lleqss_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -90,8 +90,8 @@ define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -125,8 +125,8 @@ define void @test_lleqss_sext_z_store(i16 signext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequc.ll b/test/CodeGen/PowerPC/testComparesllequc.ll index 24882576129..c2d8c3c15e8 100644 --- a/test/CodeGen/PowerPC/testComparesllequc.ll +++ b/test/CodeGen/PowerPC/testComparesllequc.ll @@ -28,8 +28,8 @@ define i64 @test_llequc_sext(i8 zeroext %a, i8 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, %b @@ -55,8 +55,8 @@ define i64 @test_llequc_sext_z(i8 zeroext %a) { ; CHECK-LABEL: test_llequc_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i8 %a, 0 @@ -90,8 +90,8 @@ define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -125,8 +125,8 @@ define void @test_llequc_sext_z_store(i8 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequi.ll b/test/CodeGen/PowerPC/testComparesllequi.ll index 2342d80d94e..e155bf1ab2e 100644 --- a/test/CodeGen/PowerPC/testComparesllequi.ll +++ b/test/CodeGen/PowerPC/testComparesllequi.ll @@ -28,8 +28,8 @@ define i64 @test_llequi_sext(i32 zeroext %a, i32 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, %b @@ -55,8 +55,8 @@ define i64 @test_llequi_sext_z(i32 zeroext %a) { ; CHECK-LABEL: test_llequi_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i32 %a, 0 @@ -90,8 +90,8 @@ define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -125,8 +125,8 @@ define void @test_llequi_sext_z_store(i32 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllequs.ll b/test/CodeGen/PowerPC/testComparesllequs.ll index e79a974c06f..97326487492 100644 --- a/test/CodeGen/PowerPC/testComparesllequs.ll +++ b/test/CodeGen/PowerPC/testComparesllequs.ll @@ -28,8 +28,8 @@ define i64 @test_llequs_sext(i16 zeroext %a, i16 zeroext %b) { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, %b @@ -55,8 +55,8 @@ define i64 @test_llequs_sext_z(i16 zeroext %a) { ; CHECK-LABEL: test_llequs_sext_z: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: cntlzw r3, r3 -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr entry: %cmp = icmp eq i16 %a, 0 @@ -90,8 +90,8 @@ define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) { ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: @@ -125,8 +125,8 @@ define void @test_llequs_sext_z_store(i16 zeroext %a) { ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: rldicr r3, r3, 58, 0 -; CHECK-NEXT: sradi r3, r3, 63 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: blr entry: diff --git a/test/CodeGen/PowerPC/testComparesllgesc.ll b/test/CodeGen/PowerPC/testComparesllgesc.ll new file mode 100644 index 00000000000..3302fe04c46 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgesc.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i8 0, align 1 + +define i64 @test_llgesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llgesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_llgesc_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgesi.ll b/test/CodeGen/PowerPC/testComparesllgesi.ll new file mode 100644 index 00000000000..ba37281617a --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgesi.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i32 0, align 4 + +define i64 @test_llgesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_llgesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_llgesi_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllgess.ll b/test/CodeGen/PowerPC/testComparesllgess.ll new file mode 100644 index 00000000000..e6a51eb5eff --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllgess.ll @@ -0,0 +1,68 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +@glob = common local_unnamed_addr global i16 0, align 2 + +define i64 @test_llgess(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llgess_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llgess_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r3, r4 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sge i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} diff --git a/test/CodeGen/PowerPC/testCompareslllesc.ll b/test/CodeGen/PowerPC/testCompareslllesc.ll new file mode 100644 index 00000000000..5f08a992c46 --- /dev/null +++ b/test/CodeGen/PowerPC/testCompareslllesc.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i8 0, align 1 + +define i64 @test_lllesc(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_lllesc_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = zext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} + +define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { +; CHECK-LABEL: test_lllesc_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stb r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i8 %a, %b + %conv3 = sext i1 %cmp to i8 + store i8 %conv3, i8* @glob, align 1 + ret void +} diff --git a/test/CodeGen/PowerPC/testCompareslllesi.ll b/test/CodeGen/PowerPC/testCompareslllesi.ll new file mode 100644 index 00000000000..71972348312 --- /dev/null +++ b/test/CodeGen/PowerPC/testCompareslllesi.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i32 0, align 4 + +define i64 @test_lllesi(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv1 = sext i1 %cmp to i64 + ret i64 %conv1 +} + +define void @test_lllesi_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @glob, align 4 + ret void +} + +define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: test_lllesi_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: stw r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i32 %a, %b + %sub = sext i1 %cmp to i32 + store i32 %sub, i32* @glob, align 4 + ret void +} diff --git a/test/CodeGen/PowerPC/testComparesllless.ll b/test/CodeGen/PowerPC/testComparesllless.ll new file mode 100644 index 00000000000..20a92c7d491 --- /dev/null +++ b/test/CodeGen/PowerPC/testComparesllless.ll @@ -0,0 +1,69 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + +@glob = common local_unnamed_addr global i16 0, align 2 + +define i64 @test_llless(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i64 + ret i64 %conv3 +} + +define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_sext: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i64 + ret i64 %conv3 +} + +define void @test_llless_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: xori r3, r3, 1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = zext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} + +define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { +; CHECK-LABEL: test_llless_sext_store: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis r5, r2, .LC0@toc@ha +; CHECK-NEXT: sub r3, r4, r3 +; CHECK-NEXT: ld r12, .LC0@toc@l(r5) +; CHECK-NEXT: rldicl r3, r3, 1, 63 +; CHECK-NEXT: addi r3, r3, -1 +; CHECK-NEXT: sth r3, 0(r12) +; CHECK-NEXT: blr +entry: + %cmp = icmp sle i16 %a, %b + %conv3 = sext i1 %cmp to i16 + store i16 %conv3, i16* @glob, align 2 + ret void +} |