diff options
168 files changed, 50480 insertions, 14903 deletions
diff --git a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 7c70a7e3d0a..60dd8ebe448 100644 --- a/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -63,21 +63,25 @@ using namespace llvm; static cl::opt<bool> EnableFutureRegs("mfuture-regs", cl::desc("Enable future registers")); -static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis", -cl::desc("Warn for missing parenthesis around predicate registers"), -cl::init(true)); -static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis", -cl::desc("Error for missing parenthesis around predicate registers"), -cl::init(false)); -static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch", -cl::desc("Warn for mismatching a signed and unsigned value"), -cl::init(true)); -static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register", -cl::desc("Warn for register names that arent contigious"), -cl::init(true)); -static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register", -cl::desc("Error for register names that aren't contigious"), -cl::init(false)); +static cl::opt<bool> WarnMissingParenthesis( + "mwarn-missing-parenthesis", + cl::desc("Warn for missing parenthesis around predicate registers"), + cl::init(true)); +static cl::opt<bool> ErrorMissingParenthesis( + "merror-missing-parenthesis", + cl::desc("Error for missing parenthesis around predicate registers"), + cl::init(false)); +static cl::opt<bool> WarnSignedMismatch( + "mwarn-sign-mismatch", + cl::desc("Warn for mismatching a signed and unsigned value"), + cl::init(true)); +static cl::opt<bool> WarnNoncontigiousRegister( + "mwarn-noncontigious-register", + cl::desc("Warn for register names that arent contigious"), cl::init(true)); +static cl::opt<bool> ErrorNoncontigiousRegister( + "merror-noncontigious-register", + cl::desc("Error for register names that aren't contigious"), + cl::init(false)); namespace { @@ -123,9 +127,11 @@ class HexagonAsmParser : public MCTargetAsmParser { bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - uint64_t &ErrorInfo, bool MatchingInlineAsm) override; + uint64_t &ErrorInfo, + bool MatchingInlineAsm) override; - unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; + unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, + unsigned Kind) override; bool OutOfRange(SMLoc IDLoc, long long Val, long long Max); int processInstruction(MCInst &Inst, OperandVector const &Operands, SMLoc IDLoc); @@ -168,11 +174,10 @@ public: bool parseInstruction(OperandVector &Operands); bool implicitExpressionLocation(OperandVector &Operands); bool parseExpressionOrOperand(OperandVector &Operands); - bool parseExpression(MCExpr const *& Expr); + bool parseExpression(MCExpr const *&Expr); bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, - SMLoc NameLoc, OperandVector &Operands) override - { + SMLoc NameLoc, OperandVector &Operands) override { llvm_unreachable("Unimplemented"); } @@ -289,45 +294,67 @@ public: return false; } - bool isf32Ext() const { return false; } - bool iss32_0Imm() const { return CheckImmRange(32, 0, true, true, false); } + bool isa30_2Imm() const { return CheckImmRange(30, 2, true, true, true); } + bool isb30_2Imm() const { return CheckImmRange(30, 2, true, true, true); } + bool isb15_2Imm() const { return CheckImmRange(15, 2, true, true, false); } + bool isb13_2Imm() const { return CheckImmRange(13, 2, true, true, false); } + + bool ism32_0Imm() const { return true; } + + bool isf32Imm() const { return false; } + bool isf64Imm() const { return false; } + bool iss32_0Imm() const { return true; } + bool iss31_1Imm() const { return true; } + bool iss30_2Imm() const { return true; } + bool iss29_3Imm() const { return true; } bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); } + bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); } + bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); } + bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); } bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); } bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); } bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); } bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); } + bool iss6_3Imm() const { return CheckImmRange(6, 3, true, false, false); } bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); } bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); } bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); } bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); } bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); } + bool iss4_7Imm() const { return CheckImmRange(4, 0, true, false, false); } + bool iss3_7Imm() const { return CheckImmRange(3, 0, true, false, false); } bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); } bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); } bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); } - bool isu32_0Imm() const { return CheckImmRange(32, 0, false, true, false); } + bool isu32_0Imm() const { return true; } + bool isu31_1Imm() const { return true; } + bool isu30_2Imm() const { return true; } + bool isu29_3Imm() const { return true; } bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); } bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); } bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); } bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); } bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); } bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); } - bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } - bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } - bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); } bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); } bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); } bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); } bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } + bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } + bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } + bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); } + bool isu5_2Imm() const { return CheckImmRange(5, 2, false, false, false); } + bool isu5_3Imm() const { return CheckImmRange(5, 3, false, false, false); } bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); } + bool isu4_2Imm() const { return CheckImmRange(4, 2, false, false, false); } bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); } + bool isu3_1Imm() const { return CheckImmRange(3, 1, false, false, false); } bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); } bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); } - bool ism6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } - bool isn8_0Imm() const { return CheckImmRange(8, 0, false, false, false); } bool isn1Const() const { if (!isImm()) return false; @@ -336,35 +363,18 @@ public: return false; return Value == -1; } - - bool iss16_0Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); } - bool iss12_0Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); } - bool iss10_0Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); } - bool iss9_0Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); } - bool iss8_0Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); } - bool iss7_0Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); } - bool iss6_0Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); } - bool iss11_0Ext() const { + bool iss11_0Imm() const { return CheckImmRange(11 + 26, 0, true, true, true); } - bool iss11_1Ext() const { + bool iss11_1Imm() const { return CheckImmRange(11 + 26, 1, true, true, true); } - bool iss11_2Ext() const { + bool iss11_2Imm() const { return CheckImmRange(11 + 26, 2, true, true, true); } - bool iss11_3Ext() const { + bool iss11_3Imm() const { return CheckImmRange(11 + 26, 3, true, true, true); } - - bool isu7_0Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); } - bool isu8_0Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); } - bool isu9_0Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); } - bool isu10_0Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); } - bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } - bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); } - bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); } - bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); } bool isu32_0MustExt() const { return isImm(); } void addRegOperands(MCInst &Inst, unsigned N) const { @@ -392,174 +402,10 @@ public: Inst.addOperand(MCOperand::createExpr(Expr)); } - void addf32ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void adds32_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds23_2ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0Imm64Operands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds6_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_1ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_2ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_3ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds3_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - - void addu64_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu32_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu26_6ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_1ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_2ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu11_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu10_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu9_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu8_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu7_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_1ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_2ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu5_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu4_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu3_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu2_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu1_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void addm6_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addn8_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void adds16_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds12_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds10_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds9_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds6_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_1ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_2ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_3ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } void addn1ConstOperands(MCInst &Inst, unsigned N) const { addImmOperands(Inst, N); } - void addu7_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu8_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu9_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu10_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_1ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_2ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_3ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu32_0MustExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void adds4_6ImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = @@ -749,10 +595,6 @@ bool HexagonAsmParser::matchBundleOptions() { HexagonMCInstrInfo::setInnerLoop(MCB); else if (Option.compare_lower("endloop1") == 0) HexagonMCInstrInfo::setOuterLoop(MCB); - else if (Option.compare_lower("mem_noshuf") == 0) - HexagonMCInstrInfo::setMemReorderDisabled(MCB); - else if (Option.compare_lower("mem_shuf") == 0) - HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB); else return true; Lex(); @@ -770,8 +612,7 @@ void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) { int64_t Value (I.getImm()); NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( MCConstantExpr::create(Value, getContext()), getContext()))); - } - else { + } else { if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() && WarnSignedMismatch) Warning (MCI.getLoc(), "Signed/Unsigned mismatch"); diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index 3e2a8229797..fbce4bfea81 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -60,7 +60,7 @@ add_llvm_target(HexagonCodeGen RDFGraph.cpp RDFLiveness.cpp RDFRegisters.cpp - ) +) add_subdirectory(AsmParser) add_subdirectory(TargetInfo) diff --git a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 640a31bee4e..694da86b546 100644 --- a/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -57,11 +57,38 @@ public: ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override; - - void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; }; +namespace { + uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, + int64_t Value) { + MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + MCB, HexagonMCInstrInfo::bundleSize(MCB)); + if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) + return Value; + unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); + uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; + int64_t Bits; + bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); + assert(Success); (void)Success; + uint32_t Upper26 = static_cast<uint32_t>(Bits); + uint32_t Operand = Upper26 | Lower6; + return Operand; + } + HexagonDisassembler const &disassembler(void const *Decoder) { + return *static_cast<HexagonDisassembler const *>(Decoder); + } + template <size_t T> + void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { + HexagonDisassembler const &Disassembler = disassembler(Decoder); + int64_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, + SignExtend64<T>(tmp)); + int64_t Extended = SignExtend64<32>(FullValue); + HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); + } +} } // end anonymous namespace // Forward declare these because the auto-generated code will reference them. @@ -70,6 +97,10 @@ public: static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -79,6 +110,9 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus +DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -98,31 +132,10 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); -static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, - void const *Decoder); - -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os); - -static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); - static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); -static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); +static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder); static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, @@ -142,6 +155,7 @@ static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); +#include "HexagonDepDecoders.h" #include "HexagonGenDisassemblerTables.inc" static MCDisassembler *createHexagonDisassembler(const Target &T, @@ -175,20 +189,31 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Size += HEXAGON_INSTR_SIZE; Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); } - if(Result == MCDisassembler::Fail) + if (Result == MCDisassembler::Fail) return Result; - HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); - if(!Checker.check()) + if (Size > HEXAGON_MAX_PACKET_SIZE) + return MCDisassembler::Fail; + HexagonMCChecker Checker(*MCII, STI, MI, MI, *getContext().getRegisterInfo()); + if (!Checker.check()) return MCDisassembler::Fail; return MCDisassembler::Success; } -static HexagonDisassembler const &disassembler(void const *Decoder) { - return *static_cast<HexagonDisassembler const *>(Decoder); +namespace { +void adjustDuplex(MCInst &MI, MCContext &Context) { + switch (MI.getOpcode()) { + case Hexagon::SA1_setin1: + MI.insert(MI.begin() + 1, + MCOperand::createExpr(MCConstantExpr::create(-1, Context))); + break; + case Hexagon::SA1_dec: + MI.insert(MI.begin() + 2, + MCOperand::createExpr(MCConstantExpr::create(-1, Context))); + break; + default: + break; + } } - -static MCContext &contextFromDecoder(void const *Decoder) { - return disassembler(Decoder).getContext(); } DecodeStatus HexagonDisassembler::getSingleInstruction( @@ -196,8 +221,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( raw_ostream &os, raw_ostream &cs, bool &Complete) const { assert(Bytes.size() >= HEXAGON_INSTR_SIZE); - uint32_t Instruction = - (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); + uint32_t Instruction = support::endian::read32le(Bytes.data()); auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); if ((Instruction & HexagonII::INST_PARSE_MASK) == @@ -210,103 +234,92 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return DecodeStatus::Fail; } - DecodeStatus Result = DecodeStatus::Success; + MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + MCB, HexagonMCInstrInfo::bundleSize(MCB)); + + DecodeStatus Result = DecodeStatus::Fail; if ((Instruction & HexagonII::INST_PARSE_MASK) == HexagonII::INST_PARSE_DUPLEX) { - // Determine the instruction class of each instruction in the duplex. - unsigned duplexIClass, IClassLow, IClassHigh; - + unsigned duplexIClass; + uint8_t const *DecodeLow, *DecodeHigh; duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); switch (duplexIClass) { default: return MCDisassembler::Fail; case 0: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_L132; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 1: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 2: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 3: - IClassLow = HexagonII::HSIG_A; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_A32; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 4: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_L132; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 5: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 6: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 7: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 8: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 9: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 10: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_S1; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_S132; break; case 11: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S1; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_S132; break; case 12: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 13: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 14: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S2; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_S232; break; } - - // Set the MCInst to be a duplex instruction. Which one doesn't matter. - MI.setOpcode(Hexagon::DuplexIClass0); - - // Decode each instruction in the duplex. - // Create an MCInst for each instruction. - unsigned instLow = Instruction & 0x1fff; - unsigned instHigh = (Instruction >> 16) & 0x1fff; - unsigned opLow; - if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; - unsigned opHigh; - if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; + MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); MCInst *MILow = new (getContext()) MCInst; - MILow->setOpcode(opLow); MCInst *MIHigh = new (getContext()) MCInst; - MIHigh->setOpcode(opHigh); - addSubinstOperands(MILow, opLow, instLow); - addSubinstOperands(MIHigh, opHigh, instHigh); - // see ConvertToSubInst() in - // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp - - // Add the duplex instruction MCInsts as operands to the passed in MCInst. + Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, + this, STI); + if (Result != DecodeStatus::Success) + return DecodeStatus::Fail; + adjustDuplex(*MILow, getContext()); + Result = decodeInstruction( + DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); + if (Result != DecodeStatus::Success) + return DecodeStatus::Fail; + adjustDuplex(*MIHigh, getContext()); MCOperand OPLow = MCOperand::createInst(MILow); MCOperand OPHigh = MCOperand::createInst(MIHigh); MI.addOperand(OPLow); @@ -316,34 +329,23 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( if ((Instruction & HexagonII::INST_PARSE_MASK) == HexagonII::INST_PARSE_PACKET_END) Complete = true; - // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); - - // If a, "standard" insn isn't found check special cases. - if (MCDisassembler::Success != Result || - MI.getOpcode() == Hexagon::A4_ext) { - Result = decodeImmext(MI, Instruction, this); - if (MCDisassembler::Success != Result) { - Result = decodeSpecial(MI, Instruction); - } - } else { - // If the instruction is a compound instruction, register values will - // follow the duplex model, so the register values in the MCInst are - // incorrect. If the instruction is a compound, loop through the - // operands and change registers appropriately. - if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCJ) { - for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { - if (i->isReg()) { - unsigned reg = i->getReg() - Hexagon::R0; - i->setReg(getRegFromSubinstEncoding(reg)); - } - } - } - } + + if (Extender != nullptr) + Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, + Address, this, STI); + + if (Result != MCDisassembler::Success) + Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, + STI); + + if (Result != MCDisassembler::Success && + STI.getFeatureBits()[Hexagon::ExtensionHVX]) + Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, + Address, this, STI); + } - switch(MI.getOpcode()) { + switch (MI.getOpcode()) { case Hexagon::J4_cmpeqn1_f_jumpnv_nt: case Hexagon::J4_cmpeqn1_f_jumpnv_t: case Hexagon::J4_cmpeqn1_fp0_jump_nt: @@ -368,7 +370,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( case Hexagon::J4_cmpgtn1_tp0_jump_t: case Hexagon::J4_cmpgtn1_tp1_jump_nt: case Hexagon::J4_cmpgtn1_tp1_jump_t: - MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); + MI.insert(MI.begin() + 1, + MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); break; default: break; @@ -423,13 +426,10 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return MCDisassembler::Fail; } - adjustExtendedInstructions(MI, MCB); - MCInst const *Extender = - HexagonMCInstrInfo::extenderForIndex(MCB, - HexagonMCInstrInfo::bundleSize(MCB)); - if(Extender != nullptr) { - MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? - *MI.getOperand(1).getInst() : MI; + if (Extender != nullptr) { + MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) + ? *MI.getOperand(1).getInst() + : MI; if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && !HexagonMCInstrInfo::isExtended(*MCII, Inst)) return MCDisassembler::Fail; @@ -437,68 +437,6 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return Result; } -void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, - MCInst const &MCB) const { - if (!HexagonMCInstrInfo::hasExtenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB))) { - unsigned opcode; - // This code is used by the disassembler to disambiguate between GP - // relative and absolute addressing instructions since they both have - // same encoding bits. However, an absolute addressing instruction must - // follow an immediate extender. Disassembler alwaus select absolute - // addressing instructions first and uses this code to change them into - // GP relative instruction in the absence of the corresponding immediate - // extender. - switch (MCI.getOpcode()) { - case Hexagon::PS_storerbabs: - opcode = Hexagon::S2_storerbgp; - break; - case Hexagon::PS_storerhabs: - opcode = Hexagon::S2_storerhgp; - break; - case Hexagon::PS_storerfabs: - opcode = Hexagon::S2_storerfgp; - break; - case Hexagon::PS_storeriabs: - opcode = Hexagon::S2_storerigp; - break; - case Hexagon::PS_storerbnewabs: - opcode = Hexagon::S2_storerbnewgp; - break; - case Hexagon::PS_storerhnewabs: - opcode = Hexagon::S2_storerhnewgp; - break; - case Hexagon::PS_storerinewabs: - opcode = Hexagon::S2_storerinewgp; - break; - case Hexagon::PS_storerdabs: - opcode = Hexagon::S2_storerdgp; - break; - case Hexagon::PS_loadrbabs: - opcode = Hexagon::L2_loadrbgp; - break; - case Hexagon::PS_loadrubabs: - opcode = Hexagon::L2_loadrubgp; - break; - case Hexagon::PS_loadrhabs: - opcode = Hexagon::L2_loadrhgp; - break; - case Hexagon::PS_loadruhabs: - opcode = Hexagon::L2_loadruhgp; - break; - case Hexagon::PS_loadriabs: - opcode = Hexagon::L2_loadrigp; - break; - case Hexagon::PS_loadrdabs: - opcode = Hexagon::L2_loadrdgp; - break; - default: - opcode = MCI.getOpcode(); - } - MCI.setOpcode(opcode); - } -} - static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef<MCPhysReg> Table) { if (RegNo < Table.size()) { @@ -530,6 +468,20 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); } +static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + static const MCPhysReg GeneralSubRegDecoderTable[] = { + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, + Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, + Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, + }; + + return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); +} + static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { @@ -557,6 +509,15 @@ static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); } +static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( + MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { + static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; + + return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); +} + static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { @@ -591,10 +552,12 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg CtrlRegDecoderTable[] = { - Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, - Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, - Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, - Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC + Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, + Hexagon::LC1, Hexagon::P3_0, Hexagon::C5, + Hexagon::C6, Hexagon::C7, Hexagon::USR, + Hexagon::PC, Hexagon::UGP, Hexagon::GP, + Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, + Hexagon::UPC }; if (RegNo >= array_lengthof(CtrlRegDecoderTable)) @@ -612,13 +575,12 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { static const MCPhysReg CtrlReg64DecoderTable[] = { - Hexagon::C1_0, Hexagon::NoRegister, - Hexagon::C3_2, Hexagon::NoRegister, - Hexagon::C7_6, Hexagon::NoRegister, - Hexagon::C9_8, Hexagon::NoRegister, - Hexagon::C11_10, Hexagon::NoRegister, - Hexagon::CS, Hexagon::NoRegister, - Hexagon::UPC, Hexagon::NoRegister + Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2, + Hexagon::NoRegister, + Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8, + Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister, + Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC, + Hexagon::NoRegister }; if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) @@ -650,123 +612,17 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, - int64_t Value) { - MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB)); - if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) - return Value; - unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); - uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; - int64_t Bits; - bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); - assert(Success);(void)Success; - uint32_t Upper26 = static_cast<uint32_t>(Bits); - uint32_t Operand = Upper26 | Lower6; - return Operand; -} - -template <size_t T> -static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { - HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, SignExtend64<T>(tmp)); - int64_t Extended = SignExtend64<32>(FullValue); - HexagonMCInstrInfo::addConstant(MI, Extended, - Disassembler.getContext()); -} - static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, tmp); + int64_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); assert(FullValue >= 0 && "Negative in unsigned decoder"); HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); return MCDisassembler::Success; } -static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<16>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<12>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<11>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); - return MCDisassembler::Success; -} - -static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<13>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<14>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<10>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, - const void *Decoder) { - signedDecoder<8>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<4>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<5>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<7>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder) { signedDecoder<10>(MI, tmp, Decoder); @@ -779,6 +635,15 @@ static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, return MCDisassembler::Success; } +static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder) { + HexagonDisassembler const &Disassembler = disassembler(Decoder); + unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); + tmp = SignExtend64(tmp, Bits); + signedDecoder<32>(MI, tmp, Decoder); + return MCDisassembler::Success; +} + // custom decoder for various jump/call immediates static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder) { @@ -787,838 +652,13 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, // r13_2 is not extendable, so if there are no extent bits, it's r13_2 if (Bits == 0) Bits = 15; - uint32_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, SignExtend64(tmp, Bits)); + uint32_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, + SignExtend64(tmp, Bits)); int64_t Extended = SignExtend64<32>(FullValue) + Address; - if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, - 0, 4)) + if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); return MCDisassembler::Success; } -// Addressing mode dependent load store opcode map. -// - If an insn is preceded by an extender the address is absolute. -// - memw(##symbol) = r0 -// - If an insn is not preceded by an extender the address is GP relative. -// - memw(gp + #symbol) = r0 -// Please note that the instructions must be ordered in the descending order -// of their opcode. -// HexagonII::INST_ICLASS_ST -static const unsigned int StoreConditionalOpcodeData[][2] = { - {S4_pstorerdfnew_abs, 0xafc02084}, - {S4_pstorerdtnew_abs, 0xafc02080}, - {S4_pstorerdf_abs, 0xafc00084}, - {S4_pstorerdt_abs, 0xafc00080}, - {S4_pstorerinewfnew_abs, 0xafa03084}, - {S4_pstorerinewtnew_abs, 0xafa03080}, - {S4_pstorerhnewfnew_abs, 0xafa02884}, - {S4_pstorerhnewtnew_abs, 0xafa02880}, - {S4_pstorerbnewfnew_abs, 0xafa02084}, - {S4_pstorerbnewtnew_abs, 0xafa02080}, - {S4_pstorerinewf_abs, 0xafa01084}, - {S4_pstorerinewt_abs, 0xafa01080}, - {S4_pstorerhnewf_abs, 0xafa00884}, - {S4_pstorerhnewt_abs, 0xafa00880}, - {S4_pstorerbnewf_abs, 0xafa00084}, - {S4_pstorerbnewt_abs, 0xafa00080}, - {S4_pstorerifnew_abs, 0xaf802084}, - {S4_pstoreritnew_abs, 0xaf802080}, - {S4_pstorerif_abs, 0xaf800084}, - {S4_pstorerit_abs, 0xaf800080}, - {S4_pstorerhfnew_abs, 0xaf402084}, - {S4_pstorerhtnew_abs, 0xaf402080}, - {S4_pstorerhf_abs, 0xaf400084}, - {S4_pstorerht_abs, 0xaf400080}, - {S4_pstorerbfnew_abs, 0xaf002084}, - {S4_pstorerbtnew_abs, 0xaf002080}, - {S4_pstorerbf_abs, 0xaf000084}, - {S4_pstorerbt_abs, 0xaf000080}}; -// HexagonII::INST_ICLASS_LD - -// HexagonII::INST_ICLASS_LD_ST_2 -static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000}, - {PS_loadriabs, 0x49800000}, - {PS_loadruhabs, 0x49600000}, - {PS_loadrhabs, 0x49400000}, - {PS_loadrubabs, 0x49200000}, - {PS_loadrbabs, 0x49000000}, - {PS_storerdabs, 0x48c00000}, - {PS_storerinewabs, 0x48a01000}, - {PS_storerhnewabs, 0x48a00800}, - {PS_storerbnewabs, 0x48a00000}, - {PS_storeriabs, 0x48800000}, - {PS_storerfabs, 0x48600000}, - {PS_storerhabs, 0x48400000}, - {PS_storerbabs, 0x48000000}}; -static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); -static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); - -static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { - unsigned MachineOpcode = 0; - unsigned LLVMOpcode = 0; - - if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { - for (size_t i = 0; i < NumCondS; ++i) { - if ((insn & StoreConditionalOpcodeData[i][1]) == - StoreConditionalOpcodeData[i][1]) { - MachineOpcode = StoreConditionalOpcodeData[i][1]; - LLVMOpcode = StoreConditionalOpcodeData[i][0]; - break; - } - } - } - if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { - for (size_t i = 0; i < NumLS; ++i) { - if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { - MachineOpcode = LoadStoreOpcodeData[i][1]; - LLVMOpcode = LoadStoreOpcodeData[i][0]; - break; - } - } - } - - if (MachineOpcode) { - unsigned Value = 0; - unsigned shift = 0; - MI.setOpcode(LLVMOpcode); - // Remove the parse bits from the insn. - insn &= ~HexagonII::INST_PARSE_MASK; - - switch (LLVMOpcode) { - default: - return MCDisassembler::Fail; - break; - - case Hexagon::S4_pstorerdf_abs: - case Hexagon::S4_pstorerdt_abs: - case Hexagon::S4_pstorerdfnew_abs: - case Hexagon::S4_pstorerdtnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Rtt - Value = (insn >> 8) & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::S4_pstorerbnewf_abs: - case Hexagon::S4_pstorerbnewt_abs: - case Hexagon::S4_pstorerbnewfnew_abs: - case Hexagon::S4_pstorerbnewtnew_abs: - case Hexagon::S4_pstorerhnewf_abs: - case Hexagon::S4_pstorerhnewt_abs: - case Hexagon::S4_pstorerhnewfnew_abs: - case Hexagon::S4_pstorerhnewtnew_abs: - case Hexagon::S4_pstorerinewf_abs: - case Hexagon::S4_pstorerinewt_abs: - case Hexagon::S4_pstorerinewfnew_abs: - case Hexagon::S4_pstorerinewtnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Nt - Value = (insn >> 8) & UINT64_C(7); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::S4_pstorerbf_abs: - case Hexagon::S4_pstorerbt_abs: - case Hexagon::S4_pstorerbfnew_abs: - case Hexagon::S4_pstorerbtnew_abs: - case Hexagon::S4_pstorerhf_abs: - case Hexagon::S4_pstorerht_abs: - case Hexagon::S4_pstorerhfnew_abs: - case Hexagon::S4_pstorerhtnew_abs: - case Hexagon::S4_pstorerif_abs: - case Hexagon::S4_pstorerit_abs: - case Hexagon::S4_pstorerifnew_abs: - case Hexagon::S4_pstoreritnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Rt - Value = (insn >> 8) & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::L4_ploadrdf_abs: - case Hexagon::L4_ploadrdt_abs: - case Hexagon::L4_ploadrdfnew_abs: - case Hexagon::L4_ploadrdtnew_abs: - // op: Rdd - Value = insn & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - // op: Pt - Value = ((insn >> 9) & UINT64_C(3)); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = ((insn >> 15) & UINT64_C(62)); - Value |= ((insn >> 8) & UINT64_C(1)); - MI.addOperand(MCOperand::createImm(Value)); - break; - - case Hexagon::L4_ploadrbf_abs: - case Hexagon::L4_ploadrbt_abs: - case Hexagon::L4_ploadrbfnew_abs: - case Hexagon::L4_ploadrbtnew_abs: - case Hexagon::L4_ploadrhf_abs: - case Hexagon::L4_ploadrht_abs: - case Hexagon::L4_ploadrhfnew_abs: - case Hexagon::L4_ploadrhtnew_abs: - case Hexagon::L4_ploadrubf_abs: - case Hexagon::L4_ploadrubt_abs: - case Hexagon::L4_ploadrubfnew_abs: - case Hexagon::L4_ploadrubtnew_abs: - case Hexagon::L4_ploadruhf_abs: - case Hexagon::L4_ploadruht_abs: - case Hexagon::L4_ploadruhfnew_abs: - case Hexagon::L4_ploadruhtnew_abs: - case Hexagon::L4_ploadrif_abs: - case Hexagon::L4_ploadrit_abs: - case Hexagon::L4_ploadrifnew_abs: - case Hexagon::L4_ploadritnew_abs: - // op: Rd - Value = insn & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - // op: Pt - Value = (insn >> 9) & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 15) & UINT64_C(62); - Value |= (insn >> 8) & UINT64_C(1); - MI.addOperand(MCOperand::createImm(Value)); - break; - - // op: g16_2 - case (Hexagon::PS_loadriabs): - ++shift; - // op: g16_1 - case Hexagon::PS_loadrhabs: - case Hexagon::PS_loadruhabs: - ++shift; - // op: g16_0 - case Hexagon::PS_loadrbabs: - case Hexagon::PS_loadrubabs: - // op: Rd - Value |= insn & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(511); - MI.addOperand(MCOperand::createImm(Value << shift)); - break; - - case Hexagon::PS_loadrdabs: - Value = insn & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(511); - MI.addOperand(MCOperand::createImm(Value << 3)); - break; - - case Hexagon::PS_storerdabs: - // op: g16_3 - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << 3)); - // op: Rtt - Value = (insn >> 8) & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - break; - - // op: g16_2 - case Hexagon::PS_storerinewabs: - ++shift; - // op: g16_1 - case Hexagon::PS_storerhnewabs: - ++shift; - // op: g16_0 - case Hexagon::PS_storerbnewabs: - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << shift)); - // op: Nt - Value = (insn >> 8) & UINT64_C(7); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - // op: g16_2 - case Hexagon::PS_storeriabs: - ++shift; - // op: g16_1 - case Hexagon::PS_storerhabs: - case Hexagon::PS_storerfabs: - ++shift; - // op: g16_0 - case Hexagon::PS_storerbabs: - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << shift)); - // op: Rt - Value = (insn >> 8) & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - } - return MCDisassembler::Success; - } - return MCDisassembler::Fail; -} - -static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, - void const *Decoder) { - // Instruction Class for a constant a extender: bits 31:28 = 0x0000 - if ((~insn & 0xf0000000) == 0xf0000000) { - unsigned Value; - // 27:16 High 12 bits of 26-bit extender. - Value = (insn & 0x0fff0000) << 4; - // 13:0 Low 14 bits of 26-bit extender. - Value |= ((insn & 0x3fff) << 6); - MI.setOpcode(Hexagon::A4_ext); - HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); - return MCDisassembler::Success; - } - return MCDisassembler::Fail; -} - -// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td -enum subInstBinaryValues { - SA1_addi_BITS = 0x0000, - SA1_addi_MASK = 0x1800, - SA1_addrx_BITS = 0x1800, - SA1_addrx_MASK = 0x1f00, - SA1_addsp_BITS = 0x0c00, - SA1_addsp_MASK = 0x1c00, - SA1_and1_BITS = 0x1200, - SA1_and1_MASK = 0x1f00, - SA1_clrf_BITS = 0x1a70, - SA1_clrf_MASK = 0x1e70, - SA1_clrfnew_BITS = 0x1a50, - SA1_clrfnew_MASK = 0x1e70, - SA1_clrt_BITS = 0x1a60, - SA1_clrt_MASK = 0x1e70, - SA1_clrtnew_BITS = 0x1a40, - SA1_clrtnew_MASK = 0x1e70, - SA1_cmpeqi_BITS = 0x1900, - SA1_cmpeqi_MASK = 0x1f00, - SA1_combine0i_BITS = 0x1c00, - SA1_combine0i_MASK = 0x1d18, - SA1_combine1i_BITS = 0x1c08, - SA1_combine1i_MASK = 0x1d18, - SA1_combine2i_BITS = 0x1c10, - SA1_combine2i_MASK = 0x1d18, - SA1_combine3i_BITS = 0x1c18, - SA1_combine3i_MASK = 0x1d18, - SA1_combinerz_BITS = 0x1d08, - SA1_combinerz_MASK = 0x1d08, - SA1_combinezr_BITS = 0x1d00, - SA1_combinezr_MASK = 0x1d08, - SA1_dec_BITS = 0x1300, - SA1_dec_MASK = 0x1f00, - SA1_inc_BITS = 0x1100, - SA1_inc_MASK = 0x1f00, - SA1_seti_BITS = 0x0800, - SA1_seti_MASK = 0x1c00, - SA1_setin1_BITS = 0x1a00, - SA1_setin1_MASK = 0x1e40, - SA1_sxtb_BITS = 0x1500, - SA1_sxtb_MASK = 0x1f00, - SA1_sxth_BITS = 0x1400, - SA1_sxth_MASK = 0x1f00, - SA1_tfr_BITS = 0x1000, - SA1_tfr_MASK = 0x1f00, - SA1_zxtb_BITS = 0x1700, - SA1_zxtb_MASK = 0x1f00, - SA1_zxth_BITS = 0x1600, - SA1_zxth_MASK = 0x1f00, - SL1_loadri_io_BITS = 0x0000, - SL1_loadri_io_MASK = 0x1000, - SL1_loadrub_io_BITS = 0x1000, - SL1_loadrub_io_MASK = 0x1000, - SL2_deallocframe_BITS = 0x1f00, - SL2_deallocframe_MASK = 0x1fc0, - SL2_jumpr31_BITS = 0x1fc0, - SL2_jumpr31_MASK = 0x1fc4, - SL2_jumpr31_f_BITS = 0x1fc5, - SL2_jumpr31_f_MASK = 0x1fc7, - SL2_jumpr31_fnew_BITS = 0x1fc7, - SL2_jumpr31_fnew_MASK = 0x1fc7, - SL2_jumpr31_t_BITS = 0x1fc4, - SL2_jumpr31_t_MASK = 0x1fc7, - SL2_jumpr31_tnew_BITS = 0x1fc6, - SL2_jumpr31_tnew_MASK = 0x1fc7, - SL2_loadrb_io_BITS = 0x1000, - SL2_loadrb_io_MASK = 0x1800, - SL2_loadrd_sp_BITS = 0x1e00, - SL2_loadrd_sp_MASK = 0x1f00, - SL2_loadrh_io_BITS = 0x0000, - SL2_loadrh_io_MASK = 0x1800, - SL2_loadri_sp_BITS = 0x1c00, - SL2_loadri_sp_MASK = 0x1e00, - SL2_loadruh_io_BITS = 0x0800, - SL2_loadruh_io_MASK = 0x1800, - SL2_return_BITS = 0x1f40, - SL2_return_MASK = 0x1fc4, - SL2_return_f_BITS = 0x1f45, - SL2_return_f_MASK = 0x1fc7, - SL2_return_fnew_BITS = 0x1f47, - SL2_return_fnew_MASK = 0x1fc7, - SL2_return_t_BITS = 0x1f44, - SL2_return_t_MASK = 0x1fc7, - SL2_return_tnew_BITS = 0x1f46, - SL2_return_tnew_MASK = 0x1fc7, - SS1_storeb_io_BITS = 0x1000, - SS1_storeb_io_MASK = 0x1000, - SS1_storew_io_BITS = 0x0000, - SS1_storew_io_MASK = 0x1000, - SS2_allocframe_BITS = 0x1c00, - SS2_allocframe_MASK = 0x1e00, - SS2_storebi0_BITS = 0x1200, - SS2_storebi0_MASK = 0x1f00, - SS2_storebi1_BITS = 0x1300, - SS2_storebi1_MASK = 0x1f00, - SS2_stored_sp_BITS = 0x0a00, - SS2_stored_sp_MASK = 0x1e00, - SS2_storeh_io_BITS = 0x0000, - SS2_storeh_io_MASK = 0x1800, - SS2_storew_sp_BITS = 0x0800, - SS2_storew_sp_MASK = 0x1e00, - SS2_storewi0_BITS = 0x1000, - SS2_storewi0_MASK = 0x1f00, - SS2_storewi1_BITS = 0x1100, - SS2_storewi1_MASK = 0x1f00 -}; - -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os) { - switch (IClass) { - case HexagonII::HSIG_L1: - if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS) - op = Hexagon::SL1_loadri_io; - else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS) - op = Hexagon::SL1_loadrub_io; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_L2: - if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS) - op = Hexagon::SL2_deallocframe; - else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS) - op = Hexagon::SL2_jumpr31; - else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS) - op = Hexagon::SL2_jumpr31_f; - else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS) - op = Hexagon::SL2_jumpr31_fnew; - else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS) - op = Hexagon::SL2_jumpr31_t; - else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS) - op = Hexagon::SL2_jumpr31_tnew; - else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS) - op = Hexagon::SL2_loadrb_io; - else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS) - op = Hexagon::SL2_loadrd_sp; - else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS) - op = Hexagon::SL2_loadrh_io; - else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS) - op = Hexagon::SL2_loadri_sp; - else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS) - op = Hexagon::SL2_loadruh_io; - else if ((inst & SL2_return_MASK) == SL2_return_BITS) - op = Hexagon::SL2_return; - else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS) - op = Hexagon::SL2_return_f; - else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS) - op = Hexagon::SL2_return_fnew; - else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS) - op = Hexagon::SL2_return_t; - else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS) - op = Hexagon::SL2_return_tnew; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_A: - if ((inst & SA1_addi_MASK) == SA1_addi_BITS) - op = Hexagon::SA1_addi; - else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS) - op = Hexagon::SA1_addrx; - else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS) - op = Hexagon::SA1_addsp; - else if ((inst & SA1_and1_MASK) == SA1_and1_BITS) - op = Hexagon::SA1_and1; - else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS) - op = Hexagon::SA1_clrf; - else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS) - op = Hexagon::SA1_clrfnew; - else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS) - op = Hexagon::SA1_clrt; - else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS) - op = Hexagon::SA1_clrtnew; - else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS) - op = Hexagon::SA1_cmpeqi; - else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS) - op = Hexagon::SA1_combine0i; - else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS) - op = Hexagon::SA1_combine1i; - else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS) - op = Hexagon::SA1_combine2i; - else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS) - op = Hexagon::SA1_combine3i; - else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS) - op = Hexagon::SA1_combinerz; - else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS) - op = Hexagon::SA1_combinezr; - else if ((inst & SA1_dec_MASK) == SA1_dec_BITS) - op = Hexagon::SA1_dec; - else if ((inst & SA1_inc_MASK) == SA1_inc_BITS) - op = Hexagon::SA1_inc; - else if ((inst & SA1_seti_MASK) == SA1_seti_BITS) - op = Hexagon::SA1_seti; - else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS) - op = Hexagon::SA1_setin1; - else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS) - op = Hexagon::SA1_sxtb; - else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS) - op = Hexagon::SA1_sxth; - else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS) - op = Hexagon::SA1_tfr; - else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS) - op = Hexagon::SA1_zxtb; - else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS) - op = Hexagon::SA1_zxth; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S1: - if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS) - op = Hexagon::SS1_storeb_io; - else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS) - op = Hexagon::SS1_storew_io; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S2: - if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS) - op = Hexagon::SS2_allocframe; - else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS) - op = Hexagon::SS2_storebi0; - else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS) - op = Hexagon::SS2_storebi1; - else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS) - op = Hexagon::SS2_stored_sp; - else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS) - op = Hexagon::SS2_storeh_io; - else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS) - op = Hexagon::SS2_storew_sp; - else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS) - op = Hexagon::SS2_storewi0; - else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS) - op = Hexagon::SS2_storewi1; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - default: - os << "<unknown>"; - return MCDisassembler::Fail; - } - return MCDisassembler::Success; -} - -static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { - if (encoded_reg < 8) - return Hexagon::R0 + encoded_reg; - else if (encoded_reg < 16) - return Hexagon::R0 + encoded_reg + 8; - - // patently false value - return Hexagon::NoRegister; -} - -static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { - if (encoded_dreg < 4) - return Hexagon::D0 + encoded_dreg; - else if (encoded_dreg < 8) - return Hexagon::D0 + encoded_dreg + 4; - - // patently false value - return Hexagon::NoRegister; -} -void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, - unsigned inst) const { - int64_t operand; - MCOperand Op; - switch (opcode) { - case Hexagon::SL2_deallocframe: - case Hexagon::SL2_jumpr31: - case Hexagon::SL2_jumpr31_f: - case Hexagon::SL2_jumpr31_fnew: - case Hexagon::SL2_jumpr31_t: - case Hexagon::SL2_jumpr31_tnew: - case Hexagon::SL2_return: - case Hexagon::SL2_return_f: - case Hexagon::SL2_return_fnew: - case Hexagon::SL2_return_t: - case Hexagon::SL2_return_tnew: - // no operands for these instructions - break; - case Hexagon::SS2_allocframe: - // u 8-4{5_3} - operand = ((inst & 0x1f0) >> 4) << 3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL1_loadri_io: - // Rd 3-0, Rs 7-4, u 11-8{4_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 6; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL1_loadrub_io: - // Rd 3-0, Rs 7-4, u 11-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrb_io: - // Rd 3-0, Rs 7-4, u 10-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x700) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrh_io: - case Hexagon::SL2_loadruh_io: - // Rd 3-0, Rs 7-4, u 10-8{3_1} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrd_sp: - // Rdd 2-0, u 7-3{5_3} - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x0f8) >> 3) << 3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadri_sp: - // Rd 3-0, u 8-4{5_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x1f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_addi: - // Rx 3-0 (x2), s7 10-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = SignExtend64<7>((inst & 0x7f0) >> 4); - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_addrx: - // Rx 3-0 (x2), Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SA1_and1: - case Hexagon::SA1_dec: - case Hexagon::SA1_inc: - case Hexagon::SA1_sxtb: - case Hexagon::SA1_sxth: - case Hexagon::SA1_tfr: - case Hexagon::SA1_zxtb: - case Hexagon::SA1_zxth: - // Rd 3-0, Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SA1_addsp: - // Rd 3-0, u 9-4{6_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x3f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_seti: - // Rd 3-0, u 9-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x3f0) >> 4; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_clrf: - case Hexagon::SA1_clrfnew: - case Hexagon::SA1_clrt: - case Hexagon::SA1_clrtnew: - case Hexagon::SA1_setin1: - // Rd 3-0 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - if (opcode == Hexagon::SA1_setin1) - break; - MI->addOperand(MCOperand::createReg(Hexagon::P0)); - break; - case Hexagon::SA1_cmpeqi: - // Rs 7-4, u 1-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0x3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_combine0i: - case Hexagon::SA1_combine1i: - case Hexagon::SA1_combine2i: - case Hexagon::SA1_combine3i: - // Rdd 2-0, u 6-5 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x060) >> 5; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_combinerz: - case Hexagon::SA1_combinezr: - // Rdd 2-0, Rs 7-4 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS1_storeb_io: - // Rs 7-4, u 11-8, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS1_storew_io: - // Rs 7-4, u 11-8{4_2}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0xf00) >> 8) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storebi0: - case Hexagon::SS2_storebi1: - // Rs 7-4, u 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0xf; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SS2_storewi0: - case Hexagon::SS2_storewi1: - // Rs 7-4, u 3-0{4_2} - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SS2_stored_sp: - // s 8-3{6_3}, Rtt 2-0 - operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storeh_io: - // Rs 7-4, u 10-8{3_1}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storew_sp: - // u 8-4{5_2}, Rd 3-0 - operand = ((inst & 0x1f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - default: - // don't crash with an invalid subinstruction - // llvm_unreachable("Invalid subinstruction in duplex instruction"); - break; - } -} diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index d310c0243e7..1566f27a3a4 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -22,11 +22,9 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // Hexagon Architectures -def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; -def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; -def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">; -def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">; +include "HexagonDepArch.td" +// Hexagon ISA Extensions def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", "Hexagon HVX instructions">; def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", @@ -37,12 +35,7 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", //===----------------------------------------------------------------------===// // Hexagon Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def HasV5T : Predicate<"HST->hasV5TOps()">; -def NoV5T : Predicate<"!HST->hasV5TOps()">; -def HasV55T : Predicate<"HST->hasV55TOps()">, - AssemblerPredicate<"ArchV55">; -def HasV60T : Predicate<"HST->hasV60TOps()">, - AssemblerPredicate<"ArchV60">; + def UseMEMOP : Predicate<"HST->useMemOps()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, @@ -81,7 +74,7 @@ class IntrinsicsRel; def getPredOpcode : InstrMapping { let FilterClass = "PredRel"; // Instructions with the same BaseOpcode and isNVStore values form a row. - let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"]; + let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; // Instructions with the same predicate sense form a column. let ColFields = ["PredSense"]; // The key column is the unpredicated instructions. @@ -132,7 +125,7 @@ def getPredNewOpcode : InstrMapping { // def getPredOldOpcode : InstrMapping { let FilterClass = "PredNewRel"; - let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; + let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; let ColFields = ["PNewValue"]; let KeyCol = ["new"]; let ValueCols = [[""]]; @@ -249,8 +242,15 @@ def getRealHWInstr : InstrMapping { include "HexagonSchedule.td" include "HexagonRegisterInfo.td" include "HexagonCallingConv.td" -include "HexagonInstrInfo.td" +include "HexagonOperands.td" +include "HexagonDepOperands.td" +include "HexagonDepITypes.td" +include "HexagonInstrFormats.td" +include "HexagonDepInstrFormats.td" +include "HexagonDepInstrInfo.td" +include "HexagonPseudo.td" include "HexagonPatterns.td" +include "HexagonDepMappings.td" include "HexagonIntrinsics.td" include "HexagonIntrinsicsDerived.td" diff --git a/lib/Target/Hexagon/HexagonDepArch.h b/lib/Target/Hexagon/HexagonDepArch.h new file mode 100644 index 00000000000..82265535ce8 --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepArch.h @@ -0,0 +1,10 @@ +//===--- HexagonDepArch.h -------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +enum HexagonArchEnum { V4,V5,V55,V60 }; diff --git a/lib/Target/Hexagon/HexagonDepArch.td b/lib/Target/Hexagon/HexagonDepArch.td new file mode 100644 index 00000000000..d1c08453c25 --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepArch.td @@ -0,0 +1,17 @@ +//===--- HexagonDepArch.td ------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Enable Hexagon V60 architecture">; +def HasV60T : Predicate<"HST->hasV60TOps()">, AssemblerPredicate<"ArchV60">; +def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Enable Hexagon V55 architecture">; +def HasV55T : Predicate<"HST->hasV55TOps()">, AssemblerPredicate<"ArchV55">; +def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Enable Hexagon V4 architecture">; +def HasV4T : Predicate<"HST->hasV4TOps()">, AssemblerPredicate<"ArchV4">; +def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Enable Hexagon V5 architecture">; +def HasV5T : Predicate<"HST->hasV5TOps()">, AssemblerPredicate<"ArchV5">; diff --git a/lib/Target/Hexagon/HexagonDepDecoders.h b/lib/Target/Hexagon/HexagonDepDecoders.h new file mode 100644 index 00000000000..9cc0a10a595 --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepDecoders.h @@ -0,0 +1,59 @@ +//===--- HexagonDepDecoders.h ---------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<4>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<14>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<8>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<7>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<12>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<13>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<9>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<5>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} diff --git a/lib/Target/Hexagon/HexagonDepITypes.h b/lib/Target/Hexagon/HexagonDepITypes.h new file mode 100644 index 00000000000..e827c7ae79b --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepITypes.h @@ -0,0 +1,52 @@ +//===--- HexagonDepITypes.h -----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +namespace llvm { +namespace HexagonII { +enum Type { + TypeALU32_2op = 0, + TypeALU32_3op = 1, + TypeALU32_ADDI = 2, + TypeALU64 = 3, + TypeCJ = 4, + TypeCR = 7, + TypeCVI_HIST = 10, + TypeCVI_VA = 16, + TypeCVI_VA_DV = 17, + TypeCVI_VINLANESAT = 18, + TypeCVI_VM_CUR_LD = 19, + TypeCVI_VM_LD = 20, + TypeCVI_VM_NEW_ST = 21, + TypeCVI_VM_ST = 22, + TypeCVI_VM_STU = 23, + TypeCVI_VM_TMP_LD = 24, + TypeCVI_VM_VP_LDU = 25, + TypeCVI_VP = 26, + TypeCVI_VP_VS = 27, + TypeCVI_VS = 28, + TypeCVI_VX = 30, + TypeCVI_VX_DV = 31, + TypeDUPLEX = 32, + TypeENDLOOP = 33, + TypeEXTENDER = 34, + TypeJ = 35, + TypeLD = 36, + TypeM = 37, + TypeMAPPING = 38, + TypeNCJ = 39, + TypePSEUDO = 40, + TypeST = 41, + TypeSUBINSN = 42, + TypeS_2op = 43, + TypeS_3op = 44, + TypeV2LDST = 47, + TypeV4LDST = 48 +}; +} +} diff --git a/lib/Target/Hexagon/HexagonDepITypes.td b/lib/Target/Hexagon/HexagonDepITypes.td new file mode 100644 index 00000000000..00524e33b15 --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepITypes.td @@ -0,0 +1,47 @@ +//===--- HexagonDepITypes.td ----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class IType<bits<6> t> { bits<6> Value = t; } +def TypeALU32_2op : IType<0>; +def TypeALU32_3op : IType<1>; +def TypeALU32_ADDI : IType<2>; +def TypeALU64 : IType<3>; +def TypeCJ : IType<4>; +def TypeCR : IType<7>; +def TypeCVI_HIST : IType<10>; +def TypeCVI_VA : IType<16>; +def TypeCVI_VA_DV : IType<17>; +def TypeCVI_VINLANESAT : IType<18>; +def TypeCVI_VM_CUR_LD : IType<19>; +def TypeCVI_VM_LD : IType<20>; +def TypeCVI_VM_NEW_ST : IType<21>; +def TypeCVI_VM_ST : IType<22>; +def TypeCVI_VM_STU : IType<23>; +def TypeCVI_VM_TMP_LD : IType<24>; +def TypeCVI_VM_VP_LDU : IType<25>; +def TypeCVI_VP : IType<26>; +def TypeCVI_VP_VS : IType<27>; +def TypeCVI_VS : IType<28>; +def TypeCVI_VX : IType<30>; +def TypeCVI_VX_DV : IType<31>; +def TypeDUPLEX : IType<32>; +def TypeENDLOOP : IType<33>; +def TypeEXTENDER : IType<34>; +def TypeJ : IType<35>; +def TypeLD : IType<36>; +def TypeM : IType<37>; +def TypeMAPPING : IType<38>; +def TypeNCJ : IType<39>; +def TypePSEUDO : IType<40>; +def TypeST : IType<41>; +def TypeSUBINSN : IType<42>; +def TypeS_2op : IType<43>; +def TypeS_3op : IType<44>; +def TypeV2LDST : IType<47>; +def TypeV4LDST : IType<48>; diff --git a/lib/Target/Hexagon/HexagonDepInstrFormats.td b/lib/Target/Hexagon/HexagonDepInstrFormats.td new file mode 100644 index 00000000000..dfd86a28ded --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -0,0 +1,4248 @@ +//===--- HexagonDepInstrFormats.td ----------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class Enc_12122225 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qd8; + let Inst{2-0} = Qd8{2-0}; +} +class Enc_16626097 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_13397056 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7315939 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{24-22} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_605928 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; +} +class Enc_15275738 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12822813 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_10282127 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_14264243 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rt16; + let Inst{11-8} = Rt16{3-0}; +} +class Enc_6778937 : OpcodeHexagon { + bits <5> Rxx32; + let Inst{20-16} = Rxx32{4-0}; + bits <0> sgp10; +} +class Enc_5480539 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_11422009 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_16357011 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <5> Vt32; + let Inst{13-9} = Vt32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; +} +class Enc_4975051 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-5} = Ii{11-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_14786238 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_15472748 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6773159 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_12535811 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_14007201 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2577026 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_7305764 : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_11682941 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_16376009 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13249928 : OpcodeHexagon { + bits <9> Ii; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_1971351 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12373826 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; +} +class Enc_13715847 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_13303422 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14574598 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_13094118 : OpcodeHexagon { + bits <5> Css32; + let Inst{20-16} = Css32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4231995 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_844699 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; +} +class Enc_8752140 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7978128 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_10492541 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_0 : OpcodeHexagon { +} +class Enc_8868098 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10380392 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} +class Enc_15733946 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_738356 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_15578334 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14400220 : OpcodeHexagon { + bits <5> Ii; + let Inst{9-5} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_15194851 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_14172170 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_10065510 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14998517 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <3> n1; + let Inst{29-29} = n1{2-2}; + let Inst{26-25} = n1{1-0}; +} +class Enc_16657398 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_14620934 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_10075393 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_8638014 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13261538 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_8990840 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5974204 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_4711514 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_11492529 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9277990 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6690615 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_1220199 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_7785569 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_2880796 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_6858527 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_11863656 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_151014 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Px4; + let Inst{6-5} = Px4{1-0}; +} +class Enc_10333841 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_14044877 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13691337 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qx4; + let Inst{6-5} = Qx4{1-0}; +} +class Enc_3817033 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3540372 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5200852 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_15949334 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3831744 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8280533 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_10969213 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_3974695 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-4} = Ii{6-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_7255914 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7212930 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12781442 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_799555 : OpcodeHexagon { + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_11083408 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_900013 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9487067 : OpcodeHexagon { + bits <12> Ii; + let Inst{19-16} = Ii{11-8}; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16014536 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_12419313 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_5503430 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_14767681 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_9093094 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <2> Pu4; + let Inst{24-23} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11542684 : OpcodeHexagon { + bits <16> Ii; + let Inst{27-21} = Ii{15-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8877260 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_1737833 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_255516 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_10721363 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_7076358 : OpcodeHexagon { + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11930928 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2410156 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_6735062 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_7965855 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5202340 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vyy32; + let Inst{4-0} = Vyy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10568534 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16730127 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11224149 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_9772987 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_9238139 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2082775 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_5790679 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_9305257 : OpcodeHexagon { + bits <5> Zu8; + let Inst{12-8} = Zu8{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_3735566 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12654528 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_15290236 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_11139981 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_15546666 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_486163 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2079016 : OpcodeHexagon { + bits <2> Ii; + let Inst{1-0} = Ii{1-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_10095813 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_13133322 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_9422954 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_10642833 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14989332 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_10263630 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_13937564 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_7171569 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_2702036 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_1928953 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_5853469 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_7692963 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_15140689 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_748676 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_3372766 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7900405 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11930027 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_971574 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{23-23} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_13453446 : OpcodeHexagon { + bits <24> Ii; + let Inst{24-16} = Ii{23-15}; + let Inst{13-1} = Ii{14-2}; +} +class Enc_6356866 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_16246706 : OpcodeHexagon { + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_5326450 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11687333 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2771456 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11282123 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_518319 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16104442 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_7912540 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_15560488 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7581852 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_10030031 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3915770 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4075554 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11326438 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4050532 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_14461004 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13344657 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13114546 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_14530015 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-23} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_5967898 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_15450971 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_15536400 : OpcodeHexagon { + bits <6> Ii; + let Inst{3-0} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_1291652 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; +} +class Enc_5636753 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; +} +class Enc_5757366 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_9752128 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13618890 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_5890213 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_5582416 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_13536408 : OpcodeHexagon { + bits <4> Ii; + let Inst{3-0} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_9773189 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rxx32; + let Inst{12-8} = Rxx32{4-0}; +} +class Enc_2152247 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_12848507 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_16279406 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_1734121 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_766909 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_4527648 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8849208 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_9894557 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4109168 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_14560494 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9773167 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_1898420 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_11498120 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_15459921 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10058269 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_10197700 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_12608570 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4804090 : OpcodeHexagon { + bits <6> Ss64; + let Inst{21-16} = Ss64{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14973146 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_5718302 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_2103742 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_7564330 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2176383 : OpcodeHexagon { + bits <6> Ii; + let Inst{9-4} = Ii{5-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_7736768 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13189194 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_5154851 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_1329520 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Cdd32; + let Inst{4-0} = Cdd32{4-0}; +} +class Enc_14057553 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9223889 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_10979813 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13490067 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_10076500 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_163381 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-5} = Ii{11-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_10328975 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_14939491 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_8891794 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_7723767 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2639299 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rd16; + let Inst{11-8} = Rd16{3-0}; +} +class Enc_11552785 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11849200 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_14868535 : OpcodeHexagon { + bits <17> Ii; + let Inst{23-22} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-1} = Ii{8-2}; + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; +} +class Enc_48594 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6608821 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_11049656 : OpcodeHexagon { + bits <9> Ii; + let Inst{13-13} = Ii{8-8}; + let Inst{7-3} = Ii{7-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_117962 : OpcodeHexagon { + bits <8> Ii; + let Inst{23-21} = Ii{7-5}; + let Inst{13-13} = Ii{4-4}; + let Inst{7-5} = Ii{3-1}; + let Inst{3-3} = Ii{0-0}; + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5900401 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_36641 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9626139 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11971407 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9852473 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_6495334 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_1186018 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_15999208 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_11477246 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_7971062 : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4327792 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_10326434 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1572239 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_6372758 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_15793331 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_11424254 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_4983213 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_16035138 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} +class Enc_8225953 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_4397470 : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_1004392 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_16319737 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_2296022 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14546668 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9664427 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qss8; + let Inst{2-0} = Qss8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_877823 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_1589406 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6900405 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14150875 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-22} = n1{3-0}; +} +class Enc_15707793 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; +} +class Enc_14689096 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_9915754 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7470998 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_11471622 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_14363183 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_15816255 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5321335 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <4> Vdd16; + let Inst{7-4} = Vdd16{3-0}; +} +class Enc_12702821 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_449439 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_2054304 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <6> Sd64; + let Inst{5-0} = Sd64{5-0}; +} +class Enc_236434 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_5598813 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8409782 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_15182416 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4501395 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6039436 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{2-0} = Qtt8{2-0}; + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_476163 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_11281763 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9929262 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; +} +class Enc_13174858 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8437395 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_16578332 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12829314 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_9744403 : OpcodeHexagon { + bits <5> Vu32; + let Inst{13-9} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10968391 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <7> n1; + let Inst{28-28} = n1{6-6}; + let Inst{25-22} = n1{5-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_64199 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_11039423 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6730375 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_16213761 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_13204995 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_13338314 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9920336 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_15380240 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_3296020 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2428539 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_10039393 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9372046 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_2901241 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_16145290 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_5555790 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13783220 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_12261611 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6135183 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_5523416 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13472494 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16303398 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3494181 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13983714 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_931653 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7622936 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_8773155 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_5401217 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <3> n1; + let Inst{28-28} = n1{2-2}; + let Inst{24-23} = n1{1-0}; +} +class Enc_6736678 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_3457570 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_3813442 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3135259 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_5486172 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_11081334 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; +} +class Enc_9470751 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_2683366 : OpcodeHexagon { + bits <3> Quu8; + let Inst{10-8} = Quu8{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} +class Enc_15830826 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; +} +class Enc_4967902 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_14287645 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8324216 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_913538 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_16311032 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_9864697 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <6> II; + let Inst{20-16} = II{5-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11205051 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_5611087 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10915758 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8943121 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_1539665 : OpcodeHexagon { + bits <5> Cs32; + let Inst{20-16} = Cs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8479583 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-23} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_313333 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_11544269 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_9018141 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Cd32; + let Inst{4-0} = Cd32{4-0}; +} +class Enc_6152036 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} +class Enc_1954437 : OpcodeHexagon { + bits <6> Sss64; + let Inst{21-16} = Sss64{5-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3742184 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1835415 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-5} = Ii{6-1}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1085466 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_13150110 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_6772177 : OpcodeHexagon { + bits <5> Zu8; + let Inst{12-8} = Zu8{4-0}; + bits <5> Zd8; + let Inst{4-0} = Zd8{4-0}; +} +class Enc_6616512 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_1886960 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2835415 : OpcodeHexagon { + bits <8> Ii; + let Inst{10-5} = Ii{7-2}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14024197 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_12297800 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_7254313 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_677558 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-5} = Ii{8-3}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_6223403 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_674613 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_16479122 : OpcodeHexagon { + bits <8> Ii; + let Inst{7-3} = Ii{7-3}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_11704059 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_9165078 : OpcodeHexagon { + bits <9> Ii; + let Inst{8-3} = Ii{8-3}; + bits <3> Rtt8; + let Inst{2-0} = Rtt8{2-0}; +} +class Enc_15376009 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8838398 : OpcodeHexagon { + bits <4> Ii; + let Inst{21-21} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_2328527 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_1451363 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_4030179 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_13770697 : OpcodeHexagon { + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ry32; + let Inst{12-8} = Ry32{4-0}; +} +class Enc_12212978 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12665927 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2082956 : OpcodeHexagon { + bits <32> Ii; + let Inst{27-16} = Ii{31-20}; + let Inst{13-0} = Ii{19-6}; +} +class Enc_220949 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_9939385 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <10> II; + let Inst{20-16} = II{9-5}; + let Inst{7-5} = II{4-2}; + let Inst{1-0} = II{1-0}; +} +class Enc_2117024 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8390029 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_10989558 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5972412 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_12851489 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9554661 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4202401 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6091631 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qt4; + let Inst{23-22} = Qt4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_10157519 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_4835423 : OpcodeHexagon { + bits <6> Ii; + let Inst{10-5} = Ii{5-0}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14046916 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_2921694 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8732960 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; +} +class Enc_5338033 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_6956613 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2153798 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_16210172 : OpcodeHexagon { + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_5023792 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_1244745 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_10002182 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_12492533 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1774350 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_2703240 : OpcodeHexagon { + bits <11> Ii; + let Inst{13-13} = Ii{10-10}; + let Inst{10-8} = Ii{9-7}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_6975103 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_9789480 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_12244921 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8674673 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-22} = n1{1-0}; +} +class Enc_8514936 : OpcodeHexagon { + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13455308 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_10188026 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_3158657 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10597934 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <2> n1; + let Inst{9-8} = n1{1-0}; +} +class Enc_10612292 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_5178985 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3967902 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_2462143 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9849208 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_12618352 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_7303598 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_13823098 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_16388420 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_8328140 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1793896 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4944558 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_13211717 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{20-16} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_8170340 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qdd8; + let Inst{2-0} = Qdd8{2-0}; +} +class Enc_14071773 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8605375 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12711252 : OpcodeHexagon { + bits <2> Pv4; + let Inst{9-8} = Pv4{1-0}; +} +class Enc_8202458 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8577055 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_1409050 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_7466005 : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2380082 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_10067774 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11000933 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_13201267 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_1989309 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_9082775 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8065534 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4631106 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pu4; + let Inst{7-6} = Pu4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_11065510 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8829170 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} +class Enc_6673186 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_8498433 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4395009 : OpcodeHexagon { + bits <7> Ii; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10926598 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_7606379 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8131399 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_11522288 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_114098 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_5654851 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_12023037 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_176263 : OpcodeHexagon { + bits <8> Ii; + let Inst{9-4} = Ii{7-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_6130414 : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{13-0} = Ii{13-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_631197 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_16214129 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_8333157 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4834775 : OpcodeHexagon { + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rd16; + let Inst{19-16} = Rd16{3-0}; +} +class Enc_16601956 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_15946706 : OpcodeHexagon { + bits <2> Ii; + let Inst{6-5} = Ii{1-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_6923828 : OpcodeHexagon { + bits <10> Ii; + let Inst{13-13} = Ii{9-9}; + let Inst{10-8} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_1332717 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1786883 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <6> Sdd64; + let Inst{5-0} = Sdd64{5-0}; +} +class Enc_14303394 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9282127 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_2813446 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_364753 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{23-23} = n1{0-0}; +} +class Enc_12477789 : OpcodeHexagon { + bits <15> Ii; + let Inst{21-21} = Ii{14-14}; + let Inst{13-13} = Ii{13-13}; + let Inst{11-1} = Ii{12-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_44555 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_8497723 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_4359901 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{22-22} = n1{0-0}; +} +class Enc_11271630 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10501894 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_9768377 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_16268019 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_8814718 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6212930 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5462762 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_6154421 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_8940892 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3531000 : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_14311138 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2216485 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12395768 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_11047413 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_1256611 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_7884306 : OpcodeHexagon { + bits <8> Ii; + let Inst{8-4} = Ii{7-3}; +} +class Enc_11244923 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8612939 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{22-22} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_16355964 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12616482 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_5915771 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_14459927 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7504828 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14209223 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3931661 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13606251 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_11475992 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_13133231 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9959498 : OpcodeHexagon { + bits <8> Ii; + let Inst{22-21} = Ii{7-6}; + let Inst{13-13} = Ii{5-5}; + let Inst{7-5} = Ii{4-2}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_8919369 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-23} = n1{3-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_2968094 : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_4813442 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4684887 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{25-23} = n1{2-0}; +} +class Enc_15606259 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_2268028 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{10-8} = Qtt8{2-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} +class Enc_13430430 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <3> Qxx8; + let Inst{2-0} = Qxx8{2-0}; +} +class Enc_13336212 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <1> n1; + let Inst{9-9} = n1{0-0}; +} +class Enc_15008287 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_4897205 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_8038806 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12669374 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_971347 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1997594 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11940513 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_2735552 : OpcodeHexagon { + bits <10> Ii; + let Inst{10-8} = Ii{9-7}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_16410950 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6226085 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14193700 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_15763937 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <6> n1; + let Inst{29-29} = n1{5-5}; + let Inst{26-25} = n1{4-3}; + let Inst{23-22} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_2492727 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_13425035 : OpcodeHexagon { + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4135257 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_14631806 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_12397062 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11959851 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} diff --git a/lib/Target/Hexagon/HexagonDepInstrInfo.td b/lib/Target/Hexagon/HexagonDepInstrInfo.td new file mode 100644 index 00000000000..7a2450b5c1a --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -0,0 +1,42279 @@ +//===--- HexagonDepInstrInfo.td -------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def A2_abs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = abs($Rs32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_absp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = abs($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000100; +} +def A2_abssat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = abs($Rs32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_add : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_addh_h16_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_sat_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_l16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_l16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_l16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_l16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,#$Ii)", +ALU32_ADDI_tc_1_SLOT0123, TypeALU32_ADDI>, Enc_11542684, PredNewRel, ImmRegRel { +let Inst{31-28} = 0b1011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isPredicable = 1; +let isAdd = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def A2_addp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let isCommutable = 1; +let isAdd = 1; +} +def A2_addpsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +let Defs = [USR_OVF]; +let isCommutable = 1; +} +def A2_addsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_addsp : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rs32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64> { +let isPseudo = 1; +} +def A2_addsph : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):raw:hi", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_addspl : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):raw:lo", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_and : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_and"; +let InputType = "reg"; +let BaseOpcode = "A2_and"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_andir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = and($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, ImmRegRel { +let Inst{31-22} = 0b0111011000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_and"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_andp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = and($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_aslh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000000; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +let isPredicable = 1; +} +def A2_asrh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000001; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +let isPredicable = 1; +} +def A2_combine_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.h,$Rs32.h)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.h,$Rs32.l)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011101; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.l,$Rs32.h)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011110; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.l,$Rs32.l)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011111; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, s8_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_14007201 { +let Inst{31-23} = 0b011111000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_combinew : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1997594, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110101000; +let InputType = "reg"; +let BaseOpcode = "A2_combinew"; +let isPredicable = 1; +} +def A2_max : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = max($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_maxp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = max($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_maxu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = maxu($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_maxup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = maxu($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_min : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = min($Rt32,$Rs32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101101; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_minp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = min($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_minu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = minu($Rt32,$Rs32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101101; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_minup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = minu($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_neg : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = neg($Rs32)", +PSEUDO, TypeALU32_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_negp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = neg($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000100; +} +def A2_negsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = neg($Rs32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_nop : HInst< +(outs), +(ins), +"nop", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b0111111100000000; +} +def A2_not : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = not($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_notp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = not($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000100; +} +def A2_or : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_or"; +let InputType = "reg"; +let BaseOpcode = "A2_or"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_orir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = or($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, ImmRegRel { +let Inst{31-22} = 0b0111011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_or"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_orp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = or($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_paddf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddifnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-23} = 0b011101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011101000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_padditnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-23} = 0b011101000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_pandf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_and"; +} +def A2_pandfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_and"; +} +def A2_pandt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_and"; +} +def A2_pandtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_and"; +} +def A2_porf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_or"; +} +def A2_porfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_or"; +} +def A2_port : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_or"; +} +def A2_portnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_or"; +} +def A2_psubf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sub"; +} +def A2_psubfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sub"; +} +def A2_psubt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sub"; +} +def A2_psubtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sub"; +} +def A2_pxorf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_xor"; +} +def A2_pxorfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_xor"; +} +def A2_pxort : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_xor"; +} +def A2_pxortnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_xor"; +} +def A2_roundsat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = round($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = sat($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sath : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sath($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satub($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satuh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satuh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_sub"; +let InputType = "reg"; +let BaseOpcode = "A2_sub"; +let isPredicable = 1; +} +def A2_subh_h16_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_sat_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_l16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_l16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_l16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_l16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = sub($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_subri : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = sub(#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, PredNewRel, ImmRegRel { +let Inst{31-22} = 0b0111011001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_sub"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_subsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_svaddh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vaddh($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svaddhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vaddh($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svadduhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vadduh($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svavgh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vavgh($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svavghs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vavgh($Rs32,$Rt32):rnd", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111001; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svnavgh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vnavgh($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_svsubh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubh($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_svsubhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubh($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110101; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_svsubuhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubuh($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110111; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_swiz : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = swiz($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_sxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000101; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +let isPredicable = 1; +} +def A2_sxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000111; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +let isPredicable = 1; +} +def A2_sxtw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = sxtw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100010; +} +def A2_tfr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPredicable = 1; +} +def A2_tfrcrr : HInst< +(outs IntRegs:$Rd32), +(ins CtrRegs:$Cs32), +"$Rd32 = $Cs32", +CR_tc_3x_SLOT3, TypeCR>, Enc_1539665 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01101010000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_tfrf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrih : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u16_0Imm:$Ii), +"$Rx32.h = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_6130414 { +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01110010; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def A2_tfril : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u16_0Imm:$Ii), +"$Rx32.l = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_6130414 { +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01110001; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def A2_tfrp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let BaseOpcode = "A2_tfrp"; +let isPredicable = 1; +let isPseudo = 1; +} +def A2_tfrpf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if (!$Pu4) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrpfnew : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if (!$Pu4.new) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrpi : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii), +"$Rdd32 = #$Ii", +ALU64_tc_1_SLOT23, TypeALU64> { +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isPseudo = 1; +} +def A2_tfrpt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if ($Pu4) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrptnew : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if ($Pu4.new) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrrcr : HInst< +(outs CtrRegs:$Cd32), +(ins IntRegs:$Rs32), +"$Cd32 = $Rs32", +CR_tc_3x_SLOT3, TypeCR>, Enc_9018141 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01100010001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_tfrsi : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii), +"$Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_7971062, PredNewRel, ImmRegRel { +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01111000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isPredicable = 1; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def A2_tfrt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vabsh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000010; +} +def A2_vabshsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsh($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000010; +let Defs = [USR_OVF]; +} +def A2_vabsw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsw($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000010; +} +def A2_vabswsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsw($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000010; +let Defs = [USR_OVF]; +} +def A2_vaddb_map : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddb($Rss32,$Rtt32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vaddh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddh($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vaddub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddub($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddubs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddub($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vadduhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vadduh($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vaddw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddws : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddw($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vavgh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavghcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32):crnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +let prefersSlot3 = 1; +} +def A2_vavghr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavgub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgub($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavgubr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgub($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguh($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavguwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguw($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavgw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavgwcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32):crnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +let prefersSlot3 = 1; +} +def A2_vavgwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vcmpbeq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b110000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpbgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b111000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpheq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmphgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmphgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpweq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpwgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpwgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vconj : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vconj($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000100; +let Defs = [USR_OVF]; +} +def A2_vmaxb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxb($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxub($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxuh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxuh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxuw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxuw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vmaxw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vminb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminb($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vminh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminub($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminuh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminuh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminuw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminuw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vnavgh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +} +def A2_vnavghcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavghr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavgw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +} +def A2_vnavgwcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavgwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vraddub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vraddub($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def A2_vraddub_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vraddub($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A2_vrsadub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrsadub($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def A2_vrsadub_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrsadub($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A2_vsubb_map : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vsubb($Rss32,$Rtt32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vsubh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubh($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsubhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubh($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubub($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsububs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubub($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubuhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubuh($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubw($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsubws : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubw($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_xor : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let BaseOpcode = "A2_xor"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_xorp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = xor($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_zxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +let isPredicable = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_zxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000110; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +let isPredicable = 1; +} +def A4_addp_c : HInst< +(outs DoubleRegs:$Rdd32, PredRegs:$Px4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), +"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_151014 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010110; +let isPredicateLate = 1; +let Constraints = "$Px4 = $Px4in"; +} +def A4_andn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = and($Rt32,~$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A4_andnp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = and($Rtt32,~$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +} +def A4_bitsplit : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = bitsplit($Rs32,$Rt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010100001; +} +def A4_bitspliti : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rdd32 = bitsplit($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_5654851 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +} +def A4_boundscheck : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rs32,$Rtt32)", +M_tc_3x_SLOT23, TypeALU64> { +let isPseudo = 1; +} +def A4_boundscheck_hi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_boundscheck_lo : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_cmpbeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.eq($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b110000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbeq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpbeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Pd4 = cmpb.eq($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101000; +let CextOpcode = "A4_cmpbeq"; +let InputType = "imm"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpbgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.gt($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbgt"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmpbgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s8_0Imm:$Ii), +"$Pd4 = cmpb.gt($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101001; +let CextOpcode = "A4_cmpbgt"; +let InputType = "imm"; +let isCompare = 1; +} +def A4_cmpbgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.gtu($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b111000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmpbgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmpb.gtu($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3531000, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011101010; +let CextOpcode = "A4_cmpbgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 0; +} +def A4_cmpheq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.eq($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpheq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpheqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmph.eq($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101000; +let CextOpcode = "A4_cmpheq"; +let InputType = "imm"; +let isCommutable = 1; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cmphgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.gt($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmphgt"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmphgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmph.gt($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101001; +let CextOpcode = "A4_cmphgt"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cmphgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.gtu($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmphgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmphgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmph.gtu($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3531000, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011101010; +let CextOpcode = "A4_cmphgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 0; +} +def A4_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9864697 { +let Inst{31-21} = 0b01111100100; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def A4_combineir : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rdd32 = combine(#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_2462143 { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011001; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_combineri : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rdd32 = combine($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_2462143 { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011000; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cround_ri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = cround($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_cround_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cround($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_ext : HInst< +(outs), +(ins u26_6Imm:$Ii), +"immext(#$Ii)", +EXTENDER_tc_1_SLOT0123, TypeEXTENDER>, Enc_2082956 { +let Inst{31-28} = 0b0000; +} +def A4_modwrapu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = modwrap($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_orn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = or($Rt32,~$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001101; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A4_ornp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = or($Rtt32,~$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +} +def A4_paslhf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +} +def A4_paslhfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_aslh"; +} +def A4_paslht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +} +def A4_paslhtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_aslh"; +} +def A4_pasrhf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrhfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrhtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_asrh"; +} +def A4_psxtbf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxthf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +} +def A4_psxthfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxth"; +} +def A4_psxtht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +} +def A4_psxthtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxth"; +} +def A4_pzxtbf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxthf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxthfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxtht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxthtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxth"; +} +def A4_rcmpeq : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeq"; +let InputType = "reg"; +let isCommutable = 1; +} +def A4_rcmpeqi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_16355964, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeqi"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_rcmpneq : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = !cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpneq"; +let InputType = "reg"; +let isCommutable = 1; +} +def A4_rcmpneqi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = !cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_16355964, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeqi"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_round_ri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = round($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_round_ri_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = round($Rs32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A4_round_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = round($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_round_rr_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = round($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A4_subp_c : HInst< +(outs DoubleRegs:$Rdd32, PredRegs:$Px4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), +"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_151014 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010111; +let isPredicateLate = 1; +let Constraints = "$Px4 = $Px4in"; +} +def A4_tfrcpp : HInst< +(outs DoubleRegs:$Rdd32), +(ins CtrRegs64:$Css32), +"$Rdd32 = $Css32", +CR_tc_3x_SLOT3, TypeCR>, Enc_13094118 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01101000000; +} +def A4_tfrpcp : HInst< +(outs CtrRegs64:$Cdd32), +(ins DoubleRegs:$Rss32), +"$Cdd32 = $Rss32", +CR_tc_3x_SLOT3, TypeCR>, Enc_1329520 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01100011001; +} +def A4_tlbmatch : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Pd4 = tlbmatch($Rss32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2492727 { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +let isPredicateLate = 1; +} +def A4_vcmpbeq_any : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_vcmpbeqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u8_0Imm:$Ii), +"$Pd4 = vcmpb.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmpbgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_vcmpbgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpb.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmpbgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmpb.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vcmpheqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmph.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmphgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmph.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmphgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmph.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vcmpweqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpw.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmpwgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpw.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmpwgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmpw.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b100; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vrmaxh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxuh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxuh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxuw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxuw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminuh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminuh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminuw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminuw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A5_ACS : HInst< +(outs DoubleRegs:$Rxx32, PredRegs:$Pe4), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", +M_tc_3stall_SLOT23, TypeM>, Enc_12822813, Requires<[HasV55T]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let isPredicateLate = 1; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A5_vaddhubs : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vaddhub($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9277990, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def C2_all8 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = all8($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011101000; +} +def C2_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = and($Pt4,$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011000000; +} +def C2_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = and($Pt4,!$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011011000; +} +def C2_any8 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = any8($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011100000; +} +def C2_bitsclr : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = bitsclr($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111100; +} +def C2_bitsclri : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u6_0Imm:$Ii), +"$Pd4 = bitsclr($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_14574598 { +let Inst{7-2} = 0b000000; +let Inst{31-21} = 0b10000101100; +} +def C2_bitsset : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = bitsset($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111010; +} +def C2_ccombinewf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewnewf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewnewt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_cmoveif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmoveit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmovenewif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmovenewit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmpeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010000; +let CextOpcode = "C2_cmpeq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def C2_cmpeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-22} = 0b0111010100; +let CextOpcode = "C2_cmpeq"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C2_cmpeqp : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCommutable = 1; +let isCompare = 1; +} +def C2_cmpgei : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s8_0Imm:$Ii), +"$Pd4 = cmp.ge($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let isCompare = 1; +let isPseudo = 1; +} +def C2_cmpgeui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Pd4 = cmp.geu($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let isCompare = 1; +let isPseudo = 1; +} +def C2_cmpgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.gt($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010010; +let CextOpcode = "C2_cmpgt"; +let InputType = "reg"; +let isCompare = 1; +} +def C2_cmpgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.gt($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-22} = 0b0111010101; +let CextOpcode = "C2_cmpgt"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C2_cmpgtp : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCompare = 1; +} +def C2_cmpgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.gtu($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010011; +let CextOpcode = "C2_cmpgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def C2_cmpgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmp.gtu($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_13249928, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-21} = 0b01110101100; +let CextOpcode = "C2_cmpgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def C2_cmpgtup : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCompare = 1; +} +def C2_cmplt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.lt($Rs32,$Rt32)", +PSEUDO, TypeALU32_3op> { +let isCompare = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_cmpltu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.ltu($Rs32,$Rt32)", +PSEUDO, TypeALU32_3op> { +let isCompare = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_mask : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4), +"$Rdd32 = mask($Pt4)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_10328975 { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b1000011000000000; +} +def C2_mux : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mux($Pu4,$Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110100000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def C2_muxii : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), +"$Rd32 = mux($Pu4,#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9093094 { +let Inst{31-25} = 0b0111101; +let hasNewValue = 1; +let opNewValue = 0; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_muxir : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = mux($Pu4,$Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011100110; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_muxri : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = mux($Pu4,#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011100111; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_not : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = not($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011110000; +} +def C2_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = or($Pt4,$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011001000; +} +def C2_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = or($Pt4,!$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011111000; +} +def C2_pxfer_map : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = $Ps4", +S_2op_tc_1_SLOT23, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_tfrpr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Ps4), +"$Rd32 = $Ps4", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_11139981 { +let Inst{13-5} = 0b000000000; +let Inst{31-18} = 0b10001001010000; +let hasNewValue = 1; +let opNewValue = 0; +} +def C2_tfrrp : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32), +"$Pd4 = $Rs32", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_4527648 { +let Inst{13-2} = 0b000000000000; +let Inst{31-21} = 0b10000101010; +} +def C2_vitpack : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Rd32 = vitpack($Ps4,$Pt4)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_6735062 { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b10001001000000; +let hasNewValue = 1; +let opNewValue = 0; +} +def C2_vmux : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_7606379 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010001000; +} +def C2_xor : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = xor($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011010000; +} +def C4_addipc : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = add(pc,#$Ii)", +CR_tc_2_SLOT3, TypeCR>, Enc_9554661 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0110101001001001; +let hasNewValue = 1; +let opNewValue = 0; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def C4_and_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,and($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011000100; +} +def C4_and_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,and($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011100100; +} +def C4_and_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,or($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011001100; +} +def C4_and_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,or($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011101100; +} +def C4_cmplte : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.gt($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010010; +let CextOpcode = "C4_cmplte"; +let InputType = "reg"; +let isCompare = 1; +} +def C4_cmpltei : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = !cmp.gt($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-22} = 0b0111010101; +let CextOpcode = "C4_cmplte"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C4_cmplteu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.gtu($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010011; +let CextOpcode = "C4_cmplteu"; +let InputType = "reg"; +let isCompare = 1; +} +def C4_cmplteui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = !cmp.gtu($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_13249928, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-21} = 0b01110101100; +let CextOpcode = "C4_cmplteu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def C4_cmpneq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010000; +let CextOpcode = "C4_cmpneq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def C4_cmpneqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = !cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-22} = 0b0111010100; +let CextOpcode = "C4_cmpneq"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C4_fastcorner9 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = fastcorner9($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b100100; +let Inst{13-10} = 0b1000; +let Inst{31-18} = 0b01101011000000; +} +def C4_fastcorner9_not : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = !fastcorner9($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b100100; +let Inst{13-10} = 0b1000; +let Inst{31-18} = 0b01101011000100; +} +def C4_nbitsclr : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !bitsclr($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111101; +} +def C4_nbitsclri : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u6_0Imm:$Ii), +"$Pd4 = !bitsclr($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_14574598 { +let Inst{7-2} = 0b000000; +let Inst{31-21} = 0b10000101101; +} +def C4_nbitsset : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !bitsset($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111011; +} +def C4_or_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,and($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011010100; +} +def C4_or_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,and($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011110100; +} +def C4_or_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,or($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011011100; +} +def C4_or_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,or($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011111100; +} +def F2_conv_d2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_d2df($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_d2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_d2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2d : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2d($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2d_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2d($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2ud : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2ud($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2ud_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2ud($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2uw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2uw($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2uw_chop : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2uw($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000101; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2w : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2w($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2w_chop : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2w($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2d : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2d($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2d_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2d($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2ud : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2ud($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2ud_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2ud($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2uw : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2uw($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2uw_chop : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2uw($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001011011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2w : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2w($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2w_chop : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2w($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_ud2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_ud2df($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_ud2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_ud2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000001; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_uw2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_uw2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_uw2sf : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_uw2sf($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011001; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_w2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_w2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_w2sf : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_w2sf($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfclass : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Pd4 = dfclass($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_14400220, Requires<[HasV5T]> { +let Inst{4-2} = 0b100; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b11011100100; +let isFP = 1; +let Uses = [USR]; +} +def F2_dfcmpeq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpge : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.ge($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpuo : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.uo($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfimm_n : HInst< +(outs DoubleRegs:$Rdd32), +(ins u10_0Imm:$Ii), +"$Rdd32 = dfmake(#$Ii):neg", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_2702036, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101100101; +let prefersSlot3 = 1; +} +def F2_dfimm_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins u10_0Imm:$Ii), +"$Rdd32 = dfmake(#$Ii):pos", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_2702036, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101100100; +let prefersSlot3 = 1; +} +def F2_sfadd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfadd($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let isCommutable = 1; +} +def F2_sfclass : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = sfclass($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101111; +let isFP = 1; +let Uses = [USR]; +} +def F2_sfcmpeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.eq($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpge : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.ge($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.gt($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpuo : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.uo($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sffixupd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sffixupd($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011110; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffixupn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sffixupn($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011110; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffixupr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sffixupr($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011101; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffma : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += sfmpy($Rs32,$Rt32)", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffma_lib : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += sfmpy($Rs32,$Rt32):lib", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffma_sc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), +"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_15194851, Requires<[HasV5T]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffms : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= sfmpy($Rs32,$Rt32)", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffms_lib : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= sfmpy($Rs32,$Rt32):lib", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sfimm_n : HInst< +(outs IntRegs:$Rd32), +(ins u10_0Imm:$Ii), +"$Rd32 = sfmake(#$Ii):neg", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9082775, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101011001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def F2_sfimm_p : HInst< +(outs IntRegs:$Rd32), +(ins u10_0Imm:$Ii), +"$Rd32 = sfmake(#$Ii):pos", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9082775, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def F2_sfinvsqrta : HInst< +(outs IntRegs:$Rd32, PredRegs:$Pe4), +(ins IntRegs:$Rs32), +"$Rd32,$Pe4 = sfinvsqrta($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_5718302, Requires<[HasV5T]> { +let Inst{13-7} = 0b0000000; +let Inst{31-21} = 0b10001011111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let isPredicateLate = 1; +let prefersSlot3 = 1; +} +def F2_sfmax : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmax($Rs32,$Rt32)", +M_tc_2_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_sfmin : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmin($Rs32,$Rt32)", +M_tc_2_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_sfmpy : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmpy($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let isCommutable = 1; +} +def F2_sfrecipa : HInst< +(outs IntRegs:$Rd32, PredRegs:$Pe4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_5853469, Requires<[HasV5T]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let isPredicateLate = 1; +let prefersSlot3 = 1; +} +def F2_sfsub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfsub($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def J2_call : HInst< +(outs), +(ins a30_2Imm:$Ii), +"call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_13453446, PredRel { +let Inst{0-0} = 0b0; +let Inst{31-25} = 0b0101101; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let isPredicable = 1; +let hasSideEffects = 1; +let Defs = VolatileV3.Regs; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 24; +let opExtentAlign = 2; +} +def J2_callf : HInst< +(outs), +(ins PredRegs:$Pu4, a30_2Imm:$Ii), +"if (!$Pu4) call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_14868535, PredRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let Defs = VolatileV3.Regs; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_callr : HInst< +(outs), +(ins IntRegs:$Rs32), +"callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010000101; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +let Defs = VolatileV3.Regs; +} +def J2_callrf : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953 { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let Defs = VolatileV3.Regs; +} +def J2_callrt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953 { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010001000; +let isPredicated = 1; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let Defs = VolatileV3.Regs; +} +def J2_callt : HInst< +(outs), +(ins PredRegs:$Pu4, a30_2Imm:$Ii), +"if ($Pu4) call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_14868535, PredRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011101; +let isPredicated = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let Defs = VolatileV3.Regs; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_endloop0 : HInst< +(outs), +(ins), +"endloop0", +PSEUDO, TypeJ> { +let Uses = [LC0, SA0]; +let Defs = [LC0, P3, PC, USR]; +let isPseudo = 1; +} +def J2_endloop01 : HInst< +(outs), +(ins), +"endloop01", +PSEUDO, TypeJ> { +let Uses = [LC0, LC1, SA0, SA1]; +let Defs = [LC0, LC1, P3, PC, USR]; +let isPseudo = 1; +} +def J2_endloop1 : HInst< +(outs), +(ins), +"endloop1", +PSEUDO, TypeJ> { +let Uses = [LC1, SA1]; +let Defs = [LC1, PC]; +let isPseudo = 1; +} +def J2_jump : HInst< +(outs), +(ins b30_2Imm:$Ii), +"jump $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_13453446, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{31-25} = 0b0101100; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isBarrier = 1; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 24; +let opExtentAlign = 2; +} +def J2_jumpf : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpf_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, b15_2Imm:$Ii), +"if (!$Pu4) jump $Ii", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumpfnew : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4.new) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b010; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpfnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4.new) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b110; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpfpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, Requires<[HasV60T]>, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b100; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpr : HInst< +(outs), +(ins IntRegs:$Rs32), +"jumpr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059, PredNewRel { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010010100; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isBarrier = 1; +let isPredicable = 1; +} +def J2_jumprf : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprf_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr $Rs32", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumprfnew : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprfnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprfpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, Requires<[HasV60T]>, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprgtez : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32>=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000101; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprgtezpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32>=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000101; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprltez : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32<=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000111; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprltezpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32<=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000111; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprnz : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32==#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprnzpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32==#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprt_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr $Rs32", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumprtnew : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprtnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprtpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, Requires<[HasV60T]>, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprz : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32!=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprzpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32!=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpt_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, b15_2Imm:$Ii), +"if ($Pu4) jump $Ii", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumptnew : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4.new) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b010; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumptnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4.new) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b110; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumptpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, Requires<[HasV60T]>, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b100; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_loop0i : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"loop0($Ii,#$II)", +CR_tc_3x_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001000; +let Defs = [LC0, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop0r : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"loop0($Ii,$Rs32)", +CR_tc_3x_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000000; +let Defs = [LC0, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop1i : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"loop1($Ii,#$II)", +CR_tc_3x_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001001; +let Defs = [LC1, SA1]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop1r : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"loop1($Ii,$Rs32)", +CR_tc_3x_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000001; +let Defs = [LC1, SA1]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_pause : HInst< +(outs), +(ins u8_0Imm:$Ii), +"pause(#$Ii)", +J_tc_2early_SLOT2, TypeJ>, Enc_8732960 { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010001000000; +let isSolo = 1; +} +def J2_ploop1si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp1loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001101; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop1sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp1loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000101; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop2si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp2loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001110; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop2sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp2loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000110; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop3si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp3loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001111; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop3sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp3loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000111; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_trap0 : HInst< +(outs), +(ins u8_0Imm:$Ii), +"trap0(#$Ii)", +J_tc_2early_SLOT2, TypeJ>, Enc_8732960 { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010000000000; +let isSolo = 1; +} +def J4_cmpeq_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4359901, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8612939, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_844699, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5338033, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14150875, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_15450971, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_14998517, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_11544269, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5401217, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12419313, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_4684887, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_220949, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8674673, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15763937, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5915771, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7315939, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7785569, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_10968391, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_364753, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8479583, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_2428539, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_8919369, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_8577055, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14530015, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmplt_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_hintjumpr : HInst< +(outs), +(ins IntRegs:$Rs32), +"hintjr($Rs32)", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010010101; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +} +def J4_jumpseti : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u6_0Imm:$II, b30_2Imm:$Ii), +"$Rd16 = #$II ; jump $Ii", +COMPOUND, TypeCJ>, Enc_4834775 { +let Inst{0-0} = 0b0; +let Inst{31-22} = 0b0001011000; +let hasNewValue = 1; +let opNewValue = 0; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_jumpsetr : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"$Rd16 = $Rs16 ; jump $Ii", +COMPOUND, TypeCJ>, Enc_2639299 { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!tstbit($Ns8.new,#0)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!tstbit($Ns8.new,#0)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (tstbit($Ns8.new,#0)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (tstbit($Ns8.new,#0)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def L2_deallocframe : HInst< +(outs), +(ins), +"deallocframe", +LD_tc_ld_SLOT01, TypeLD>, Enc_0 { +let Inst{4-0} = 0b11110; +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010000000; +let Inst{20-16} = 0b11110; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [R29, R30, R31]; +} +def L2_loadalignb_io : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Ryy32 = memb_fifo($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_449439 { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignb_pbr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110100; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pci : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_971347 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pcr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pi : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Ryy32 = memb_fifo($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6372758 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_zomap : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), +"$Ryy32 = memb_fifo($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignh_io : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), +"$Ryy32 = memh_fifo($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11930027 { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignh_pbr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110010; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pci : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_1971351 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pcr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pi : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Ryy32 = memh_fifo($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_3372766 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_zomap : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), +"$Ryy32 = memh_fifo($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadbsw2_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = membh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738 { +let Inst{24-21} = 0b0001; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadbsw2_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = membh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = membh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbsw4_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rdd32 = membh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_9852473 { +let Inst{24-21} = 0b0111; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadbsw4_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110111; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_3931661 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rdd32 = membh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_8752140 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = membh($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbzw2_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memubh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738 { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadbzw2_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110011; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memubh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memubh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbzw4_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rdd32 = memubh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_9852473 { +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadbzw4_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110101; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_3931661 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rdd32 = memubh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_8752140 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memubh($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrb_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memb($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_14461004, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def L2_loadrb_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_16303398 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5598813, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrbgp : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memb(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrb_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def L2_loadrd_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s29_3Imm:$Ii), +"$Rdd32 = memd($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_163381, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def L2_loadrd_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111110; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_931653 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii), +"$Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_9752128, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrdgp : HInst< +(outs DoubleRegs:$Rdd32), +(ins u29_3Imm:$Ii), +"$Rdd32 = memd(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4975051, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b01001; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrd_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def L2_loadrh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadrh_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111010; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrhgp : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memh(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrh_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def L2_loadri_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rd32 = memw($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_8990840, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadri_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111100; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_14303394 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_16376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrigp : HInst< +(outs IntRegs:$Rd32), +(ins u30_2Imm:$Ii), +"$Rd32 = memw(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_8814718, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadri_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def L2_loadrub_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memub($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_14461004, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def L2_loadrub_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_16303398 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5598813, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrubgp : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memub(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrub_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def L2_loadruh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memuh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadruh_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111011; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadruhgp : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memuh(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadruh_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def L2_loadw_locked : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memw_locked($Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4075554 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let isSoloAX = 1; +let mayLoad = 1; +} +def L2_ploadrbf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbt_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbt_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbt_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdf_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdf_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdf_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdfnew_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdfnew_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdfnew_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdt_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdt_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdt_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdtnew_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdtnew_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdtnew_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrht_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrht_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrht_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrif_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrif_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrif_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrifnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrifnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrifnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrit_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrit_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrit_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadritnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadritnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadritnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubt_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubt_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubt_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruht_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruht_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruht_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_add_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_add_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_add_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_and_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_and_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_and_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_iadd_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_iadd_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_iadd_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_iand_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_iand_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_iand_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ior_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_ior_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_ior_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_isub_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_isub_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_isub_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_loadalignb_ap : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Re32), +(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), +"$Ryy32 = memb_fifo($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11047413 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010100; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignb_ur : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_7303598 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100100; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 4; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignh_ap : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Re32), +(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), +"$Ryy32 = memh_fifo($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11047413 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010010; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignh_ur : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_7303598 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100010; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 4; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadbsw2_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = membh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010001; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw2_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = membh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw4_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = membh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010111; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw4_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = membh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100111; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw2_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memubh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010011; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw2_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memubh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw4_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = memubh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010101; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw4_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = memubh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100101; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadd_locked : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memd_locked($Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4030179 { +let Inst{13-5} = 0b010000000; +let Inst{31-21} = 0b10010010000; +let accessSize = DoubleWordAccess; +let isSoloAX = 1; +let mayLoad = 1; +} +def L4_loadrb_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memb($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011000; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrb_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +let isPredicable = 1; +} +def L4_loadrb_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memb($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrd_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = memd($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011110; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrd_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7581852, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010110; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +let isPredicable = 1; +} +def L4_loadrd_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = memd($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101110; +let addrMode = BaseLongOffset; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrh_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011010; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrh_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +let isPredicable = 1; +} +def L4_loadrh_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadri_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memw($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011100; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadri_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +let isPredicable = 1; +} +def L4_loadri_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memw($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrub_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memub($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011001; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrub_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +let isPredicable = 1; +} +def L4_loadrub_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memub($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadruh_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memuh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011011; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadruh_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +let isPredicable = 1; +} +def L4_loadruh_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memuh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_or_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_or_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_or_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_or_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_or_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_or_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ploadrbf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbt_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbt_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrdf_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdf_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdfnew_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdfnew_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdt_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdt_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110000110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdtnew_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdtnew_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110010110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrhf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrhfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrht_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrht_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrhtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrif_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrif_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrifnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrifnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrit_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrit_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadritnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadritnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrubf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubt_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubt_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadruhf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruhfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruht_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruht_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruhtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_return : HInst< +(outs), +(ins), +"dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_0, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isBarrier = 1; +let isPredicable = 1; +let isTaken = 1; +} +def L4_return_f : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4) dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1100; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_fnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:nt", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_fnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:t", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1110; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_t : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4) dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_tnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:nt", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_tnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:t", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_sub_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_sub_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_sub_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_sub_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_sub_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_sub_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M2_acci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += add($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889, ImmRegRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_acci"; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_accii : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 += add($Rs32,#$Ii)", +M_tc_2_acc_SLOT23, TypeM>, Enc_11522288, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100010000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_acci"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_cmaci_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpyi($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacr_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpyr($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacsc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32*):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacsc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmpyi_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpyi($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_cmpyr_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpyr($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_cmpyrs_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrs_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrsc_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrsc_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpys_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpysc_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32*):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpysc_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cnacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacsc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32*):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacsc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_nac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_rnd_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_dpmpyss_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_dpmpyuu_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyuu_nac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyuu_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M2_hmmpyh_rs1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyl_rs1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_maci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyi($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_maci"; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_macsin : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rx32 -= mpyi($Rs32,#$Ii)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_11522288 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_macsip : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rx32 += mpyi($Rs32,#$Ii)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_11522288, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_maci"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mmachs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmpyh_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_acc_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_nac_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_rnd_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_sat_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_up_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_up_s1_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpyd_acc_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_nac_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_rnd_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyi($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_mpyi"; +let InputType = "reg"; +} +def M2_mpysin : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Rd32 = -mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, Enc_16355964 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100000100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpysip : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rd32 = +mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, Enc_16355964 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100000000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def M2_mpysmi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, m32_0Imm:$Ii), +"$Rd32 = mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, ImmRegRel { +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "M2_mpyi"; +let InputType = "imm"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def M2_mpysu_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpysu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_acc_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_nac_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyud_acc_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_nac_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyui : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyui($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M2_nacci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= add($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_naccii : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 -= add($Rs32,#$Ii)", +M_tc_2_acc_SLOT23, TypeM>, Enc_11522288 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100010100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_subacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), +"$Rx32 += sub($Rt32,$Rs32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_7692963 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_vabsdiffh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffh($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M2_vabsdiffw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffw($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +} +def M2_vcmac_s0_sat_i : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vcmac_s0_sat_r : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vcmpy_s0_sat_i : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s0_sat_r : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s1_sat_i : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s1_sat_r : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpy($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vdmacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vdmpyrs_s0 : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpyrs_s1 : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpys_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpy($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmac2 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2s_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2s_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2su_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2su_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmpy2es_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2es_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyh($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s0pack : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s1pack : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2su_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2su_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vraddh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vraddh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_vradduh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vradduh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_vrcmaci_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyi($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmaci_s0c : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmacr_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyr($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmacr_s0c : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpyi_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyi($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_vrcmpyi_s0c : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def M2_vrcmpyr_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyr($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_vrcmpyr_s0c : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M2_vrcmpys_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM> { +let isPseudo = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_acc_s1_h : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_acc_s1_l : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM> { +let isPseudo = 1; +} +def M2_vrcmpys_s1_h : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1_l : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1rp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def M2_vrcmpys_s1rp_h : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1rp_l : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrmac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrmpy_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_xor_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_xor : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_cmpyi_wh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyi_whc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyr_wh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyr_whc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_mac_up_s1_sat : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_mpyri_addi : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), +"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_971574, ImmRegRel { +let Inst{31-24} = 0b11011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyri_addr"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyri_addr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_236434, ImmRegRel { +let Inst{31-23} = 0b110111111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyri_addr"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyri_addr_u2 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_9959498 { +let Inst{31-23} = 0b110111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M4_mpyrr_addi : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_2216485, ImmRegRel { +let Inst{31-23} = 0b110101110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyrr_addr"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyrr_addr : HInst< +(outs IntRegs:$Ry32), +(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), +"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", +M_tc_3x_SLOT23, TypeM>, Enc_13770697, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyrr_addr"; +let InputType = "reg"; +let Constraints = "$Ry32 = $Ry32in"; +} +def M4_nac_up_s1_sat : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_xor : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_pmpyw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = pmpyw($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M4_pmpyw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 ^= pmpyw($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vpmpyh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vpmpyh($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101110; +let prefersSlot3 = 1; +} +def M4_vpmpyh_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 ^= vpmpyh($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyweh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyweh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def M4_vrmpyeh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M4_vrmpyoh_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpywoh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyoh_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyoh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpywoh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +} +def M4_vrmpyoh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +} +def M4_xor_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 ^= xor($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vdmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vdmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M5_vmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpybsu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vmacbuu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpybu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpybsu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M5_vmpybuu : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpybu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +} +def M5_vrmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpybsu($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vrmacbuu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpybu($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vrmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpybsu($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M5_vrmpybuu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpybu($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +} +def PS_loadrbabs : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memb(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_loadrdabs : HInst< +(outs DoubleRegs:$Rdd32), +(ins u29_3Imm:$Ii), +"$Rdd32 = memd(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4975051, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def PS_loadrhabs : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memh(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_loadriabs : HInst< +(outs IntRegs:$Rd32), +(ins u30_2Imm:$Ii), +"$Rd32 = memw(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_8814718, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def PS_loadrubabs : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memub(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_loadruhabs : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memuh(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerbabs : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Rt32), +"memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_12395768, AddrModeRel { +let Inst{24-21} = 0b0000; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_storerbnewabs : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Nt8), +"memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_4050532, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +let opNewValue = 1; +} +def PS_storerdabs : HInst< +(outs), +(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_11682941, AddrModeRel { +let Inst{24-21} = 0b0110; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def PS_storerfabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerhabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerhnewabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Nt8), +"memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_13618890, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +let opNewValue = 1; +} +def PS_storeriabs : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Rt32), +"memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_15999208, AddrModeRel { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def PS_storerinewabs : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Nt8), +"memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_12297800, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +let opNewValue = 1; +} +def S2_addasl_rrri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), +"$Rd32 = addasl($Rt32,$Rs32,#$Ii)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_3494181 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_allocframe : HInst< +(outs), +(ins u11_3Imm:$Ii), +"allocframe(#$Ii)", +ST_tc_ld_SLOT0, TypeST>, Enc_15830826 { +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10100000100; +let Inst{20-16} = 0b11101; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [R29, R30, R31]; +let Defs = [R29, R30]; +} +def S2_asl_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asl($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000000000; +} +def S2_asl_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asl($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asl_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asl($Rs32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asl_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vaslh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_asl_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vaslw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_asl_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = asl($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_asl_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asl($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asl_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asl($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asl_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vaslh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_asl_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vaslw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_asr_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asr($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000000000; +} +def S2_asr_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_rnd : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asr($Rss32,#$Ii):rnd", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000000110; +let prefersSlot3 = 1; +} +def S2_asr_i_p_rnd_goodsyntax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asrrnd($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let isPseudo = 1; +} +def S2_asr_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asr($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_rnd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asr($Rs32,#$Ii):rnd", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_asr_i_r_rnd_goodsyntax : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asrrnd($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def S2_asr_i_svw_trun : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rd32 = vasrw($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2380082 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_asr_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vasrw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_asr_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = asr($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_asr_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asr($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asr($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asr_r_svw_trun : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = vasrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vasrh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_asr_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vasrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_brev : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = brev($Rs32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_brevp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = brev($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000110; +} +def S2_cabacdecbin : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = decbin($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let isPredicateLate = 1; +let prefersSlot3 = 1; +let Defs = [P0]; +} +def S2_cl0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = cl0($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl0p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = cl0($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = cl1($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl1p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = cl1($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = clb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clbnorm : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = normamt($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clbp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = clb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clrbit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = clrbit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clrbit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = clrbit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = ct0($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct0p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = ct0($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = ct1($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct1p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = ct1($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_deinterleave : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = deinterleave($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000110; +} +def S2_extractu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rd32 = extractu($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_11930928 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_extractu_rp : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rd32 = extractu($Rs32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_15472748 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_extractup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rdd32 = extractu($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_9894557 { +let Inst{31-24} = 0b10000001; +let prefersSlot3 = 1; +} +def S2_extractup_rp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = extractu($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +let prefersSlot3 = 1; +} +def S2_insert : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = insert($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2880796 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011110; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_insert_rp : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rx32 = insert($Rs32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_16311032 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_insertp : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rxx32 = insert($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_631197 { +let Inst{31-24} = 0b10000011; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_insertp_rp : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 = insert($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001010000; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_interleave : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = interleave($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000110; +} +def S2_lfsp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = lfs($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +let prefersSlot3 = 1; +} +def S2_lsl_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = lsl($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_lsl_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = lsl($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsl_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlslh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_lsl_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlslw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_lsr_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = lsr($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000000000; +} +def S2_lsr_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = lsr($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsr_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vlsrh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b001; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_lsr_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vlsrw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_lsr_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = lsr($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_lsr_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = lsr($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsr_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlsrh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_lsr_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlsrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_packhl : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = packhl($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110101100; +let InputType = "reg"; +} +def S2_parityp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = parity($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010000000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_pstorerbf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S2_pstorerbf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerbfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S2_pstorerbnewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerbnewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S2_pstorerbnewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerbnewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S2_pstorerbt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerbtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S2_pstorerdf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerdfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S2_pstorerdt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerdtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerff_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerff_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerff_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerffnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerft_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000011; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerft_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerft_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerftnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerhf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerhfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S2_pstorerhnewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerhnewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S2_pstorerhnewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerhnewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerht_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerht_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerht_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerhtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerif_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S2_pstorerif_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerif_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerifnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S2_pstorerinewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerinewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S2_pstorerinewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerinewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerit_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000100; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S2_pstorerit_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerit_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstoreritnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_setbit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = setbit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_setbit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = setbit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_shuffeb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = shuffeb($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffeh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = shuffeh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffob : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = shuffob($Rtt32,$Rss32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffoh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = shuffoh($Rtt32,$Rss32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_storerb_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_13150110, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def S2_storerb_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111000; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_3915770 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_12492533, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerbgp : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Rt32), +"memb(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_12395768, AddrModeRel { +let Inst{24-21} = 0b0000; +let Inst{31-27} = 0b01001; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def S2_storerbnew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10002182, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S2_storerbnew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101111101; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_5326450 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_5900401, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerbnewgp : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Nt8), +"memb(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_4050532, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +let opNewValue = 1; +} +def S2_storerd_io : HInst< +(outs), +(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_16319737, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def S2_storerd_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++$Mu2:brev) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111110; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_4501395 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++I:circ($Mu2)) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11271630, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++$Mu2) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerdgp : HInst< +(outs), +(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd(gp+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11682941, AddrModeRel { +let Inst{24-21} = 0b0110; +let Inst{31-27} = 0b01001; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerdabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def S2_storerf_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7736768, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def S2_storerf_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2:brev) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111011; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_10915758 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++I:circ($Mu2)) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11492529, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerfgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(gp+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerfabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def S2_storerh_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7736768, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def S2_storerh_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111010; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_10915758 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11492529, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerhgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def S2_storerhnew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), +"memh($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_748676, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +let opNewValue = 2; +} +def S2_storerhnew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101111101; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10326434 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_6900405, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b001; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerhnewgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Nt8), +"memh(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_13618890, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +let opNewValue = 1; +} +def S2_storeri_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_6673186, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def S2_storeri_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111100; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_9915754 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10492541, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerigp : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Rt32), +"memw(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_15999208, AddrModeRel { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b01001; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def S2_storerinew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), +"memw($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_8409782, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +let opNewValue = 2; +} +def S2_storerinew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101111101; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_11326438 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_7900405, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b010; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_pi"; +let isPredicable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerinewgp : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Nt8), +"memw(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_12297800, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +let opNewValue = 1; +} +def S2_storew_locked : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw_locked($Rs32,$Pd4) = $Rt32", +ST_tc_ld_SLOT0, TypeST>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000101; +let accessSize = WordAccess; +let isSoloAX = 1; +let mayStore = 1; +let isPredicateLate = 1; +} +def S2_svsathb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsathb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_svsathub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsathub($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_tableidxb : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxb_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxb($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxd : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxd_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxd($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxh : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxh_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxh($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxw : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxw_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxw($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_togglebit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = togglebit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_togglebit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = togglebit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_tstbit_i : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = tstbit($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101000; +} +def S2_tstbit_r : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = tstbit($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111000; +} +def S2_valignib : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), +"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11971407 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000000000; +} +def S2_valignrb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), +"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11552785 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010000; +} +def S2_vcnegh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vcnegh($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S2_vcrotate : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vcrotate($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S2_vrcnegh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += vrcnegh($Rss32,$Rt32)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_vrndpackwh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vrndwh($Rss32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vrndpackwhs : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vrndwh($Rss32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsathb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathb_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsathb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsathub : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsathub($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathub_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsathub($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsatwh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsatwh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsatwh_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsatwh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsatwuh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsatwuh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsatwuh_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsatwuh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsplatrb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsplatb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vsplatrh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsplath($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100010; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vspliceib : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), +"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_16730127 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000000100; +} +def S2_vsplicerb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), +"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_5178985 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010100; +} +def S2_vsxtbh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsxtbh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vsxthw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsxthw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vtrunehb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vtrunehb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vtrunewh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunewh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_vtrunohb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vtrunohb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vtrunowh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunowh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_vzxtbh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vzxtbh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vzxthw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vzxthw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S4_addaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,add($Ru32,#$Ii))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6495334 { +let Inst{31-23} = 0b110110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_addi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = add(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b100; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_addi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b100; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_andi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = and(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b000; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_andi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b000; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_clbaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s6_0Imm:$Ii), +"$Rd32 = add(clb($Rs32),#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_5523416 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10001100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_clbpaddi : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, s6_0Imm:$Ii), +"$Rd32 = add(clb($Rss32),#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_10188026 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_clbpnorm : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = normamt($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +} +def S4_extract : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rd32 = extract($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_11930928 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_extract_rp : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rd32 = extract($Rs32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_15472748 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_extractp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rdd32 = extract($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_9894557 { +let Inst{31-24} = 0b10001010; +let prefersSlot3 = 1; +} +def S4_extractp_rp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = extract($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +} +def S4_lsli : HInst< +(outs IntRegs:$Rd32), +(ins s6_0Imm:$Ii, IntRegs:$Rt32), +"$Rd32 = lsl(#$Ii,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_518319 { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S4_ntstbit_i : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = !tstbit($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101001; +} +def S4_ntstbit_r : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !tstbit($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111001; +} +def S4_or_andi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 |= and($Rs32,#$Ii)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6356866 { +let Inst{31-22} = 0b1101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_or_andix : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), +"$Rx32 = or($Ru32,and($Rx32in,#$Ii))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_7504828 { +let Inst{31-22} = 0b1101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_or_ori : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 |= or($Rs32,#$Ii)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6356866 { +let Inst{31-22} = 0b1101101010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_ori_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = or(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b010; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_ori_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b010; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_parity : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = parity($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_pstorerbf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerbnewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b000; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_pstorerbnewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerbnewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b000; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_pstorerbnewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerbt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100000; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110000; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerdf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110101110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S4_pstorerdfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerdt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110100110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S4_pstorerdtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110110110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerff_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerff_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerffnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerffnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerffnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerffnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerft_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerft_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100011; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerftnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerftnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010011; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerftnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110011; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerftnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerhf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerhfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerhnewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b001; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S4_pstorerhnewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerhnewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b001; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S4_pstorerhnewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerht_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerht_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100010; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerhtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110010; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerif_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerif_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstorerifnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerifnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S4_pstorerifnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstorerifnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerinewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b010; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S4_pstorerinewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerinewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b010; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S4_pstorerinewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerit_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerit_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100100; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstoreritnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstoreritnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010100; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S4_pstoreritnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110100; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstoreritnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_stored_locked : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd_locked($Rs32,$Pd4) = $Rtt32", +ST_tc_ld_SLOT0, TypeST>, Enc_2921694 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; +let accessSize = DoubleWordAccess; +let isSoloAX = 1; +let mayStore = 1; +let isPredicateLate = 1; +} +def S4_storeirb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11282123, PredNewRel { +let Inst{31-21} = 0b00111100000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeirb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111000000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111001000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirh_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_10282127, PredNewRel { +let Inst{31-21} = 0b00111100001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeirh_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirht_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111000001; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirht_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111001001; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeiri_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9282127, PredNewRel { +let Inst{31-21} = 0b00111100010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeiri_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirif_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirif_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirifnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirifnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirit_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111000010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirit_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeiritnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111001010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeiritnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storerb_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memb($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerb_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011000; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storerb_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memb($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101000; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storerb_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerbnew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memb($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerbnew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0000; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerbnew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memb($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S4_storerb_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_storerd_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, DoubleRegs:$Rtt32), +"memd($Re32=#$II) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_8131399 { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S4_storerd_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerd_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9772987, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011110; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +let isPredicable = 1; +} +def S4_storerd_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), +"memd($Ru32<<#$Ii+#$II) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_12848507, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101110; +let addrMode = BaseLongOffset; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerf_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memh($Re32=#$II) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_11477246 { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S4_storerf_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerf_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011011; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +let isPredicable = 1; +} +def S4_storerf_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memh($Ru32<<#$Ii+#$II) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101011; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S4_storerf_rr"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerh_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memh($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerh_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011010; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storerh_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memh($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101010; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerhnew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memh($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b001; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerhnew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0001; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerhnew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memh($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_storeri_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memw($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storeri_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeri_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011100; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storeri_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memw($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101100; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerinew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memw($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b010; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerinew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0010; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerinew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memw($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_subaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), +"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6495334 { +let Inst{31-23} = 0b110110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_subi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b110; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_subi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b110; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_vrcrotate : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_114098 { +let Inst{7-6} = 0b11; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +} +def S4_vrcrotate_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_13114546 { +let Inst{7-6} = 0b00; +let Inst{31-21} = 0b11001011101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S4_vxaddsubh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxaddsubhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S4_vxaddsubw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxsubaddh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxsubaddhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S4_vxsubaddw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S5_asrhub_rnd_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):raw", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8038806, Requires<[HasV5T]> { +let Inst{7-5} = 0b100; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S5_asrhub_rnd_sat_goodsyntax : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def S5_asrhub_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8038806, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S5_popcountp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = popcount($Rss32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S5_vasrhrnd : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000001; +let prefersSlot3 = 1; +} +def S5_vasrhrnd_goodsyntax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii):rnd", +S_2op_tc_1_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let isPseudo = 1; +} +def S6_rol_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000000000; +} +def S6_rol_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S6_rol_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def SA1_addi : HInst< +(outs GeneralSubRegs:$Rx16), +(ins IntRegs:$Rx16in, s32_0Imm:$Ii), +"$Rx16 = add($Rx16in,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_3974695 { +let Inst{12-11} = 0b00; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 7; +let opExtentAlign = 0; +let Constraints = "$Rx16 = $Rx16in"; +} +def SA1_addrx : HInst< +(outs GeneralSubRegs:$Rx16), +(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), +"$Rx16 = add($Rx16in,$Rs16)", +PSEUDO, TypeSUBINSN>, Enc_6135183 { +let Inst{12-8} = 0b11000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let Constraints = "$Rx16 = $Rx16in"; +} +def SA1_addsp : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u6_2Imm:$Ii), +"$Rd16 = add(r29,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_176263 { +let Inst{12-10} = 0b011; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_and1 : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = and($Rs16,#1)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrf : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (!p0) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrfnew : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (!p0.new) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrt : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (p0) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrtnew : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (p0.new) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_cmpeqi : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), +"p0 = cmp.eq($Rs16,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_2079016 { +let Inst{3-2} = 0b00; +let Inst{12-8} = 0b11001; +let AsmVariantName = "NonParsable"; +let Defs = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine0i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#0,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b00; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine1i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#1,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b01; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine2i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#2,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b10; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine3i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#3,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b11; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combinerz : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins GeneralSubRegs:$Rs16), +"$Rdd8 = combine($Rs16,#0)", +PSEUDO, TypeSUBINSN>, Enc_10501894 { +let Inst{3-3} = 0b1; +let Inst{12-8} = 0b11101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combinezr : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins GeneralSubRegs:$Rs16), +"$Rdd8 = combine(#0,$Rs16)", +PSEUDO, TypeSUBINSN>, Enc_10501894 { +let Inst{3-3} = 0b0; +let Inst{12-8} = 0b11101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_dec : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, n1Const:$n1), +"$Rd16 = add($Rs16,#$n1)", +PSEUDO, TypeSUBINSN>, Enc_10597934 { +let Inst{12-8} = 0b10011; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_inc : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = add($Rs16,#1)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10001; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_seti : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u32_0Imm:$Ii), +"$Rd16 = #$Ii", +PSEUDO, TypeSUBINSN>, Enc_2176383 { +let Inst{12-10} = 0b010; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def SA1_setin1 : HInst< +(outs GeneralSubRegs:$Rd16), +(ins n1Const:$n1), +"$Rd16 = #$n1", +PSEUDO, TypeSUBINSN>, Enc_13336212 { +let Inst{12-4} = 0b110100000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_sxtb : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = sxtb($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_sxth : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = sxth($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10100; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_tfr : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = $Rs16", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_zxtb : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = and($Rs16,#255)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10111; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_zxth : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = zxth($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10110; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SL1_loadri_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"$Rd16 = memw($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_13606251 { +let Inst{12-12} = 0b0; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L1"; +} +def SL1_loadrub_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"$Rd16 = memub($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15606259 { +let Inst{12-12} = 0b1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L1"; +} +def SL2_deallocframe : HInst< +(outs), +(ins), +"deallocframe", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111100000000; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [R30, R29, R31]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31 : HInst< +(outs), +(ins), +"jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000000; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [R31]; +let Defs = [PC]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_f : HInst< +(outs), +(ins), +"if (!p0) jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_fnew : HInst< +(outs), +(ins), +"if (!p0.new) jumpr:nt r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_t : HInst< +(outs), +(ins), +"if (p0) jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000100; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_tnew : HInst< +(outs), +(ins), +"if (p0.new) jumpr:nt r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrb_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), +"$Rd16 = memb($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_3135259 { +let Inst{12-11} = 0b10; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrd_sp : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u5_3Imm:$Ii), +"$Rdd8 = memd(r29+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_16479122 { +let Inst{12-8} = 0b11110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrh_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), +"$Rd16 = memh($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_4135257 { +let Inst{12-11} = 0b00; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadri_sp : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u5_2Imm:$Ii), +"$Rd16 = memw(r29+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_64199 { +let Inst{12-9} = 0b1110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadruh_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), +"$Rd16 = memuh($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_4135257 { +let Inst{12-11} = 0b01; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return : HInst< +(outs), +(ins), +"dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000000; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R30, R29, R31]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_f : HInst< +(outs), +(ins), +"if (!p0) dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_fnew : HInst< +(outs), +(ins), +"if (!p0.new) dealloc_return:nt", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_t : HInst< +(outs), +(ins), +"if (p0) dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000100; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_tnew : HInst< +(outs), +(ins), +"if (p0.new) dealloc_return:nt", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SS1_storeb_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), +"memb($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_13204995 { +let Inst{12-12} = 0b1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S1"; +} +def SS1_storew_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), +"memw($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_11205051 { +let Inst{12-12} = 0b0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S1"; +} +def SS2_allocframe : HInst< +(outs), +(ins u5_3Imm:$Ii), +"allocframe(#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_7884306 { +let Inst{3-0} = 0b0000; +let Inst{12-9} = 0b1110; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R30, R29, R31]; +let Defs = [R30, R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storebi0 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"memb($Rs16+#$Ii) = #0", +PSEUDO, TypeSUBINSN>, Enc_13536408 { +let Inst{12-8} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storebi1 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"memb($Rs16+#$Ii) = #1", +PSEUDO, TypeSUBINSN>, Enc_13536408 { +let Inst{12-8} = 0b10011; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_stored_sp : HInst< +(outs), +(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), +"memd(r29+#$Ii) = $Rtt8", +PSEUDO, TypeSUBINSN>, Enc_9165078 { +let Inst{12-9} = 0b0101; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storeh_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), +"memh($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_1734121 { +let Inst{12-11} = 0b00; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storew_sp : HInst< +(outs), +(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), +"memw(r29+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_6690615 { +let Inst{12-9} = 0b0100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storewi0 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"memw($Rs16+#$Ii) = #0", +PSEUDO, TypeSUBINSN>, Enc_15536400 { +let Inst{12-8} = 0b10000; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storewi1 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"memw($Rs16+#$Ii) = #1", +PSEUDO, TypeSUBINSN>, Enc_15536400 { +let Inst{12-8} = 0b10001; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def V6_MAP_equb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_extractw : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs:$Vu32, IntRegs:$Rs32), +"$Rd32 = vextract($Vu32,$Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let isSolo = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_extractw_128B : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +"$Rd32 = vextract($Vu32,$Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let isSolo = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_extractw_alt : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs:$Vu32, IntRegs:$Rs32), +"$Rd32.w = vextract($Vu32,$Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_extractw_alt_128B : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +"$Rd32.w = vextract($Vu32,$Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_hi : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vss32), +"$Vd32 = hi($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_hi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vss32), +"$Vd32 = hi($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ld0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ld0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ldnt0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32):nt", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ldnt0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32):nt", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ldu0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmemu($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ldu0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmemu($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lo : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vss32), +"$Vd32 = lo($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lo_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vss32), +"$Vd32 = lo($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lvsplatw : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vsplat($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lvsplatw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vsplat($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_and : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = and($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_and_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = and($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_and_n : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = and($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_and_n_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = and($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_not : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4), +"$Qd4 = not($Qs4)", +CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_not_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4), +"$Qd4 = not($Qs4)", +CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_or : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = or($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_or_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = or($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_or_n : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = or($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_or_n_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = or($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_scalar2 : HInst< +(outs VecPredRegs:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { +let Inst{13-2} = 0b000000010001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_scalar2_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { +let Inst{13-2} = 0b000000010001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_xor : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = xor($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000011; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_xor_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = xor($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000011; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_st0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_st0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stn0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Os8), +"vmem($Rt32) = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 1; +} +def V6_stn0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +"vmem($Rt32) = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def V6_stnnt0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Os8), +"vmem($Rt32):nt = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 1; +} +def V6_stnnt0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +"vmem($Rt32):nt = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def V6_stnp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnpnt0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnpnt0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnq0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnq0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnqnt0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnqnt0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnt0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnt0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stpnt0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stpnt0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stq0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stq0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stqnt0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stqnt0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stu0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stu0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stunp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stunp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stup0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stup0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32Ub_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32 = vmemu($Rt32+#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32Ub_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32 = vmemu($Rt32+#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32Ub_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32 = vmemu($Rx32++#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32 = vmemu($Rx32++#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmemu($Rx32++$Mu2)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmemu($Rx32++$Mu2)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_cur_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_cur_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_tmp_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_tmp_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_6Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_tmp_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_7Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_tmp_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_new_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 2; +} +def V6_vS32b_new_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def V6_vS32b_new_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_new_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_new_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001101; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001101; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_new_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_new_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nqpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nqpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_new_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 2; +} +def V6_vS32b_nt_new_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def V6_vS32b_nt_new_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_nt_new_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_nt_new_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001111; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001111; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_nt_new_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_nt_new_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001010; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001010; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_nqpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_nqpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_qpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_qpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_qpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_qpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_6Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_7Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vabsdiffh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vabs($Vu32.h)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vabs($Vu32.h)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vabs($Vu32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vabs($Vu32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsh($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsh($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vabs($Vu32.w)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vabs($Vu32.w)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vabs($Vu32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vabs($Vu32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsw($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsw($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddbnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vadduh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vadduh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_valignb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = valign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_valignb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = valign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_valignbi : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vd32 = valign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_valignbi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vd32 = valign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vand : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vand($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vand_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vand($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandqrt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandqrt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandqrt_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandqrt_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvrt : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qd4 = vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvrt_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qd4 = vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvrt_acc : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qx4 |= vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qx4 |= vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_alt : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_alt_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_alt : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvrt_alt_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasl($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasl($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vasl($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vasl($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaslh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaslh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslw_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vasl($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vasl($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaslw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaslw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasr($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasr($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhbrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhbrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhbrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhubrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhubrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhubrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhubsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhubsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhubsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vasr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vasr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vasrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vasrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrw_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwhrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwhrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwhrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwuhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwuhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwuhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vasr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vasr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vasrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vasrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vassign : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vassign_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vassignp : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32), +"$Vdd32 = $Vuu32", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vassignp_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32), +"$Vdd32 = $Vuu32", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavghrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavghrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavghrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavghrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgubrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgubrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgubrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgubrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguhrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguhrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguhrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguhrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgwrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgwrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgwrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgwrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vccombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vccombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0h : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.uh = vcl0($Vu32.uh)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0h_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.uh = vcl0($Vu32.uh)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0h_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vcl0h($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0h_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vcl0h($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0w : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.uw = vcl0($Vu32.uw)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0w_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.uw = vcl0($Vu32.uw)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0w_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vcl0w($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0w_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vcl0w($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcmov : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32), +"if ($Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcmov_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +"if ($Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isRegSequence = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isRegSequence = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vd0 : HInst< +(outs VectorRegs:$Vd32), +(ins), +"$Vd32 = #0", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vd0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins), +"$Vd32 = #0", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdeal : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vdeal($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vdeal_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vdeal($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vdealb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.b = vdeal($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb4w_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdealb4w($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdealb4w($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.b = vdeal($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vdealb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vdealb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vdeal($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vdeal($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vdealh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vdealh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealvdd : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealvdd_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdelta : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdelta_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_dv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_dv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhisat : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhisat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhisat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhisat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsuisat : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsuisat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsuisat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsuisat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsusat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsusat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsusat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsusat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhvsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhvsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhvsat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhvsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdsaduh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdsaduh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdsaduh_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdsaduh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgth_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgth_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtub_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtub_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtuh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtuh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtuw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtuw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vhist : HInst< +(outs), +(ins), +"vhist", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vhist_128B : HInst< +(outs), +(ins), +"vhist", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vhistq : HInst< +(outs), +(ins VecPredRegs:$Qv4), +"vhist($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vhistq_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4), +"vhist($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vinsertwr : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, IntRegs:$Rt32), +"$Vx32.w = vinsert($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b100000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vinsertwr_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"$Vx32.w = vinsert($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b100000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlalignb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlalignb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlalignbi : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlalignbi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vlsrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vlsrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vlsrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vlsrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvvb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvvb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvvb_oracc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvvb_oracc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvwh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvwh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvwh_oracc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vlutvwh_oracc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmaxh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmax($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmax($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmax($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmax($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmin($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmin($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmin($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmin($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabusv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabusv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabusv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vmpabus($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabusv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vmpabus($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabuuv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuuv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabuuv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuuv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpahb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpahb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpahb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpahb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybusv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybusv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybusv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybusv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyewuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyewuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyewuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyewuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhsat_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsrs : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhsrs_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhsrs_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhsrs_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhss : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhss_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhss_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhss_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhvsrs : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhvsrs_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhvsrs_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhvsrs_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyieoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyieoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiewh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyiewh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyiewh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiewuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiewuh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiewuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyih : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyih_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyih_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyih_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyihb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyihb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyihb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyihb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiowh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiowh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiowh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyiowh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiowh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyiowh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_rnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_rnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd_sacc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyub : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyub_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyub_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyub_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyubv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyubv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyubv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyubv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuh_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuhv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuhv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuhv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuhv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmux : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmux_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnccombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnccombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vncmov : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32), +"if (!$Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vncmov_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +"if (!$Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamth : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vnormamt($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamth_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vnormamt($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamth_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnormamth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamth_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnormamth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamtw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vnormamt($Vu32.w)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamtw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vnormamt($Vu32.w)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamtw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnormamtw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamtw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnormamtw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnot : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnot($Vu32)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnot_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnot($Vu32)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vor : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vor_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhb_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhb_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhb_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhb_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhub_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhub_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhub_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhub_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackob : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackob_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackob_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackob_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackoh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackoh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwuh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwuh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwuh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwuh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpopcounth : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vpopcount($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpopcounth_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vpopcount($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpopcounth_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vpopcounth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpopcounth_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vpopcounth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrdelta : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrdelta_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybus : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybus_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybus_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybus_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyub_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vror : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vror($Vu32,$Rt32)", +CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vror_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vror($Vu32,$Rt32)", +CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrsadubi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrsadubi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrsadubi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrsadubi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsathub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsathub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsathub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsathub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsathub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsathub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsat($Vu32.w,$Vv32.w)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsat($Vu32.w,$Vv32.w)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsatwh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsatwh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.h = vsxt($Vu32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.h = vsxt($Vu32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vsxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vsxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.w = vsxt($Vu32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.w = vsxt($Vu32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vsxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vsxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufeh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufeh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufeh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufeh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuff : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vshuff($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vshuff_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vshuff($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vshuffb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.b = vshuff($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.b = vshuff($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vshuffb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vshuffb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffeb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffeb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffeb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffeb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vshuff($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vshuff($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vshuffh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vshuffh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffob : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffob_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffob_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffob_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffvdd : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffvdd_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vshuffoeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vshuffoeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vshuffoeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vshuffoeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubbnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vswap : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vswap_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpybus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpybus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpybus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpybus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyhb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyhb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyhb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyhb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtran2x2_map : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vtrans2x2($Vy32,$Vx32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vtran2x2_map_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vtrans2x2($Vy32,$Vx32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vunpackb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.h = vunpack($Vu32.b)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.h = vunpack($Vu32.b)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.w = vunpack($Vu32.h)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.w = vunpack($Vu32.h)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackob : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32.h |= vunpacko($Vu32.b)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32.h |= vunpacko($Vu32.b)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32 |= vunpackob($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32 |= vunpackob($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32.w |= vunpacko($Vu32.h)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32.w |= vunpacko($Vu32.h)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32 |= vunpackoh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32 |= vunpackoh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackub : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uh = vunpack($Vu32.ub)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackub_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uh = vunpack($Vu32.ub)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackub_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackub($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackub_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackub($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackuh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uw = vunpack($Vu32.uh)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackuh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uw = vunpack($Vu32.uh)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackuh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackuh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackuh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackuh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vxor : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vxor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vxor_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vxor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uh = vzxt($Vu32.ub)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uh = vzxt($Vu32.ub)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vzxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vzxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uw = vzxt($Vu32.uh)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uw = vzxt($Vu32.uh)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vzxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vzxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def Y2_barrier : HInst< +(outs), +(ins), +"barrier", +ST_tc_3stall_SLOT0, TypeST>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b1010100000000000; +let isSoloAX = 1; +let hasSideEffects = 1; +} +def Y2_break : HInst< +(outs), +(ins), +"brkpt", +CR_tc_3x_SLOT3, TypeCR>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b0110110000100000; +let isSolo = 1; +} +def Y2_dccleana : HInst< +(outs), +(ins IntRegs:$Rs32), +"dccleana($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000000; +let isSoloAin1 = 1; +} +def Y2_dccleaninva : HInst< +(outs), +(ins IntRegs:$Rs32), +"dccleaninva($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000010; +let isSoloAin1 = 1; +} +def Y2_dcfetch : HInst< +(outs), +(ins IntRegs:$Rs32), +"dcfetch($Rs32)", +PSEUDO, TypeMAPPING> { +let hasSideEffects = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def Y2_dcfetchbo : HInst< +(outs), +(ins IntRegs:$Rs32, u11_3Imm:$Ii), +"dcfetch($Rs32+#$Ii)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4983213 { +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10010100000; +let addrMode = BaseImmOffset; +let hasSideEffects = 1; +} +def Y2_dcinva : HInst< +(outs), +(ins IntRegs:$Rs32), +"dcinva($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000001; +let isSoloAin1 = 1; +} +def Y2_dczeroa : HInst< +(outs), +(ins IntRegs:$Rs32), +"dczeroa($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000110; +let mayStore = 1; +let isSoloAin1 = 1; +} +def Y2_icinva : HInst< +(outs), +(ins IntRegs:$Rs32), +"icinva($Rs32)", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010110110; +let isSolo = 1; +} +def Y2_isync : HInst< +(outs), +(ins), +"isync", +J_tc_2early_SLOT2, TypeJ>, Enc_0 { +let Inst{13-0} = 0b00000000000010; +let Inst{31-16} = 0b0101011111000000; +let isSolo = 1; +} +def Y2_syncht : HInst< +(outs), +(ins), +"syncht", +ST_tc_ld_SLOT0, TypeST>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b1010100001000000; +let isSolo = 1; +} +def Y4_l2fetch : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"l2fetch($Rs32,$Rt32)", +ST_tc_3stall_SLOT0, TypeST>, Enc_14620934 { +let Inst{7-0} = 0b00000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100110000; +let isSoloAX = 1; +let mayStore = 1; +let hasSideEffects = 1; +} +def Y4_trace : HInst< +(outs), +(ins IntRegs:$Rs32), +"trace($Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01100010010; +let isSoloAX = 1; +} +def Y5_l2fetch : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"l2fetch($Rs32,$Rtt32)", +ST_tc_3stall_SLOT0, TypeST>, Enc_8943121, Requires<[HasV5T]> { +let Inst{7-0} = 0b00000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100110100; +let isSoloAX = 1; +let mayStore = 1; +let hasSideEffects = 1; +} +def dep_A2_addsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32):sat:deprecated", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def dep_A2_subsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32):sat:deprecated", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def dep_S2_packhl : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = packhl($Rs32,$Rt32):deprecated", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010100000; +} diff --git a/lib/Target/Hexagon/HexagonDepMappings.td b/lib/Target/Hexagon/HexagonDepMappings.td new file mode 100644 index 00000000000..77a56a9adf1 --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepMappings.td @@ -0,0 +1,654 @@ +//===--- HexagonDepMappings.td --------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def A2_negAlias : InstAlias<"$Rd32=neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>; +def A2_notAlias : InstAlias<"$Rd32=not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>; +def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_vaddb_mapAlias : InstAlias<"$Rdd32=vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_vsubb_mapAlias : InstAlias<"$Rdd32=vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_zxtbAlias : InstAlias<"$Rd32=zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>; +def C2_cmpltAlias : InstAlias<"$Pd4=cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_cmpltuAlias : InstAlias<"$Pd4=cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_pxfer_mapAlias : InstAlias<"$Pd4=$Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>; +def J2_jumpf_nopred_mapAlias : InstAlias<"if (!$Pu4) jump $Ii", (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii)>; +def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>; +def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>; +def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>; +def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32=memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32=memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32=membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32=membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32=memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32=memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrb_zomapAlias : InstAlias<"$Rd32=memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrd_zomapAlias : InstAlias<"$Rdd32=memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrh_zomapAlias : InstAlias<"$Rd32=memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadri_zomapAlias : InstAlias<"$Rd32=memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrub_zomapAlias : InstAlias<"$Rd32=memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadruh_zomapAlias : InstAlias<"$Rd32=memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32)+=$Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32)+=$Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32)+=$Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32)&=$Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32)&=$Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32)&=$Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32)+=#$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32)+=#$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32)+=#$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32)=clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32)=clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32)=clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32)=setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32)=setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32)=setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=#$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=#$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=#$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32)|=$Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32)|=$Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32)|=$Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=$Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=$Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=$Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def M2_mpyuiAlias : InstAlias<"$Rd32=mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>; +def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerb_zomapAlias : InstAlias<"memb($Rs32)=$Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32)=$Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storerd_zomapAlias : InstAlias<"memd($Rs32)=$Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_storerf_zomapAlias : InstAlias<"memh($Rs32)=$Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerh_zomapAlias : InstAlias<"memh($Rs32)=$Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32)=$Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storeri_zomapAlias : InstAlias<"memw($Rs32)=$Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32)=$Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32=tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>; +def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32)=#$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=#$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=#$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=#$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=#$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32)=#$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=#$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=#$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=#$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=#$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32)=#$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; +def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; +def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>; diff --git a/lib/Target/Hexagon/HexagonDepOperands.td b/lib/Target/Hexagon/HexagonDepOperands.td new file mode 100644 index 00000000000..2835d3beb2c --- /dev/null +++ b/lib/Target/Hexagon/HexagonDepOperands.td @@ -0,0 +1,141 @@ +//===--- HexagonDepOperands.td --------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } +def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; +def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; } +def s29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 3>(N->getSExtValue());}]>; +def s10_6ImmOperand : AsmOperandClass { let Name = "s10_6Imm"; let RenderMethod = "addSignedImmOperands"; } +def s10_6Imm : Operand<i32> { let ParserMatchClass = s10_6ImmOperand; let DecoderMethod = "s10_6ImmDecoder"; } +def s10_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 6>(N->getSExtValue());}]>; +def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } +def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; +def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def a30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } +def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; +def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; } +def s8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<8, 0>(N->getSExtValue());}]>; +def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; } +def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>; +def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } +def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; +def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } +def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; +def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b15_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<15, 2>(N->getSExtValue());}]>; +def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } +def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u11_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; +def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } +def s4_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; +def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } +def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def m32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } +def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u3_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; +def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; } +def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u1_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>; +def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; } +def s31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 1>(N->getSExtValue());}]>; +def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; } +def s30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; } +def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>; +def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; } +def s6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 0>(N->getSExtValue());}]>; +def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } +def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; +def s4_7ImmOperand : AsmOperandClass { let Name = "s4_7Imm"; } +def s4_7Imm : Operand<i32> { let ParserMatchClass = s4_7ImmOperand; let DecoderMethod = "s4_7ImmDecoder"; let PrintMethod = "prints4_7ImmOperand"; } +def s4_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 7>(N->getSExtValue());}]>; +def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; } +def s32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } +def s6_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; +def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; } +def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>; +def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; } +def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; let DecoderMethod = "s3_6ImmDecoder"; let PrintMethod = "prints3_6ImmOperand"; } +def s3_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 6>(N->getSExtValue());}]>; +def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } +def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; +def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } +def s4_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; +def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } +def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u16_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; +def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; } +def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>; +def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; } +def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>; +def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } +def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u26_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; +def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } +def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; +def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } +def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u7_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; +def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b13_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; +def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } +def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; +def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } +def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u2_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; +def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } +def s4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; +def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } +def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; +def s3_7ImmOperand : AsmOperandClass { let Name = "s3_7Imm"; } +def s3_7Imm : Operand<i32> { let ParserMatchClass = s3_7ImmOperand; let DecoderMethod = "s3_7ImmDecoder"; let PrintMethod = "prints3_7ImmOperand"; } +def s3_7ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 7>(N->getSExtValue());}]>; +def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } +def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; +def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; } +def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; let DecoderMethod = "s4_6ImmDecoder"; let PrintMethod = "prints4_6ImmOperand"; } +def s4_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 6>(N->getSExtValue());}]>; +def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; } +def s10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 0>(N->getSExtValue());}]>; diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index d0aa62132bc..39c2a6e4f5a 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -7,29 +7,6 @@ // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Hexagon Instruction Flags + -// -// *** Must match HexagonBaseInfo.h *** -//===----------------------------------------------------------------------===// - -class IType<bits<6> t> { - bits<6> Value = t; -} -def TypePSEUDO : IType<0>; -def TypeCR : IType<2>; -def TypeJ : IType<4>; -def TypeLD : IType<5>; -def TypeST : IType<6>; -def TypeENDLOOP: IType<40>; -def TypeS_2op: IType<41>; -def TypeS_3op: IType<42>; -def TypeALU64: IType<43>; -def TypeM: IType<44>; -def TypeALU32_2op: IType<45>; -def TypeALU32_3op: IType<46>; -def TypeALU32_ADDI: IType<47>; - // Maintain list of valid subtargets for each instruction. class SubTarget<bits<6> value> { bits<6> Value = value; @@ -57,6 +34,7 @@ class MemAccessSize<bits<4> value> { bits<4> Value = value; } +// MemAccessSize is represented as 1+log2(N) where N is size in bits. def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction. def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). @@ -73,10 +51,9 @@ def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv) class OpcodeHexagon { field bits<32> Inst = ?; // Default to an invalid insn. bits<4> IClass = 0; // ICLASS + bits<1> zero = 0; let Inst{31-28} = IClass; - - bits<1> zero = 0; } class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, @@ -182,6 +159,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bits<1> isAccumulator = 0; let TSFlags{55} = isAccumulator; + bits<1> prefersSlot3 = 0; + let TSFlags{56} = prefersSlot3; // Complex XU + bit cofMax1 = 0; let TSFlags{60} = cofMax1; @@ -207,6 +187,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } +class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> : + InstHexagon<outs, ins, asmstr, [], "", itin, type>; + //===----------------------------------------------------------------------===// // Instruction Classes Definitions + //===----------------------------------------------------------------------===// @@ -218,14 +201,13 @@ class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; -let mayLoad = 1 in -class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; +class PseudoLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; + : PseudoLDInst<outs, ins, asmstr, pattern, cstr>; // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. @@ -251,6 +233,11 @@ class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; +let mayStore = 1 in +class STInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; + class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> : STInst<outs, ins, asmstr, pattern, cstr>; @@ -273,25 +260,6 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> : STInst<outs, ins, asmstr, pattern, cstr, itin>; -// SYSTEM Instruction Class in V4 can take SLOT0 only -// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. -class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, - OpcodeHexagon; - -// ALU32 Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. -class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>, OpcodeHexagon; - -// ALU32 Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. -class ALU32Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32_2op>; - // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. @@ -374,12 +342,6 @@ class JInst_CJUMP_UCJUMP<dag outs, dag ins, string asmstr, list<dag> pattern = [ string cstr = "", InstrItinClass itin = J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon; -// JR Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. -class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon; - // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -408,26 +370,6 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Instruction Classes Definitions - //===----------------------------------------------------------------------===// - -// -// ALU32 patterns -//. -class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - // // ALU64 patterns. // diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/lib/Target/Hexagon/HexagonInstrFormatsV4.td index 688e6d93bf1..1fdf930c62f 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -11,18 +11,6 @@ // //===----------------------------------------------------------------------===// -//----------------------------------------------------------------------------// -// Hexagon Instruction Flags -// -// *** Must match BaseInfo.h *** -//----------------------------------------------------------------------------// - -def TypeV4LDST : IType<9>; -def TypeNCJ : IType<10>; -def TypeDUPLEX : IType<11>; -def TypeCJ : IType<12>; -def TypeEXTENDER : IType<39>; - // Duplex Instruction Class Declaration //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/lib/Target/Hexagon/HexagonInstrFormatsV60.td index b9f4373a0b7..c8a7faea5ed 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -12,28 +12,6 @@ //===----------------------------------------------------------------------===// //----------------------------------------------------------------------------// -// Hexagon Instruction Flags + -// -// *** Must match BaseInfo.h *** -//----------------------------------------------------------------------------// - -def TypeCVI_VA : IType<13>; -def TypeCVI_VA_DV : IType<14>; -def TypeCVI_VX : IType<15>; -def TypeCVI_VX_DV : IType<16>; -def TypeCVI_VP : IType<17>; -def TypeCVI_VP_VS : IType<18>; -def TypeCVI_VS : IType<19>; -def TypeCVI_VINLANESAT : IType<20>; -def TypeCVI_VM_LD : IType<21>; -def TypeCVI_VM_TMP_LD : IType<22>; -def TypeCVI_VM_CUR_LD : IType<23>; -def TypeCVI_VM_VP_LDU : IType<24>; -def TypeCVI_VM_ST : IType<25>; -def TypeCVI_VM_NEW_ST : IType<26>; -def TypeCVI_VM_STU : IType<27>; -def TypeCVI_HIST : IType<28>; -//----------------------------------------------------------------------------// // Instruction Classes Definitions + //----------------------------------------------------------------------------// diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 813f4f81b41..15590174980 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -3419,7 +3419,9 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const { return NVOpcode; switch (MI.getOpcode()) { - default: llvm_unreachable("Unknown .new type"); + default: + llvm::report_fatal_error(std::string("Unknown .new type: ") + + std::to_string(MI.getOpcode()).c_str()); case Hexagon::S4_storerb_ur: return Hexagon::S4_storerbnew_ur; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td deleted file mode 100644 index ece8e3b5cd3..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ /dev/null @@ -1,4796 +0,0 @@ -//==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -include "HexagonInstrFormats.td" -include "HexagonOperands.td" -include "HexagonInstrEnc.td" - -//===----------------------------------------------------------------------===// -// Compare -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1, - opExtendable = 2 in -class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp> - : ALU32Inst <(outs PredRegs:$dst), - (ins IntRegs:$src1, ImmOp:$src2), - "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)", - [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel { - bits<2> dst; - bits<5> src1; - bits<10> src2; - let CextOpcode = mnemonic; - let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10); - let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1); - - let IClass = 0b0111; - - let Inst{27-24} = 0b0101; - let Inst{23-22} = MajOp; - let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9}); - let Inst{20-16} = src1; - let Inst{13-5} = src2{8-0}; - let Inst{4} = isNot; - let Inst{3-2} = 0b00; - let Inst{1-0} = dst; - } - -def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10_0Ext>; -def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10_0Ext>; -def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9_0Ext>; - -//===----------------------------------------------------------------------===// -// ALU32/ALU + -//===----------------------------------------------------------------------===// -// Add. - -let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in -class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev, - bit IsComm> - : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel { - let isCommutable = IsComm; - let BaseOpcode = mnemonic#_rr; - let CextOpcode = mnemonic; - let Type = TypeALU32_3op; - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1111; - let Inst{27} = 0b0; - let Inst{26-24} = MajOp; - let Inst{23-21} = MinOp; - let Inst{20-16} = !if(OpsRev,Rt,Rs); - let Inst{12-8} = !if(OpsRev,Rs,Rt); - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev, bit PredNot, bit PredNew> - : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), - "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "# - "$Rd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { - let isPredicated = 1; - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - let BaseOpcode = mnemonic#_rr; - let CextOpcode = mnemonic; - let Type = TypeALU32_3op; - - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1111; - let Inst{27} = 0b1; - let Inst{26-24} = MajOp; - let Inst{23-21} = MinOp; - let Inst{20-16} = !if(OpsRev,Rt,Rs); - let Inst{13} = PredNew; - let Inst{12-8} = !if(OpsRev,Rs,Rt); - let Inst{7} = PredNot; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> - : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> { - let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")"; -} - -def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>; -def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>; -def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>; -def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>; - -class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp, - bits<3> MinOp, bit OpsRev, bit IsComm> - : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> { - let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix; -} - -def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>; -def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>; - -let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in { - def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>; - def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; - def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>; - def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>; - def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>; - def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>; -} - -let Itinerary = ALU32_3op_tc_2_SLOT0123 in -def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>; - -def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>; -def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>; - -multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> { - def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>; - def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>; - def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>; - def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>; -} - -multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev, bit IsComm> { - let isPredicable = 1 in - def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>; - defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>; -} - -defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; -defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; -defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; -defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; -defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; - -// A few special cases producing register pairs: -let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in { - def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>; - - let isPredicable = 1 in - def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>; - - // Conditional combinew uses "newt/f" instead of "t/fnew". - def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>; - def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>; - def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>; - def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>; -} - -let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in -class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm> - : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { - let CextOpcode = mnemonic; - let isCommutable = IsComm; - let Type = TypeALU32_3op; - bits<5> Rs; - bits<5> Rt; - bits<2> Pd; - - let IClass = 0b1111; - let Inst{27-24} = 0b0010; - let Inst{22-21} = MinOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4} = IsNeg; - let Inst{3-2} = 0b00; - let Inst{1-0} = Pd; -} - -let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { - def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; - def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; - def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; -} - -let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in -def C2_mux: ALU32_rr<(outs IntRegs:$Rd), - (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), - "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - - let CextOpcode = "mux"; - let InputType = "reg"; - let hasSideEffects = 0; - let IClass = 0b1111; - let Type = TypeALU32_3op; - - let Inst{27-24} = 0b0100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -// Combines the two immediates into a double register. -// Increase complexity to make it greater than any complexity of a combine -// that involves a register. - -let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1, - AddedComplexity = 75 in -def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8_0Ext:$s8, s8_0Imm:$S8), - "$Rdd = combine(#$s8, #$S8)", - []> { - bits<5> Rdd; - bits<8> s8; - bits<8> S8; - - let IClass = 0b0111; - let Inst{27-23} = 0b11000; - let Inst{22-16} = S8{7-1}; - let Inst{13} = S8{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated ADD of a reg and an Immediate value. -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_Addri_Pred <bit PredNot, bit PredNew> - : ALU32_ri <(outs IntRegs:$Rd), - (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8), - !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ", - ") $Rd = ")#"add($Rs, #$s8)"> { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<8> s8; - - let isPredicatedNew = PredNew; - let IClass = 0b0111; - - let Inst{27-24} = 0b0100; - let Inst{23} = PredNot; - let Inst{22-21} = Pu; - let Inst{20-16} = Rs; - let Inst{13} = PredNew; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// A2_addi: Add a signed immediate to a register. -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_Addri <Operand immOp> - : ALU32_ri <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, immOp:$s16), - "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> { - let Type = TypeALU32_ADDI; - bits<5> Rd; - bits<5> Rs; - bits<16> s16; - - let IClass = 0b1011; - - let Inst{27-21} = s16{15-9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s16{8-0}; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// Multiclass for ADD of a register and an immediate value. -//===----------------------------------------------------------------------===// -multiclass Addri_Pred<string mnemonic, bit PredNot> { - let isPredicatedFalse = PredNot in { - def NAME : T_Addri_Pred<PredNot, 0>; - // Predicate new - def NAME#new : T_Addri_Pred<PredNot, 1>; - } -} - -let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in -multiclass Addri_base<string mnemonic, SDNode OpNode> { - let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in { - let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in - def A2_#NAME : T_Addri<s16_0Ext>; - - let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in { - defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>; - defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>; - } - } -} - -defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel; - -let hasNewValue = 1, hasSideEffects = 0, isPseudo = 1 in -def A2_iconst - : ALU32_ri <(outs IntRegs:$Rd), - (ins s23_2Imm:$s23_2), - "$Rd = iconst(#$s23_2)"> {} - -//===----------------------------------------------------------------------===// -// Template class used for the following ALU32 instructions. -// Rd=and(Rs,#s10) -// Rd=or(Rs,#s10) -//===----------------------------------------------------------------------===// -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10, -InputType = "imm", hasNewValue = 1 in -class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp> - : ALU32_ri <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, s10_0Ext:$s10), - "$Rd = "#mnemonic#"($Rs, #$s10)" , - []> { - bits<5> Rd; - bits<5> Rs; - bits<10> s10; - let CextOpcode = mnemonic; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0110; - let Inst{23-22} = MinOp; - let Inst{21} = s10{9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rd; - } - -def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel; -def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel; - -// Subtract register from immediate -// Rd32=sub(#s10,Rs32) -let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1, - opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in -def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10_0Ext:$s10, IntRegs:$Rs), - "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel { - bits<5> Rd; - bits<10> s10; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-22} = 0b011001; - let Inst{21} = s10{9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rd; - } - -// Nop. -let hasSideEffects = 0 in -def A2_nop: ALU32Inst <(outs), (ins), "nop" > { - let IClass = 0b0111; - let Inst{27-24} = 0b1111; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_tfr16<bit isHi> - : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16_0Imm:$u16), - "$Rx"#!if(isHi, ".h", ".l")#" = #$u16", - [], "$src1 = $Rx" > { - bits<5> Rx; - bits<16> u16; - - let IClass = 0b0111; - let Inst{27-26} = 0b00; - let Inst{25-24} = !if(isHi, 0b10, 0b01); - let Inst{23-22} = u16{15-14}; - let Inst{21} = 0b1; - let Inst{20-16} = Rx; - let Inst{13-0} = u16{13-0}; - } - -def A2_tfril: T_tfr16<0>; -def A2_tfrih: T_tfr16<1>; - -// Conditional transfer is an alias to conditional "Rd = add(Rs, #0)". -let isPredicated = 1, hasNewValue = 1, isCodeGenOnly = 1, opNewValue = 0, - isPseudo = 1 in -class T_tfr_pred<bit isPredNot, bit isPredNew> - : ALU32Inst<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2), - ""> { - bits<5> dst; - bits<2> src1; - bits<5> src2; - - let isPredicatedFalse = isPredNot; - let isPredicatedNew = isPredNew; - let IClass = 0b0111; - - let Inst{27-24} = 0b0100; - let Inst{23} = isPredNot; - let Inst{13} = isPredNew; - let Inst{12-5} = 0; - let Inst{4-0} = dst; - let Inst{22-21} = src1; - let Inst{20-16} = src2; - } - -let isPredicable = 1 in -class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src), - "$dst = $src"> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0111; - - let Inst{27-21} = 0b0000011; - let Inst{20-16} = src; - let Inst{13} = 0b0; - let Inst{4-0} = dst; - } - -let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in -multiclass tfr_base<string CextOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp in { - def NAME : T_tfr; - - // Predicate - def t : T_tfr_pred<0, 0>; - def f : T_tfr_pred<1, 0>; - // Predicate new - def tnew : T_tfr_pred<0, 1>; - def fnew : T_tfr_pred<1, 1>; - } -} - -// Assembler mapped to C2_ccombinew[t|f|newt|newf]. -// Please don't add bits to this instruction as it'll be converted into -// 'combine' before object code emission. -let isPredicated = 1 in -class T_tfrp_pred<bit PredNot, bit PredNew> - : ALU32_rr <(outs DoubleRegs:$dst), - (ins PredRegs:$src1, DoubleRegs:$src2), - "if ("#!if(PredNot, "!", "")#"$src1" - #!if(PredNew, ".new", "")#") $dst = $src2" > { - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - } - -// Assembler mapped to A2_combinew. -// Please don't add bits to this instruction as it'll be converted into -// 'combine' before object code emission. -class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst), - (ins DoubleRegs:$src), - "$dst = $src">; - -let hasSideEffects = 0 in -multiclass TFR64_base<string BaseName> { - let BaseOpcode = BaseName in { - let isPredicable = 1 in - def NAME : T_tfrp; - // Predicate - def t : T_tfrp_pred <0, 0>; - def f : T_tfrp_pred <1, 0>; - // Predicate new - def tnew : T_tfrp_pred <0, 1>; - def fnew : T_tfrp_pred <1, 1>; - } -} - -def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; - -let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12, - isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR", - hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in -class T_TFRI_Pred<bit PredNot, bit PredNew> - : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12_0Ext:$s12), - "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12", - [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - - bits<5> Rd; - bits<2> Pu; - bits<12> s12; - - let IClass = 0b0111; - let Inst{27-24} = 0b1110; - let Inst{23} = PredNot; - let Inst{22-21} = Pu; - let Inst{20} = 0b0; - let Inst{19-16,12-5} = s12; - let Inst{13} = PredNew; - let Inst{4-0} = Rd; -} - -def C2_cmoveit : T_TFRI_Pred<0, 0>; -def C2_cmoveif : T_TFRI_Pred<1, 0>; -def C2_cmovenewit : T_TFRI_Pred<0, 1>; -def C2_cmovenewif : T_TFRI_Pred<1, 1>; - -let InputType = "imm", isExtendable = 1, isExtentSigned = 1, - CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0, - isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1, - isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in -def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16_0Ext:$s16), "$Rd = #$s16", - [], "", ALU32_2op_tc_1_SLOT0123>, - ImmRegRel, PredRel { - bits<5> Rd; - bits<16> s16; - - let IClass = 0b0111; - let Inst{27-24} = 0b1000; - let Inst{23-22,20-16,13-5} = s16; - let Inst{4-0} = Rd; -} - -defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel; -let isAsmParserOnly = 1 in -defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel; - -// Assembler mapped -let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, - isAsmParserOnly = 1 in -def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8_0Imm64:$src1), - "$dst = #$src1", - []>; - -// TODO: see if this instruction can be deleted.. -let isExtendable = 1, opExtendable = 1, opExtentBits = 6, - isAsmParserOnly = 1 in { -def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1), - "$dst = #$src1">; -def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), - (ins s8_0Ext:$src1, s8_0Imm:$src2), - "$dst = combine(##$src1, #$src2)">; -} - -//===----------------------------------------------------------------------===// -// ALU32/ALU - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PERM + -//===----------------------------------------------------------------------===// -// Scalar mux register immediate. -let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX", - InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in -class T_MUX1 <bit MajOp, dag ins, string AsmStr> - : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel { - bits<5> Rd; - bits<2> Pu; - bits<8> s8; - bits<5> Rs; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{23} = MajOp; - let Inst{22-21} = Pu; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; -} - -let opExtendable = 2 in -def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8_0Ext:$s8, IntRegs:$Rs), - "$Rd = mux($Pu, #$s8, $Rs)">; - -let opExtendable = 3 in -def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8), - "$Rd = mux($Pu, $Rs, #$s8)">; - -// C2_muxii: Scalar mux immediates. -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, - opExtentBits = 8, opExtendable = 2 in -def C2_muxii: ALU32Inst <(outs IntRegs:$Rd), - (ins PredRegs:$Pu, s8_0Ext:$s8, s8_0Imm:$S8), - "$Rd = mux($Pu, #$s8, #$S8)" , - []> { - bits<5> Rd; - bits<2> Pu; - bits<8> s8; - bits<8> S8; - - let IClass = 0b0111; - - let Inst{27-25} = 0b101; - let Inst{24-23} = Pu; - let Inst{22-16} = S8{7-1}; - let Inst{13} = S8{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; - } - -let isCodeGenOnly = 1, isPseudo = 1 in -def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd), - (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), - ".error \"should not emit\" ", []>; - - -//===----------------------------------------------------------------------===// -// template class for non-predicated alu32_2op instructions -// - aslh, asrh, sxtb, sxth, zxth -//===----------------------------------------------------------------------===// -let hasNewValue = 1, opNewValue = 0 in -class T_ALU32_2op <string mnemonic, bits<3> minOp> : - ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = "#mnemonic#"($Rs)", [] > { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0000; - let Inst{23-21} = minOp; - let Inst{13} = 0b0; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; -} - -//===----------------------------------------------------------------------===// -// template class for predicated alu32_2op instructions -// - aslh, asrh, sxtb, sxth, zxtb, zxth -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot, - bit isPredNew > : - ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs), - !if(isPredNot, "if (!$Pu", "if ($Pu") - #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0000; - let Inst{23-21} = minOp; - let Inst{13} = 0b1; - let Inst{11} = isPredNot; - let Inst{10} = isPredNew; - let Inst{4-0} = Rd; - let Inst{9-8} = Pu; - let Inst{20-16} = Rs; -} - -multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> { - let isPredicatedFalse = PredNot in { - def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>; - - // Predicate new - let isPredicatedNew = 1 in - def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>; - } -} - -multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { - let BaseOpcode = mnemonic in { - let isPredicable = 1, hasSideEffects = 0 in - def A2_#NAME : T_ALU32_2op<mnemonic, minOp>; - - let isPredicated = 1, hasSideEffects = 0 in { - defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; - defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; - } - } -} - -defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; -defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel; -defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; -defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; -defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; - -// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). -// Compiler would want to generate 'zxtb' instead of 'and' because 'zxtb' has -// predicated forms while 'and' doesn't. Since integrated assembler can't -// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where -// immediate operand is set to '255'. - -let hasNewValue = 1, opNewValue = 0, isPseudo = 1, isCodeGenOnly = 1 in -class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd=zxtb($Rs)", [] >; - -//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255) -multiclass ZXTB_base <string mnemonic, bits<3> minOp> { - let BaseOpcode = mnemonic in { - let isPredicable = 1, hasSideEffects = 0 in - def A2_#NAME : T_ZXTB; - - let isPredicated = 1, hasSideEffects = 0 in { - defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; - defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; - } - } -} - -defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel; - -//===----------------------------------------------------------------------===// -// Template class for vector add and avg -//===----------------------------------------------------------------------===// - -class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp, - bit isSat, bit isRnd, bit isCrnd, bit SwapOps > - : ALU64_rr < (outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "") - #!if(isCrnd,":crnd","") - #!if(isSat, ":sat", ""), - [], "", ALU64_tc_2_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-24} = 0b0011; - let Inst{23-21} = majOp; - let Inst{20-16} = !if (SwapOps, Rtt, Rss); - let Inst{12-8} = !if (SwapOps, Rss, Rtt); - let Inst{7-5} = minOp; - let Inst{4-0} = Rdd; - } - -// ALU64 - Vector add -// Rdd=vadd[u][bhw](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>; - def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; - def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>; -} - -// Rdd=vadd[u][bhw](Rss,Rtt):sat -let Defs = [USR_OVF] in { - def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>; - def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>; - def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>; - def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>; -} - -// ALU64 - Vector average -// Rdd=vavg[u][bhw](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; - def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; - def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; - def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>; - def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>; -} - -// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd] -def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; -def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; -def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; -def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; - -def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>; -def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; -def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>; - -// Rdd=vnavg[bh](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>; - def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>; -} - -// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat -let Defs = [USR_OVF] in { - def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>; - def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>; - def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>; - def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>; -} - -// Rdd=vsub[u][bh](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>; - def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>; - def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>; -} - -// Rdd=vsub[u][bh](Rss,Rtt):sat -let Defs = [USR_OVF] in { - def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>; - def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>; - def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>; - def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>; -} - -// Rdd=vmax[u][bhw](Rss,Rtt) -def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>; -def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>; -def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>; -def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>; -def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>; -def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>; - -// Rdd=vmin[u][bhw](Rss,Rtt) -def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>; -def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>; -def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>; -def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>; -def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>; -def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>; - -//===----------------------------------------------------------------------===// -// Template class for vector compare -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_vcmp <string Str, bits<4> minOp> - : ALU64_rr <(outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = "#Str#"($Rss, $Rtt)", [], - "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = minOp{3}; - let Inst{7-5} = minOp{2-0}; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector compare bytes -def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>; -def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>; - -// Vector compare halfwords -def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>; -def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>; -def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>; - -// Vector compare words -def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>; -def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>; -def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>; - -//===----------------------------------------------------------------------===// -// ALU32/PERM - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PRED + -//===----------------------------------------------------------------------===// -// No bits needed. If cmp.ge is found the assembler parser will -// transform it to cmp.gt subtracting 1 from the immediate. -let isPseudo = 1 in { -def C2_cmpgei: ALU32Inst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Pd = cmp.ge($Rs, #$s8)">; -def C2_cmpgeui: ALU32Inst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8_0Ext:$s8), - "$Pd = cmp.geu($Rs, #$s8)">; -} - - -//===----------------------------------------------------------------------===// -// ALU32/PRED - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU64/ALU + -//===----------------------------------------------------------------------===// -// Add. -//===----------------------------------------------------------------------===// -// Template Class -// Add/Subtract halfword -// Rd=add(Rt.L,Rs.[HL])[:sat] -// Rd=sub(Rt.L,Rs.[HL])[:sat] -// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] -// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub> - : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), - "$Rd = "#!if(isSub,"sub","add")#"($Rt." - #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs." - #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)")) - #!if(isSat,":sat","") - #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - let IClass = 0b1101; - - let Inst{27-23} = 0b01010; - let Inst{22} = hasShift; - let Inst{21} = isSub; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rd; - let Inst{12-8} = Rt; - let Inst{20-16} = Rs; - } - -//Rd=sub(Rt.L,Rs.[LH]) -def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>; -def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>; - -//Rd=add(Rt.L,Rs.[LH]) -def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>; -def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>; - -let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { - //Rd=sub(Rt.L,Rs.[LH]):sat - def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>; - def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>; - - //Rd=add(Rt.L,Rs.[LH]):sat - def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>; - def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>; -} - -//Rd=sub(Rt.[LH],Rs.[LH]):<<16 -def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>; -def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>; -def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>; -def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>; - -//Rd=add(Rt.[LH],Rs.[LH]):<<16 -def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>; -def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>; -def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>; -def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>; - -let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { - //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 - def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>; - def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>; - def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>; - def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>; - - //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 - def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>; - def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>; - def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>; - def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>; -} - -let hasSideEffects = 0, hasNewValue = 1 in -def S2_parityp: ALU64Inst<(outs IntRegs:$Rd), - (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0000; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in -class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned > - : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), - "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") - #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - - let IClass = 0b1101; - - let Inst{27-23} = 0b01011; - let Inst{22-21} = !if(isMax, 0b10, 0b01); - let Inst{7} = isUnsigned; - let Inst{4-0} = Rd; - let Inst{12-8} = !if(isMax, Rs, Rt); - let Inst{20-16} = !if(isMax, Rt, Rs); - } - -def A2_min : T_XTYPE_MIN_MAX < 0, 0 >; -def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >; -def A2_max : T_XTYPE_MIN_MAX < 1, 0 >; -def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >; - -class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm> - : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> { - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0010100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{1-0} = Pd; -} - -def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>; -def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>; -def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>; - -def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd), - (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { - let hasSideEffects = 0; - - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0001; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType, - bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm, - string Op2Pfx> - : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [], - "", ALU64_tc_1_SLOT23> { - let hasSideEffects = 0; - let isCommutable = IsComm; - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1101; - let Inst{27-24} = RegType; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if (OpsRev,Rt,Rs); - let Inst{12-8} = !if (OpsRev,Rs,Rt); - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat, - bit OpsRev, bit IsComm> - : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev, - IsComm, "">; - -let isAdd = 1 in -def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>; -def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>; - -class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm, - bit IsNeg> - : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm, - !if(IsNeg,"~","")>; - -def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>; -def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>; -def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>; - -//===----------------------------------------------------------------------===// -// ALU64/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/BIT + -//===----------------------------------------------------------------------===// -// -//===----------------------------------------------------------------------===// -// ALU64/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/PERM + -//===----------------------------------------------------------------------===// -// -//===----------------------------------------------------------------------===// -// ALU64/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// CR + -//===----------------------------------------------------------------------===// -// Logical reductions on predicates. - -// Looping instructions. - -// Pipelined looping instructions. - -// Logical operations on predicates. -let hasSideEffects = 0 in -class T_LOGICAL_1OP<string MnOp, bits<2> OpBits> - : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps), - "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - - let IClass = 0b0110; - let Inst{27-23} = 0b10111; - let Inst{22-21} = OpBits; - let Inst{20} = 0b0; - let Inst{17-16} = Ps; - let Inst{13} = 0b0; - let Inst{1-0} = Pd; -} - -def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>; -def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>; -def C2_not : T_LOGICAL_1OP<"not", 0b10>; - -let hasSideEffects = 0 in -class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev> - : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt), - "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)", - [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - bits<2> Pt; - - let IClass = 0b0110; - let Inst{27-24} = 0b1011; - let Inst{23-21} = OpBits; - let Inst{20} = 0b0; - let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some - let Inst{13} = 0b0; // instructions. - let Inst{9-8} = !if(Rev,Ps,Pt); - let Inst{1-0} = Pd; -} - -def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>; -def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>; -def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>; -def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>; -def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>; - -let hasSideEffects = 0, hasNewValue = 1 in -def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt), - "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Ps; - bits<2> Pt; - - let IClass = 0b1000; - let Inst{27-24} = 0b1001; - let Inst{22-21} = 0b00; - let Inst{17-16} = Ps; - let Inst{9-8} = Pt; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt), - "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Pt; - - let IClass = 0b1000; - let Inst{27-24} = 0b0110; - let Inst{9-8} = Pt; - let Inst{4-0} = Rd; -} - -// User control register transfer. -//===----------------------------------------------------------------------===// -// CR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// JR + -//===----------------------------------------------------------------------===// - -class CondStr<string CReg, bit True, bit New> { - string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; -} -class JumpOpcStr<string Mnemonic, bit New, bit Taken> { - string S = Mnemonic # !if(Taken, ":t", ":nt"); -} - -let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, - isPredicable = 1, - isExtendable = 1, opExtendable = 0, isExtentSigned = 1, - opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in -class T_JMP<string ExtStr> - : JInst_CJUMP_UCJUMP<(outs), (ins brtarget:$dst), - "jump " # ExtStr # "$dst", - [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> { - bits<24> dst; - let IClass = 0b0101; - - let Inst{27-25} = 0b100; - let Inst{24-16} = dst{23-15}; - let Inst{13-1} = dst{14-2}; -} - -let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1, - isExtendable = 1, opExtendable = 1, isExtentSigned = 1, - opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in -class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr> - : JInst_CJUMP_UCJUMP<(outs), (ins PredRegs:$src, brtarget:$dst), - CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # - JumpOpcStr<"jump", isPredNew, isTak>.S # " " # - ExtStr # "$dst", - [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>, ImmRegRel { - let isTaken = isTak; - let isPredicatedFalse = PredNot; - let isPredicatedNew = isPredNew; - bits<2> src; - bits<17> dst; - - let IClass = 0b0101; - - let Inst{27-24} = 0b1100; - let Inst{21} = PredNot; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{9-8} = src; - let Inst{23-22} = dst{16-15}; - let Inst{20-16} = dst{14-10}; - let Inst{13} = dst{9}; - let Inst{7-1} = dst{8-2}; - } - -multiclass JMP_Pred<bit PredNot, string ExtStr> { - def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken - // Predicate new - def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken - def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken -} - -multiclass JMP_base<string BaseOp, string ExtStr> { - let BaseOpcode = BaseOp in { - def NAME : T_JMP<ExtStr>; - defm t : JMP_Pred<0, ExtStr>; - defm f : JMP_Pred<1, ExtStr>; - } -} - -// Jumps to address stored in a register, JUMPR_MISC -// if ([[!]P[.new]]) jumpr[:t/nt] Rs -let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], - isPredicable = 1, hasSideEffects = 0, InputType = "reg" in -class T_JMPr - : JRInst<(outs), (ins IntRegs:$dst), - "jumpr $dst", [], "", J_tc_2early_SLOT2> { - bits<5> dst; - - let IClass = 0b0101; - let Inst{27-21} = 0b0010100; - let Inst{20-16} = dst; -} - -let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, - hasSideEffects = 0, InputType = "reg" in -class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> - : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst), - CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # - JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [], - "", J_tc_2early_SLOT2> { - - let isTaken = isTak; - let isPredicatedFalse = PredNot; - let isPredicatedNew = isPredNew; - bits<2> src; - bits<5> dst; - - let IClass = 0b0101; - - let Inst{27-22} = 0b001101; - let Inst{21} = PredNot; - let Inst{20-16} = dst; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{9-8} = src; -} - -multiclass JMPR_Pred<bit PredNot> { - def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken - // Predicate new - def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken - def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken -} - -multiclass JMPR_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def NAME : T_JMPr; - defm t : JMPR_Pred<0>; - defm f : JMPR_Pred<1>; - } -} - -let isCall = 1, hasSideEffects = 1 in -class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, - dag InputDag = (ins IntRegs:$Rs)> - : JRInst<(outs), InputDag, - !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", - "if ($Pu) callr $Rs"), - "callr $Rs"), - [], "", J_tc_2early_SLOT2> { - bits<5> Rs; - bits<2> Pu; - let isPredicated = isPred; - let isPredicatedFalse = isPredNot; - - let IClass = 0b0101; - let Inst{27-25} = 0b000; - let Inst{24-23} = !if (isPred, 0b10, 0b01); - let Inst{22} = 0; - let Inst{21} = isPredNot; - let Inst{9-8} = !if (isPred, Pu, 0b00); - let Inst{20-16} = Rs; - - } - -let Defs = VolatileV3.Regs in { - def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>; - def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>; -} - -let isTerminator = 1, hasSideEffects = 0 in { - defm J2_jump : JMP_base<"JMP", "">, PredNewRel; - - defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel; - - let isReturn = 1, isPseudo = 1, isCodeGenOnly = 1 in - defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel; -} - -let validSubTargets = HasV60SubT in -multiclass JMPpt_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def tpt : T_JMP_c <0, 0, 1, "">; // Predicate true - taken - def fpt : T_JMP_c <1, 0, 1, "">; // Predicate false - taken - } -} - -let validSubTargets = HasV60SubT in -multiclass JMPRpt_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def tpt : T_JMPr_c<0, 0, 1>; // predicate true - taken - def fpt : T_JMPr_c<1, 0, 1>; // predicate false - taken - } -} - -defm J2_jumpr : JMPRpt_base<"JMPr">; -defm J2_jump : JMPpt_base<"JMP">; - -// A return through builtin_eh_return. -let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, - isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in -def EH_RETURN_JMPR : T_JMPr; - -//===----------------------------------------------------------------------===// -// JR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// LD + -//===----------------------------------------------------------------------===// - -// Load - Base with Immediate offset addressing mode -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in -class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp, - Operand ImmOp> - : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset), - "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel { - bits<4> name; - bits<5> dst; - bits<5> src1; - bits<14> offset; - bits<11> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3}, - !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2}, - !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1}, - /* s11_0Ext */ offset{10-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, - !if (!eq(ImmOpStr, "s11_2Ext"), 13, - !if (!eq(ImmOpStr, "s11_1Ext"), 12, - /* s11_0Ext */ 11))); - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in -class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp, - Operand ImmOp, bit isNot, bit isPredNew> - : LDInst<(outs RC:$dst), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "if ("#!if(isNot, "!$src1", "$src1") - #!if(isPredNew, ".new", "") - #") $dst = "#mnemonic#"($src2 + #$offset)", - [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<9> offset; - bits<6> offsetBits; - string ImmOpStr = !cast<string>(ImmOp); - - let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3}, - !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2}, - !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1}, - /* u6_0Ext */ offset{5-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, - !if (!eq(ImmOpStr, "u6_2Ext"), 8, - !if (!eq(ImmOpStr, "u6_1Ext"), 7, - /* u6_0Ext */ 6))); - let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isNot; - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{27} = 0b0; - let Inst{26} = isNot; - let Inst{25} = isPredNew; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b0; - let Inst{12-11} = src1; - let Inst{10-5} = offsetBits; - let Inst{4-0} = dst; - } - -let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in -multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<4>MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - let isPredicable = 1 in - def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>; - - // Predicated - def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>; - def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>; - - // Predicated new - def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>; - def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>; - } -} - -let accessSize = ByteAccess in { - defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>; - defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; -} - -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>; - defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>; -} - -let accessSize = WordAccess, opExtentAlign = 2 in -defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>; - -let accessSize = DoubleWordAccess, opExtentAlign = 3 in -defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>; - def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>; -} - -let accessSize = WordAccess, opExtentAlign = 2 in { - def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>; - def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>; -} - -let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0, - opExtendable = 3, isExtentSigned = 1 in -class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp> - : LDInst<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "$dst = "#str#"($src2 + #$offset)", [], - "$src1 = $dst">, AddrModeRel { - bits<4> name; - bits<5> dst; - bits<5> src2; - bits<12> offset; - bits<11> offsetBits; - - let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1}, - /* s11_0Ext */ offset{10-0}); - let IClass = 0b1001; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in -def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>; - -let accessSize = ByteAccess, opExtentBits = 11 in -def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>; - -//===----------------------------------------------------------------------===// -// Post increment load -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment loads with immediate offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp > - : LDInstPI <(outs RC:$dst, IntRegs:$dst2), - (ins IntRegs:$src1, ImmOp:$offset), - "$dst = "#mnemonic#"($src1++#$offset)" , - [], - "$src1 = $dst2" > , - PredNewRel { - bits<5> dst; - bits<5> src1; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13-12} = 0b00; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment loads with immediate offset. -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in -class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isPredNot, bit isPredNew > - : LDInst <(outs RC:$dst, IntRegs:$dst2), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2++#$offset)", - [] , - "$src2 = $dst2" > , - PredNewRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<7> offset; - bits<4> offsetBits; - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12} = isPredNew; - let Inst{11} = isPredNot; - let Inst{10-9} = src1; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Multiclass for post increment loads with immediate offset. -//===----------------------------------------------------------------------===// - -multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<4> MajOp> { - let BaseOpcode = "POST_"#BaseOp in { - let isPredicable = 1 in - def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>; - - // Predicated - def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>; - def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>; - - // Predicated new - def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>; - def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>; - } -} - -// post increment byte loads with immediate offset -let accessSize = ByteAccess in { - defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; - defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; -} - -// post increment halfword loads with immediate offset -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>; - defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>; -} - -// post increment word loads with immediate offset -let accessSize = WordAccess, opExtentAlign = 2 in -defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>; - -// post increment doubleword loads with immediate offset -let accessSize = DoubleWordAccess, opExtentAlign = 3 in -defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; - -// Rd=memb[u]h(Rx++#s4:1) -// Rdd=memb[u]h(Rx++#s4:2) -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>; - def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>; -} -let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in { - def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>; - def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>; -} - -//===----------------------------------------------------------------------===// -// Template class for post increment fifo loads with immediate offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp > - : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2), - (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "$dst = "#mnemonic#"($src2++#$offset)" , - [], "$src2 = $dst2, $src1 = $dst" > , - PredNewRel { - bits<5> dst; - bits<5> src2; - bits<5> offset; - bits<4> offsetBits; - - let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}); - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13-12} = 0b00; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -// Ryy=memh_fifo(Rx++#s4:1) -// Ryy=memb_fifo(Rx++#s4:0) -let accessSize = ByteAccess in -def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in -def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>; - -//===----------------------------------------------------------------------===// -// Template class for post increment loads with register offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp, - MemAccessSize AccessSz> - : LDInstPI <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2), - "$dst = "#mnemonic#"($src1++$src2)" , - [], "$src1 = $_dst_" > { - bits<5> dst; - bits<5> src1; - bits<1> src2; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let hasNewValue = 1 in { - def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>; - def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>; - def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>; - def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>; - def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>; - - def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>; -} - -def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>; -def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>; - -// Load predicate. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def LDriw_pred : LDInst<(outs PredRegs:$dst), - (ins IntRegs:$addr, s11_2Ext:$off), - ".error \"should not emit\"", []>; -// Load modifier. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def LDriw_mod : LDInst<(outs ModRegs:$dst), - (ins IntRegs:$addr, s11_2Ext:$off), - ".error \"should not emit\"", []>; - -let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in - def L2_deallocframe : LDInst<(outs), (ins), - "deallocframe", - []> { - let IClass = 0b1001; - - let Inst{27-16} = 0b000000011110; - let Inst{13} = 0b0; - let Inst{4-0} = 0b11110; -} - -// Load / Post increment circular addressing mode. -let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in -class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp> - : LDInst <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], - "$Rz = $_dst_" > { - bits<5> dst; - bits<5> Rz; - bit Mu; - - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - let IClass = 0b1001; - - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b1; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let accessSize = ByteAccess in { - def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>; - def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>; -} - -let accessSize = HalfWordAccess in { - def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>; - def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>; - def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>; - def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>; -} - -let accessSize = WordAccess in { - def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>; - let hasNewValue = 0 in { - def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>; - def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>; - } -} - -let accessSize = DoubleWordAccess in -def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>; - -// Load / Post increment circular addressing mode. -let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz > - : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_), - (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], - "$Rz = $_dst_, $dst = $_src_" > { - bits<5> dst; - bits<5> Rz; - bit Mu; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b1; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>; -def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>; - -//===----------------------------------------------------------------------===// -// Circular loads with immediate offset. -//===----------------------------------------------------------------------===// -let Uses = [CS], mayLoad = 1, hasSideEffects = 0, addrMode = PostInc in -class T_load_pci <string mnemonic, RegisterClass RC, - Operand ImmOp, bits<4> MajOp> - : LDInstPI<(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [], - "$Rz = $_dst_"> { - bits<5> dst; - bits<5> Rz; - bits<1> Mu; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let IClass = 0b1001; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b0; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -// Byte variants of circ load -let accessSize = ByteAccess in { - def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>; - def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>; -} - -// Half word variants of circ load -let accessSize = HalfWordAccess in { - def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>; - def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>; - def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>; - def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>; -} - -// Word variants of circ load -let accessSize = WordAccess in -def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>; - -let accessSize = WordAccess, hasNewValue = 0 in { - def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>; - def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>; -} - -let accessSize = DoubleWordAccess, hasNewValue = 0 in -def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>; - - -// TODO: memb_fifo and memh_fifo must take destination register as input. -// One-off circ loads - not enough in common to break into a class. -let accessSize = ByteAccess in -def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in -def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>; - -// L[24]_load[wd]_locked: Load word/double with lock. -let isSoloAX = 1 in -class T_load_locked <string mnemonic, RegisterClass RC> - : LD0Inst <(outs RC:$dst), - (ins IntRegs:$src), - "$dst = "#mnemonic#"($src)"> { - bits<5> dst; - bits<5> src; - let IClass = 0b1001; - let Inst{27-21} = 0b0010000; - let Inst{20-16} = src; - let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00); - let Inst{5} = 0; - let Inst{4-0} = dst; -} -let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in - def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>; -let accessSize = DoubleWordAccess in - def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>; - -// S[24]_store[wd]_locked: Store word/double conditionally. -let isSoloAX = 1, isPredicateLate = 1 in -class T_store_locked <string mnemonic, RegisterClass RC> - : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt), - mnemonic#"($Rs, $Pd) = $Rt"> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1010; - let Inst{27-23} = 0b00001; - let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1); - let Inst{21} = 0b1; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -let accessSize = WordAccess in -def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>; - -let accessSize = DoubleWordAccess in -def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>; - -//===----------------------------------------------------------------------===// -// Bit-reversed loads with auto-increment register -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pbr<string mnemonic, RegisterClass RC, - MemAccessSize addrSize, bits<4> majOp> - : LDInst - <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" , - [] , "$Rz = $_dst_" > { - - let accessSize = addrSize; - - bits<5> dst; - bits<5> Rz; - bits<1> Mu; - - let IClass = 0b1001; - - let Inst{27-25} = 0b111; - let Inst{24-21} = majOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let hasNewValue =1, opNewValue = 0 in { - def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>; - def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>; - def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>; - def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>; - def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>; - def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>; - def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>; -} - -def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>; -def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>; -def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>; - -def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>; -def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs, - HalfWordAccess, 0b0010>; - -//===----------------------------------------------------------------------===// -// LD - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/ALU + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/COMPLEX + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/COMPLEX - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/MPYH + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords -//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd, - bit hasShift, bit isUnsigned> - : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isRnd,":rnd","") - #!if(isSat,":sat",""), - [], "", M_tc_3x_SLOT23 > { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1100; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isRnd; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>; -def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>; -def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>; -def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>; -def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>; -def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>; -def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>; -def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>; - -//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>; -def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>; -def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>; -def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>; -def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>; -def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>; -def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>; -def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd -def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>; -def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>; -def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>; -def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>; -def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>; -def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>; -def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>; -def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -let Defs = [USR_OVF] in { - def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>; - def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>; - def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>; - def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>; - def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>; - def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>; - def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>; - def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>; - - def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>; -} - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the accumulator. -//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac, - bit hasShift, bit isUnsigned > - : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") - #"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - [], "$dst2 = $Rx", M_tc_3x_SLOT23 > { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - let Inst{27-24} = 0b1110; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isNac; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>; -def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>; -def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>; -def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>; -def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>; -def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>; -def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>; -def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>; - -//Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>; -def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>; -def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>; -def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>; -def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>; -def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>; -def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>; -def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>; - -//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>; -def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>; -def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>; -def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>; -def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>; -def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>; -def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>; -def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>; - -//Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>; -def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>; -def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>; -def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>; -def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>; -def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>; -def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>; -def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>; - -//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat -def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>; -def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>; -def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>; -def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>; -def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>; -def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>; -def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>; -def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>; - -//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat -def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>; -def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>; -def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>; -def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>; -def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>; -def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>; -def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>; -def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the 64-bit destination register. -//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned> - : MInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") - #"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1",""), - [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0110; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isNac; - let Inst{7} = 0; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>; -def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>; -def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>; -def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>; - -def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>; -def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>; -def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>; -def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>; - -def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>; -def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>; -def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>; -def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>; - -def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>; -def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>; -def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>; -def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>; - -def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>; -def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>; -def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>; -def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>; - -def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>; -def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>; -def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>; -def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>; - -def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>; -def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>; -def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>; -def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>; - -def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>; -def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>; -def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>; -def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>; - -//===----------------------------------------------------------------------===// -// Template Class -- Vector Multipy -// Used for complex multiply real or imaginary, dual multiply and even halfwords -//===----------------------------------------------------------------------===// -class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, - bit isRnd, bit isSat > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd","") - #!if(isSat,":sat",""), - [] > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat -let Defs = [USR_OVF] in { -def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>; -def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>; - -// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat -def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>; -def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>; - -// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat -def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>; -def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>; - -// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat -def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>; -def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>; - -//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>; -def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>; -def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>; -def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>; - -//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>; -def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>; -def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>; -def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>; - -//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>; -def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>; -def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>; -def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>; - -//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>; -def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>; -def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>; -def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>; -} - -let hasNewValue = 1, opNewValue = 0 in -class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC, - bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0, - string op2Suffix = "", bit isRaw = 0, bit isHi = 0 > - : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2), - "$dst = "#mnemonic - #"($src1, $src2"#op2Suffix#")" - #!if(MajOp{2}, ":<<1", "") - #!if(isRnd, ":rnd", "") - #!if(isSat, ":sat", "") - #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1110; - - let Inst{27-24} = RegTyBits; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-8} = src2; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi> - : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>; - -class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0 > - : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>; - -class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0 > - : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>; - -class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0, string op2str = "" > - : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>; - -def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>; -def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>; -def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>; - -let CextOpcode = "mpyi", InputType = "reg" in -def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel; - -def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>; -def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>; - -def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>; - -def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>; -def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>; - -def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">; -def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">; - -def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>; -def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>; -def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">; -def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">; - -// V4 Instructions -def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>; -def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>; -def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>; -def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>; - -def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">; -def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">; - -let hasNewValue = 1, opNewValue = 0 in -class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern> - : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8), - "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" , - pattern, "", M_tc_3x_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<8> u8; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0000; - let Inst{23} = isNeg; - let Inst{13} = 0b0; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{12-5} = u8; - } - -let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in -def M2_mpysip : T_MType_mpy_ri <0, u8_0Ext, []>; - -def M2_mpysin : T_MType_mpy_ri <1, u8_0Imm, []>; - -// Assember mapped to M2_mpyi -let isAsmParserOnly = 1 in -def M2_mpyui : MInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2), - "$dst = mpyui($src1, $src2)">; - -// Rd=mpyi(Rs,#m9) -// s9 is NOT the same as m9 - but it works.. so far. -// Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8) -// depending on the value of m9. See Arch Spec. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9, - CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1, - isAsmParserOnly = 1 in -def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9_0Ext:$src2), - "$dst = mpyi($src1, #$src2)", []>, ImmRegRel; - -let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3, - InputType = "imm" in -class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp, - list<dag> pattern = []> - : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3), - "$dst "#mnemonic#"($src2, #$src3)", - pattern, "$src1 = $dst", M_tc_2_SLOT23> { - bits<5> dst; - bits<5> src2; - bits<8> src3; - - let IClass = 0b1110; - - let Inst{27-26} = 0b00; - let Inst{25-23} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b0; - let Inst{12-5} = src3; - let Inst{4-0} = dst; - } - -let InputType = "reg", hasNewValue = 1 in -class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0, - bit isSat = 0, bit isShift = 0> - : MInst < (outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)") - #!if(isShift, ":<<1", "") - #!if(isSat, ":sat", ""), - pattern, "$src1 = $dst", M_tc_2_SLOT23 > { - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if(isSwap, src3, src2); - let Inst{13} = 0b0; - let Inst{12-8} = !if(isSwap, src2, src3); - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in { - def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8_0Ext, []>, ImmRegRel; - - def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0, []>, ImmRegRel; -} - -let CextOpcode = "ADD_acc" in { - let isExtentSigned = 1 in - def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8_0Ext, []>, ImmRegRel; - - def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, []>, ImmRegRel; -} - -let CextOpcode = "SUB_acc" in { - let isExtentSigned = 1 in - def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8_0Ext>, ImmRegRel; - - def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel; -} - -let Itinerary = M_tc_3x_SLOT23 in -def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8_0Ext>; - -def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>; -def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>; - -//===----------------------------------------------------------------------===// -// Template Class -- XType Vector Instructions -//===----------------------------------------------------------------------===// -class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), - [] > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > - : MInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), - [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_XTYPE_Vect_diff < bits<3> MajOp, string opc > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss), - "$Rdd = "#opc#"($Rtt, $Rss)", - [], "",M_tc_2_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32) -def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>; -def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>; - -// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) -def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>; -def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>; - -// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) -def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">; - -// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) -def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">; - -// Vector reduce complex multiply real or imaginary: -// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) -def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>; -def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>; -def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>; -def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>; - -def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>; -def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>; -def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>; -def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>; - -// Vector reduce halfwords: -// Rdd[+]=vrmpyh(Rss,Rtt) -def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>; -def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -- Vector Multipy with accumulation. -// Used for complex multiply real or imaginary, dual multiply and even halfwords -//===----------------------------------------------------------------------===// -let Defs = [USR_OVF] in -class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, - bit hasShift, bit isRnd > - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd","")#":sat", - [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp, - bit hasShift, bit isRnd > - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd",""), - [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector multiply word by signed half with accumulation -// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>; -def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>; -def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>; -def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>; - -def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>; -def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>; -def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>; -def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>; - -// Vector multiply word by unsigned half with accumulation -// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>; -def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>; -def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>; -def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>; - -def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>; -def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>; -def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>; -def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>; - -// Vector multiply even halfwords with accumulation -// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] -def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>; -def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>; -def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>; - -// Vector dual multiply with accumulation -// Rxx+=vdmpy(Rss,Rtt)[:sat] -def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>; -def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>; - -// Vector complex multiply real or imaginary with accumulation -// Rxx+=vcmpy[ir](Rss,Rtt):sat -def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>; -def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -- Multiply signed/unsigned halfwords with and without -// saturation and rounding -//===----------------------------------------------------------------------===// -class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned > - : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isRnd,":rnd",""), - [] > { - bits<5> Rdd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0100; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isRnd; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; -} - -def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>; -def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>; -def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>; -def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>; - -def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>; -def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>; -def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>; -def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>; - -def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>; -def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>; -def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>; -def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>; - -def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>; -def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>; -def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>; -def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>; - -//Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1] -def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>; -def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>; -def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>; -def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>; - -def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>; -def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>; -def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>; -def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>; - -//===----------------------------------------------------------------------===// -// Template Class for xtype mpy: -// Vector multiply -// Complex multiply -// multiply 32X32 and use full result -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit hasShift, bit isConj> - : MInst <(outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - [] > { - bits<5> Rdd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0101; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// Template Class for xtype mpy with accumulation into 64-bit: -// Vector multiply -// Complex multiply -// multiply 32X32 and use full result -//===----------------------------------------------------------------------===// -class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit hasShift, bit isConj> - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - - [] , "$dst2 = $Rxx" > { - bits<5> Rxx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0111; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - } - -// MPY - Multiply and use full result -// Rdd = mpy[u](Rs,Rt) -def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>; -def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>; - -// Rxx[+-]= mpy[u](Rs,Rt) -def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>; -def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>; -def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>; -def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>; - -// Complex multiply real or imaginary -// Rxx=cmpy[ir](Rs,Rt) -def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>; -def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>; - -// Rxx+=cmpy[ir](Rs,Rt) -def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>; -def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>; - -// Complex multiply -// Rdd=cmpy(Rs,Rt)[:<<]:sat -def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>; -def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>; - -// Rdd=cmpy(Rs,Rt*)[:<<]:sat -def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>; -def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>; - -// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat -def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>; -def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>; -def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>; -def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>; - -// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat -def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>; -def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>; -def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>; -def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>; - -// Vector multiply halfwords -// Rdd=vmpyh(Rs,Rt)[:<<]:sat -//let Defs = [USR_OVF] in { - def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>; - def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>; -//} - -// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] -def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>; -def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>; -def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>; - -//===----------------------------------------------------------------------===// -// MTYPE/MPYH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/MPYS + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/MPYS - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/VB + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/VB - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/VH + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/VH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ST + -//===----------------------------------------------------------------------===// -/// -// Store doubleword. -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in -class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isHalf > - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), - mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""), - [], "$src1 = $_dst_" >, - AddrModeRel { - bits<5> src1; - bits<5> src2; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-8} = src2; - let Inst{7} = 0b0; - let Inst{6-3} = offsetBits; - let Inst{1} = 0b0; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in -class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew> - : STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""), - [], "$src2 = $_dst_" >, - AddrModeRel { - bits<2> src1; - bits<5> src2; - bits<7> offset; - bits<5> src3; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b1010; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12-8} = src3; - let Inst{7} = isPredNew; - let Inst{6-3} = offsetBits; - let Inst{2} = isPredNot; - let Inst{1-0} = src1; - } - -multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > { - - let BaseOpcode = "POST_"#BaseOp in { - def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>; - - // Predicated - def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>; - def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>; - - // Predicated new - def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, - isHalf, 0, 1>; - def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, - isHalf, 1, 1>; - } -} - -let accessSize = ByteAccess in -defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>; - -let accessSize = HalfWordAccess in -defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>; - -let accessSize = WordAccess in -defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>; - -let accessSize = DoubleWordAccess in -defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; - -let accessSize = HalfWordAccess, isNVStorable = 0 in -defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; - -//===----------------------------------------------------------------------===// -// Template class for post increment stores with register offset. -//===----------------------------------------------------------------------===// -class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, - MemAccessSize AccessSz, bit isHalf = 0> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, RC:$src3), - mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""), - [], "$src1 = $_dst_" > { - bits<5> src1; - bits<1> src2; - bits<5> src3; - let accessSize = AccessSz; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1101; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12-8} = src3; - let Inst{7} = 0b0; - } - -def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>; -def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>; -def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>; -def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>; -def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>; - -let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in -class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp, bit isH = 0> - : STInst <(outs), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>, - AddrModeRel, ImmRegRel { - bits<5> src1; - bits<14> src2; // Actual address offset - bits<5> src3; - bits<11> offsetBits; // Represents offset encoding - - string ImmOpStr = !cast<string>(ImmOp); - - let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, - !if (!eq(ImmOpStr, "s11_2Ext"), 13, - !if (!eq(ImmOpStr, "s11_1Ext"), 12, - /* s11_0Ext */ 11))); - let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3}, - !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2}, - !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1}, - /* s11_0Ext */ src2{10-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - let IClass = 0b1010; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24} = 0b1; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = offsetBits{8}; - let Inst{12-8} = src3; - let Inst{7-0} = offsetBits{7-0}; - } - -let opExtendable = 2, isPredicated = 1 in -class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0> - : STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""), - [],"",V2LDST_tc_st_SLOT01 >, - AddrModeRel, ImmRegRel { - bits<2> src1; - bits<5> src2; - bits<9> src3; // Actual address offset - bits<5> src4; - bits<6> offsetBits; // Represents offset encoding - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = PredNot; - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, - !if (!eq(ImmOpStr, "u6_2Ext"), 8, - !if (!eq(ImmOpStr, "u6_1Ext"), 7, - /* u6_0Ext */ 6))); - let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3}, - !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2}, - !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1}, - /* u6_0Ext */ src3{5-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{26} = PredNot; - let Inst{25} = isPredNew; - let Inst{24} = 0b0; - let Inst{23-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = offsetBits{5}; - let Inst{12-8} = src4; - let Inst{7-3} = offsetBits{4-0}; - let Inst{1-0} = src1; - } - -let isExtendable = 1, hasSideEffects = 0 in -multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>; - - // Predicated - def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>; - def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>; - - // Predicated new - def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp, - MajOp, 0, 1, isH>; - def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp, - MajOp, 1, 1, isH>; - } -} - -let addrMode = BaseImmOffset, InputType = "imm" in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>; - - let accessSize = WordAccess, opExtentAlign = 2 in - defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>; - - let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in - defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, - u6_3Ext, 0b110>; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext, - u6_1Ext, 0b011, 1>; -} - -// Store predicate. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def STriw_pred : STInst<(outs), - (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1), - ".error \"should not emit\"", []>; -// Store modifier. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def STriw_mod : STInst<(outs), - (ins IntRegs:$addr, s11_2Ext:$off, ModRegs:$src1), - ".error \"should not emit\"", []>; - -// S2_allocframe: Allocate stack frame. -let Defs = [R29, R30], Uses = [R29, R31, R30], - hasSideEffects = 0, accessSize = DoubleWordAccess in -def S2_allocframe: ST0Inst < - (outs), (ins u11_3Imm:$u11_3), - "allocframe(#$u11_3)" > { - bits<14> u11_3; - - let IClass = 0b1010; - let Inst{27-16} = 0b000010011101; - let Inst{13-11} = 0b000; - let Inst{10-0} = u11_3{13-3}; - } - -// S2_storer[bhwdf]_pci: Store byte/half/word/double. -// S2_storer[bhwdf]_pci -> S2_storerbnew_pci -let Uses = [CS], addrMode = PostInc in -class T_store_pci <string mnemonic, RegisterClass RC, - Operand Imm, bits<4>MajOp, - MemAccessSize AlignSize, string RegSrc = "Rt"> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt), - #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"", - [] , - "$Rz = $_dst_" > { - bits<5> Rz; - bits<7> offset; - bits<1> Mu; - bits<5> Rt; - let accessSize = AlignSize; - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, - !if(!eq(RegSrc,"Rt.h"), 0, 1)); - - let IClass = 0b1010; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{6-3} = - !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3}, - !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, - !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, - /* ByteAccess */ offset{3-0}))); - let Inst{1} = 0b0; - } - -def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000, - ByteAccess>; -def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010, - HalfWordAccess>; -def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011, - HalfWordAccess, "Rt.h">; -def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100, - WordAccess>; -def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110, - DoubleWordAccess>; - -let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4, - addrMode = PostInc in -class T_storenew_pci <string mnemonic, Operand Imm, - bits<2>MajOp, MemAccessSize AlignSize> - : NVInst < (outs IntRegs:$_dst_), - (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new", - [], - "$Rz = $_dst_"> { - bits<5> Rz; - bits<6> offset; - bits<1> Mu; - bits<3> Nt; - - let accessSize = AlignSize; - - let IClass = 0b1010; - let Inst{27-21} = 0b1001101; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-11} = MajOp; - let Inst{10-8} = Nt; - let Inst{7} = 0b0; - let Inst{6-3} = - !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, - !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, - /* ByteAccess */ offset{3-0})); - let Inst{1} = 0b0; - } - -def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>; -def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>; -def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Circular stores with auto-increment register -//===----------------------------------------------------------------------===// -let Uses = [CS], addrMode = PostInc in -class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, - MemAccessSize AlignSize, string RegSrc = "Rt"> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt), - #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"", - [], - "$Rz = $_dst_" > { - bits<5> Rz; - bits<1> Mu; - bits<5> Rt; - - let accessSize = AlignSize; - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, - !if(!eq(RegSrc,"Rt.h"), 0, 1)); - - let IClass = 0b1010; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{1} = 0b1; - } - -def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>; -def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>; -def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>; -def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>; -def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011, - HalfWordAccess, "Rt.h">; - -//===----------------------------------------------------------------------===// -// Circular .new stores with auto-increment register -//===----------------------------------------------------------------------===// -let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, - addrMode = PostInc in -class T_storenew_pcr <string mnemonic, bits<2>MajOp, - MemAccessSize AlignSize> - : NVInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" , - [] , - "$Rz = $_dst_"> { - bits<5> Rz; - bits<1> Mu; - bits<3> Nt; - - let accessSize = AlignSize; - - let IClass = 0b1010; - let Inst{27-21} = 0b1001101; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-11} = MajOp; - let Inst{10-8} = Nt; - let Inst{7} = 0b0; - let Inst{1} = 0b1; - } - -def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>; -def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>; -def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Bit-reversed stores with auto-increment register -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_store_pbr<string mnemonic, RegisterClass RC, - MemAccessSize addrSize, bits<3> majOp, - bit isHalf = 0> - : STInst - <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src), - #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""), - [], "$Rz = $_dst_" > { - - let accessSize = addrSize; - - bits<5> Rz; - bits<1> Mu; - bits<5> src; - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = majOp; - let Inst{7} = 0b0; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = src; - } - -let isNVStorable = 1 in { - let BaseOpcode = "S2_storerb_pbr" in - def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess, - 0b000>, NewValueRel; - let BaseOpcode = "S2_storerh_pbr" in - def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, - 0b010>, NewValueRel; - let BaseOpcode = "S2_storeri_pbr" in - def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess, - 0b100>, NewValueRel; -} - -def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>; -def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>; - -//===----------------------------------------------------------------------===// -// Bit-reversed .new stores with auto-increment register -//===----------------------------------------------------------------------===// -let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, - hasSideEffects = 0, addrMode = PostInc in -class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp> - : NVInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [], - "$Rz = $_dst_">, NewValueRel { - let accessSize = addrSize; - bits<5> Rz; - bits<1> Mu; - bits<3> Nt; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1111101; - let Inst{12-11} = majOp; - let Inst{7} = 0b0; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{10-8} = Nt; - } - -let BaseOpcode = "S2_storerb_pbr" in -def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>; - -let BaseOpcode = "S2_storerh_pbr" in -def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>; - -let BaseOpcode = "S2_storeri_pbr" in -def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>; - -//===----------------------------------------------------------------------===// -// ST - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template class for S_2op instructions. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, - RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> - : SInst <(outs RCOut:$dst), (ins RCIn:$src), - "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""), - [], "", S_2op_tc_1_SLOT23 > { - bits<5> dst; - bits<5> src; - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23-22} = MajOp; - let Inst{21} = 0b0; - let Inst{20-16} = src; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp> - : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>; - -let hasNewValue = 1 in -class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> - : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>; - -let hasNewValue = 1 in -class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> - : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>; - -// Vector sign/zero extend -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>; - def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>; - def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>; - def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>; -} - -// Vector splat bytes/halfwords -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>; - def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>; -} - -// Sign extend word to doubleword -def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; - -// Vector saturate and pack -let Defs = [USR_OVF] in { - def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>; - def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>; - def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>; - def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>; - def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>; - def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>; -} - -// Vector truncate -def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>; -def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>; - -// Swizzle the bytes of a word -def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; - -// Saturate -let Defs = [USR_OVF] in { - def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>; - def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>; - def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; - def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; - def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; - def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>; -} - -let Itinerary = S_2op_tc_2_SLOT23 in { - // Vector round and pack - def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>; - - let Defs = [USR_OVF] in - def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>; - - // Bit reverse - def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>; - - // Absolute value word - def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>; - - let Defs = [USR_OVF] in - def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>; - - // Negate with saturation - let Defs = [USR_OVF] in - def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>; -} - -class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, - RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit isRnd, list<dag> pattern = []> - : SInst <(outs RCOut:$dst), - (ins RCIn:$src, u5_0Imm:$u5), - "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "") - #!if(isRnd, ":rnd", ""), - pattern, "", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src; - bits<5> u5; - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23-21} = MajOp; - let Inst{20-16} = src; - let Inst{13} = 0b0; - let Inst{12-8} = u5; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>; - -let hasNewValue = 1 in -class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>; - -let hasNewValue = 1 in -class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0, list<dag> pattern = []> - : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, - isSat, isRnd, pattern>; - -class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd> - : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0, []>; - -// Vector arithmetic shift right by immediate with truncate and pack -def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>; - -// Arithmetic/logical shift right/left by immediate -let Itinerary = S_2op_tc_1_SLOT23 in { - def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>; - def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>; - def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>; -} - -// Shift left by immediate with saturation -let Defs = [USR_OVF] in -def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>; - -// Shift right with round -def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>; - -let isAsmParserOnly = 1 in -def S2_asr_i_r_rnd_goodsyntax - : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5_0Imm:$u5), - "$dst = asrrnd($src, #$u5)", - [], "", S_2op_tc_1_SLOT23>; - -let isAsmParserOnly = 1 in -def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src), - "$dst = not($src)">; - -class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0> - : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), - "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> { - bits<5> Rss; - bits<5> Rdd; - let IClass = 0b1000; - let Inst{27-24} = 0; - let Inst{23-22} = MajOp; - let Inst{20-16} = Rss; - let Inst{7-5} = minOp; - let Inst{4-0} = Rdd; -} - -def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>; -def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>; -def A2_notp : T_S2op_3 <"not", 0b10, 0b100>; - -// Innterleave/deinterleave -def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>; -def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; - -// Vector Complex conjugate -def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; - -// Vector saturate without pack -def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>; -def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>; -def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>; -def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>; - -// Vector absolute value halfwords with and without saturation -// Rdd64=vabsh(Rss64)[:sat] -def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>; -def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>; - -// Vector absolute value words with and without saturation -def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>; -def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>; - -//===----------------------------------------------------------------------===// -// STYPE/BIT + -//===----------------------------------------------------------------------===// -// Bit count - -let hasSideEffects = 0, hasNewValue = 1 in -class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32, - dag Out, dag Inp> - : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rs; - bits<5> Rd; - let IClass = 0b1000; - let Inst{27} = 0b1; - let Inst{26} = Is32; - let Inst{25-24} = 0b00; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp> - : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1, - (outs IntRegs:$Rd), (ins IntRegs:$Rs)>; - -class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp> - : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0, - (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>; - -def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>; -def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>; -def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>; -def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>; -def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>; -def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>; -def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>; -def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>; -def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>; - -// The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td. - -// Bit set/clear/toggle - -let hasSideEffects = 0, hasNewValue = 1 in -class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp> - : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5_0Imm:$u5), - "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> u5; - let IClass = 0b1000; - let Inst{27-21} = 0b1100110; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = u5; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_SCT_BIT_REG<string MnOp, bits<2> MinOp> - : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-22} = 0b011010; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-6} = MinOp; - let Inst{4-0} = Rd; -} - -def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>; -def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>; -def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>; -def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>; -def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>; -def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>; - -// Bit test - -let hasSideEffects = 0 in -class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5_0Imm:$u5), - "$Pd = "#MnOp#"($Rs, #$u5)", - [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> u5; - let IClass = 0b1000; - let Inst{27-24} = 0b0101; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0; - let Inst{12-8} = u5; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0 in -class T_TEST_BIT_REG<string MnOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#MnOp#"($Rs, $Rt)", - [], "", S_3op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-22} = 0b011100; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>; -def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>; - -let hasSideEffects = 0 in -class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6_0Imm:$u6), - "$Pd = "#MnOp#"($Rs, #$u6)", - [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<6> u6; - let IClass = 0b1000; - let Inst{27-24} = 0b0101; - let Inst{23-22} = MajOp; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{13-8} = u6; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0 in -class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#MnOp#"($Rs, $Rt)", - [], "", S_3op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-24} = 0b0111; - let Inst{23-22} = MajOp; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>; -def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>; -def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>; - -//===----------------------------------------------------------------------===// -// STYPE/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/COMPLEX + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/COMPLEX - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/PERM + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/PRED + -//===----------------------------------------------------------------------===// - -// Predicate transfer. -let hasSideEffects = 0, hasNewValue = 1 in -def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps), - "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Ps; - - let IClass = 0b1000; - let Inst{27-24} = 0b1001; - let Inst{22} = 0b1; - let Inst{17-16} = Ps; - let Inst{4-0} = Rd; -} - -// Transfer general register to predicate. -let hasSideEffects = 0 in -def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs), - "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - - let IClass = 0b1000; - let Inst{27-21} = 0b0101010; - let Inst{20-16} = Rs; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0, isCodeGenOnly = 1 in -def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src), - "$dst = $src">; - -//===----------------------------------------------------------------------===// -// STYPE/PRED - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/SHIFT + -//===----------------------------------------------------------------------===// -class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp, - Operand Imm, list<dag> pattern = [], bit isRnd = 0> - : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2), - "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""), - pattern> { - bits<5> src1; - bits<5> dst; - let IClass = 0b1000; - let Inst{27-24} = 0; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; -} - -class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp> - : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6_0Imm, []> { - bits<6> src2; - let Inst{13-8} = src2; -} - -// Shift by immediate. -def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>; -def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>; -def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>; - -// Shift left by small amount and add. -let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in -def S2_addasl_rrri: SInst <(outs IntRegs:$Rd), - (ins IntRegs:$Rt, IntRegs:$Rs, u3_0Imm:$u3), - "$Rd = addasl($Rt, $Rs, #$u3)" , [], - "", S_3op_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - bits<3> u3; - - let IClass = 0b1100; - - let Inst{27-21} = 0b0100000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7-5} = u3; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// STYPE/SHIFT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/VH + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/VH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/VW + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/VW - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// SYSTEM/SUPER + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// SYSTEM/USER + -//===----------------------------------------------------------------------===// -let hasSideEffects = 1, isSoloAX = 1 in -def Y2_barrier : SYSInst<(outs), (ins), "barrier", [],"",ST_tc_st_SLOT0> { - let Inst{31-28} = 0b1010; - let Inst{27-21} = 0b1000000; -} - -//===----------------------------------------------------------------------===// -// SYSTEM/SUPER - -//===----------------------------------------------------------------------===// - -// Generate frameindex addresses. The main reason for the offset operand is -// that every instruction that is allowed to have frame index as an operand -// will then have that operand followed by an immediate operand (the offset). -// This simplifies the frame-index elimination code. -// -let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, - isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { - def PS_fi : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$fi, s32_0Imm:$off), "">; - def PS_fia : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">; -} - -//===----------------------------------------------------------------------===// -// CRUSER - Type. -//===----------------------------------------------------------------------===// -// HW loop -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, hasSideEffects = 0 in -class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> - : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2), - #mnemonic#"($offset, #$src2)", - [], "" , CR_tc_3x_SLOT3> { - bits<9> offset; - bits<10> src2; - - let IClass = 0b0110; - - let Inst{27-22} = 0b100100; - let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); - let Inst{20-16} = src2{9-5}; - let Inst{12-8} = offset{8-4}; - let Inst{7-5} = src2{4-2}; - let Inst{4-3} = offset{3-2}; - let Inst{1-0} = src2{1-0}; -} - -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, hasSideEffects = 0 in -class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> - : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), - #mnemonic#"($offset, $src2)", - [], "" ,CR_tc_3x_SLOT3> { - bits<9> offset; - bits<5> src2; - - let IClass = 0b0110; - - let Inst{27-22} = 0b000000; - let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); - let Inst{20-16} = src2; - let Inst{12-8} = offset{8-4}; - let Inst{4-3} = offset{3-2}; - } - -multiclass LOOP_ri<string mnemonic> { - def i : LOOP_iBase<mnemonic, brtarget>; - def r : LOOP_rBase<mnemonic, brtarget>; - - let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { - def iext: LOOP_iBase<mnemonic, brtargetExt, 1>; - def rext: LOOP_rBase<mnemonic, brtargetExt, 1>; - } -} - - -let Defs = [SA0, LC0, USR] in -defm J2_loop0 : LOOP_ri<"loop0">; - -// Interestingly only loop0's appear to set usr.lpcfg -let Defs = [SA1, LC1] in -defm J2_loop1 : LOOP_ri<"loop1">; - -let isBranch = 1, isTerminator = 1, hasSideEffects = 0, - Defs = [PC, LC0], Uses = [SA0, LC0] in { -def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset), - ":endloop0", - []>; -} - -let isBranch = 1, isTerminator = 1, hasSideEffects = 0, - Defs = [PC, LC1], Uses = [SA1, LC1] in { -def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset), - ":endloop1", - []>; -} - -// Pipelined loop instructions, sp[123]loop0 -let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, isPredicateLate = 1 in -class SPLOOP_iBase<string SP, bits<2> op> - : CRInst <(outs), (ins brtarget:$r7_2, u10_0Imm:$U10), - "p3 = sp"#SP#"loop0($r7_2, #$U10)" > { - bits<9> r7_2; - bits<10> U10; - - let IClass = 0b0110; - - let Inst{22-21} = op; - let Inst{27-23} = 0b10011; - let Inst{20-16} = U10{9-5}; - let Inst{12-8} = r7_2{8-4}; - let Inst{7-5} = U10{4-2}; - let Inst{4-3} = r7_2{3-2}; - let Inst{1-0} = U10{1-0}; - } - -let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, isPredicateLate = 1 in -class SPLOOP_rBase<string SP, bits<2> op> - : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs), - "p3 = sp"#SP#"loop0($r7_2, $Rs)" > { - bits<9> r7_2; - bits<5> Rs; - - let IClass = 0b0110; - - let Inst{22-21} = op; - let Inst{27-23} = 0b00001; - let Inst{20-16} = Rs; - let Inst{12-8} = r7_2{8-4}; - let Inst{4-3} = r7_2{3-2}; - } - -multiclass SPLOOP_ri<string mnemonic, bits<2> op> { - def i : SPLOOP_iBase<mnemonic, op>; - def r : SPLOOP_rBase<mnemonic, op>; -} - -defm J2_ploop1s : SPLOOP_ri<"1", 0b01>; -defm J2_ploop2s : SPLOOP_ri<"2", 0b10>; -defm J2_ploop3s : SPLOOP_ri<"3", 0b11>; - -// if (Rs[!>=<]=#0) jump:[t/nt] -let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0, - hasSideEffects = 0 in -class J2_jump_0_Base<string compare, bit isTak, bits<2> op> - : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2), - "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > { - bits<5> Rs; - bits<15> r13_2; - - let IClass = 0b0110; - - let Inst{27-24} = 0b0001; - let Inst{23-22} = op; - let Inst{12} = isTak; - let Inst{21} = r13_2{14}; - let Inst{20-16} = Rs; - let Inst{11-1} = r13_2{12-2}; - let Inst{13} = r13_2{13}; - } - -multiclass J2_jump_compare_0<string compare, bits<2> op> { - def NAME : J2_jump_0_Base<compare, 0, op>; - def NAME#pt : J2_jump_0_Base<compare, 1, op>; -} - -defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>; -defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>; -defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>; -defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>; - -// Transfer to/from Control/GPR Guest/GPR -let hasSideEffects = 0 in -class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble> - : CRInst <(outs CTRC:$dst), (ins RC:$src), - "$dst = $src", [], "", CR_tc_3x_SLOT3> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0110; - - let Inst{27-25} = 0b001; - let Inst{24} = isDouble; - let Inst{23-21} = 0b001; - let Inst{20-16} = src; - let Inst{4-0} = dst; - } - -def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>; -def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>; -def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; -def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; - -let hasSideEffects = 0 in -class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle> - : CRInst <(outs RC:$dst), (ins CTRC:$src), - "$dst = $src", [], "", CR_tc_3x_SLOT3> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0110; - - let Inst{27-26} = 0b10; - let Inst{25} = isSingle; - let Inst{24-21} = 0b0000; - let Inst{20-16} = src; - let Inst{4-0} = dst; - } - -let hasNewValue = 1, opNewValue = 0 in -def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>; -def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>; -def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; -def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; - -// Y4_trace: Send value to etm trace. -let isSoloAX = 1, hasSideEffects = 0 in -def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs), - "trace($Rs)"> { - bits<5> Rs; - - let IClass = 0b0110; - let Inst{27-21} = 0b0010010; - let Inst{20-16} = Rs; - } - -// HI/LO Instructions -let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, - hasNewValue = 1, opNewValue = 0 in -class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp> - : ALU32_ri<(outs IntRegs:$dst), - (ins u16_0Imm:$imm_value), - "$dst"#RegHalf#" = $imm_value", []> { - bits<5> dst; - bits<32> imm_value; - let IClass = 0b0111; - - let Inst{27} = Rs; - let Inst{26-24} = MajOp; - let Inst{21} = MinOp; - let Inst{20-16} = dst; - let Inst{23-22} = imm_value{15-14}; - let Inst{13-0} = imm_value{13-0}; -} - -let isAsmParserOnly = 1 in { - def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>; - def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>; -} - -let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in { - def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v), - "$Rd = CONST32(#$v)", []>; - def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v), - "$Rd = CONST64(#$v)", []>; -} - -let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, - isCodeGenOnly = 1 in -def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>; - -let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, - isCodeGenOnly = 1 in -def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>; - -let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in -def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), - ".error \"should not emit\" ", []>; - -let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in -def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), - ".error \"should not emit\" ", []>; - -// Call subroutine indirectly. -let Defs = VolatileV3.Regs in -def J2_callr : JUMPR_MISC_CALLR<0, 1>; - -// Indirect tail-call. -let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, - isTerminator = 1, isCodeGenOnly = 1 in -def PS_tailcall_r : T_JMPr; - -// Direct tail-calls. -let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, - isTerminator = 1, isCodeGenOnly = 1 in -def PS_tailcall_i : JInst<(outs), (ins calltarget:$dst), "", []>; - -// The reason for the custom inserter is to record all ALLOCA instructions -// in MachineFunctionInfo. -let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in -def PS_alloca: ALU32Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, u32_0Imm:$A), "", []>; - -let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in -def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>; - -// XTYPE/SHIFT -// -//===----------------------------------------------------------------------===// -// Template Class -// Shift by immediate/register and accumulate/logical -//===----------------------------------------------------------------------===// - -// Rx[+-&|]=asr(Rs,#u5) -// Rx[+-&|^]=lsr(Rs,#u5) -// Rx[+-&|^]=asl(Rs,#u5) - -let hasNewValue = 1, opNewValue = 0 in -class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, u5_0Imm:$u5), - "$Rx "#opc2#opc1#"($Rs, #$u5)", [], - "$src1 = $Rx", S_2op_tc_2_SLOT23> { - bits<5> Rx; - bits<5> Rs; - bits<5> u5; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1110; - let Inst{23-22} = majOp{2-1}; - let Inst{13} = 0b0; - let Inst{7} = majOp{0}; - let Inst{6-5} = minOp; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = u5; - } - -// Rx[+-&|]=asr(Rs,Rt) -// Rx[+-&|^]=lsr(Rs,Rt) -// Rx[+-&|^]=asl(Rs,Rt) - -let hasNewValue = 1, opNewValue = 0 in -class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<2> majOp, bits<2> minOp> - : SInst_acc<(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#opc2#opc1#"($Rs, $Rt)", [], - "$src1 = $Rx", S_3op_tc_2_SLOT23 > { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b1100; - let Inst{23-22} = majOp; - let Inst{7-6} = minOp; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -// Rxx[+-&|]=asr(Rss,#u6) -// Rxx[+-&|^]=lsr(Rss,#u6) -// Rxx[+-&|^]=asl(Rss,#u6) - -class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6_0Imm:$u6), - "$Rxx "#opc2#opc1#"($Rss, #$u6)", [], - "$src1 = $Rxx", S_2op_tc_2_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<6> u6; - - let IClass = 0b1000; - - let Inst{27-24} = 0b0010; - let Inst{23-22} = majOp{2-1}; - let Inst{7} = majOp{0}; - let Inst{6-5} = minOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{13-8} = u6; - } - - -// Rxx[+-&|]=asr(Rss,Rt) -// Rxx[+-&|^]=lsr(Rss,Rt) -// Rxx[+-&|^]=asl(Rss,Rt) -// Rxx[+-&|^]=lsl(Rss,Rt) - -class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt), - "$Rxx "#opc2#opc1#"($Rss, $Rt)", [], - "$src1 = $Rxx", S_3op_tc_2_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = majOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rt; - let Inst{7-6} = minOp; - let Inst{4-0} = Rxx; - } - -//===----------------------------------------------------------------------===// -// Multi-class for the shift instructions with logical/arithmetic operators. -//===----------------------------------------------------------------------===// - -multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp > { - def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1, - OpNode2, majOp, minOp >; - def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1, - OpNode2, majOp, minOp >; -} - -multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>; - - defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>; - defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>; - defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>; -} - -multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { -let AddedComplexity = 100 in - defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>; -} - -defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>; - -defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>, - xtype_xor_imm_acc<"lsr", srl, 0b01>; - -defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>, - xtype_xor_imm_acc<"asl", shl, 0b10>; - -multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>; - - def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>; - def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>; - def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>; -} - -multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>; - - def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>; - def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>; - def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>; - def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>; -} - -multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > { - defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>; - defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>; -} - -defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>; -defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>; -defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>; -defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>; - -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp, - bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0> - : SInst <(outs RC:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2), - "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "") - #!if(hasShift,":>>1","") - #!if(isSat, ":sat", ""), - [], "", S_3op_tc_2_SLOT23 > { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0001; - let Inst{23-22} = MajOp; - let Inst{20-16} = !if (SwapOps, src2, src1); - let Inst{12-8} = !if (SwapOps, src1, src2); - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps, - bit isSat = 0, bit isRnd = 0, bit hasShift = 0 > - : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps, - isSat, isRnd, hasShift>; - -let Itinerary = S_3op_tc_1_SLOT23 in { - def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>; - def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>; - def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>; - def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>; - - def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>; - def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>; -} - -def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; - -let hasSideEffects = 0 in -class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps> - : SInst < (outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), - "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)", - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<2> Pu; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0010; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if (SwapOps, Rtt, Rss); - let Inst{12-8} = !if (SwapOps, Rss, Rtt); - let Inst{6-5} = Pu; - let Inst{4-0} = Rdd; - } - -def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>; -def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>; - -//===----------------------------------------------------------------------===// -// Template class used by vector shift, vector rotate, vector neg, -// 32-bit shift, 64-bit shifts, etc. -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0 in -class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp, - bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] > - : SInst <(outs RC:$dst), - (ins RC:$src1, IntRegs:$src2), - "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""), - pattern, "", S_3op_tc_1_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1100; - - let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011); - let Inst{23-22} = MajOp; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{7-6} = MinOp; - let Inst{4-0} = dst; - } - -let hasNewValue = 1 in -class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp> - : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0, []>; - -let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in -class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp> - : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>; - - -class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp> - : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0, []>; - - -class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp> - : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>; - - -// Shift by register -// Rdd=[asr|lsr|asl|lsl](Rss,Rt) - -def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>; -def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>; -def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>; -def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>; - -// Rd=[asr|lsr|asl|lsl](Rs,Rt) - -def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>; -def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>; -def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>; -def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>; - -// Shift by register with saturation -// Rd=asr(Rs,Rt):sat -// Rd=asl(Rs,Rt):sat - -let Defs = [USR_OVF] in { - def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>; - def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; -} - -let hasNewValue = 1, hasSideEffects = 0 in -class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0> - : SInst < (outs IntRegs:$Rd), - (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")" - #!if(hasShift, ":<<1", "") - #!if(isRnd, ":rnd", "") - #!if(isSat, ":sat", ""), - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rd; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0101; - let Inst{20-16} = Rss; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>; - -let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; - -let hasSideEffects = 0 in -class T_S3op_7 <string mnemonic, bit MajOp > - : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3_0Imm:$u3), - "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" , - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<3> u3; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0000; - let Inst{23} = MajOp; - let Inst{20-16} = !if(MajOp, Rss, Rtt); - let Inst{12-8} = !if(MajOp, Rtt, Rss); - let Inst{7-5} = u3; - let Inst{4-0} = Rdd; - } - -def S2_valignib : T_S3op_7 < "valignb", 0>; -def S2_vspliceib : T_S3op_7 < "vspliceb", 1>; - -//===----------------------------------------------------------------------===// -// Template class for 'insert bitfield' instructions -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S3op_insert <string mnemonic, RegisterClass RC> - : SInst <(outs RC:$dst), - (ins RC:$src1, RC:$src2, DoubleRegs:$src3), - "$dst = "#mnemonic#"($src2, $src3)" , - [], "$src1 = $dst", S_3op_tc_1_SLOT23 > { - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let IClass = 0b1100; - - let Inst{27-26} = 0b10; - let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10); - let Inst{23} = 0b0; - let Inst{20-16} = src2; - let Inst{12-8} = src3; - let Inst{4-0} = dst; - } - -let hasSideEffects = 0 in -class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp> - : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3), - "$dst = insert($src1, #$src2, #$src3)", - [], "$dst2 = $dst", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<6> src2; - bits<6> src3; - bit bit23; - bit bit13; - string ImmOpStr = !cast<string>(ImmOp); - - let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, 0); - let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0); - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23} = bit23; - let Inst{22-21} = src3{4-3}; - let Inst{20-16} = src1; - let Inst{13} = bit13; - let Inst{12-8} = src2{4-0}; - let Inst{7-5} = src3{2-0}; - let Inst{4-0} = dst; - } - -// Rx=insert(Rs,Rtt) -// Rx=insert(Rs,#u5,#U5) -let hasNewValue = 1 in { - def S2_insert_rp : T_S3op_insert <"insert", IntRegs>; - def S2_insert : T_S2op_insert <0b1111, IntRegs, u5_0Imm>; -} - -// Rxx=insert(Rss,Rtt) -// Rxx=insert(Rss,#u6,#U6) -def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>; -def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6_0Imm>; - - -//===----------------------------------------------------------------------===// -// Template class for 'extract bitfield' instructions -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_S3op_extract <string mnemonic, bits<2> MinOp> - : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), - "$Rd = "#mnemonic#"($Rs, $Rtt)", - [], "", S_3op_tc_2_SLOT23 > { - bits<5> Rd; - bits<5> Rs; - bits<5> Rtt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b100100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rtt; - let Inst{7-6} = MinOp; - let Inst{4-0} = Rd; - } - -let hasSideEffects = 0 in -class T_S2op_extract <string mnemonic, bits<4> RegTyBits, - RegisterClass RC, Operand ImmOp> - : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3), - "$dst = "#mnemonic#"($src1, #$src2, #$src3)", - [], "", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<6> src2; - bits<6> src3; - bit bit23; - bit bit13; - string ImmOpStr = !cast<string>(ImmOp); - - let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, - !if (!eq(mnemonic, "extractu"), 0, 1)); - - let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0); - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23} = bit23; - let Inst{22-21} = src3{4-3}; - let Inst{20-16} = src1; - let Inst{13} = bit13; - let Inst{12-8} = src2{4-0}; - let Inst{7-5} = src3{2-0}; - let Inst{4-0} = dst; - } - -// Extract bitfield - -// Rdd=extractu(Rss,Rtt) -// Rdd=extractu(Rss,#u6,#U6) -def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>; -def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6_0Imm>; - -// Rd=extractu(Rs,Rtt) -// Rd=extractu(Rs,#u5,#U5) -let hasNewValue = 1 in { - def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>; - def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5_0Imm>; -} - -//===----------------------------------------------------------------------===// -// :raw for of tableindx[bdhw] insns -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class tableidxRaw<string OpStr, bits<2>MinOp> - : SInst <(outs IntRegs:$Rx), - (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, s6_0Imm:$S6), - "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw", - [], "$Rx = $_dst_" > { - bits<5> Rx; - bits<5> Rs; - bits<4> u4; - bits<6> S6; - - let IClass = 0b1000; - - let Inst{27-24} = 0b0111; - let Inst{23-22} = MinOp; - let Inst{21} = u4{3}; - let Inst{20-16} = Rs; - let Inst{13-8} = S6; - let Inst{7-5} = u4{2-0}; - let Inst{4-0} = Rx; - } - -def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>; -def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>; -def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>; -def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>; - -//===----------------------------------------------------------------------===// -// Template class for 'table index' instructions which are assembler mapped -// to their :raw format. -//===----------------------------------------------------------------------===// -let isPseudo = 1 in -class tableidx_goodsyntax <string mnemonic> - : SInst <(outs IntRegs:$Rx), - (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, u5_0Imm:$u5), - "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)", - [], "$Rx = $_dst_" >; - -def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">; -def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">; -def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">; -def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">; - -//===----------------------------------------------------------------------===// -// V3 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV3.td" - -//===----------------------------------------------------------------------===// -// V3 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V4 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV4.td" - -//===----------------------------------------------------------------------===// -// V4 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V5 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV5.td" - -//===----------------------------------------------------------------------===// -// V5 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V60 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV60.td" - -//===----------------------------------------------------------------------===// -// V60 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU32/64/Vector + -//===----------------------------------------------------------------------===/// - -include "HexagonInstrInfoVector.td" - -include "HexagonInstrAlias.td" -include "HexagonSystemInst.td" - diff --git a/lib/Target/Hexagon/HexagonInstrInfoV3.td b/lib/Target/Hexagon/HexagonInstrInfoV3.td deleted file mode 100644 index 5b7610a68af..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ /dev/null @@ -1,215 +0,0 @@ -//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V3 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// J + -//===----------------------------------------------------------------------===// -// Call subroutine. -let isCall = 1, hasSideEffects = 1, isPredicable = 1, - isExtended = 0, isExtendable = 1, opExtendable = 0, - isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in -class T_Call<bit CSR, string ExtStr> - : JInst<(outs), (ins calltarget:$dst), - "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> { - let BaseOpcode = "call"; - bits<24> dst; - - let Defs = !if (CSR, VolatileV3.Regs, []); - let IClass = 0b0101; - let Inst{27-25} = 0b101; - let Inst{24-16,13-1} = dst{23-2}; - let Inst{0} = 0b0; -} - -let isCall = 1, hasSideEffects = 1, isPredicated = 1, - isExtended = 0, isExtendable = 1, opExtendable = 1, - isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in -class T_CallPred<bit CSR, bit IfTrue, string ExtStr> - : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst), - CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst", - [], "", J_tc_2early_SLOT23> { - let BaseOpcode = "call"; - let isPredicatedFalse = !if(IfTrue,0,1); - bits<2> Pu; - bits<17> dst; - - let Defs = !if (CSR, VolatileV3.Regs, []); - let IClass = 0b0101; - let Inst{27-24} = 0b1101; - let Inst{23-22,20-16,13,7-1} = dst{16-2}; - let Inst{21} = !if(IfTrue,0,1); - let Inst{11} = 0b0; - let Inst{9-8} = Pu; -} - -multiclass T_Calls<bit CSR, string ExtStr> { - def NAME : T_Call<CSR, ExtStr>; - def t : T_CallPred<CSR, 1, ExtStr>; - def f : T_CallPred<CSR, 0, ExtStr>; -} - -defm J2_call: T_Calls<1, "">, PredRel; - -let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, - Defs = VolatileV3.Regs, isPseudo = 1 in -def PS_call_nr : T_Call<1, "">, PredRel; - -let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, - Defs = [PC, R31, R6, R7, P0] in -def PS_call_stk : T_Call<0, "">, PredRel; - -//===----------------------------------------------------------------------===// -// J - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// JR + -//===----------------------------------------------------------------------===// -// Call subroutine from register. - -let isCodeGenOnly = 1, Defs = VolatileV3.Regs in { - def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. -} - -//===----------------------------------------------------------------------===// -// JR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/ALU + -//===----------------------------------------------------------------------===// - -let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in -def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>; - -class T_ALU64_addsp_hl<string suffix, bits<3> MinOp> - : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">; - -def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>; -def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>; - -let hasSideEffects = 0, isAsmParserOnly = 1 in -def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", [], - "", ALU64_tc_1_SLOT23>; - - -let hasSideEffects = 0 in -class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned> - : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs), - "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") - #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00111; - let Inst{22-21} = !if(isMax, 0b10, 0b01); - let Inst{20-16} = !if(isMax, Rt, Rs); - let Inst{12-8} = !if(isMax, Rs, Rt); - let Inst{7} = 0b1; - let Inst{6} = !if(isMax, 0b0, 0b1); - let Inst{5} = isUnsigned; - let Inst{4-0} = Rd; -} - -def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>; -def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>; -def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>; -def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>; - -//===----------------------------------------------------------------------===// -// ALU64/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// :raw form of vrcmpys:hi/lo insns -//===----------------------------------------------------------------------===// -// Vector reduce complex multiply by scalar. -let Defs = [USR_OVF], hasSideEffects = 0 in -class T_vrcmpRaw<string HiLo, bits<3>MajOp>: - MInst<(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b100; - let Inst{4-0} = Rdd; -} - -def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>; -def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>; - -// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l -let hasSideEffects = 0, isAsmParserOnly = 1 in -def M2_vrcmpys_s1 - : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">; - -// Vector reduce complex multiply by scalar with accumulation. -let Defs = [USR_OVF], hasSideEffects = 0 in -class T_vrcmpys_acc<string HiLo, bits<3>MajOp>: - MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [], - "$Rxx = $_src_"> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b100; - let Inst{4-0} = Rxx; - } - -def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>; -def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>; - -// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l - -let isAsmParserOnly = 1 in -def M2_vrcmpys_acc_s1 - : MInst <(outs DoubleRegs:$dst), - (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2), - "$dst += vrcmpys($src1, $src2):<<1:sat", [], - "$dst2 = $dst">; - -def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>; -def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>; - -// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l -let isAsmParserOnly = 1 in -def M2_vrcmpys_s1rp - : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">; - - -// S2_cabacdecbin: Cabac decode bin. -let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in -def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>; diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td deleted file mode 100644 index 46f2b525442..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ /dev/null @@ -1,3318 +0,0 @@ -//=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V4 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -def DuplexIClass0: InstDuplex < 0 >; -def DuplexIClass1: InstDuplex < 1 >; -def DuplexIClass2: InstDuplex < 2 >; -let isExtendable = 1 in { - def DuplexIClass3: InstDuplex < 3 >; - def DuplexIClass4: InstDuplex < 4 >; - def DuplexIClass5: InstDuplex < 5 >; - def DuplexIClass6: InstDuplex < 6 >; - def DuplexIClass7: InstDuplex < 7 >; -} -def DuplexIClass8: InstDuplex < 8 >; -def DuplexIClass9: InstDuplex < 9 >; -def DuplexIClassA: InstDuplex < 0xA >; -def DuplexIClassB: InstDuplex < 0xB >; -def DuplexIClassC: InstDuplex < 0xC >; -def DuplexIClassD: InstDuplex < 0xD >; -def DuplexIClassE: InstDuplex < 0xE >; -def DuplexIClassF: InstDuplex < 0xF >; - -let hasSideEffects = 0 in -class T_Immext<Operand ImmType> - : EXTENDERInst<(outs), (ins ImmType:$imm), - "immext(#$imm)", []> { - bits<32> imm; - let IClass = 0b0000; - - let Inst{27-16} = imm{31-20}; - let Inst{13-0} = imm{19-6}; - } - -def A4_ext : T_Immext<u26_6Imm>; - -// Hexagon V4 Architecture spec defines 8 instruction classes: -// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the -// compiler) - -// LD Instructions: -// ======================================== -// Loads (8/16/32/64 bit) -// Deallocframe - -// ST Instructions: -// ======================================== -// Stores (8/16/32/64 bit) -// Allocframe - -// ALU32 Instructions: -// ======================================== -// Arithmetic / Logical (32 bit) -// Vector Halfword - -// XTYPE Instructions (32/64 bit): -// ======================================== -// Arithmetic, Logical, Bit Manipulation -// Multiply (Integer, Fractional, Complex) -// Permute / Vector Permute Operations -// Predicate Operations -// Shift / Shift with Add/Sub/Logical -// Vector Byte ALU -// Vector Halfword (ALU, Shift, Multiply) -// Vector Word (ALU, Shift) - -// J Instructions: -// ======================================== -// Jump/Call PC-relative - -// JR Instructions: -// ======================================== -// Jump/Call Register - -// MEMOP Instructions: -// ======================================== -// Operation on memory (8/16/32 bit) - -// NV Instructions: -// ======================================== -// New-value Jumps -// New-value Stores - -// CR Instructions: -// ======================================== -// Control-Register Transfers -// Hardware Loop Setup -// Predicate Logicals & Reductions - -// SYSTEM Instructions (not implemented in the compiler): -// ======================================== -// Prefetch -// Cache Maintenance -// Bus Operations - - -//===----------------------------------------------------------------------===// -// ALU32 + -//===----------------------------------------------------------------------===// - -class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> - : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> { - let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)"; -} - -let BaseOpcode = "andn_rr", CextOpcode = "andn" in -def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>; -let BaseOpcode = "orn_rr", CextOpcode = "orn" in -def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>; - -let CextOpcode = "rcmp.eq" in -def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>; -let CextOpcode = "!rcmp.eq" in -def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>; - -def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>; -def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>; -def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>; - -class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>, - ImmRegRel { - let InputType = "reg"; - let CextOpcode = mnemonic; - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1100; - let Inst{27-21} = 0b0111110; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{1-0} = Pd; -} - -def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>; -def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>; -def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>; -def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>; -def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>; -def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>; - -class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm, - Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits> - : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm), - "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>, - ImmRegRel { - let InputType = "imm"; - let CextOpcode = mnemonic; - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - let isExtendable = IsImmExt; - let opExtendable = !if (IsImmExt, 2, 0); - let isExtentSigned = IsImmSigned; - let opExtentBits = ImmBits; - - bits<2> Pd; - bits<5> Rs; - bits<8> Imm; - - let IClass = 0b1101; - let Inst{27-24} = 0b1101; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-5} = Imm; - let Inst{4} = 0b0; - let Inst{3} = IsHalf; - let Inst{1-0} = Pd; -} - -def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8_0Imm, 0, 0, 8>; -def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8_0Imm, 0, 1, 8>; -def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7_0Ext, 1, 0, 7>; -def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8_0Ext, 1, 1, 8>; -def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8_0Ext, 1, 1, 8>; -def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7_0Ext, 1, 0, 7>; - -class T_RCMP_EQ_ri<string mnemonic, bit IsNeg> - : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>, - ImmRegRel { - let InputType = "imm"; - let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq"); - let isExtendable = 1; - let opExtendable = 2; - let isExtentSigned = 1; - let opExtentBits = 8; - let hasNewValue = 1; - - bits<5> Rd; - bits<5> Rs; - bits<8> s8; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{22} = 0b1; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; -} - -def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>; -def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>; - -//===----------------------------------------------------------------------===// -// ALU32 - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PERM + -//===----------------------------------------------------------------------===// - -// Combine a word and an immediate into a register pair. -let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1, - opExtentBits = 8 in -class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr> - : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> { - bits<5> Rdd; - bits<5> Rs; - bits<8> s8; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -let opExtendable = 2 in -def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Rdd = combine($Rs, #$s8)">; - -let opExtendable = 1 in -def A4_combineir : T_Combine1<0b01, (ins s8_0Ext:$s8, IntRegs:$Rs), - "$Rdd = combine(#$s8, $Rs)">; - -// A4_combineii: Set two small immediates. -let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in -def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8_0Imm:$s8, u6_0Ext:$U6), - "$Rdd = combine(#$s8, #$U6)"> { - bits<5> Rdd; - bits<8> s8; - bits<6> U6; - - let IClass = 0b0111; - let Inst{27-23} = 0b11001; - let Inst{20-16} = U6{5-1}; - let Inst{13} = U6{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// ALU32/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// LD + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template class for load instructions with Absolute set addressing mode. -//===----------------------------------------------------------------------===// -let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet, - hasSideEffects = 0 in -class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>: - LDInst<(outs RC:$dst1, IntRegs:$dst2), - (ins u6_0Ext:$addr), - "$dst1 = "#mnemonic#"($dst2 = #$addr)", - []> { - bits<7> name; - bits<5> dst1; - bits<5> dst2; - bits<6> addr; - - let IClass = 0b1001; - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{13-12} = 0b01; - let Inst{4-0} = dst1; - let Inst{20-16} = dst2; - let Inst{11-8} = addr{5-2}; - let Inst{6-5} = addr{1-0}; -} - -let accessSize = ByteAccess, hasNewValue = 1 in { - def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>; - def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>; - def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>; - def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>; - def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in - def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>; - -let accessSize = WordAccess in { - def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>; - def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>; -} - -let accessSize = DoubleWordAccess in -def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>; - -let accessSize = ByteAccess in - def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>; - -let accessSize = HalfWordAccess in -def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>; - -// Load - Indirect with long offset -let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1, -opExtentBits = 6, opExtendable = 3 in -class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC, - bits<4> MajOp> - : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3), - "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)", - [] >, ImmRegShl { - bits<5> dst; - bits<5> src1; - bits<2> src2; - bits<6> src3; - let CextOpcode = CextOp; - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12} = 0b1; - let Inst{11-8} = src3{5-2}; - let Inst{7} = src2{0}; - let Inst{6-5} = src3{1-0}; - let Inst{4-0} = dst; - } - -let accessSize = ByteAccess in { - def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>; - def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>; - def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo", - DoubleRegs, 0b0100>; -} - -let accessSize = HalfWordAccess in { - def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>; - def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>; - def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>; - def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>; - def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo", - DoubleRegs, 0b0010>; -} - -let accessSize = WordAccess in { - def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>; - def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>; - def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>; -} - -let accessSize = DoubleWordAccess in -def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>; - - -//===----------------------------------------------------------------------===// -// Template classes for the non-predicated load instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>: - LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2_0Imm:$u2), - "$dst = "#mnemonic#"($src1 + $src2<<#$u2)", - [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<2> u2; - - let IClass = 0b0011; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated load instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isNot, bit isPredNew>: - LDInst <(outs RC:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2_0Imm:$u2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)", - [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<5> src3; - bits<2> u2; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - - let IClass = 0b0011; - - let Inst{27-26} = 0b00; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = MajOp; - let Inst{20-16} = src2; - let Inst{12-8} = src3; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = src1; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// multiclass for load instructions with base + register offset -// addressing mode -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = BaseRegOffset in -multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp > { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl, - InputType = "reg" in { - let isPredicable = 1 in - def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>; - - // Predicated - def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>; - def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>; - - // Predicated new - def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>; - def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>; - } -} - -let hasNewValue = 1, accessSize = ByteAccess in { - defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>; - defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>; -} - -let hasNewValue = 1, accessSize = HalfWordAccess in { - defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>; - defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>; -} - -let hasNewValue = 1, accessSize = WordAccess in -defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>; - -let accessSize = DoubleWordAccess in -defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>; - -//===----------------------------------------------------------------------===// -// LD - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ST + -//===----------------------------------------------------------------------===// -/// -//===----------------------------------------------------------------------===// -// Template class for store instructions with Absolute set addressing mode. -//===----------------------------------------------------------------------===// -let isExtended = 1, opExtendable = 1, opExtentBits = 6, - addrMode = AbsoluteSet in -class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC, - bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0> - : STInst<(outs IntRegs:$dst), - (ins u6_0Ext:$addr, RC:$src), - mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel { - bits<5> dst; - bits<6> addr; - bits<5> src; - let accessSize = AccessSz; - let BaseOpcode = BaseOp#"_AbsSet"; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = dst; - let Inst{13} = 0b0; - let Inst{12-8} = src; - let Inst{7} = 0b1; - let Inst{5-0} = addr; - } - -def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>; -def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010, - HalfWordAccess>; -def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>; - -let isNVStorable = 0 in { - def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs, - 0b011, HalfWordAccess, 1>; - def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs, - 0b110, DoubleWordAccess>; -} - -let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2, -isExtended = 1, opExtentBits= 6 in -class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp, - MemAccessSize AccessSz > - : NVInst <(outs IntRegs:$dst), - (ins u6_0Ext:$addr, IntRegs:$src), - mnemonic#"($dst = #$addr) = $src.new">, NewValueRel { - bits<5> dst; - bits<6> addr; - bits<3> src; - let accessSize = AccessSz; - let BaseOpcode = BaseOp#"_AbsSet"; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = dst; - let Inst{13-11} = 0b000; - let Inst{12-11} = MajOp; - let Inst{10-8} = src; - let Inst{7} = 0b1; - let Inst{5-0} = addr; - } - -let mayStore = 1, addrMode = AbsoluteSet in { - def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>; - def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>; - def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>; -} - -let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm", - addrMode = BaseLongOffset, AddedComplexity = 40 in -class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0> - : STInst<(outs), - (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, RC:$src4), - mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""), - []>, ImmRegShl, NewValueRel { - - bits<5> src1; - bits<2> src2; - bits<6> src3; - bits<5> src4; - - let accessSize = AccessSz; - let CextOpcode = CextOp; - let BaseOpcode = CextOp#"_shl"; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} =0b1101; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12-8} = src4; - let Inst{7} = 0b1; - let Inst{6} = src2{0}; - let Inst{5-0} = src3; -} - -def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>; -def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010, - HalfWordAccess>; -def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011, - HalfWordAccess, 1>; -def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>; -def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110, - DoubleWordAccess>; - -let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset, - opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in -class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp, - MemAccessSize AccessSz> - : NVInst <(outs ), - (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, IntRegs:$src4), - mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel { - bits<5> src1; - bits<2> src2; - bits<6> src3; - bits<3> src4; - - let CextOpcode = CextOp; - let BaseOpcode = CextOp#"_shl"; - let IClass = 0b1010; - - let Inst{27-21} = 0b1101101; - let Inst{12-11} = 0b00; - let Inst{7} = 0b1; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src4; - let Inst{6} = src2{0}; - let Inst{5-0} = src3; - } - -def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>; -def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>; -def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Template classes for the non-predicated store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicable = 1 in -class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH> - : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt), - mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""), - [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel { - - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<5> Rt; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0011; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-0} = Rt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isNot, bit isPredNew, bit isH> - : STInst <(outs), - (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt), - - !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""), - [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{ - bits<2> Pv; - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<5> Rt; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0011; - - let Inst{27-26} = 0b01; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = Pv; - let Inst{4-0} = Rt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the new-value store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicable = 1, isNewValue = 1, opNewValue = 3 in -class T_store_new_rr <string mnemonic, bits<2> MajOp> : - NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt), - mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new", - [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel { - - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<3> Nt; - - let IClass = 0b0011; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-3} = MajOp; - let Inst{2-0} = Nt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated new-value store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1, isNewValue = 1, opNewValue = 4 in -class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew> - : NVInst<(outs), - (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt), - !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new", - [], "", V4LDST_tc_st_SLOT0>, AddrModeRel { - bits<2> Pv; - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<3> Nt; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - - let IClass = 0b0011; - let Inst{27-26} = 0b01; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = 0b101; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = Pv; - let Inst{4-3} = MajOp; - let Inst{2-0} = Nt; - } - -//===----------------------------------------------------------------------===// -// multiclass for store instructions with base + register offset addressing -// mode -//===----------------------------------------------------------------------===// -let isNVStorable = 1 in -multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp, bit isH = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>; - - // Predicated - def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>; - def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>; - - // Predicated new - def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>; - def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>; - } -} - -//===----------------------------------------------------------------------===// -// multiclass for new-value store instructions with base + register offset -// addressing mode. -//===----------------------------------------------------------------------===// -let mayStore = 1, isNVStore = 1 in -multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>; - - // Predicated - def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>; - def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>; - - // Predicated new - def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>; - def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>; - } -} - -let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>, - ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>; - - let accessSize = HalfWordAccess in - defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>, - ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>; - - let accessSize = WordAccess in - defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>, - ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>; - - let isNVStorable = 0, accessSize = DoubleWordAccess in - defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>; - - let isNVStorable = 0, accessSize = HalfWordAccess in - defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>; -} - -//===----------------------------------------------------------------------===// -// Template class -//===----------------------------------------------------------------------===// -let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8, - opExtendable = 2 in -class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp > - : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8_0Ext:$S8), - mnemonic#"($Rs+#$offset)=#$S8", - [], "", V4LDST_tc_st_SLOT01>, - ImmRegRel, PredNewRel { - bits<5> Rs; - bits<8> S8; - bits<8> offset; - bits<6> offsetBits; - - string OffsetOpStr = !cast<string>(OffsetOp); - let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, - !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, - /* u6_0Imm */ offset{5-0})); - - let IClass = 0b0011; - - let Inst{27-25} = 0b110; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-7} = offsetBits; - let Inst{13} = S8{7}; - let Inst{6-0} = S8{6-0}; - } - -let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6, - opExtendable = 3 in -class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp, - bit isPredNot, bit isPredNew > - : STInst <(outs ), - (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6_0Ext:$S6), - !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+#$offset)=#$S6", - [], "", V4LDST_tc_st_SLOT01>, - ImmRegRel, PredNewRel { - bits<2> Pv; - bits<5> Rs; - bits<6> S6; - bits<8> offset; - bits<6> offsetBits; - - string OffsetOpStr = !cast<string>(OffsetOp); - let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, - !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, - /* u6_0Imm */ offset{5-0})); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b0011; - - let Inst{27-25} = 0b100; - let Inst{24} = isPredNew; - let Inst{23} = isPredNot; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = S6{5}; - let Inst{12-7} = offsetBits; - let Inst{6-5} = Pv; - let Inst{4-0} = S6{4-0}; - } - - -//===----------------------------------------------------------------------===// -// multiclass for store instructions with base + immediate offset -// addressing mode and immediate stored value. -// mem[bhw](Rx++#s4:3)=#s8 -// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6 -//===----------------------------------------------------------------------===// - -multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp, - bit PredNot> { - def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>; - // Predicate new - def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>; -} - -multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in { - def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>; - - defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>; - defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>; - } -} - -let hasSideEffects = 0, addrMode = BaseImmOffset, - InputType = "imm" in { - let accessSize = ByteAccess in - defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>; - - let accessSize = HalfWordAccess in - defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>; - - let accessSize = WordAccess in - defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>; -} - -//===----------------------------------------------------------------------=== -// ST - -//===----------------------------------------------------------------------=== - - -//===----------------------------------------------------------------------===// -// NV/ST + -//===----------------------------------------------------------------------===// - -let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in -class T_store_io_nv <string mnemonic, RegisterClass RC, - Operand ImmOp, bits<2>MajOp> - : NVInst_V4 <(outs), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2) = $src3.new", - [],"",ST_tc_st_SLOT0> { - bits<5> src1; - bits<13> src2; // Actual address offset - bits<3> src3; - bits<11> offsetBits; // Represents offset encoding - - let opExtentBits = !if (!eq(mnemonic, "memb"), 11, - !if (!eq(mnemonic, "memh"), 12, - !if (!eq(mnemonic, "memw"), 13, 0))); - - let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, - !if (!eq(mnemonic, "memh"), 1, - !if (!eq(mnemonic, "memw"), 2, 0))); - - let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0}, - !if (!eq(mnemonic, "memh"), src2{11-1}, - !if (!eq(mnemonic, "memw"), src2{12-2}, 0))); - - let IClass = 0b1010; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = 0b1101; - let Inst{20-16} = src1; - let Inst{13} = offsetBits{8}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7-0} = offsetBits{7-0}; - } - -let opExtendable = 2, opNewValue = 3, isPredicated = 1 in -class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp, - bits<2>MajOp, bit PredNot, bit isPredNew> - : NVInst_V4 <(outs), - (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4), - !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = $src4.new", - [],"",V2LDST_tc_st_SLOT0> { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src4; - bits<6> offsetBits; // Represents offset encoding - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = PredNot; - let opExtentBits = !if (!eq(mnemonic, "memb"), 6, - !if (!eq(mnemonic, "memh"), 7, - !if (!eq(mnemonic, "memw"), 8, 0))); - - let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, - !if (!eq(mnemonic, "memh"), 1, - !if (!eq(mnemonic, "memw"), 2, 0))); - - let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0}, - !if (!eq(mnemonic, "memh"), src3{6-1}, - !if (!eq(mnemonic, "memw"), src3{7-2}, 0))); - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{26} = PredNot; - let Inst{25} = isPredNew; - let Inst{24-21} = 0b0101; - let Inst{20-16} = src2; - let Inst{13} = offsetBits{5}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src4; - let Inst{7-3} = offsetBits{4-0}; - let Inst{2} = 0b0; - let Inst{1-0} = src1; - } - -// multiclass for new-value store instructions with base + immediate offset. -// -let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0, - isExtendable = 1 in -multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<2> MajOp> { - - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>; - // Predicated - def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>; - def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>; - // Predicated new - def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp, - MajOp, 0, 1>; - def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp, - MajOp, 1, 1>; - } -} - -let addrMode = BaseImmOffset, InputType = "imm" in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, - u6_0Ext, 0b00>, AddrModeRel; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, - u6_1Ext, 0b01>, AddrModeRel; - - let accessSize = WordAccess, opExtentAlign = 2 in - defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, - u6_2Ext, 0b10>, AddrModeRel; -} - -//===----------------------------------------------------------------------===// -// Post increment loads with register offset. -//===----------------------------------------------------------------------===// - -let hasNewValue = 1 in -def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>; - -def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>; - -let hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz> - : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_), - (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3), - "$dst = "#mnemonic#"($src2++$src3)", [], - "$src1 = $dst, $src2 = $_dst_"> { - bits<5> dst; - bits<5> src2; - bits<1> src3; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = src3; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>; -def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>; - -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment .new stores -// mem[bhwd](Rx++#s4:[0123])=Nt.new -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1, - isNewValue = 1, opNewValue = 3 in -class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp > - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2), - mnemonic#"($src1++#$offset) = $src2.new", - [], "$src1 = $_dst_">, - AddrModeRel { - bits<5> src1; - bits<3> src2; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0})); - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-11} = MajOp; - let Inst{10-8} = src2; - let Inst{7} = 0b0; - let Inst{6-3} = offsetBits; - let Inst{1} = 0b0; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment .new stores -// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1, - isNewValue = 1, opNewValue = 4 in -class T_StorePI_nv_pred <string mnemonic, Operand ImmOp, - bits<2> MajOp, bit isPredNot, bit isPredNew > - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, - ImmOp:$offset, IntRegs:$src3), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3.new", - [], "$src2 = $_dst_">, - AddrModeRel { - bits<2> src1; - bits<5> src2; - bits<3> src3; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0})); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7} = isPredNew; - let Inst{6-3} = offsetBits; - let Inst{2} = isPredNot; - let Inst{1-0} = src1; - } - -multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp, - bits<2> MajOp, bit PredNot> { - def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>; - - // Predicate new - def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>; -} - -multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp, - bits<2> MajOp> { - let BaseOpcode = "POST_"#BaseOp in { - def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>; - - // Predicated - defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>; - defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>; - } -} - -let accessSize = ByteAccess in -defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>; - -let accessSize = HalfWordAccess in -defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>; - -let accessSize = WordAccess in -defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>; - -//===----------------------------------------------------------------------===// -// Template class for post increment .new stores with register offset -//===----------------------------------------------------------------------===// -let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in -class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz> - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3), - #mnemonic#"($src1++$src2) = $src3.new", - [], "$src1 = $_dst_"> { - bits<5> src1; - bits<1> src2; - bits<3> src3; - let accessSize = AccessSz; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1101101; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7} = 0b0; - } - -def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>; -def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>; -def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>; - -// memb(Rx++#s4:0:circ(Mu))=Nt.new -// memb(Rx++I:circ(Mu))=Nt.new -// memb(Rx++Mu:brev)=Nt.new -// memh(Rx++#s4:1:circ(Mu))=Nt.new -// memh(Rx++I:circ(Mu))=Nt.new -// memh(Rx++Mu)=Nt.new -// memh(Rx++Mu:brev)=Nt.new - -// memw(Rx++#s4:2:circ(Mu))=Nt.new -// memw(Rx++I:circ(Mu))=Nt.new -// memw(Rx++Mu)=Nt.new -// memw(Rx++Mu:brev)=Nt.new - -//===----------------------------------------------------------------------===// -// NV/ST - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// NV/J + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps with the register -// operands. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum, - bit isNegCond, bit isTak> - : NVInst_V4<(outs), - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), - "if ("#!if(isNegCond, "!","")#mnemonic# - "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")# - "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - bits<5> src1; - bits<5> src2; - bits<3> Ns; // New-Value Operand - bits<5> RegOp; // Non-New-Value Operand - bits<11> offset; - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let opNewValue{0} = NvOpNum; - - let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0}); - let RegOp = !if(!eq(NvOpNum, 0), src2, src1); - - let IClass = 0b0010; - let Inst{27-26} = 0b00; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = Ns; - let Inst{13} = isTak; - let Inst{12-8} = RegOp; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - - -multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum, - bit isNegCond> { - // Branch not taken: - def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>; - // Branch taken: - def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>; -} - -// NvOpNum = 0 -> First Operand is a new-value Register -// NvOpNum = 1 -> Second Operand is a new-value Register - -multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp, - bit NvOpNum> { - let BaseOpcode = BaseOp#_NVJ in { - defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond - defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond - } -} - -// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel; - defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel; - defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel; - defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel; - defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel; -} - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps instruction -// with a register and an unsigned immediate (U5) operand. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond, - bit isTak> - : NVInst_V4<(outs), - (ins IntRegs:$src1, u5_0Imm:$src2, brtarget:$offset), - "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let isTaken = isTak; - - bits<3> src1; - bits<5> src2; - bits<11> offset; - - let IClass = 0b0010; - let Inst{26} = 0b1; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = src1; - let Inst{13} = isTak; - let Inst{12-8} = src2; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - -multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> { - // Branch not taken: - def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>; - // Branch taken: - def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>; -} - -multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> { - let BaseOpcode = BaseOp#_NVJri in { - defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond - defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond - } -} - -// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel; - defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel; - defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel; -} - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps instruction -// with a register and an hardcoded 0/-1 immediate value. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal, - bit isNegCond, bit isTak> - : NVInst_V4<(outs), - !if(!eq(ImmVal, "{-1}"), - (ins IntRegs:$src1, n1Const:$n1, brtarget:$offset), - (ins IntRegs:$src1, brtarget:$offset)), - "if ("#!if(isNegCond, "!","")#mnemonic - #"($src1.new, #" # !if(!eq(ImmVal, "{-1}"), "$n1", ImmVal) # ")) jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let isTaken = isTak; - let opExtendable = !if(!eq(ImmVal, "{-1}"), 2, 1); - - bits<3> src1; - bits<11> offset; - let IClass = 0b0010; - let Inst{26} = 0b1; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = src1; - let Inst{13} = isTak; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - -multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal, - bit isNegCond> { - // Branch not taken: - def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>; - // Branch taken: - def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>; -} - -multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp, - string ImmVal> { - let BaseOpcode = BaseOp#_NVJ_ConstImm in { - defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True - defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False - } -} - -// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2 -// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel; - defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "{-1}">, PredRel; - defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "{-1}">, PredRel; -} - -// J4_hintjumpr: Hint indirect conditional jump. -let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def J4_hintjumpr: JRInst < - (outs), - (ins IntRegs:$Rs), - "hintjr($Rs)"> { - bits<5> Rs; - let IClass = 0b0101; - let Inst{27-21} = 0b0010101; - let Inst{20-16} = Rs; - } - -//===----------------------------------------------------------------------===// -// NV/J - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// CR + -//===----------------------------------------------------------------------===// - -// PC-relative add -let hasNewValue = 1, isExtendable = 1, opExtendable = 1, - isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in -def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6_0Ext:$u6), - "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > { - bits<5> Rd; - bits<6> u6; - - let IClass = 0b0110; - let Inst{27-16} = 0b101001001001; - let Inst{12-7} = u6; - let Inst{4-0} = Rd; - } - - - -let hasSideEffects = 0 in -class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg> - : CRInst<(outs PredRegs:$Pd), - (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu), - "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " # - !if (IsNeg,"!","") # "$Pu))", - [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - bits<2> Pt; - bits<2> Pu; - - let IClass = 0b0110; - let Inst{27-24} = 0b1011; - let Inst{23} = IsNeg; - let Inst{22-21} = OpBits; - let Inst{20} = 0b1; - let Inst{17-16} = Ps; - let Inst{13} = 0b0; - let Inst{9-8} = Pt; - let Inst{7-6} = Pu; - let Inst{1-0} = Pd; -} - -def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>; -def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>; -def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>; -def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>; -def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>; -def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>; -def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>; -def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>; - -//===----------------------------------------------------------------------===// -// CR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/ALU + -//===----------------------------------------------------------------------===// - -// Logical with-not instructions. -def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>; -def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>; - -let hasNewValue = 1, hasSideEffects = 0 in -def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101111; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -// Add and accumulate. -// Rd=add(Rs,add(Ru,#s6)) -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6, - opExtendable = 3 in -def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Ru, s6_0Ext:$s6), - "$Rd = add($Rs, add($Ru, #$s6))" , [], - "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Ru; - bits<6> s6; - - let IClass = 0b1101; - - let Inst{27-23} = 0b10110; - let Inst{22-21} = s6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = s6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = s6{2-0}; - let Inst{4-0} = Ru; - } - -let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1, - opExtentBits = 6, opExtendable = 2 in -def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, s6_0Ext:$s6, IntRegs:$Ru), - "$Rd = add($Rs, sub(#$s6, $Ru))", - [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<6> s6; - bits<5> Ru; - - let IClass = 0b1101; - - let Inst{27-23} = 0b10111; - let Inst{22-21} = s6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = s6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = s6{2-0}; - let Inst{4-0} = Ru; - } - -def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>; -def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6_0Imm>; - -let hasNewValue = 1 in { - def S4_extract_rp : T_S3op_extract<"extract", 0b01>; - def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5_0Imm>; -} - -// Complex add/sub halfwords/words -let Defs = [USR_OVF] in { - def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>; - def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>; - def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>; - def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>; -} - -let Defs = [USR_OVF] in { - def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>; - def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>; -} - -let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in { - def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>; - def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>; -} - -// Logical xor with xor accumulation. -// Rxx^=xor(Rss,Rtt) -let hasSideEffects = 0 in -def M4_xor_xacc - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx ^= xor($Rss, $Rtt)", [], - "$dst2 = $Rxx", S_3op_tc_1_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b101010; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rxx; - } - -// Rotate and reduce bytes -// Rdd=vrcrotate(Rss,Rt,#u2) -let hasSideEffects = 0 in -def S4_vrcrotate - : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2), - "$Rdd = vrcrotate($Rss, $Rt, #$u2)", - [], "", S_3op_tc_3x_SLOT23> { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rt; - bits<2> u2; - - let IClass = 0b1100; - - let Inst{27-22} = 0b001111; - let Inst{20-16} = Rss; - let Inst{13} = u2{1}; - let Inst{12-8} = Rt; - let Inst{7-6} = 0b11; - let Inst{5} = u2{0}; - let Inst{4-0} = Rdd; - } - -// Rotate and reduce bytes with accumulation -// Rxx+=vrcrotate(Rss,Rt,#u2) -let hasSideEffects = 0 in -def S4_vrcrotate_acc - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2), - "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [], - "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - bits<2> u2; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rss; - let Inst{13} = u2{1}; - let Inst{12-8} = Rt; - let Inst{5} = u2{0}; - let Inst{4-0} = Rxx; - } - -// Vector reduce conditional negate halfwords -let hasSideEffects = 0 in -def S2_vrcnegh - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt), - "$Rxx += vrcnegh($Rss, $Rt)", [], - "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011001; - let Inst{20-16} = Rss; - let Inst{13} = 0b1; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b111; - let Inst{4-0} = Rxx; - } - -// Split bitfield -def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>; - -// Arithmetic/Convergent round -def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>; - -def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>; - -let Defs = [USR_OVF] in -def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>; - -// Logical-logical words. -// Compound or-and -- Rx=or(Ru,and(Rx,#s10)) -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10, - opExtendable = 3 in -def S4_or_andix: - ALU64Inst<(outs IntRegs:$Rx), - (ins IntRegs:$Ru, IntRegs:$_src_, s10_0Ext:$s10), - "$Rx = or($Ru, and($_src_, #$s10))" , [] , - "$_src_ = $Rx", ALU64_tc_2_SLOT23> { - bits<5> Rx; - bits<5> Ru; - bits<10> s10; - - let IClass = 0b1101; - - let Inst{27-22} = 0b101001; - let Inst{20-16} = Rx; - let Inst{21} = s10{9}; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Ru; - } - -// Miscellaneous ALU64 instructions. -// -let hasNewValue = 1, hasSideEffects = 0 in -def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0011111; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b111; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0100; - let Inst{21} = 0b1; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0100; - let Inst{21} = 0b0; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, hasSideEffects = 0 in -def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, hasSideEffects = 0 in -def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101100; - let Inst{20-16} = Rt; - let Inst{12-8} = Rs; - let Inst{7} = 0b1; - let Inst{4-0} = Rd; -} - -// Rx[&|]=xor(Rs,Rt) -def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>; -def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>; - -// Rx[&|^]=or(Rs,Rt) -def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>; - -let CextOpcode = "ORr_ORr" in -def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>; -def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>; - -// Rx[&|^]=and(Rs,Rt) -def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>; - -let CextOpcode = "ORr_ANDr" in -def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>; -def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>; - -// Rx[&|^]=and(Rs,~Rt) -def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>; -def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>; -def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>; - -// Compound or-or and or-and -let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1, - opExtentBits = 10, opExtendable = 3 in -class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode> - : MInst_acc <(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, s10_0Ext:$s10), - "$Rx |= "#mnemonic#"($Rs, #$s10)", [], - "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel { - bits<5> Rx; - bits<5> Rs; - bits<10> s10; - - let IClass = 0b1101; - - let Inst{27-24} = 0b1010; - let Inst{23-22} = MajOp; - let Inst{20-16} = Rs; - let Inst{21} = s10{9}; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rx; - } - -let CextOpcode = "ORr_ANDr" in -def S4_or_andi : T_CompOR <"and", 0b00, and>; - -let CextOpcode = "ORr_ORr" in -def S4_or_ori : T_CompOR <"or", 0b10, or>; - -// Modulo wrap -// Rd=modwrap(Rs,Rt) -// Round -// Rd=cround(Rs,#u5) -// Rd=cround(Rs,Rt) -// Rd=round(Rs,#u5)[:sat] -// Rd=round(Rs,Rt)[:sat] -// Vector reduce add unsigned halfwords -// Rd=vraddh(Rss,Rtt) -// Vector add bytes -// Rdd=vaddb(Rss,Rtt) -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -// Rxx+=vrcnegh(Rss,Rt) -// Vector maximum bytes -// Rdd=vmaxb(Rtt,Rss) -// Vector reduce maximum halfwords -// Rxx=vrmaxh(Rss,Ru) -// Rxx=vrmaxuh(Rss,Ru) -// Vector reduce maximum words -// Rxx=vrmaxuw(Rss,Ru) -// Rxx=vrmaxw(Rss,Ru) -// Vector minimum bytes -// Rdd=vminb(Rtt,Rss) -// Vector reduce minimum halfwords -// Rxx=vrminh(Rss,Ru) -// Rxx=vrminuh(Rss,Ru) -// Vector reduce minimum words -// Rxx=vrminuw(Rss,Ru) -// Rxx=vrminw(Rss,Ru) -// Vector subtract bytes -// Rdd=vsubb(Rss,Rtt) - -//===----------------------------------------------------------------------===// -// XTYPE/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/BIT + -//===----------------------------------------------------------------------===// - -// Bit reverse -def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>; - -// Bit count -def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>; -def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>; -def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>; - -let hasSideEffects = 0, hasNewValue = 1 in -def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6_0Imm:$s6), - "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> { - bits<5> Rs; - bits<5> Rd; - bits<6> s6; - let IClass = 0b1000; - let Inst{27-24} = 0b1100; - let Inst{23-21} = 0b001; - let Inst{20-16} = Rs; - let Inst{13-8} = s6; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6_0Imm:$s6), - "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> { - bits<5> Rs; - bits<5> Rd; - bits<6> s6; - let IClass = 0b1000; - let Inst{27-24} = 0b1000; - let Inst{23-21} = 0b011; - let Inst{20-16} = Rs; - let Inst{13-8} = s6; - let Inst{7-5} = 0b010; - let Inst{4-0} = Rd; -} - - -// Bit test/set/clear -def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>; -def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>; - -def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>; -def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>; -def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>; - -//===----------------------------------------------------------------------===// -// XTYPE/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/MPY + -//===----------------------------------------------------------------------===// - -// Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed. - -let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in -def M4_mpyri_addi : MInst<(outs IntRegs:$Rd), - (ins u6_0Ext:$u6, IntRegs:$Rs, u6_0Imm:$U6), - "$Rd = add(#$u6, mpyi($Rs, #$U6))" , [],"",ALU64_tc_3x_SLOT23> { - bits<5> Rd; - bits<6> u6; - bits<5> Rs; - bits<6> U6; - - let IClass = 0b1101; - - let Inst{27-24} = 0b1000; - let Inst{23} = U6{5}; - let Inst{22-21} = u6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = u6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = u6{2-0}; - let Inst{4-0} = U6{4-0}; - } - -// Rd=add(#u6,mpyi(Rs,Rt)) -let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1, - isExtendable = 1, opExtentBits = 6, opExtendable = 1 in -def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd), - (ins u6_0Ext:$u6, IntRegs:$Rs, IntRegs:$Rt), - "$Rd = add(#$u6, mpyi($Rs, $Rt))" , [], "", ALU64_tc_3x_SLOT23>, ImmRegRel { - bits<5> Rd; - bits<6> u6; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b01110; - let Inst{22-21} = u6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = u6{3}; - let Inst{12-8} = Rt; - let Inst{7-5} = u6{2-0}; - let Inst{4-0} = Rd; - } - -let hasNewValue = 1 in -class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins> - : ALU64Inst <(outs IntRegs:$dst), ins, - "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))", - "#$src2, $src3))"), [], - "", ALU64_tc_3x_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<8> src2; - bits<5> src3; - - let IClass = 0b1101; - - bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2}); - - let Inst{27-24} = 0b1111; - let Inst{23} = MajOp; - let Inst{22-21} = ImmValue{5-4}; - let Inst{20-16} = src3; - let Inst{13} = ImmValue{3}; - let Inst{12-8} = dst; - let Inst{7-5} = ImmValue{2-0}; - let Inst{4-0} = src1; - } - -def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred, - (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>; - -let isExtendable = 1, opExtentBits = 6, opExtendable = 3, - CextOpcode = "ADD_MPY", InputType = "imm" in -def M4_mpyri_addr : T_AddMpy<0b1, u32_0ImmPred, - (ins IntRegs:$src1, IntRegs:$src3, u6_0Ext:$src2)>, ImmRegRel; - -// Rx=add(Ru,mpyi(Rx,Rs)) -let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in -def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx), - (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs), - "$Rx = add($Ru, mpyi($_src_, $Rs))", [], - "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel { - bits<5> Rx; - bits<5> Ru; - bits<5> Rs; - - let IClass = 0b1110; - - let Inst{27-21} = 0b0011000; - let Inst{12-8} = Rx; - let Inst{4-0} = Ru; - let Inst{20-16} = Rs; - } - - -// Vector reduce multiply word by signed half (32x16) -//Rdd=vrmpyweh(Rss,Rtt)[:<<1] -def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>; -def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>; -def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>; - -//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] -def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>; -def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>; -def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>; - -// Vector multiply halfwords, signed by unsigned -// Rdd=vmpyhsu(Rs,Rt)[:<<]:sat -def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>; -def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>; - -// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat -def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>; -def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>; - -// Vector polynomial multiply halfwords -// Rdd=vpmpyh(Rs,Rt) -def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>; - -// Rxx^=vpmpyh(Rs,Rt) -def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>; - -// Polynomial multiply words -// Rdd=pmpyw(Rs,Rt) -def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>; - -// Rxx^=pmpyw(Rs,Rt) -def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>; - -//===----------------------------------------------------------------------===// -// XTYPE/MPY - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/Vector compare -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Template class for vector compare -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0 in -class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd> - : ALU64_rr <(outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, ImmOprnd:$Imm), - "$Pd = "#Str#"($Rss, #$Imm)", - [], "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rss; - bits<32> Imm; - bits<8> ImmBits; - let ImmBits{6-0} = Imm{6-0}; - let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu - - let IClass = 0b1101; - - let Inst{27-24} = 0b1100; - let Inst{22-21} = cmpOp; - let Inst{20-16} = Rss; - let Inst{12-5} = ImmBits; - let Inst{4-3} = minOp; - let Inst{1-0} = Pd; - } - -// Vector compare bytes -def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>; - -let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in -def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>; - -def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8_0Imm>; -def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8_0Imm>; -def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7_0Imm>; - -// Vector compare halfwords -def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8_0Imm>; -def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8_0Imm>; -def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7_0Imm>; - -// Vector compare words -def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8_0Imm>; -def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8_0Imm>; -def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7_0Imm>; - -//===----------------------------------------------------------------------===// -// XTYPE/SHIFT + -//===----------------------------------------------------------------------===// -// Shift by immediate and accumulate/logical. -// Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5)) -// Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5)) -// Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5)) -// Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, - hasNewValue = 1, opNewValue = 0 in -class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr, - bits<2> MajOp, InstrItinClass Itin> - : MInst_acc<(outs IntRegs:$Rd), (ins u8_0Ext:$u8, IntRegs:$Rx, u5_0Imm:$U5), - "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))", - [], "$Rd = $Rx", Itin> { - - bits<5> Rd; - bits<8> u8; - bits<5> Rx; - bits<5> U5; - - let IClass = 0b1101; - let Inst{27-24} = 0b1110; - let Inst{23-21} = u8{7-5}; - let Inst{20-16} = Rd; - let Inst{13} = u8{4}; - let Inst{12-8} = U5; - let Inst{7-5} = u8{3-1}; - let Inst{4} = asl_lsr; - let Inst{3} = u8{0}; - let Inst{2-1} = MajOp; -} - -multiclass T_ShiftOperate<string mnemonic, bits<2> MajOp, InstrItinClass Itin> { - def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", 0, MajOp, Itin>; - def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", 1, MajOp, Itin>; -} - -defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>; -defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>; -defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>; -defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>; - -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>; - -// Rd=[cround|round](Rs,Rt) -let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in { - def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>; - def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>; -} - -// Rd=round(Rs,Rt):sat -let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>; - -// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat -let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in { - def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>; - def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>; -} - -// Rdd=[add|sub](Rss,Rtt,Px):carry -let isPredicateLate = 1, hasSideEffects = 0 in -class T_S3op_carry <string mnemonic, bits<3> MajOp> - : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), - "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry", - [], "$Px = $Pu", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<2> Pu; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0010; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rdd; - } - -def A4_addp_c : T_S3op_carry < "add", 0b110 >; -def A4_subp_c : T_S3op_carry < "sub", 0b111 >; - -let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in -class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned> - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru), - "$Rxx = "#mnemonic#"($Rss, $Ru)" , - [] , "$dst2 = $Rxx"> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Ru; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011001; - let Inst{20-16} = Rss; - let Inst{13} = isUnsigned; - let Inst{12-8} = Rxx; - let Inst{7-5} = MinOp; - let Inst{4-0} = Ru; - } - -// Vector reduce maximum halfwords -// Rxx=vrmax[u]h(Rss,Ru) -def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>; -def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>; - -// Vector reduce maximum words -// Rxx=vrmax[u]w(Rss,Ru) -def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>; -def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>; - -// Vector reduce minimum halfwords -// Rxx=vrmin[u]h(Rss,Ru) -def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>; -def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>; - -// Vector reduce minimum words -// Rxx=vrmin[u]w(Rss,Ru) -def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>; -def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>; - -// Shift an immediate left by register amount. -let hasNewValue = 1, hasSideEffects = 0 in -def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6_0Imm:$s6, IntRegs:$Rt), - "$Rd = lsl(#$s6, $Rt)" , [], "", S_3op_tc_1_SLOT23> { - bits<5> Rd; - bits<6> s6; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b011010; - let Inst{20-16} = s6{5-1}; - let Inst{12-8} = Rt; - let Inst{7-6} = 0b11; - let Inst{4-0} = Rd; - let Inst{5} = s6{0}; - } - -//===----------------------------------------------------------------------===// -// XTYPE/SHIFT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MEMOP -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// Template class for MemOp instructions with the register value. -//===----------------------------------------------------------------------===// -class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp, - string memOp, bits<2> memOpBits> : - MEMInst_V4<(outs), - (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta), - opc#"($base+#$offset)"#memOp#"$delta", - []>, - Requires<[UseMEMOP]> { - - bits<5> base; - bits<5> delta; - bits<32> offset; - bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2 - - let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0}, - !if (!eq(opcBits, 0b01), offset{6-1}, - !if (!eq(opcBits, 0b10), offset{7-2},0))); - - let opExtentAlign = opcBits; - let IClass = 0b0011; - let Inst{27-24} = 0b1110; - let Inst{22-21} = opcBits; - let Inst{20-16} = base; - let Inst{13} = 0b0; - let Inst{12-7} = offsetBits; - let Inst{6-5} = memOpBits; - let Inst{4-0} = delta; -} - -//===----------------------------------------------------------------------===// -// Template class for MemOp instructions with the immediate value. -//===----------------------------------------------------------------------===// -class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp, - string memOp, bits<2> memOpBits> : - MEMInst_V4 <(outs), - (ins IntRegs:$base, ImmOp:$offset, u5_0Imm:$delta), - opc#"($base+#$offset)"#memOp#"#$delta" - #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')' - []>, - Requires<[UseMEMOP]> { - - bits<5> base; - bits<5> delta; - bits<32> offset; - bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2 - - let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0}, - !if (!eq(opcBits, 0b01), offset{6-1}, - !if (!eq(opcBits, 0b10), offset{7-2},0))); - - let opExtentAlign = opcBits; - let IClass = 0b0011; - let Inst{27-24} = 0b1111; - let Inst{22-21} = opcBits; - let Inst{20-16} = base; - let Inst{13} = 0b0; - let Inst{12-7} = offsetBits; - let Inst{6-5} = memOpBits; - let Inst{4-0} = delta; -} - -// multiclass to define MemOp instructions with register operand. -multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> { - def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add - def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub - def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and - def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or -} - -// multiclass to define MemOp instructions with immediate Operand. -multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> { - def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >; - def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >; - def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>; - def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>; -} - -multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> { - defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>; - defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>; -} - -// Define MemOp instructions. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in { - let opExtentBits = 6, accessSize = ByteAccess in - defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>; - - let opExtentBits = 7, accessSize = HalfWordAccess in - defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>; - - let opExtentBits = 8, accessSize = WordAccess in - defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>; -} - - -//===----------------------------------------------------------------------===// -// XTYPE/PRED + -//===----------------------------------------------------------------------===// - -// Hexagon V4 only supports these flavors of byte/half compare instructions: -// EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by -// hardware. However, compiler can still implement these patterns through -// appropriate patterns combinations based on current implemented patterns. -// The implemented patterns are: EQ/GT/GTU. -// Missing patterns are: GE/GEU/LT/LTU/LE/LEU. - -// Following instruction is not being extended as it results into the -// incorrect code for negative numbers. -// Pd=cmpb.eq(Rs,#u8) - -// p=!cmp.eq(r1,#s10) -def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10_0Ext>; -def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10_0Ext>; -def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9_0Ext>; - -//===----------------------------------------------------------------------===// -// XTYPE/PRED - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Multiclass for DeallocReturn -//===----------------------------------------------------------------------===// -class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak> - : LD0Inst<(outs), (ins PredRegs:$src), - !if(isNot, "if (!$src", "if ($src")# - !if(isPredNew, ".new) ", ") ")#mnemonic# - !if(isPredNew, #!if(isTak,":t", ":nt"),""), - [], "", LD_tc_3or4stall_SLOT0> { - - bits<2> src; - let BaseOpcode = "L4_RETURN"; - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - let isTaken = isTak; - let IClass = 0b1001; - - let Inst{27-16} = 0b011000011110; - - let Inst{13} = isNot; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{10} = 0b0; - let Inst{9-8} = src; - let Inst{4-0} = 0b11110; - } - -// Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt -multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> { - let isPredicated = 1 in { - def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>; - def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>; - def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>; - } -} - -multiclass LD_MISC_L4_RETURN<string mnemonic> { - let isBarrier = 1, isPredicable = 1 in - def NAME : LD0Inst <(outs), (ins), mnemonic, [], "", - LD_tc_3or4stall_SLOT0> { - let BaseOpcode = "L4_RETURN"; - let IClass = 0b1001; - let Inst{27-16} = 0b011000011110; - let Inst{13-10} = 0b0000; - let Inst{4-0} = 0b11110; - } - defm t : L4_RETURN_PRED<mnemonic, 0 >; - defm f : L4_RETURN_PRED<mnemonic, 1 >; -} - -let isReturn = 1, isTerminator = 1, - Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in -defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel; - -// Restore registers and dealloc return function call. -let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, - Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in { - def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">; - - let Defs = [R14, R15, R28, R29, R30, R31, PC] in { - def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">; - } -} - -// Restore registers and dealloc frame before a tail call. -let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in { - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, R29, R30, R31, PC] in { - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel; - } -} - -// Save registers function call. -let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { - def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel; - - let Defs = [P0] in - def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel; - - let Defs = [P0], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28] in - def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, P0] in - def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel; -} - -//===----------------------------------------------------------------------===// -// Template class for non predicated store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicable = 1 in -class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<2>MajOp, bit isAbs, bit isHalf> - : STInst<(outs), (ins ImmOp:$addr, RC:$src), - mnemonic # "(" # !if(isAbs,"","gp+") # "#$addr) = $src" # !if(isHalf,".h",""), - [], "", V2LDST_tc_st_SLOT01> { - bits<19> addr; - bits<5> src; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - let Uses = !if (isAbs, [], [GP]); - - let IClass = 0b0100; - let Inst{27} = 1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24} = 0b0; - let Inst{23-22} = MajOp; - let Inst{21} = isHalf; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13} = offsetBits{8}; - let Inst{12-8} = src; - let Inst{7-0} = offsetBits{7-0}; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in -class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp, - bit isHalf, bit isNot, bit isNew> - : STInst<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, RC: $src2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ", - ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""), - [], "", ST_tc_st_SLOT01>, AddrModeRel { - bits<2> src1; - bits<6> absaddr; - bits<5> src2; - - let isPredicatedNew = isNew; - let isPredicatedFalse = isNot; - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-22} = MajOp; - let Inst{21} = isHalf; - let Inst{17-16} = absaddr{5-4}; - let Inst{13} = isNew; - let Inst{12-8} = src2; - let Inst{7} = 0b1; - let Inst{6-3} = absaddr{3-0}; - let Inst{2} = isNot; - let Inst{1-0} = src1; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<2> MajOp, bit isHalf> - : T_StoreAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1, isHalf>, - AddrModeRel { - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); -} - -//===----------------------------------------------------------------------===// -// Multiclass for store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -let addrMode = Absolute, isExtended = 1 in -multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, bits<2> MajOp, bit isHalf = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 0, isPredicable = 1 in - def PS_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>; - - // Predicated - def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>; - def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>; - - // .new Predicated - def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>; - def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>; - } -} - -//===----------------------------------------------------------------------===// -// Template class for non predicated new-value store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1, - isNewValue = 1, opNewValue = 1 in -class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp, bit isAbs> - : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src), - mnemonic #"(" # !if(isAbs, "", "gp+") # "#$addr) = $src.new", - [], "", V2LDST_tc_st_SLOT0> { - bits<19> addr; - bits<3> src; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); - let IClass = 0b0100; - - let Inst{27} = 1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24-21} = 0b0101; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13} = offsetBits{8}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src; - let Inst{7-0} = offsetBits{7-0}; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated new-value store instructions with -// absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1, - isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in -class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew> - : NVInst_V4<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, IntRegs:$src2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ", - ") ")#mnemonic#"(#$absaddr) = $src2.new", - [], "", ST_tc_st_SLOT0>, AddrModeRel { - bits<2> src1; - bits<6> absaddr; - bits<3> src2; - - let isPredicatedNew = isNew; - let isPredicatedFalse = isNot; - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = 0b101; - let Inst{17-16} = absaddr{5-4}; - let Inst{13} = isNew; - let Inst{12-11} = MajOp; - let Inst{10-8} = src2; - let Inst{7} = 0b1; - let Inst{6-3} = absaddr{3-0}; - let Inst{2} = isNot; - let Inst{1-0} = src1; -} - -//===----------------------------------------------------------------------===// -// Template class for non-predicated new-value store instructions with -// absolute addressing. -//===----------------------------------------------------------------------===// -class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp> - : T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp, 1>, AddrModeRel { - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); -} - -//===----------------------------------------------------------------------===// -// Multiclass for new-value store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -let addrMode = Absolute, isExtended = 1 in -multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 0, isPredicable = 1 in - def PS_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>; - - // Predicated - def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>; - def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>; - - // .new Predicated - def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>; - def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>; - } -} - -//===----------------------------------------------------------------------===// -// Stores with absolute addressing -//===----------------------------------------------------------------------===// -let accessSize = ByteAccess in -defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>, - ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>; - -let accessSize = HalfWordAccess in -defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>, - ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>; - -let accessSize = WordAccess in -defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>, - ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>; - -let isNVStorable = 0, accessSize = DoubleWordAccess in -defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>; - -let isNVStorable = 0, accessSize = HalfWordAccess in -defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>; - -//===----------------------------------------------------------------------===// -// GP-relative stores. -// mem[bhwd](#global)=Rt -// Once predicated, these instructions map to absolute addressing mode. -// if ([!]Pv[.new]) mem[bhwd](##global)=Rt -//===----------------------------------------------------------------------===// - -let Uses = [GP], isAsmParserOnly = 1 in -class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<2> MajOp, bit isHalf = 0> - : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> { - // Set BaseOpcode same as absolute addressing instructions so that - // non-predicated GP-Rel instructions can have relate with predicated - // Absolute instruction. - let BaseOpcode = BaseOp#_abs; - } - -let Uses = [GP], isAsmParserOnly = 1 in -multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp, - bits<2> MajOp, bit isHalf = 0> { - // Set BaseOpcode same as absolute addressing instructions so that - // non-predicated GP-Rel instructions can have relate with predicated - // Absolute instruction. - let BaseOpcode = BaseOp#_abs in { - def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp, - 0, isHalf>; - // New-value store - def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ; - } -} - -let accessSize = ByteAccess in -defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel; - -let accessSize = HalfWordAccess in -defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel; - -let accessSize = WordAccess in -defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel; - -let isNVStorable = 0, accessSize = DoubleWordAccess in -def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs, - u16_3Imm, 0b11>, PredNewRel; - -let isNVStorable = 0, accessSize = HalfWordAccess in -def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs, - u16_1Imm, 0b01, 1>, PredNewRel; - -//===----------------------------------------------------------------------===// -// Template class for non predicated load instructions with -// absolute addressing mode. -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0 in -class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp, bit isAbs> - : LDInst <(outs RC:$dst), (ins ImmOp:$addr), - "$dst = " # mnemonic # "(" # !if(isAbs, "", "gp+") # "#$addr)", - [], "", V2LDST_tc_ld_SLOT01> { - bits<5> dst; - bits<19> addr; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); - - let IClass = 0b0100; - - let Inst{27} = 0b1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24} = 0b1; - let Inst{23-21} = MajOp; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp> - : T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1>, AddrModeRel { - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); - } - -//===----------------------------------------------------------------------===// -// Template class for predicated load instructions with -// absolute addressing mode. -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6, - opExtendable = 2 in -class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isPredNot, bit isPredNew> - : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32_0MustExt:$absaddr), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<6> absaddr; - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = MajOp; - let Inst{20-16} = absaddr{5-1}; - let Inst{13} = 0b1; - let Inst{12} = isPredNew; - let Inst{11} = isPredNot; - let Inst{10-9} = src1; - let Inst{8} = absaddr{0}; - let Inst{7} = 0b1; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Multiclass for the load instructions with absolute addressing mode. -//===----------------------------------------------------------------------===// -multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp, - bit PredNot> { - def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>; - // Predicate new - def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>; -} - -let addrMode = Absolute, isExtended = 1 in -multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, bits<3> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 1, isPredicable = 1 in - def PS_#NAME#abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>; - - // Predicated - defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>; - defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>; - } -} - -let accessSize = ByteAccess, hasNewValue = 1 in { - defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>; - defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>; - defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in -defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>; - -let accessSize = DoubleWordAccess in -defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>; - -//===----------------------------------------------------------------------===// -// multiclass for load instructions with GP-relative addressing mode. -// Rx=mem[bhwd](##global) -// Once predicated, these instructions map to absolute addressing mode. -// if ([!]Pv[.new]) Rx=mem[bhwd](##global) -//===----------------------------------------------------------------------===// - -let isAsmParserOnly = 1, Uses = [GP] in -class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp, - bits<3> MajOp> - : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, 0>, PredNewRel { - let BaseOpcode = BaseOp#_abs; - } - -let accessSize = ByteAccess, hasNewValue = 1 in { - def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>; - def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>; - def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in -def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>; - -let accessSize = DoubleWordAccess in -def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>; - -//===----------------------------------------------------------------------===// -// :raw for of boundscheck:hi:lo insns -//===----------------------------------------------------------------------===// - -// A4_boundscheck_lo: Detect if a register is within bounds. -let hasSideEffects = 0 in -def A4_boundscheck_lo: ALU64Inst < - (outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = boundscheck($Rss, $Rtt):raw:lo"> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = 0b1; - let Inst{7-5} = 0b100; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// A4_boundscheck_hi: Detect if a register is within bounds. -let hasSideEffects = 0 in -def A4_boundscheck_hi: ALU64Inst < - (outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = boundscheck($Rss, $Rtt):raw:hi"> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = 0b1; - let Inst{7-5} = 0b101; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -let hasSideEffects = 0, isAsmParserOnly = 1 in -def A4_boundscheck : MInst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), - "$Pd=boundscheck($Rs,$Rtt)">; - -// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry. -let isPredicateLate = 1, hasSideEffects = 0 in -def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd), - (ins DoubleRegs:$Rs, IntRegs:$Rt), - "$Pd = tlbmatch($Rs, $Rt)", - [], "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-23} = 0b00100; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b011; - let Inst{1-0} = Pd; - } - -// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't -// really do a load. -let hasSideEffects = 1, mayLoad = 0 in -def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3), - "dcfetch($Rs + #$u11_3)", - [], "", LD_tc_ld_SLOT0> { - bits<5> Rs; - bits<14> u11_3; - - let IClass = 0b1001; - let Inst{27-21} = 0b0100000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{10-0} = u11_3{13-3}; -} - - -//===----------------------------------------------------------------------===// -// Compound instructions -//===----------------------------------------------------------------------===// - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, - opExtentBits = 11, opExtentAlign = 2, opExtendable = 1, - isTerminator = 1 in -class CJInst_tstbit_R0<string px, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2), - ""#px#" = tstbit($Rs, #0); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { - bits<4> Rs; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{24-23} = 0b11; - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{9-8} = 0b11; - let Inst{7-1} = r9_2{8-2}; -} - -let Defs = [PC, P0], Uses = [P0] in { - def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">; - def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">; - def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">; - def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">; -} - -let Defs = [PC, P1], Uses = [P1] in { - def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">; - def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">; - def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">; - def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">; -} - - -let isBranch = 1, hasSideEffects = 0, - isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1, - isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, - opExtendable = 2, isTerminator = 1 in -class CJInst_RR<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs, $Rt); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { - bits<4> Rs; - bits<4> Rt; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-23} = !if (!eq(op, "eq"), 0b01000, - !if (!eq(op, "gt"), 0b01001, - !if (!eq(op, "gtu"), 0b01010, 0))); - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - // px: Predicate reg 0/1 - let Inst{12} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{11-8} = Rt; - let Inst{7-1} = r9_2{8-2}; -} - -// P[10] taken/not taken. -multiclass T_tnt_CJInst_RR<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_RR<string op>{ - defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>; - defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>; -} -// TypeCJ Instructions compare RR and jump -defm eq : T_pnp_CJInst_RR<"eq">; -defm gt : T_pnp_CJInst_RR<"gt">; -defm gtu : T_pnp_CJInst_RR<"gtu">; - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in -class CJInst_RU5<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs, #$U5); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { - bits<4> Rs; - bits<5> U5; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - // px: Predicate reg 0/1 - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{24-23} = !if (!eq(op, "eq"), 0b00, - !if (!eq(op, "gt"), 0b01, - !if (!eq(op, "gtu"), 0b10, 0))); - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{12-8} = U5; - let Inst{7-1} = r9_2{8-2}; -} -// P[10] taken/not taken. -multiclass T_tnt_CJInst_RU5<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_RU5<string op>{ - defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>; - defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>; -} -// TypeCJ Instructions compare RI and jump -defm eq : T_pnp_CJInst_RU5<"eq">; -defm gt : T_pnp_CJInst_RU5<"gt">; -defm gtu : T_pnp_CJInst_RU5<"gtu">; - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, - isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 2, - isTerminator = 1 in -class CJInst_Rn1<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs,#$n1); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon { - bits<4> Rs; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - - let Inst{24-23} = 0b11; - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{9-8} = !if (!eq(op, "eq"), 0b00, - !if (!eq(op, "gt"), 0b01, 0)); - let Inst{7-1} = r9_2{8-2}; -} - -// P[10] taken/not taken. -multiclass T_tnt_CJInst_Rn1<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_Rn1<string op>{ - defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>; - defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>; -} -// TypeCJ Instructions compare -1 and jump -defm eq : T_pnp_CJInst_Rn1<"eq">; -defm gt : T_pnp_CJInst_Rn1<"gt">; - -// J4_jumpseti: Direct unconditional jump and set register to immediate. -let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1, - isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2 in -def J4_jumpseti: CJInst_JMPSET < - (outs IntRegs:$Rd), - (ins u6_0Imm:$U6, brtarget:$r9_2), - "$Rd = #$U6 ; jump $r9_2"> { - bits<4> Rd; - bits<6> U6; - bits<11> r9_2; - - let IClass = 0b0001; - let Inst{27-24} = 0b0110; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rd; - let Inst{13-8} = U6; - let Inst{7-1} = r9_2{8-2}; - } - -// J4_jumpsetr: Direct unconditional jump and transfer register. -let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1, - isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2 in -def J4_jumpsetr: CJInst_JMPSET < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, brtarget:$r9_2), - "$Rd = $Rs ; jump $r9_2"> { - bits<4> Rd; - bits<4> Rs; - bits<11> r9_2; - - let IClass = 0b0001; - let Inst{27-24} = 0b0111; - let Inst{21-20} = r9_2{10-9}; - let Inst{11-8} = Rd; - let Inst{19-16} = Rs; - let Inst{7-1} = r9_2{8-2}; - } - -// Duplex instructions -//===----------------------------------------------------------------------===// -include "HexagonIsetDx.td" diff --git a/lib/Target/Hexagon/HexagonInstrInfoV5.td b/lib/Target/Hexagon/HexagonInstrInfoV5.td deleted file mode 100644 index cd19b6916f2..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfoV5.td +++ /dev/null @@ -1,497 +0,0 @@ -//=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V5 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/MPY -//===----------------------------------------------------------------------===// - - //Rdd[+]=vrmpybsu(Rss,Rtt) -let Predicates = [HasV5T] in { - def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>; - def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>; - - //Rdd[+]=vrmpybu(Rss,Rtt) - def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>; - def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>; - - def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>; - def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>; -} - -// Vector multiply bytes -// Rdd=vmpyb[s]u(Rs,Rt) -let Predicates = [HasV5T] in { - def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>; - def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>; - - // Rxx+=vmpyb[s]u(Rs,Rt) - def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>; - def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>; - - // Rd=vaddhub(Rss,Rtt):sat - let hasNewValue = 1, opNewValue = 0 in - def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>; -} - -def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6_0Imm, [], 1>, - Requires<[HasV5T]> { - bits<6> src2; - let Inst{13-8} = src2; -} - -let isAsmParserOnly = 1 in -def S2_asr_i_p_rnd_goodsyntax - : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6_0Imm:$src2), - "$dst = asrrnd($src1, #$src2)">; - -def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>, - Requires<[HasV5T]> { - let Inst{13,7,4} = 0b111; -} - -def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>, - Requires<[HasV5T]> { - let Inst{20,13,7,4} = 0b1111; -} - -let hasNewValue = 1, validSubTargets = HasV5SubT in -def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss), - "$Rd = popcount($Rss)", [], "", S_2op_tc_2_SLOT23>, - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1000011; - let Inst{7-5} = 0b011; - let Inst{4-0} = Rd; - let Inst{20-16} = Rss; - } - -let isFP = 1, hasNewValue = 1, opNewValue = 0 in -class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : MInst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#mnemonic#"($Rs, $Rt)", [], - "" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -let isCommutable = 1 in { - def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>; - def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>; -} - -def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>; - -let Itinerary = M_tc_3x_SLOT23 in { - def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>; - def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>; -} - -let Itinerary = M_tc_3or4x_SLOT23 in { -def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>; -def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>; -} - -// F2_sfrecipa: Reciprocal approximation for division. -let Uses = [USR], isPredicateLate = 1, isFP = 1, - hasSideEffects = 0, hasNewValue = 1, Itinerary = M_tc_3or4x_SLOT23 in -def F2_sfrecipa: MInst < - (outs IntRegs:$Rd, PredRegs:$Pe), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd, $Pe = sfrecipa($Rs, $Rt)">, - Requires<[HasV5T]> { - bits<5> Rd; - bits<2> Pe; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - let Inst{27-21} = 0b1011111; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6-5} = Pe; - let Inst{4-0} = Rd; - } - -// F2_dfcmpeq: Floating point compare for equal. -let Uses = [USR], isCompare = 1, isFP = 1 in -class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp, - list<dag> pattern = [] > - : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2), - "$dst = "#mnemonic#"($src1, $src2)", pattern, - "" , ALU64_tc_2early_SLOT23 > , - Requires<[HasV5T]> { - bits<2> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1101; - - let Inst{27-21} = 0b0010111; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{7-5} = MinOp; - let Inst{1-0} = dst; - } - -class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp> - : T_fcmp <mnemonic, DoubleRegs, MinOp, []> { - let IClass = 0b1101; - let Inst{27-21} = 0b0010111; -} - -class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp> - : T_fcmp <mnemonic, IntRegs, MinOp, []> { - let IClass = 0b1100; - let Inst{27-21} = 0b0111111; -} - -def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>; -def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>; -def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>; -def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>; - -def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>; -def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>; -def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>; -def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>; - -// F2 convert template classes: -let Uses = [USR], isFP = 1 in -class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), - "$Rdd = "#mnemonic#"($Rss)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rdd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0000111; - let Inst{20-16} = Rss; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -let Uses = [USR], isFP = 1 in -class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs), - "$Rdd = "#mnemonic#"($Rs)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rdd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0100100; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss), - "$Rd = "#mnemonic#"($Rss)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MinOp; - let Inst{20-16} = Rss; - let Inst{7-5} = 0b001; - let Inst{4-0} = Rd; - } - -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp, - string chop =""> - : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = "#mnemonic#"($Rs)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -// Convert single precision to double precision and vice-versa. -def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000>; -def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000>; - -// Convert Integer to Floating Point. -def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010>; -def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001>; -def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000>; -def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000>; -def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011>; -def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010>; -def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001>; -def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010>; - -// Convert Floating Point to Integer. -def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101, ":chop">; -def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111, ":chop">; -def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001, - ":chop">; -def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001, - ":chop">; -def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110, ":chop">; -def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111, ":chop">; -def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110, ":chop">; -def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101, ":chop">; - -// Convert Floating Point to Integer: non-chopped. -let AddedComplexity = 20, Predicates = [HasV5T] in { - def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000>; - def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001>; - def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011>; - def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100>; - def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011>; - def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100>; - def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000>; - def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000>; -} - -// Fix up radicand. -let Uses = [USR], isFP = 1, hasNewValue = 1 in -def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = sffixupr($Rs)", - [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rs; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rd; - } - -// F2_sffma: Floating-point fused multiply add. -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class T_sfmpy_acc <bit isSub, bit isLib> - : MInst<(outs IntRegs:$Rx), - (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""), - [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-21} = 0b1111000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6} = isLib; - let Inst{5} = isSub; - let Inst{4-0} = Rx; - } - -def F2_sffma: T_sfmpy_acc <0, 0>; -def F2_sffms: T_sfmpy_acc <1, 0>; -def F2_sffma_lib: T_sfmpy_acc <0, 1>; -def F2_sffms_lib: T_sfmpy_acc <1, 1>; - -// Floating-point fused multiply add w/ additional scaling (2**pu). -let Uses = [USR], isFP = 1, hasNewValue = 1 in -def F2_sffma_sc: MInst < - (outs IntRegs:$Rx), - (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu), - "$Rx += sfmpy($Rs, $Rt, $Pu):scale" , - [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - bits<2> Pu; - - let IClass = 0b1110; - - let Inst{27-21} = 0b1111011; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6-5} = Pu; - let Inst{4-0} = Rx; - } - -//===----------------------------------------------------------------------===// -// :natural forms of vasrh and vasrhub insns -//===----------------------------------------------------------------------===// -// S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round, -// saturate, and pack. -let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_ASRHUB<bit isSat> - : SInst <(outs IntRegs:$Rd), - (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"), - [], "", S_2op_tc_2_SLOT23>, - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rss; - bits<4> u4; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1000011; - let Inst{20-16} = Rss; - let Inst{13-12} = 0b00; - let Inst{11-8} = u4; - let Inst{7-6} = 0b10; - let Inst{5} = isSat; - let Inst{4-0} = Rd; - } - -def S5_asrhub_rnd_sat : T_ASRHUB <0>; -def S5_asrhub_sat : T_ASRHUB <1>; - -let isAsmParserOnly = 1 in -def S5_asrhub_rnd_sat_goodsyntax - : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>; - -// S5_vasrhrnd: Vector arithmetic shift right by immediate with round. -let hasSideEffects = 0 in -def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rdd = vasrh($Rss, #$u4):raw">, - Requires<[HasV5T]> { - bits<5> Rdd; - bits<5> Rss; - bits<4> u4; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0000001; - let Inst{20-16} = Rss; - let Inst{13-12} = 0b00; - let Inst{11-8} = u4; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rdd; - } - -let isAsmParserOnly = 1 in -def S5_vasrhrnd_goodsyntax - : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>; - -// Floating point reciprocal square root approximation -let Uses = [USR], isPredicateLate = 1, isFP = 1, - hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, - validSubTargets = HasV5SubT in -def F2_sfinvsqrta: SInst < - (outs IntRegs:$Rd, PredRegs:$Pe), - (ins IntRegs:$Rs), - "$Rd, $Pe = sfinvsqrta($Rs)" > , - Requires<[HasV5T]> { - bits<5> Rd; - bits<2> Pe; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1011111; - let Inst{20-16} = Rs; - let Inst{7} = 0b0; - let Inst{6-5} = Pe; - let Inst{4-0} = Rd; - } - -// Complex multiply 32x16 -let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in { - def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>; - def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>; -} - -// Classify floating-point value -let Uses = [USR], isFP = 1 in -def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>, Requires<[HasV5T]>; - -let Uses = [USR], isFP = 1 in -def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5_0Imm:$u5), - "$Pd = dfclass($Rss, #$u5)", - [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> { - bits<2> Pd; - bits<5> Rss; - bits<5> u5; - - let IClass = 0b1101; - let Inst{27-21} = 0b1100100; - let Inst{20-16} = Rss; - let Inst{12-10} = 0b000; - let Inst{9-5} = u5; - let Inst{4-3} = 0b10; - let Inst{1-0} = Pd; - } - -// Instructions to create floating point constant -class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg> - : ALU64Inst<(outs RC:$dst), (ins u10_0Imm:$src), - "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"), - [], "", ALU64_tc_2_SLOT23>, Requires<[HasV5T]> { - bits<5> dst; - bits<10> src; - - let IClass = 0b1101; - let Inst{27-24} = RegType; - let Inst{23} = 0b0; - let Inst{22} = isNeg; - let Inst{21} = src{9}; - let Inst{13-5} = src{8-0}; - let Inst{4-0} = dst; - } - -let hasNewValue = 1, opNewValue = 0 in { - def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>; - def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>; -} - -def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>; -def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>; diff --git a/lib/Target/Hexagon/HexagonInstrInfoV60.td b/lib/Target/Hexagon/HexagonInstrInfoV60.td deleted file mode 100644 index c50141b18ea..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfoV60.td +++ /dev/null @@ -1,2068 +0,0 @@ -//=- HexagonInstrInfoV60.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V60 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// -// Vector load -let Predicates = [HasV60T, UseHVX] in -let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in - class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VM_LD, - IType type = TypeCVI_VM_LD> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -// Vector store -let Predicates = [HasV60T, UseHVX] in -let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in -class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VM_ST, - IType type = TypeCVI_VM_ST> -: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -//===----------------------------------------------------------------------===// -// Vector loads with base + immediate offset -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, accessSize = Vector64Access in -class T_vload_ai<string asmStr> - : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2), - asmStr>; - -let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in -class T_vload_ai_128B<string asmStr> - : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2), - asmStr>; - -let isCVLoadable = 1, hasNewValue = 1 in { - def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">, - V6_vL32b_ai_enc; - def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">, - V6_vL32b_nt_ai_enc; - // 128B - def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">, - V6_vL32b_ai_128B_enc; - def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">, - V6_vL32b_nt_ai_128B_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU, hasNewValue = 1 in { - def V6_vL32Ub_ai : T_vload_ai <"$dst = vmemu($src1+#$src2)">, - V6_vL32Ub_ai_enc; - def V6_vL32Ub_ai_128B : T_vload_ai_128B <"$dst = vmemu($src1+#$src2)">, - V6_vL32Ub_ai_128B_enc; -} - -let Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD, isCVLoad = 1, - hasNewValue = 1 in { - def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">, - V6_vL32b_cur_ai_enc; - def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">, - V6_vL32b_nt_cur_ai_enc; - // 128B - def V6_vL32b_cur_ai_128B : T_vload_ai_128B - <"$dst.cur = vmem($src1+#$src2)">, - V6_vL32b_cur_ai_128B_enc; - def V6_vL32b_nt_cur_ai_128B : T_vload_ai_128B - <"$dst.cur = vmem($src1+#$src2):nt">, - V6_vL32b_nt_cur_ai_128B_enc; -} - - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD, hasNewValue = 1 in { - def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_tmp_ai_enc; - def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">, - V6_vL32b_nt_tmp_ai_enc; - // 128B - def V6_vL32b_tmp_ai_128B : T_vload_ai_128B - <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_tmp_ai_128B_enc; - def V6_vL32b_nt_tmp_ai_128B : T_vload_ai_128B - <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_nt_tmp_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - unconditional -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, accessSize = Vector64Access, isPredicable = 1 in -class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isNT> - : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_ai_64B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_ai_128B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_ai : T_vstore_ai_64B <"vmem", "vS32b_ai">, - V6_vS32b_ai_enc; - def V6_vS32b_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai">, - V6_vS32b_ai_128B_enc; -} - -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_ai : T_vstore_ai_64B <"vmem", "vS32b_ai", 1>, - V6_vS32b_nt_ai_enc; - def V6_vS32b_nt_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai", 1>, - V6_vS32b_nt_ai_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_ai : T_vstore_ai_64B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_ai_enc; - def V6_vS32Ub_ai_128B : T_vstore_ai_128B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_ai_128B_enc; -} -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - unconditional new -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1, - isPredicable = 1, Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST in -class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT> - : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - "vmem($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3.new">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_ai_64B <string baseOp, bit isNT = 0> - : T_vstore_new_ai <baseOp, s4_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_ai_128B <string baseOp, bit isNT = 0> - : T_vstore_new_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>; - -def V6_vS32b_new_ai : T_vstore_new_ai_64B <"vS32b_ai">, V6_vS32b_new_ai_enc; -def V6_vS32b_new_ai_128B : T_vstore_new_ai_128B <"vS32b_ai">, - V6_vS32b_new_ai_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_ai : T_vstore_new_ai_64B<"vS32b_ai", 1>, - V6_vS32b_nt_new_ai_enc; - def V6_vS32b_nt_new_ai_128B : T_vstore_new_ai_128B<"vS32b_ai", 1>, - V6_vS32b_nt_new_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - conditional -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isPredicated = 1 in -class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) " - #mnemonic#"($src2+#$src3)"#!if(isNT, ":nt", "")#" = $src4">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pred_ai_64B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pred_ai_128B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, - isPredNot, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai">, - V6_vS32b_pred_ai_enc; - def V6_vS32b_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1>, - V6_vS32b_npred_ai_enc; - // 128B - def V6_vS32b_pred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai">, - V6_vS32b_pred_ai_128B_enc; - def V6_vS32b_npred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai", 1>, - V6_vS32b_npred_ai_128B_enc; -} - - -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 0, 1>, - V6_vS32b_nt_pred_ai_enc; - def V6_vS32b_nt_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1, 1>, - V6_vS32b_nt_npred_ai_enc; - // 128B - def V6_vS32b_nt_pred_ai_128B : T_vstore_pred_ai_128B - <"vmem", "vS32b_ai", 0, 1>, - V6_vS32b_nt_pred_ai_128B_enc; - def V6_vS32b_nt_npred_ai_128B : T_vstore_pred_ai_128B - <"vmem", "vS32b_ai", 1, 1>, - V6_vS32b_nt_npred_ai_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_pred_ai_enc; - def V6_vS32Ub_npred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai", 1>, - V6_vS32Ub_npred_ai_enc; - // 128B - def V6_vS32Ub_pred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_pred_ai_128B_enc; - def V6_vS32Ub_npred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai", 1>, - V6_vS32Ub_npred_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset in -class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC, - bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs), - (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)" - #!if(isNT, ":nt", "")#" = $src4"> { - let isPredicatedFalse = isPredNot; -} - -let accessSize = Vector64Access in -class T_vstore_qpred_ai_64B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_ai <s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_qpred_ai_128B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_ai <s4_7Imm, VectorRegs128B, isPredNot, isNT>; - -def V6_vS32b_qpred_ai : T_vstore_qpred_ai_64B, V6_vS32b_qpred_ai_enc; -def V6_vS32b_nqpred_ai : T_vstore_qpred_ai_64B <1>, - V6_vS32b_nqpred_ai_enc; -def V6_vS32b_nt_qpred_ai : T_vstore_qpred_ai_64B <0, 1>, - V6_vS32b_nt_qpred_ai_enc; -def V6_vS32b_nt_nqpred_ai : T_vstore_qpred_ai_64B <1, 1>, - V6_vS32b_nt_nqpred_ai_enc; -// 128B -def V6_vS32b_qpred_ai_128B : T_vstore_qpred_ai_128B, V6_vS32b_qpred_ai_128B_enc; -def V6_vS32b_nqpred_ai_128B : T_vstore_qpred_ai_128B<1>, - V6_vS32b_nqpred_ai_128B_enc; -def V6_vS32b_nt_qpred_ai_128B : T_vstore_qpred_ai_128B<0, 1>, - V6_vS32b_nt_qpred_ai_128B_enc; -def V6_vS32b_nt_nqpred_ai_128B : T_vstore_qpred_ai_128B<1, 1>, - V6_vS32b_nt_nqpred_ai_128B_enc; - - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - conditional new -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3, - isNVStore = 1, Type = TypeCVI_VM_NEW_ST, Itinerary = CVI_VM_NEW_ST in -class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC, - bit isPredNot, bit isNT> - : V6_STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)" - #!if(isNT, ":nt", "")#" = $src4.new">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pred_ai_64B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_ai <baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pred_ai_128B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, - isPredNot, isNT>; - - -def V6_vS32b_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai">, - V6_vS32b_new_pred_ai_enc; -def V6_vS32b_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1>, - V6_vS32b_new_npred_ai_enc; -// 128B -def V6_vS32b_new_pred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai">, - V6_vS32b_new_pred_ai_128B_enc; -def V6_vS32b_new_npred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai", 1>, - V6_vS32b_new_npred_ai_128B_enc; -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 0, 1>, - V6_vS32b_nt_new_pred_ai_enc; - def V6_vS32b_nt_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1, 1>, - V6_vS32b_nt_new_npred_ai_enc; - // 128B - def V6_vS32b_nt_new_pred_ai_128B : T_vstore_new_pred_ai_128B - <"vS32b_ai", 0, 1>, - V6_vS32b_nt_new_pred_ai_128B_enc; - def V6_vS32b_nt_new_npred_ai_128B : T_vstore_new_pred_ai_128B - <"vS32b_ai", 1, 1>, - V6_vS32b_nt_new_npred_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector loads with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, hasNewValue = 1 in -class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC> - : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2), asmStr, [], - "$src1 = $_dst_">; - -let accessSize = Vector64Access in -class T_vload_pi_64B <string asmStr> - : T_vload_pi <asmStr, s3_6Imm, VectorRegs>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vload_pi_128B <string asmStr> - : T_vload_pi <asmStr, s3_7Imm, VectorRegs128B>; - -let isCVLoadable = 1 in { - def V6_vL32b_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2)">, - V6_vL32b_pi_enc; - def V6_vL32b_nt_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2):nt">, - V6_vL32b_nt_pi_enc; - // 128B - def V6_vL32b_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2)">, - V6_vL32b_pi_128B_enc; - def V6_vL32b_nt_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2):nt">, - V6_vL32b_nt_pi_128B_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in { - def V6_vL32Ub_pi : T_vload_pi_64B <"$dst = vmemu($src1++#$src2)">, - V6_vL32Ub_pi_enc; - // 128B - def V6_vL32Ub_pi_128B : T_vload_pi_128B <"$dst = vmemu($src1++#$src2)">, - V6_vL32Ub_pi_128B_enc; -} - -let isCVLoad = 1, Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD in { - def V6_vL32b_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2)">, - V6_vL32b_cur_pi_enc; - def V6_vL32b_nt_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2):nt">, - V6_vL32b_nt_cur_pi_enc; - // 128B - def V6_vL32b_cur_pi_128B : T_vload_pi_128B - <"$dst.cur = vmem($src1++#$src2)">, - V6_vL32b_cur_pi_128B_enc; - def V6_vL32b_nt_cur_pi_128B : T_vload_pi_128B - <"$dst.cur = vmem($src1++#$src2):nt">, - V6_vL32b_nt_cur_pi_128B_enc; -} - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in { - def V6_vL32b_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2)">, - V6_vL32b_tmp_pi_enc; - def V6_vL32b_nt_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2):nt">, - V6_vL32b_nt_tmp_pi_enc; - //128B - def V6_vL32b_tmp_pi_128B : T_vload_pi_128B - <"$dst.tmp = vmem($src1++#$src2)">, - V6_vL32b_tmp_pi_128B_enc; - def V6_vL32b_nt_tmp_pi_128B : T_vload_pi_128B - <"$dst.tmp = vmem($src1++#$src2):nt">, - V6_vL32b_nt_tmp_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, isPredicable = 1 in -class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3", [], - "$src1 = $_dst_">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pi_64B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pi_128B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pi : T_vstore_pi_64B <"vmem", "vS32b_pi">, V6_vS32b_pi_enc; - def V6_vS32b_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi">, - V6_vS32b_pi_128B_enc; -} - -let isNVStorable = 1 , isNonTemporal = 1 in { - def V6_vS32b_nt_pi : T_vstore_pi_64B <"vmem", "vS32b_pi", 1>, - V6_vS32b_nt_pi_enc; - def V6_vS32b_nt_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi", 1>, - V6_vS32b_nt_pi_128B_enc; -} - - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pi : T_vstore_pi_64B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pi_enc; - def V6_vS32Ub_pi_128B : T_vstore_pi_128B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment unconditional .new vector stores with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, isNVStore = 1 in -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1, - isPredicable = 1, opNewValue = 3, isNVStore = 1 in -class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - "vmem($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [], - "$src1 = $_dst_">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pi_64B <string baseOp, bit isNT = 0> - : T_vstore_new_pi <baseOp, s3_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pi_128B <string baseOp, bit isNT = 0> - : T_vstore_new_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>; - - -def V6_vS32b_new_pi : T_vstore_new_pi_64B <"vS32b_pi">, - V6_vS32b_new_pi_enc; -def V6_vS32b_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi">, - V6_vS32b_new_pi_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pi : T_vstore_new_pi_64B <"vS32b_pi", 1>, - V6_vS32b_nt_new_pi_enc; - def V6_vS32b_nt_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi", 1>, - V6_vS32b_nt_new_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment conditional vector stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicated = 1, addrMode = PostInc in -class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isPredNot, bit isNT> - : V6_STInst<(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pred_pi_64B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pred_pi_128B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, - isPredNot, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi">, - V6_vS32b_pred_pi_enc; - def V6_vS32b_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1>, - V6_vS32b_npred_pi_enc; - // 128B - def V6_vS32b_pred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi">, - V6_vS32b_pred_pi_128B_enc; - def V6_vS32b_npred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi", 1>, - V6_vS32b_npred_pi_128B_enc; -} -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 0, 1>, - V6_vS32b_nt_pred_pi_enc; - def V6_vS32b_nt_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1, 1>, - V6_vS32b_nt_npred_pi_enc; - // 128B - def V6_vS32b_nt_pred_pi_128B : T_vstore_pred_pi_128B - <"vmem", "vS32b_pi", 0, 1>, - V6_vS32b_nt_pred_pi_128B_enc; - def V6_vS32b_nt_npred_pi_128B : T_vstore_pred_pi_128B - <"vmem", "vS32b_pi", 1, 1>, - V6_vS32b_nt_npred_pi_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pred_pi_enc; - def V6_vS32Ub_npred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi", 1>, - V6_vS32Ub_npred_pi_enc; - // 128B - def V6_vS32Ub_pred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pred_pi_128B_enc; - def V6_vS32Ub_npred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi", 1>, - V6_vS32Ub_npred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with immediate offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -let addrMode = PostInc in -class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0, - bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">; - -let accessSize = Vector64Access in -class T_vstore_qpred_pi_64B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_pi <s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_qpred_pi_128B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_pi <s3_7Imm, VectorRegs128B, isPredNot, isNT>; - -def V6_vS32b_qpred_pi : T_vstore_qpred_pi_64B, V6_vS32b_qpred_pi_enc; -def V6_vS32b_nqpred_pi : T_vstore_qpred_pi_64B <1>, V6_vS32b_nqpred_pi_enc; -// 128B -def V6_vS32b_qpred_pi_128B : T_vstore_qpred_pi_128B, - V6_vS32b_qpred_pi_128B_enc; -def V6_vS32b_nqpred_pi_128B : T_vstore_qpred_pi_128B<1>, - V6_vS32b_nqpred_pi_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_qpred_pi : T_vstore_qpred_pi_64B <0, 1>, - V6_vS32b_nt_qpred_pi_enc; - def V6_vS32b_nt_nqpred_pi : T_vstore_qpred_pi_64B <1, 1>, - V6_vS32b_nt_nqpred_pi_enc; - // 128B - def V6_vS32b_nt_qpred_pi_128B : T_vstore_qpred_pi_128B<0, 1>, - V6_vS32b_nt_qpred_pi_128B_enc; - def V6_vS32b_nt_nqpred_pi_128B : T_vstore_qpred_pi_128B<1, 1>, - V6_vS32b_nt_nqpred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with immediate offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1, - isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in -class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC, - bit isPredNot, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4.new", [], - "$src2 = $_dst_"> , NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pred_pi_64B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_pi <baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pred_pi_128B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, - isPredNot, isNT>; - -def V6_vS32b_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi">, - V6_vS32b_new_pred_pi_enc; -def V6_vS32b_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1>, - V6_vS32b_new_npred_pi_enc; -// 128B -def V6_vS32b_new_pred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi">, - V6_vS32b_new_pred_pi_128B_enc; -def V6_vS32b_new_npred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi", 1>, - V6_vS32b_new_npred_pi_128B_enc; -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 0, 1>, - V6_vS32b_nt_new_pred_pi_enc; - def V6_vS32b_nt_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1, 1>, - V6_vS32b_nt_new_npred_pi_enc; - // 128B - def V6_vS32b_nt_new_pred_pi_128B : T_vstore_new_pred_pi_128B - <"vS32b_pi", 0, 1>, - V6_vS32b_nt_new_pred_pi_128B_enc; - def V6_vS32b_nt_new_npred_pi_128B : T_vstore_new_pred_pi_128B - <"vS32b_pi", 1, 1>, - V6_vS32b_nt_new_npred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector loads with register offset -//===----------------------------------------------------------------------===// -let hasNewValue = 1 in -class T_vload_ppu<string asmStr> - : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2), asmStr, [], - "$src1 = $_dst_">, NewValueRel; - -let isCVLoadable = 1 in { - def V6_vL32b_ppu : T_vload_ppu <"$dst = vmem($src1++$src2)">, - V6_vL32b_ppu_enc; - def V6_vL32b_nt_ppu : T_vload_ppu <"$dst = vmem($src1++$src2):nt">, - V6_vL32b_nt_ppu_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in -def V6_vL32Ub_ppu : T_vload_ppu <"$dst = vmemu($src1++$src2)">, - V6_vL32Ub_ppu_enc; - -let isCVLoad = 1, Itinerary = CVI_VM_CUR_LD, Type = TypeCVI_VM_CUR_LD in { - def V6_vL32b_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2)">, - V6_vL32b_cur_ppu_enc; - def V6_vL32b_nt_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2):nt">, - V6_vL32b_nt_cur_ppu_enc; -} - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in { - def V6_vL32b_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2)">, - V6_vL32b_tmp_ppu_enc; - def V6_vL32b_nt_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2):nt">, - V6_vL32b_nt_tmp_ppu_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with register offset -//===----------------------------------------------------------------------===// -let isPredicable = 1 in -class T_vstore_ppu <string mnemonic, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3), - mnemonic#"($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3", [], - "$src1 = $_dst_">, NewValueRel; - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_ppu : T_vstore_ppu <"vmem">, - V6_vS32b_ppu_enc; - let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in - def V6_vS32b_nt_ppu : T_vstore_ppu <"vmem", 1>, - V6_vS32b_nt_ppu_enc; -} - -let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in -def V6_vS32Ub_ppu : T_vstore_ppu <"vmemu">, V6_vS32Ub_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment .new vector stores with register offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1, - isPredicable = 1, opNewValue = 3, isNVStore = 1 in -class T_vstore_new_ppu <bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3), - "vmem($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [], - "$src1 = $_dst_">, NewValueRel; - -let BaseOpcode = "vS32b_ppu" in -def V6_vS32b_new_ppu : T_vstore_new_ppu, V6_vS32b_new_ppu_enc; - -let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in -def V6_vS32b_nt_new_ppu : T_vstore_new_ppu<1>, V6_vS32b_nt_new_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with register offset -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_vstore_pred_ppu <string mnemonic, bit isPredNot = 0, bit isNT = 0> - : V6_STInst<(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; -} - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_pred_ppu : T_vstore_pred_ppu<"vmem">, V6_vS32b_pred_ppu_enc; - def V6_vS32b_npred_ppu: T_vstore_pred_ppu<"vmem", 1>, V6_vS32b_npred_ppu_enc; -} - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in { - def V6_vS32b_nt_pred_ppu : T_vstore_pred_ppu <"vmem", 0, 1>, - V6_vS32b_nt_pred_ppu_enc; - def V6_vS32b_nt_npred_ppu : T_vstore_pred_ppu <"vmem", 1, 1>, - V6_vS32b_nt_npred_ppu_enc; -} - -let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, - Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_ppu : T_vstore_pred_ppu <"vmemu">, - V6_vS32Ub_pred_ppu_enc; - def V6_vS32Ub_npred_ppu : T_vstore_pred_ppu <"vmemu", 1>, - V6_vS32Ub_npred_ppu_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with register offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -class T_vstore_qpred_ppu <bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel; - -def V6_vS32b_qpred_ppu : T_vstore_qpred_ppu, V6_vS32b_qpred_ppu_enc; -def V6_vS32b_nqpred_ppu : T_vstore_qpred_ppu<1>, V6_vS32b_nqpred_ppu_enc; -def V6_vS32b_nt_qpred_ppu : T_vstore_qpred_ppu<0, 1>, - V6_vS32b_nt_qpred_ppu_enc; -def V6_vS32b_nt_nqpred_ppu : T_vstore_qpred_ppu<1, 1>, - V6_vS32b_nt_nqpred_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with register offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1, - isNewValue = 1, opNewValue = 4, isNVStore = 1 in -class T_vstore_new_pred_ppu <bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4.new", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; -} - -let BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_new_pred_ppu : T_vstore_new_pred_ppu, - V6_vS32b_new_pred_ppu_enc; - def V6_vS32b_new_npred_ppu : T_vstore_new_pred_ppu<1>, - V6_vS32b_new_npred_ppu_enc; -} - -let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in { -def V6_vS32b_nt_new_pred_ppu : T_vstore_new_pred_ppu<0, 1>, - V6_vS32b_nt_new_pred_ppu_enc; -def V6_vS32b_nt_new_npred_ppu : T_vstore_new_pred_ppu<1, 1>, - V6_vS32b_nt_new_npred_ppu_enc; -} - - -// Vector load/store pseudos - -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in -class STrivv_template<RegisterClass RC> - : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; - -def PS_vstorerw_ai: STrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerwu_ai: STrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; - - -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in -class LDrivv_template<RegisterClass RC> - : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; - -def PS_vloadrw_ai: LDrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; - -// Store vector predicate pseudo. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { - def PS_vstorerq_ai : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vstorerq_ai_128B : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXDbl]>; -} - -// Load vector predicate pseudo. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { - def PS_vloadrq_ai : LDInst<(outs VecPredRegs:$dst), - (ins IntRegs:$base, s32_0Imm:$offset), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vloadrq_ai_128B : LDInst<(outs VecPredRegs128B:$dst), - (ins IntRegs:$base, s32_0Imm:$offset), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXDbl]>; -} - -class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VA_DV, - IType type = TypeCVI_VA_DV> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { - def PS_vselect: VSELInst<(outs VectorRegs:$dst), - (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), - (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; - def PS_wselect: VSELInst<(outs VecDblRegs:$dst), - (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), - (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; -} - -let hasNewValue = 1 in -class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2), - asmString >; - -multiclass T_vmpy <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_vmpy <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_vmpy <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_vmpy_VV <string asmString>: - T_vmpy <asmString, VectorRegs, VectorRegs>; - -multiclass T_vmpy_WW <string asmString>: - T_vmpy <asmString, VecDblRegs, VecDblRegs>; - -multiclass T_vmpy_VW <string asmString>: - T_vmpy <asmString, VectorRegs, VecDblRegs>; - -multiclass T_vmpy_WV <string asmString>: - T_vmpy <asmString, VecDblRegs, VectorRegs>; - -defm V6_vtmpyb :T_vmpy_WW<"$dst.h = vtmpy($src1.b,$src2.b)">, V6_vtmpyb_enc; -defm V6_vtmpybus :T_vmpy_WW<"$dst.h = vtmpy($src1.ub,$src2.b)">, V6_vtmpybus_enc; -defm V6_vdsaduh :T_vmpy_WW<"$dst.uw = vdsad($src1.uh,$src2.uh)">, V6_vdsaduh_enc; -defm V6_vmpybus :T_vmpy_WV<"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybus_enc; -defm V6_vmpabus :T_vmpy_WW<"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabus_enc; -defm V6_vmpahb :T_vmpy_WW<"$dst.w = vmpa($src1.h,$src2.b)">, V6_vmpahb_enc; -defm V6_vmpyh :T_vmpy_WV<"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyh_enc; -defm V6_vmpyuh :T_vmpy_WV<"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuh_enc; -defm V6_vmpyiwh :T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_enc; -defm V6_vtmpyhb :T_vmpy_WW<"$dst.w = vtmpy($src1.h,$src2.b)">, V6_vtmpyhb_enc; -defm V6_vmpyub :T_vmpy_WV<"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyub_enc; - -let Itinerary = CVI_VX_LONG, Type = TypeCVI_VX in -defm V6_vmpyihb :T_vmpy_VV<"$dst.h = vmpyi($src1.h,$src2.b)">, V6_vmpyihb_enc; - -defm V6_vdmpybus_dv : - T_vmpy_WW <"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_dv_enc; -defm V6_vdmpyhsusat : - T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.uh):sat">, V6_vdmpyhsusat_enc; -defm V6_vdmpyhsuisat : - T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.uh,#1):sat">, V6_vdmpyhsuisat_enc; -defm V6_vdmpyhsat : - T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhsat_enc; -defm V6_vdmpyhisat : - T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhisat_enc; -defm V6_vdmpyhb_dv : - T_vmpy_WW <"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_dv_enc; -defm V6_vmpyhss : - T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:sat">, V6_vmpyhss_enc; -defm V6_vmpyhsrs : - T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhsrs_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in -defm V6_vror : T_vmpy_VV <"$dst = vror($src1,$src2)">, V6_vror_enc; - -let Itinerary = CVI_VX, Type = TypeCVI_VX in { -defm V6_vdmpyhb : T_vmpy_VV<"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_enc; -defm V6_vrmpybus : T_vmpy_VV<"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybus_enc; -defm V6_vdmpybus : T_vmpy_VV<"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_enc; -defm V6_vmpyiwb : T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.b)">, V6_vmpyiwb_enc; -defm V6_vrmpyub : T_vmpy_VV<"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyub_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vasrw : T_vmpy_VV <"$dst.w = vasr($src1.w,$src2)">, V6_vasrw_enc; -defm V6_vasrh : T_vmpy_VV <"$dst.h = vasr($src1.h,$src2)">, V6_vasrh_enc; -defm V6_vaslw : T_vmpy_VV <"$dst.w = vasl($src1.w,$src2)">, V6_vaslw_enc; -defm V6_vaslh : T_vmpy_VV <"$dst.h = vasl($src1.h,$src2)">, V6_vaslh_enc; -defm V6_vlsrw : T_vmpy_VV <"$dst.uw = vlsr($src1.uw,$src2)">, V6_vlsrw_enc; -defm V6_vlsrh : T_vmpy_VV <"$dst.uh = vlsr($src1.uh,$src2)">, V6_vlsrh_enc; -} - -let hasNewValue = 1 in -class T_HVX_alu <string asmString, InstrItinClass itin, - RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2), - asmString >{ - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_alu <string asmString, RegisterClass RCout, - RegisterClass RCin, InstrItinClass itin> { - def NAME : T_HVX_alu <asmString, itin, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_alu_VV <string asmString>: - T_HVX_alu <asmString, VectorRegs, VectorRegs, CVI_VA>; - -multiclass T_HVX_alu_WW <string asmString>: - T_HVX_alu <asmString, VecDblRegs, VecDblRegs, CVI_VA_DV>; - -multiclass T_HVX_alu_WV <string asmString>: - T_HVX_alu <asmString, VecDblRegs, VectorRegs, CVI_VX_DV>; - - -let Itinerary = CVI_VX, Type = TypeCVI_VX in { -defm V6_vrmpyubv : - T_HVX_alu_VV <"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyubv_enc; -defm V6_vrmpybv : - T_HVX_alu_VV <"$dst.w = vrmpy($src1.b,$src2.b)">, V6_vrmpybv_enc; -defm V6_vrmpybusv : - T_HVX_alu_VV <"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybusv_enc; -defm V6_vabsdiffub : - T_HVX_alu_VV <"$dst.ub = vabsdiff($src1.ub,$src2.ub)">, V6_vabsdiffub_enc; -defm V6_vabsdiffh : - T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.h,$src2.h)">, V6_vabsdiffh_enc; -defm V6_vabsdiffuh : - T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.uh,$src2.uh)">, V6_vabsdiffuh_enc; -defm V6_vabsdiffw : - T_HVX_alu_VV <"$dst.uw = vabsdiff($src1.w,$src2.w)">, V6_vabsdiffw_enc; -} - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vdmpyhvsat : - T_HVX_alu_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhvsat_enc; -defm V6_vmpyhvsrs : - T_HVX_alu_VV<"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhvsrs_enc; -defm V6_vmpyih : - T_HVX_alu_VV <"$dst.h = vmpyi($src1.h,$src2.h)">, V6_vmpyih_enc; -} - -defm V6_vand : - T_HVX_alu_VV <"$dst = vand($src1,$src2)">, V6_vand_enc; -defm V6_vor : - T_HVX_alu_VV <"$dst = vor($src1,$src2)">, V6_vor_enc; -defm V6_vxor : - T_HVX_alu_VV <"$dst = vxor($src1,$src2)">, V6_vxor_enc; -defm V6_vaddw : - T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_enc; -defm V6_vaddubsat : - T_HVX_alu_VV <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_enc; -defm V6_vadduhsat : - T_HVX_alu_VV <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_enc; -defm V6_vaddhsat : - T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_enc; -defm V6_vaddwsat : - T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_enc; -defm V6_vsubb : - T_HVX_alu_VV <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_enc; -defm V6_vsubh : - T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_enc; -defm V6_vsubw : - T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_enc; -defm V6_vsububsat : - T_HVX_alu_VV <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_enc; -defm V6_vsubuhsat : - T_HVX_alu_VV <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_enc; -defm V6_vsubhsat : - T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_enc; -defm V6_vsubwsat : - T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_enc; -defm V6_vavgub : - T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub)">, V6_vavgub_enc; -defm V6_vavguh : - T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh)">, V6_vavguh_enc; -defm V6_vavgh : - T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h)">, V6_vavgh_enc; -defm V6_vavgw : - T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w)">, V6_vavgw_enc; -defm V6_vnavgub : - T_HVX_alu_VV <"$dst.b = vnavg($src1.ub,$src2.ub)">, V6_vnavgub_enc; -defm V6_vnavgh : - T_HVX_alu_VV <"$dst.h = vnavg($src1.h,$src2.h)">, V6_vnavgh_enc; -defm V6_vnavgw : - T_HVX_alu_VV <"$dst.w = vnavg($src1.w,$src2.w)">, V6_vnavgw_enc; -defm V6_vavgubrnd : - T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub):rnd">, V6_vavgubrnd_enc; -defm V6_vavguhrnd : - T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh):rnd">, V6_vavguhrnd_enc; -defm V6_vavghrnd : - T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h):rnd">, V6_vavghrnd_enc; -defm V6_vavgwrnd : - T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w):rnd">, V6_vavgwrnd_enc; - -defm V6_vmpybv : - T_HVX_alu_WV <"$dst.h = vmpy($src1.b,$src2.b)">, V6_vmpybv_enc; -defm V6_vmpyubv : - T_HVX_alu_WV <"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyubv_enc; -defm V6_vmpybusv : - T_HVX_alu_WV <"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybusv_enc; -defm V6_vmpyhv : - T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyhv_enc; -defm V6_vmpyuhv : - T_HVX_alu_WV <"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuhv_enc; -defm V6_vmpyhus : - T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.uh)">, V6_vmpyhus_enc; -defm V6_vaddubh : - T_HVX_alu_WV <"$dst.h = vadd($src1.ub,$src2.ub)">, V6_vaddubh_enc; -defm V6_vadduhw : - T_HVX_alu_WV <"$dst.w = vadd($src1.uh,$src2.uh)">, V6_vadduhw_enc; -defm V6_vaddhw : - T_HVX_alu_WV <"$dst.w = vadd($src1.h,$src2.h)">, V6_vaddhw_enc; -defm V6_vsububh : - T_HVX_alu_WV <"$dst.h = vsub($src1.ub,$src2.ub)">, V6_vsububh_enc; -defm V6_vsubuhw : - T_HVX_alu_WV <"$dst.w = vsub($src1.uh,$src2.uh)">, V6_vsubuhw_enc; -defm V6_vsubhw : - T_HVX_alu_WV <"$dst.w = vsub($src1.h,$src2.h)">, V6_vsubhw_enc; - -defm V6_vaddb_dv : - T_HVX_alu_WW <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_dv_enc; -defm V6_vaddh_dv : - T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_dv_enc; -defm V6_vaddw_dv : - T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_dv_enc; -defm V6_vaddubsat_dv : - T_HVX_alu_WW <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_dv_enc; -defm V6_vadduhsat_dv : - T_HVX_alu_WW <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_dv_enc; -defm V6_vaddhsat_dv : - T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_dv_enc; -defm V6_vaddwsat_dv : - T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_dv_enc; -defm V6_vsubb_dv : - T_HVX_alu_WW <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_dv_enc; -defm V6_vsubh_dv : - T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_dv_enc; -defm V6_vsubw_dv : - T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_dv_enc; -defm V6_vsububsat_dv : - T_HVX_alu_WW <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_dv_enc; -defm V6_vsubuhsat_dv : - T_HVX_alu_WW <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_dv_enc; -defm V6_vsubhsat_dv : - T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_dv_enc; -defm V6_vsubwsat_dv : - T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_dv_enc; - -let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV in { -defm V6_vmpabusv : - T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabusv_enc; -defm V6_vmpabuuv : - T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.ub)">, V6_vmpabuuv_enc; -} - -let isAccumulator = 1, hasNewValue = 1 in -class T_HVX_vmpyacc <string asmString, InstrItinClass itin, RegisterClass RCout, - RegisterClass RCin1, RegisterClass RCin2> - : CVI_VA_Resource1 <(outs RCout:$dst), - (ins RCout:$_src_, RCin1:$src1, RCin2:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_vmpyacc_both <string asmString, RegisterClass RCout, - RegisterClass RCin1, RegisterClass RCin2, InstrItinClass itin > { - def NAME : T_HVX_vmpyacc <asmString, itin, RCout, RCin1, RCin2>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpyacc <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin1#"128B"), - !cast<RegisterClass>(RCin2# - !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>; -} - -multiclass T_HVX_vmpyacc_VVR <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>; - -multiclass T_HVX_vmpyacc_VWR <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WVR <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WWR <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_VVV <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, VectorRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WVV <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, VectorRegs, CVI_VX_DV>; - - -defm V6_vtmpyb_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.b,$src2.b)">, - V6_vtmpyb_acc_enc; -defm V6_vtmpybus_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.ub,$src2.b)">, - V6_vtmpybus_acc_enc; -defm V6_vtmpyhb_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vtmpy($src1.h,$src2.b)">, - V6_vtmpyhb_acc_enc; -defm V6_vdmpyhb_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.b)">, - V6_vdmpyhb_acc_enc; -defm V6_vrmpyub_acc : - T_HVX_vmpyacc_VVR <"$dst.uw += vrmpy($src1.ub,$src2.ub)">, - V6_vrmpyub_acc_enc; -defm V6_vrmpybus_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vrmpy($src1.ub,$src2.b)">, - V6_vrmpybus_acc_enc; -defm V6_vdmpybus_acc : - T_HVX_vmpyacc_VVR <"$dst.h += vdmpy($src1.ub,$src2.b)">, - V6_vdmpybus_acc_enc; -defm V6_vdmpybus_dv_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vdmpy($src1.ub,$src2.b)">, - V6_vdmpybus_dv_acc_enc; -defm V6_vdmpyhsuisat_acc : - T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.uh,#1):sat">, - V6_vdmpyhsuisat_acc_enc; -defm V6_vdmpyhisat_acc : - T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhisat_acc_enc; -defm V6_vdmpyhb_dv_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vdmpy($src1.h,$src2.b)">, - V6_vdmpyhb_dv_acc_enc; -defm V6_vmpybus_acc : - T_HVX_vmpyacc_WVR <"$dst.h += vmpy($src1.ub,$src2.b)">, - V6_vmpybus_acc_enc; -defm V6_vmpabus_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vmpa($src1.ub,$src2.b)">, - V6_vmpabus_acc_enc; -defm V6_vmpahb_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vmpa($src1.h,$src2.b)">, - V6_vmpahb_acc_enc; -defm V6_vmpyhsat_acc : - T_HVX_vmpyacc_WVR <"$dst.w += vmpy($src1.h,$src2.h):sat">, - V6_vmpyhsat_acc_enc; -defm V6_vmpyuh_acc : - T_HVX_vmpyacc_WVR <"$dst.uw += vmpy($src1.uh,$src2.uh)">, - V6_vmpyuh_acc_enc; -defm V6_vmpyiwb_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vmpyi($src1.w,$src2.b)">, - V6_vmpyiwb_acc_enc; -defm V6_vdsaduh_acc : - T_HVX_vmpyacc_WWR <"$dst.uw += vdsad($src1.uh,$src2.uh)">, - V6_vdsaduh_acc_enc; -defm V6_vmpyihb_acc : - T_HVX_vmpyacc_VVR <"$dst.h += vmpyi($src1.h,$src2.b)">, - V6_vmpyihb_acc_enc; -defm V6_vmpyub_acc : - T_HVX_vmpyacc_WVR <"$dst.uh += vmpy($src1.ub,$src2.ub)">, - V6_vmpyub_acc_enc; - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vdmpyhsusat_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.uh):sat">, - V6_vdmpyhsusat_acc_enc; -defm V6_vdmpyhsat_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhsat_acc_enc; -defm V6_vmpyiwh_acc : T_HVX_vmpyacc_VVR - <"$dst.w += vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_acc_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vaslw_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vasl($src1.w,$src2)">, V6_vaslw_acc_enc; -defm V6_vasrw_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vasr($src1.w,$src2)">, V6_vasrw_acc_enc; -} - -defm V6_vdmpyhvsat_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhvsat_acc_enc; -defm V6_vmpybusv_acc : - T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.ub,$src2.b)">, - V6_vmpybusv_acc_enc; -defm V6_vmpybv_acc : - T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.b,$src2.b)">, V6_vmpybv_acc_enc; -defm V6_vmpyhus_acc : - T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.uh)">, V6_vmpyhus_acc_enc; -defm V6_vmpyhv_acc : - T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.h)">, V6_vmpyhv_acc_enc; -defm V6_vmpyiewh_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.h)">, - V6_vmpyiewh_acc_enc; -defm V6_vmpyiewuh_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.uh)">, - V6_vmpyiewuh_acc_enc; -defm V6_vmpyih_acc : - T_HVX_vmpyacc_VVV <"$dst.h += vmpyi($src1.h,$src2.h)">, V6_vmpyih_acc_enc; -defm V6_vmpyowh_rnd_sacc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:rnd:sat:shift">, - V6_vmpyowh_rnd_sacc_enc; -defm V6_vmpyowh_sacc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:sat:shift">, - V6_vmpyowh_sacc_enc; -defm V6_vmpyubv_acc : - T_HVX_vmpyacc_WVV <"$dst.uh += vmpy($src1.ub,$src2.ub)">, - V6_vmpyubv_acc_enc; -defm V6_vmpyuhv_acc : - T_HVX_vmpyacc_WVV <"$dst.uw += vmpy($src1.uh,$src2.uh)">, - V6_vmpyuhv_acc_enc; -defm V6_vrmpybusv_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.ub,$src2.b)">, - V6_vrmpybusv_acc_enc; -defm V6_vrmpybv_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.b,$src2.b)">, V6_vrmpybv_acc_enc; -defm V6_vrmpyubv_acc : - T_HVX_vmpyacc_VVV <"$dst.uw += vrmpy($src1.ub,$src2.ub)">, - V6_vrmpyubv_acc_enc; - - -class T_HVX_vcmp <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, RCin:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = CVI_VA; - let Type = TypeCVI_VA; -} - -multiclass T_HVX_vcmp <string asmString> { - def NAME : T_HVX_vcmp <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vcmp <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_veqb_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc; -defm V6_veqh_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc; -defm V6_veqw_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc; -defm V6_vgtb_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc; -defm V6_vgth_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc; -defm V6_vgtw_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc; -defm V6_vgtub_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc; -defm V6_vgtuh_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc; -defm V6_vgtuw_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc; -defm V6_veqb_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc; -defm V6_veqh_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.h,$src2.h)">, V6_veqh_or_enc; -defm V6_veqw_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.w,$src2.w)">, V6_veqw_or_enc; -defm V6_vgtb_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_or_enc; -defm V6_vgth_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.h,$src2.h)">, V6_vgth_or_enc; -defm V6_vgtw_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_or_enc; -defm V6_vgtub_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_or_enc; -defm V6_vgtuh_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_or_enc; -defm V6_vgtuw_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_or_enc; -defm V6_veqb_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.b,$src2.b)">, V6_veqb_xor_enc; -defm V6_veqh_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.h,$src2.h)">, V6_veqh_xor_enc; -defm V6_veqw_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.w,$src2.w)">, V6_veqw_xor_enc; -defm V6_vgtb_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_xor_enc; -defm V6_vgth_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.h,$src2.h)">, V6_vgth_xor_enc; -defm V6_vgtw_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_xor_enc; -defm V6_vgtub_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_xor_enc; -defm V6_vgtuh_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_xor_enc; -defm V6_vgtuw_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_xor_enc; - -defm V6_vminub : - T_HVX_alu_VV <"$dst.ub = vmin($src1.ub,$src2.ub)">, V6_vminub_enc; -defm V6_vminuh : - T_HVX_alu_VV <"$dst.uh = vmin($src1.uh,$src2.uh)">, V6_vminuh_enc; -defm V6_vminh : - T_HVX_alu_VV <"$dst.h = vmin($src1.h,$src2.h)">, V6_vminh_enc; -defm V6_vminw : - T_HVX_alu_VV <"$dst.w = vmin($src1.w,$src2.w)">, V6_vminw_enc; -defm V6_vmaxub : - T_HVX_alu_VV <"$dst.ub = vmax($src1.ub,$src2.ub)">, V6_vmaxub_enc; -defm V6_vmaxuh : - T_HVX_alu_VV <"$dst.uh = vmax($src1.uh,$src2.uh)">, V6_vmaxuh_enc; -defm V6_vmaxh : - T_HVX_alu_VV <"$dst.h = vmax($src1.h,$src2.h)">, V6_vmaxh_enc; -defm V6_vmaxw : - T_HVX_alu_VV <"$dst.w = vmax($src1.w,$src2.w)">, V6_vmaxw_enc; -defm V6_vshuffeb : - T_HVX_alu_VV <"$dst.b = vshuffe($src1.b,$src2.b)">, V6_vshuffeb_enc; -defm V6_vshuffob : - T_HVX_alu_VV <"$dst.b = vshuffo($src1.b,$src2.b)">, V6_vshuffob_enc; -defm V6_vshufeh : - T_HVX_alu_VV <"$dst.h = vshuffe($src1.h,$src2.h)">, V6_vshufeh_enc; -defm V6_vshufoh : - T_HVX_alu_VV <"$dst.h = vshuffo($src1.h,$src2.h)">, V6_vshufoh_enc; - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vmpyowh_rnd : - T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:rnd:sat">, - V6_vmpyowh_rnd_enc; -defm V6_vmpyiewuh : - T_HVX_alu_VV <"$dst.w = vmpyie($src1.w,$src2.uh)">, V6_vmpyiewuh_enc; -defm V6_vmpyewuh : - T_HVX_alu_VV <"$dst.w = vmpye($src1.w,$src2.uh)">, V6_vmpyewuh_enc; -defm V6_vmpyowh : - T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:sat">, V6_vmpyowh_enc; -defm V6_vmpyiowh : - T_HVX_alu_VV <"$dst.w = vmpyio($src1.w,$src2.h)">, V6_vmpyiowh_enc; -} -let Itinerary = CVI_VX, Type = TypeCVI_VX in -defm V6_vmpyieoh : - T_HVX_alu_VV <"$dst.w = vmpyieo($src1.h,$src2.h)">, V6_vmpyieoh_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in { -defm V6_vshufoeh : - T_HVX_alu_WV <"$dst.h = vshuffoe($src1.h,$src2.h)">, V6_vshufoeh_enc; -defm V6_vshufoeb : - T_HVX_alu_WV <"$dst.b = vshuffoe($src1.b,$src2.b)">, V6_vshufoeb_enc; -} - -let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in -defm V6_vcombine : - T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc; - -let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in { -defm V6_vsathub : - T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc; -defm V6_vsatwh : - T_HVX_alu_VV <"$dst.h = vsat($src1.w,$src2.w)">, V6_vsatwh_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vroundwh : - T_HVX_alu_VV <"$dst.h = vround($src1.w,$src2.w):sat">, V6_vroundwh_enc; -defm V6_vroundwuh : - T_HVX_alu_VV <"$dst.uh = vround($src1.w,$src2.w):sat">, V6_vroundwuh_enc; -defm V6_vroundhb : - T_HVX_alu_VV <"$dst.b = vround($src1.h,$src2.h):sat">, V6_vroundhb_enc; -defm V6_vroundhub : - T_HVX_alu_VV <"$dst.ub = vround($src1.h,$src2.h):sat">, V6_vroundhub_enc; -defm V6_vasrwv : - T_HVX_alu_VV <"$dst.w = vasr($src1.w,$src2.w)">, V6_vasrwv_enc; -defm V6_vlsrwv : - T_HVX_alu_VV <"$dst.w = vlsr($src1.w,$src2.w)">, V6_vlsrwv_enc; -defm V6_vlsrhv : - T_HVX_alu_VV <"$dst.h = vlsr($src1.h,$src2.h)">, V6_vlsrhv_enc; -defm V6_vasrhv : - T_HVX_alu_VV <"$dst.h = vasr($src1.h,$src2.h)">, V6_vasrhv_enc; -defm V6_vaslwv : - T_HVX_alu_VV <"$dst.w = vasl($src1.w,$src2.w)">, V6_vaslwv_enc; -defm V6_vaslhv : - T_HVX_alu_VV <"$dst.h = vasl($src1.h,$src2.h)">, V6_vaslhv_enc; -} - -defm V6_vaddb : - T_HVX_alu_VV <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_enc; -defm V6_vaddh : - T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in { -defm V6_vdelta : - T_HVX_alu_VV <"$dst = vdelta($src1,$src2)">, V6_vdelta_enc; -defm V6_vrdelta : - T_HVX_alu_VV <"$dst = vrdelta($src1,$src2)">, V6_vrdelta_enc; -defm V6_vdealb4w : - T_HVX_alu_VV <"$dst.b = vdeale($src1.b,$src2.b)">, V6_vdealb4w_enc; -defm V6_vpackeb : - T_HVX_alu_VV <"$dst.b = vpacke($src1.h,$src2.h)">, V6_vpackeb_enc; -defm V6_vpackeh : - T_HVX_alu_VV <"$dst.h = vpacke($src1.w,$src2.w)">, V6_vpackeh_enc; -defm V6_vpackhub_sat : - T_HVX_alu_VV <"$dst.ub = vpack($src1.h,$src2.h):sat">, V6_vpackhub_sat_enc; -defm V6_vpackhb_sat : - T_HVX_alu_VV <"$dst.b = vpack($src1.h,$src2.h):sat">, V6_vpackhb_sat_enc; -defm V6_vpackwuh_sat : - T_HVX_alu_VV <"$dst.uh = vpack($src1.w,$src2.w):sat">, V6_vpackwuh_sat_enc; -defm V6_vpackwh_sat : - T_HVX_alu_VV <"$dst.h = vpack($src1.w,$src2.w):sat">, V6_vpackwh_sat_enc; -defm V6_vpackob : - T_HVX_alu_VV <"$dst.b = vpacko($src1.h,$src2.h)">, V6_vpackob_enc; -defm V6_vpackoh : - T_HVX_alu_VV <"$dst.h = vpacko($src1.w,$src2.w)">, V6_vpackoh_enc; -} - -let hasNewValue = 1, hasSideEffects = 0 in -class T_HVX_condALU <string asmString, RegisterClass RC1, RegisterClass RC2> - : CVI_VA_Resource1 <(outs RC2:$dst), - (ins RC1:$src1, RC2:$_src_, RC2:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = CVI_VA; - let Type = TypeCVI_VA; -} - -multiclass T_HVX_condALU <string asmString> { - def NAME : T_HVX_condALU <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_condALU <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_vaddbq : T_HVX_condALU <"if ($src1) $dst.b += $src2.b">, - V6_vaddbq_enc; -defm V6_vaddhq : T_HVX_condALU <"if ($src1) $dst.h += $src2.h">, - V6_vaddhq_enc; -defm V6_vaddwq : T_HVX_condALU <"if ($src1) $dst.w += $src2.w">, - V6_vaddwq_enc; -defm V6_vsubbq : T_HVX_condALU <"if ($src1) $dst.b -= $src2.b">, - V6_vsubbq_enc; -defm V6_vsubhq : T_HVX_condALU <"if ($src1) $dst.h -= $src2.h">, - V6_vsubhq_enc; -defm V6_vsubwq : T_HVX_condALU <"if ($src1) $dst.w -= $src2.w">, - V6_vsubwq_enc; -defm V6_vaddbnq : T_HVX_condALU <"if (!$src1) $dst.b += $src2.b">, - V6_vaddbnq_enc; -defm V6_vaddhnq : T_HVX_condALU <"if (!$src1) $dst.h += $src2.h">, - V6_vaddhnq_enc; -defm V6_vaddwnq : T_HVX_condALU <"if (!$src1) $dst.w += $src2.w">, - V6_vaddwnq_enc; -defm V6_vsubbnq : T_HVX_condALU <"if (!$src1) $dst.b -= $src2.b">, - V6_vsubbnq_enc; -defm V6_vsubhnq : T_HVX_condALU <"if (!$src1) $dst.h -= $src2.h">, - V6_vsubhnq_enc; -defm V6_vsubwnq : T_HVX_condALU <"if (!$src1) $dst.w -= $src2.w">, - V6_vsubwnq_enc; - -let hasNewValue = 1 in -class T_HVX_alu_2op <string asmString, InstrItinClass itin, - RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1), - asmString >{ - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_alu_2op <string asmString, RegisterClass RCout, - RegisterClass RCin, InstrItinClass itin> { - def NAME : T_HVX_alu_2op <asmString, itin, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu_2op <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -let hasNewValue = 1 in -multiclass T_HVX_alu_2op_VV <string asmString>: - T_HVX_alu_2op <asmString, VectorRegs, VectorRegs, CVI_VA>; - -multiclass T_HVX_alu_2op_WV <string asmString>: - T_HVX_alu_2op <asmString, VecDblRegs, VectorRegs, CVI_VA_DV>; - - -defm V6_vabsh : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h)">, - V6_vabsh_enc; -defm V6_vabsw : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w)">, - V6_vabsw_enc; -defm V6_vabsh_sat : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h):sat">, - V6_vabsh_sat_enc; -defm V6_vabsw_sat : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w):sat">, - V6_vabsw_sat_enc; -defm V6_vnot : T_HVX_alu_2op_VV <"$dst = vnot($src1)">, - V6_vnot_enc; -defm V6_vassign : T_HVX_alu_2op_VV <"$dst = $src1">, - V6_vassign_enc; - -defm V6_vzb : T_HVX_alu_2op_WV <"$dst.uh = vzxt($src1.ub)">, - V6_vzb_enc; -defm V6_vzh : T_HVX_alu_2op_WV <"$dst.uw = vzxt($src1.uh)">, - V6_vzh_enc; -defm V6_vsb : T_HVX_alu_2op_WV <"$dst.h = vsxt($src1.b)">, - V6_vsb_enc; -defm V6_vsh : T_HVX_alu_2op_WV <"$dst.w = vsxt($src1.h)">, - V6_vsh_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in { -defm V6_vdealh : T_HVX_alu_2op_VV <"$dst.h = vdeal($src1.h)">, - V6_vdealh_enc; -defm V6_vdealb : T_HVX_alu_2op_VV <"$dst.b = vdeal($src1.b)">, - V6_vdealb_enc; -defm V6_vshuffh : T_HVX_alu_2op_VV <"$dst.h = vshuff($src1.h)">, - V6_vshuffh_enc; -defm V6_vshuffb : T_HVX_alu_2op_VV <"$dst.b = vshuff($src1.b)">, - V6_vshuffb_enc; -} - -let Itinerary = CVI_VP_VS, Type = TypeCVI_VP_VS in { -defm V6_vunpackub : T_HVX_alu_2op_WV <"$dst.uh = vunpack($src1.ub)">, - V6_vunpackub_enc; -defm V6_vunpackuh : T_HVX_alu_2op_WV <"$dst.uw = vunpack($src1.uh)">, - V6_vunpackuh_enc; -defm V6_vunpackb : T_HVX_alu_2op_WV <"$dst.h = vunpack($src1.b)">, - V6_vunpackb_enc; -defm V6_vunpackh : T_HVX_alu_2op_WV <"$dst.w = vunpack($src1.h)">, - V6_vunpackh_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vcl0w : T_HVX_alu_2op_VV <"$dst.uw = vcl0($src1.uw)">, - V6_vcl0w_enc; -defm V6_vcl0h : T_HVX_alu_2op_VV <"$dst.uh = vcl0($src1.uh)">, - V6_vcl0h_enc; -defm V6_vnormamtw : T_HVX_alu_2op_VV <"$dst.w = vnormamt($src1.w)">, - V6_vnormamtw_enc; -defm V6_vnormamth : T_HVX_alu_2op_VV <"$dst.h = vnormamt($src1.h)">, - V6_vnormamth_enc; -defm V6_vpopcounth : T_HVX_alu_2op_VV <"$dst.h = vpopcount($src1.h)">, - V6_vpopcounth_enc; -} - -let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG, - Type = TypeCVI_VX_DV in -class T_HVX_vmpyacc2 <string asmString, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$dst), - (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1_0Imm:$src3), - asmString, [], "$dst = $_src_" > ; - - -multiclass T_HVX_vmpyacc2 <string asmString> { - def NAME : T_HVX_vmpyacc2 <asmString, VecDblRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpyacc2 <asmString, VecDblRegs128B>; -} - -defm V6_vrmpybusi_acc : - T_HVX_vmpyacc2<"$dst.w += vrmpy($src1.ub,$src2.b,#$src3)">, - V6_vrmpybusi_acc_enc; -defm V6_vrsadubi_acc : - T_HVX_vmpyacc2<"$dst.uw += vrsad($src1.ub,$src2.ub,#$src3)">, - V6_vrsadubi_acc_enc; -defm V6_vrmpyubi_acc : - T_HVX_vmpyacc2<"$dst.uw += vrmpy($src1.ub,$src2.ub,#$src3)">, - V6_vrmpyubi_acc_enc; - - -let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in -class T_HVX_vmpy2 <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1_0Imm:$src3), - asmString>; - - -multiclass T_HVX_vmpy2 <string asmString> { - def NAME : T_HVX_vmpy2 <asmString, VecDblRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpy2 <asmString, VecDblRegs128B>; -} - -defm V6_vrmpybusi : - T_HVX_vmpy2 <"$dst.w = vrmpy($src1.ub,$src2.b,#$src3)">, V6_vrmpybusi_enc; -defm V6_vrsadubi : - T_HVX_vmpy2 <"$dst.uw = vrsad($src1.ub,$src2.ub,#$src3)">, V6_vrsadubi_enc; -defm V6_vrmpyubi : - T_HVX_vmpy2 <"$dst.uw = vrmpy($src1.ub,$src2.ub,#$src3)">, V6_vrmpyubi_enc; - - -let Itinerary = CVI_VP_VS_LONG_EARLY, Type = TypeCVI_VP_VS, - hasSideEffects = 0, hasNewValue2 = 1, opNewValue2 = 1 in -class T_HVX_perm <string asmString, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$_dst1_, RC:$_dst2_), - (ins RC:$src1, RC:$src2, IntRegs:$src3), - asmString, [], "$_dst1_ = $src1, $_dst2_ = $src2" >; - -multiclass T_HVX_perm <string asmString> { - def NAME : T_HVX_perm <asmString, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_perm <asmString, VectorRegs128B>; -} - -let hasNewValue = 1, opNewValue = 0, hasNewValue2 = 1, opNewValue2 = 1 in { - defm V6_vshuff : T_HVX_perm <"vshuff($src1,$src2,$src3)">, V6_vshuff_enc; - defm V6_vdeal : T_HVX_perm <"vdeal($src1,$src2,$src3)">, V6_vdeal_enc; -} - -// Conditional vector move. -let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_HVX_cmov <bit isPredNot, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$dst), (ins PredRegs:$src1, RC:$src2), - "if ("#!if(isPredNot, "!", "")#"$src1) $dst = $src2"> { - let isPredicatedFalse = isPredNot; -} - -multiclass T_HVX_cmov <bit isPredNot = 0> { - def NAME : T_HVX_cmov <isPredNot, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_cmov <isPredNot, VectorRegs128B>; -} - -defm V6_vcmov : T_HVX_cmov, V6_vcmov_enc; -defm V6_vncmov : T_HVX_cmov<1>, V6_vncmov_enc; - -// Conditional vector combine. -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, isPredicated = 1, - hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_HVX_ccombine <bit isPredNot, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 < (outs RCout:$dst), - (ins PredRegs:$src1, RCin:$src2, RCin:$src3), - "if ("#!if(isPredNot, "!", "")#"$src1) $dst = vcombine($src2,$src3)"> { - let isPredicatedFalse = isPredNot; -} - -multiclass T_HVX_ccombine <bit isPredNot = 0> { - def NAME : T_HVX_ccombine <isPredNot, VecDblRegs, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_ccombine <isPredNot, VecDblRegs128B, VectorRegs128B>; -} - -defm V6_vccombine : T_HVX_ccombine, V6_vccombine_enc; -defm V6_vnccombine : T_HVX_ccombine<1>, V6_vnccombine_enc; - -let hasNewValue = 1 in -class T_HVX_shift <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), - (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), - asmString >; - -multiclass T_HVX_shift <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_shift <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_shift <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_shift_VV <string asmString>: - T_HVX_shift <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_shift_WV <string asmString>: - T_HVX_shift <asmString, VecDblRegs, VectorRegs>; - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in { -defm V6_valignb : - T_HVX_shift_VV <"$dst = valign($src1,$src2,$src3)">, V6_valignb_enc; -defm V6_vlalignb : - T_HVX_shift_VV <"$dst = vlalign($src1,$src2,$src3)">, V6_vlalignb_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vasrwh : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3)">, V6_vasrwh_enc; -defm V6_vasrwhsat : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):sat">, - V6_vasrwhsat_enc; -defm V6_vasrwhrndsat : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):rnd:sat">, - V6_vasrwhrndsat_enc; -defm V6_vasrwuhsat : - T_HVX_shift_VV <"$dst.uh = vasr($src1.w,$src2.w,$src3):sat">, - V6_vasrwuhsat_enc; -defm V6_vasrhubsat : - T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):sat">, - V6_vasrhubsat_enc; -defm V6_vasrhubrndsat : - T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):rnd:sat">, - V6_vasrhubrndsat_enc; -defm V6_vasrhbrndsat : - T_HVX_shift_VV <"$dst.b = vasr($src1.h,$src2.h,$src3):rnd:sat">, - V6_vasrhbrndsat_enc; -} - -// Assembler mapped -- alias? -//defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc; -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in { -defm V6_vshuffvdd : - T_HVX_shift_WV <"$dst = vshuff($src1,$src2,$src3)">, V6_vshuffvdd_enc; -defm V6_vdealvdd : - T_HVX_shift_WV <"$dst = vdeal($src1,$src2,$src3)">, V6_vdealvdd_enc; -} - -let hasNewValue = 1, Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in -class T_HVX_unpack <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCout:$_src_, RCin:$src1), - asmString, [], "$dst = $_src_">; - -multiclass T_HVX_unpack <string asmString> { - def NAME : T_HVX_unpack <asmString, VecDblRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_unpack <asmString, VecDblRegs128B, VectorRegs128B>; -} - -defm V6_vunpackob : T_HVX_unpack <"$dst.h |= vunpacko($src1.b)">, V6_vunpackob_enc; -defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_enc; - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1, - hasSideEffects = 0 in -class T_HVX_valign <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3_0Imm:$src3), - asmString>; - -multiclass T_HVX_valign <string asmString> { - def NAME : T_HVX_valign <asmString, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_valign <asmString, VectorRegs128B>; -} - -defm V6_valignbi : - T_HVX_valign <"$dst = valign($src1,$src2,#$src3)">, V6_valignbi_enc; -defm V6_vlalignbi : - T_HVX_valign <"$dst = vlalign($src1,$src2,#$src3)">, V6_vlalignbi_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in -class T_HVX_predAlu <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2), - asmString>; - -multiclass T_HVX_predAlu <string asmString> { - def NAME : T_HVX_predAlu <asmString, VecPredRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_predAlu <asmString, VecPredRegs128B>; -} - -defm V6_pred_and : T_HVX_predAlu <"$dst = and($src1,$src2)">, V6_pred_and_enc; -defm V6_pred_or : T_HVX_predAlu <"$dst = or($src1,$src2)">, V6_pred_or_enc; -defm V6_pred_xor : T_HVX_predAlu <"$dst = xor($src1,$src2)">, V6_pred_xor_enc; -defm V6_pred_or_n : T_HVX_predAlu <"$dst = or($src1,!$src2)">, V6_pred_or_n_enc; -defm V6_pred_and_n : - T_HVX_predAlu <"$dst = and($src1,!$src2)">, V6_pred_and_n_enc; - -let Itinerary = CVI_VA, Type = TypeCVI_VA in -class T_HVX_prednot <RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1), - "$dst = not($src1)">, V6_pred_not_enc; - -def V6_pred_not : T_HVX_prednot <VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_pred_not_128B : T_HVX_prednot <VecPredRegs128B>; - -let Itinerary = CVI_VA, Type = TypeCVI_VA in -class T_HVX_vcmp2 <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2), - asmString >; - -multiclass T_HVX_vcmp2 <string asmString> { - def NAME : T_HVX_vcmp2 <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vcmp2 <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_veqb : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.b,$src2.b)">, V6_veqb_enc; -defm V6_veqh : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.h,$src2.h)">, V6_veqh_enc; -defm V6_veqw : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.w,$src2.w)">, V6_veqw_enc; -defm V6_vgtb : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.b,$src2.b)">, V6_vgtb_enc; -defm V6_vgth : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.h,$src2.h)">, V6_vgth_enc; -defm V6_vgtw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.w,$src2.w)">, V6_vgtw_enc; -defm V6_vgtub : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_enc; -defm V6_vgtuh : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_enc; -defm V6_vgtuw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_enc; - -let isAccumulator = 1, hasNewValue = 1, hasSideEffects = 0 in -class T_V6_vandqrt_acc <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, IntRegs:$src2), - "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandqrt_acc_enc; - -def V6_vandqrt_acc : T_V6_vandqrt_acc <VectorRegs, VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_vandqrt_acc_128B : T_V6_vandqrt_acc <VectorRegs128B, VecPredRegs128B>; - -let isAccumulator = 1 in -class T_V6_vandvrt_acc <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, IntRegs:$src2), - "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandvrt_acc_enc; - -def V6_vandvrt_acc : T_V6_vandvrt_acc <VecPredRegs, VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vandvrt_acc_128B : T_V6_vandvrt_acc <VecPredRegs128B, VectorRegs128B>; - -let hasNewValue = 1, hasSideEffects = 0 in -class T_V6_vandqrt <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCin:$src1, IntRegs:$src2), - "$dst = vand($src1,$src2)" >, V6_vandqrt_enc; - -def V6_vandqrt : T_V6_vandqrt <VectorRegs, VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_vandqrt_128B : T_V6_vandqrt <VectorRegs128B, VecPredRegs128B>; - -let hasNewValue = 1, hasSideEffects = 0 in -class T_V6_lvsplatw <RegisterClass RC> - : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1), - "$dst = vsplat($src1)" >, V6_lvsplatw_enc; - -def V6_lvsplatw : T_V6_lvsplatw <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_lvsplatw_128B : T_V6_lvsplatw <VectorRegs128B>; - - -let hasNewValue = 1 in -class T_V6_vinsertwr <RegisterClass RC> - : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1), - "$dst.w = vinsert($src1)", [], "$dst = $_src_">, - V6_vinsertwr_enc; - -def V6_vinsertwr : T_V6_vinsertwr <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vinsertwr_128B : T_V6_vinsertwr <VectorRegs128B>; - - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in -class T_V6_pred_scalar2 <RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1), - "$dst = vsetq($src1)">, V6_pred_scalar2_enc; - -def V6_pred_scalar2 : T_V6_pred_scalar2 <VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_pred_scalar2_128B : T_V6_pred_scalar2 <VecPredRegs128B>; - -class T_V6_vandvrt <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2), - "$dst = vand($src1,$src2)">, V6_vandvrt_enc; - -def V6_vandvrt : T_V6_vandvrt <VecPredRegs, VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vandvrt_128B : T_V6_vandvrt <VecPredRegs128B, VectorRegs128B>; - -let validSubTargets = HasV60SubT in -class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp > - : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>; - -class T_HVX_rol_R <string asmString> - : T_HVX_rol <asmString, IntRegs, u5_0Imm>; -class T_HVX_rol_P <string asmString> - : T_HVX_rol <asmString, DoubleRegs, u6_0Imm>; - -def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc; -let hasNewValue = 1, opNewValue = 0 in -def S6_rol_i_r : T_HVX_rol_R <"$dst = rol($src1,#$src2)">, S6_rol_i_r_enc; - -let validSubTargets = HasV60SubT in -class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp> - : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2), - asmString, [], "$dst = $_src_" >; - -class T_HVX_rol_acc_P <string asmString> - : T_HVX_rol_acc <asmString, DoubleRegs, u6_0Imm>; - -class T_HVX_rol_acc_R <string asmString> - : T_HVX_rol_acc <asmString, IntRegs, u5_0Imm>; - -def S6_rol_i_p_nac : - T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc; -def S6_rol_i_p_acc : - T_HVX_rol_acc_P <"$dst += rol($src1,#$src2)">, S6_rol_i_p_acc_enc; -def S6_rol_i_p_and : - T_HVX_rol_acc_P <"$dst &= rol($src1,#$src2)">, S6_rol_i_p_and_enc; -def S6_rol_i_p_or : - T_HVX_rol_acc_P <"$dst |= rol($src1,#$src2)">, S6_rol_i_p_or_enc; -def S6_rol_i_p_xacc : - T_HVX_rol_acc_P<"$dst ^= rol($src1,#$src2)">, S6_rol_i_p_xacc_enc; - -let hasNewValue = 1, opNewValue = 0 in { -def S6_rol_i_r_nac : - T_HVX_rol_acc_R <"$dst -= rol($src1,#$src2)">, S6_rol_i_r_nac_enc; -def S6_rol_i_r_acc : - T_HVX_rol_acc_R <"$dst += rol($src1,#$src2)">, S6_rol_i_r_acc_enc; -def S6_rol_i_r_and : - T_HVX_rol_acc_R <"$dst &= rol($src1,#$src2)">, S6_rol_i_r_and_enc; -def S6_rol_i_r_or : - T_HVX_rol_acc_R <"$dst |= rol($src1,#$src2)">, S6_rol_i_r_or_enc; -def S6_rol_i_r_xacc : - T_HVX_rol_acc_R <"$dst ^= rol($src1,#$src2)">, S6_rol_i_r_xacc_enc; -} - -let isSolo = 1, Itinerary = LD_tc_ld_SLOT0, Type = TypeLD in -class T_V6_extractw <RegisterClass RC> - : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2), - "$dst = vextract($src1,$src2)">, V6_extractw_enc; - -def V6_extractw : T_V6_extractw <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_extractw_128B : T_V6_extractw <VectorRegs128B>; - -let Itinerary = ST_tc_st_SLOT0, validSubTargets = HasV55SubT in -class T_sys0op <string asmString> - : ST1Inst <(outs), (ins), asmString>; - -let isSolo = 1, validSubTargets = HasV55SubT in { -def Y5_l2gunlock : T_sys0op <"l2gunlock">, Y5_l2gunlock_enc; -def Y5_l2gclean : T_sys0op <"l2gclean">, Y5_l2gclean_enc; -def Y5_l2gcleaninv : T_sys0op <"l2gcleaninv">, Y5_l2gcleaninv_enc; -} - -class T_sys1op <string asmString, RegisterClass RC> - : ST1Inst <(outs), (ins RC:$src1), asmString>; - -class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>; -class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>; - -let isSoloAX = 1, validSubTargets = HasV55SubT in -def Y5_l2unlocka : T_sys1op_R <"l2unlocka($src1)">, Y5_l2unlocka_enc; - -let isSolo = 1, validSubTargets = HasV60SubT in { -def Y6_l2gcleanpa : T_sys1op_P <"l2gclean($src1)">, Y6_l2gcleanpa_enc; -def Y6_l2gcleaninvpa : T_sys1op_P <"l2gcleaninv($src1)">, Y6_l2gcleaninvpa_enc; -} - -let Itinerary = ST_tc_3stall_SLOT0, isPredicateLate = 1, isSoloAX = 1, - validSubTargets = HasV55SubT in -def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1), - "$dst = l2locka($src1)">, Y5_l2locka_enc; - -// not defined on etc side. why? -// defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc; - -let Defs = [USR_OVF], Itinerary = M_tc_3stall_SLOT23, isPredicateLate = 1, - hasSideEffects = 0, -validSubTargets = HasV55SubT in -def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2), - (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2), - "$dst1,$dst2 = vacsh($src1,$src2)", [], - "$dst1 = $_src_" >, Requires<[HasV55T]>, A5_ACS_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, hasNewValue = 1, - hasSideEffects = 0 in -class T_HVX_alu2 <string asmString, RegisterClass RCout, RegisterClass RCin1, - RegisterClass RCin2> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCin1:$src1, RCin2:$src2, RCin2:$src3), asmString>; - -multiclass T_HVX_alu2 <string asmString, RegisterClass RC > { - def NAME : T_HVX_alu2 <asmString, RC, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu2 <asmString, !cast<RegisterClass>(RC#"128B"), - VecPredRegs128B, VectorRegs128B>; -} - -multiclass T_HVX_alu2_V <string asmString> : - T_HVX_alu2 <asmString, VectorRegs>; - -multiclass T_HVX_alu2_W <string asmString> : - T_HVX_alu2 <asmString, VecDblRegs>; - -defm V6_vswap : T_HVX_alu2_W <"$dst = vswap($src1,$src2,$src3)">, V6_vswap_enc; - -let Itinerary = CVI_VA, Type = TypeCVI_VA, hasNewValue = 1, - hasSideEffects = 0 in -defm V6_vmux : T_HVX_alu2_V <"$dst = vmux($src1,$src2,$src3)">, V6_vmux_enc; - -class T_HVX_vlutb <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), asmString>; - -multiclass T_HVX_vlutb <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_vlutb <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vlutb <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_vlutb_V <string asmString> : - T_HVX_vlutb <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_vlutb_W <string asmString> : - T_HVX_vlutb <asmString, VecDblRegs, VectorRegs>; - -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, isAccumulator = 1 in -class T_HVX_vlutb_acc <string asmString, RegisterClass RCout, - RegisterClass RCin> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, RCin:$src2, IntRegsLow8:$src3), - asmString, [], "$dst = $_src_">; - -multiclass T_HVX_vlutb_acc <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_vlutb_acc <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vlutb_acc<asmString, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_vlutb_acc_V <string asmString> : - T_HVX_vlutb_acc <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_vlutb_acc_W <string asmString> : - T_HVX_vlutb_acc <asmString, VecDblRegs, VectorRegs>; - - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1 in -defm V6_vlutvvb: - T_HVX_vlutb_V <"$dst.b = vlut32($src1.b,$src2.b,$src3)">, V6_vlutvvb_enc; - -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, hasNewValue = 1 in -defm V6_vlutvwh: - T_HVX_vlutb_W <"$dst.h = vlut16($src1.b,$src2.h,$src3)">, V6_vlutvwh_enc; - -let hasNewValue = 1 in { - defm V6_vlutvvb_oracc: - T_HVX_vlutb_acc_V <"$dst.b |= vlut32($src1.b,$src2.b,$src3)">, - V6_vlutvvb_oracc_enc; - defm V6_vlutvwh_oracc: - T_HVX_vlutb_acc_W <"$dst.h |= vlut16($src1.b,$src2.h,$src3)">, - V6_vlutvwh_oracc_enc; -} - -// It's a fake instruction and should not be defined? -def S2_cabacencbin - : SInst2<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - "$dst = encbin($src1,$src2,$src3)">, S2_cabacencbin_enc; - -// Vhist instructions -def V6_vhistq - : CVI_HIST_Resource1 <(outs), (ins VecPredRegs:$src1), - "vhist($src1)">, V6_vhistq_enc; - -def V6_vhist - : CVI_HIST_Resource1 <(outs), (ins), - "vhist" >, V6_vhist_enc; - - -let isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { - def V6_vd0: CVI_VA_Resource<(outs VectorRegs:$dst), (ins), "$dst = #0", []>; - def V6_vd0_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), (ins), - "$dst = #0", []>; - - def V6_vassignp: CVI_VA_Resource<(outs VecDblRegs:$dst), - (ins VecDblRegs:$src), "", []>; - def V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst), - (ins VecDblRegs128B:$src), "", []>; - - def V6_lo: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1), - "", []>; - def V6_lo_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), - (ins VecDblRegs128B:$src1), "", []>; - - def V6_hi: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1), - "", []>; - def V6_hi_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), - (ins VecDblRegs128B:$src1), "", []>; -} diff --git a/lib/Target/Hexagon/HexagonInstrInfoVector.td b/lib/Target/Hexagon/HexagonInstrInfoVector.td deleted file mode 100644 index e3520bd6e51..00000000000 --- a/lib/Target/Hexagon/HexagonInstrInfoVector.td +++ /dev/null @@ -1,69 +0,0 @@ -//===- HexagonInstrInfoVector.td - Hexagon Vector Patterns -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon Vector instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -// Vector shift support. Vector shifting in Hexagon is rather different -// from internal representation of LLVM. -// LLVM assumes all shifts (in vector case) will have the form -// <VT> = SHL/SRA/SRL <VT> by <VT> -// while Hexagon has the following format: -// <VT> = SHL/SRA/SRL <VT> by <IT/i32> -// As a result, special care is needed to guarantee correctness and -// performance. -class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp> - : S_2OpInstImm<Str, MajOp, MinOp, u4_0Imm, []> { - bits<4> src2; - let Inst{11-8} = src2; -} - -class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp> - : S_2OpInstImm<Str, MajOp, MinOp, u5_0Imm, []> { - bits<5> src2; - let Inst{12-8} = src2; -} - -def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>; -def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>; -def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>; - -def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>; -def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>; -def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>; - -// Vector shift words by register -def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>; -def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>; -def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>; -def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>; - -// Vector shift halfwords by register -def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>; -def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>; -def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>; -def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>; - - -// Hexagon doesn't have a vector multiply with C semantics. -// Instead, generate a pseudo instruction that gets expaneded into two -// scalar MPYI instructions. -// This is expanded by ExpandPostRAPseudos. -let isPseudo = 1 in -def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>; - -let isPseudo = 1 in -def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [], - "$Rd = $Rx">; - - - diff --git a/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/lib/Target/Hexagon/HexagonIntrinsicsV60.td index a45e1c9d7be..f438b3e0368 100644 --- a/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ b/lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -790,7 +790,7 @@ def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; -def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; +//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; def: Pat<(v64i16 (trunc v64i32:$Vdd)), (v64i16 (V6_vpackwh_sat_128B diff --git a/lib/Target/Hexagon/HexagonOperands.td b/lib/Target/Hexagon/HexagonOperands.td index 98331057156..f87a1b8e424 100644 --- a/lib/Target/Hexagon/HexagonOperands.td +++ b/lib/Target/Hexagon/HexagonOperands.td @@ -1,298 +1,33 @@ -//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===// +//===--- HexagonOperands.td -----------------------------------------------===// // // The LLVM Compiler Infrastructure // -// This file is distributed under the University of Illnois Open Source +// This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; } -def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; } -def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; } -def s8_0Imm64Operand : AsmOperandClass { let Name = "s8_0Imm64"; } -def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; } -def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; } -def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; } -def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; } -def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; } -def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; } -def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; } -def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; } -def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; } -def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; } -def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; } -def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; } -def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; } -def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; } -def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; } -def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; } -def u9_0ImmOperand : AsmOperandClass { let Name = "u9_0Imm"; } -def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; } -def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; } -def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; } -def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; } -def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; } -def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; } -def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; } -def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; } -def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; } -def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; } -def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; } -def n8_0ImmOperand : AsmOperandClass { let Name = "n8_0Imm"; } -// Immediate operands. - -let OperandType = "OPERAND_IMMEDIATE", - DecoderMethod = "unsignedImmDecoder" in { - def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; - let DecoderMethod = "s32_0ImmDecoder"; } - def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; } - def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s8_0Imm64 : Operand<i64> { let ParserMatchClass = s8_0Imm64Operand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; - let DecoderMethod = "s6_0ImmDecoder"; } - def s6_3Imm : Operand<i32>; - def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; - let DecoderMethod = "s4_0ImmDecoder"; } - def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; - let DecoderMethod = "s4_1ImmDecoder"; } - def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; - let DecoderMethod = "s4_2ImmDecoder"; } - def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; - let DecoderMethod = "s4_3ImmDecoder"; } - def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; } - def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; } - def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; } - def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; } - def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; } - def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; } - def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; } - def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; } - def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; } - def u9_0Imm : Operand<i32> { let ParserMatchClass = u9_0ImmOperand; } - def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; } - def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; } - def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; } - def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; } - def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; } - def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; } - def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; } - def u5_1Imm : Operand<i32>; - def u5_2Imm : Operand<i32>; - def u5_3Imm : Operand<i32>; - def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; } - def u4_1Imm : Operand<i32>; - def u4_2Imm : Operand<i32>; - def u4_3Imm : Operand<i32>; - def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; } - def u3_1Imm : Operand<i32>; - def u3_2Imm : Operand<i32>; - def u3_3Imm : Operand<i32>; - def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; } - def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; } - def n8_0Imm : Operand<i32> { let ParserMatchClass = n8_0ImmOperand; } -} - -let OperandType = "OPERAND_IMMEDIATE" in { - def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; - let PrintMethod = "prints4_6ImmOperand"; - let DecoderMethod = "s4_6ImmDecoder";} - def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand"; - let DecoderMethod = "s4_6ImmDecoder";} - def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; - let PrintMethod = "prints3_6ImmOperand"; - let DecoderMethod = "s3_6ImmDecoder";} - def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand"; - let DecoderMethod = "s3_6ImmDecoder";} -} -def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; } -def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; } - -// -// Immediate predicates -// -def s32_0ImmPred : PatLeaf<(i32 imm), [{ +def f32ImmOperand : AsmOperandClass { let Name = "f32Imm"; } +def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; } +def f64ImmOperand : AsmOperandClass { let Name = "f64Imm"; } +def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; } +def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>; +def s9_0ImmOperand : AsmOperandClass { let Name = "s9_0Imm"; } +def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; } +def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; } +def r32_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isInt<32>(v); }]>; - -def s31_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<31,1>(v); -}]>; - -def s30_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<30,2>(v); -}]>; - -def s29_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<29,3>(v); -}]>; - -def s10_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<10>(v); -}]>; - -def s8_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<8>(v); -}]>; - -def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<8>(v); -}]>; - -def s6_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<6>(v); -}]>; - -def s4_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<4>(v); -}]>; - -def s4_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,1>(v); -}]>; - -def s4_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,2>(v); -}]>; - -def s4_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,3>(v); -}]>; - -def u32_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<32>(v); -}]>; - -def u16_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<16>(v); -}]>; - -def u11_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<11,3>(v); -}]>; - def u9_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isUInt<9>(v); }]>; - -def u8_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<8>(v); -}]>; - -def u6_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<6>(v); -}]>; - -def u6_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<6,1>(v); -}]>; - -def u6_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<6,2>(v); -}]>; - -def u5_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<5>(v); -}]>; - -def u4_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<4>(v); -}]>; - -def u3_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<3>(v); -}]>; - -def u2_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<2>(v); -}]>; - -// Extendable immediate operands. -def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; } -def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; } -def s12_0ExtOperand : AsmOperandClass { let Name = "s12_0Ext"; } -def s10_0ExtOperand : AsmOperandClass { let Name = "s10_0Ext"; } -def s9_0ExtOperand : AsmOperandClass { let Name = "s9_0Ext"; } -def s8_0ExtOperand : AsmOperandClass { let Name = "s8_0Ext"; } -def s7_0ExtOperand : AsmOperandClass { let Name = "s7_0Ext"; } -def s6_0ExtOperand : AsmOperandClass { let Name = "s6_0Ext"; } -def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; } -def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; } -def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; } -def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; } -def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; } -def u7_0ExtOperand : AsmOperandClass { let Name = "u7_0Ext"; } -def u8_0ExtOperand : AsmOperandClass { let Name = "u8_0Ext"; } -def u9_0ExtOperand : AsmOperandClass { let Name = "u9_0Ext"; } -def u10_0ExtOperand : AsmOperandClass { let Name = "u10_0Ext"; } -def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; } -def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; } -def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; } -def u32_0MustExtOperand : AsmOperandClass { let Name = "u32_0MustExt"; } - - - -let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand", - DecoderMethod = "unsignedImmDecoder" in { - def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; } - def s16_0Ext : Operand<i32> { let ParserMatchClass = s16_0ExtOperand; - let DecoderMethod = "s16_0ImmDecoder"; } - def s12_0Ext : Operand<i32> { let ParserMatchClass = s12_0ExtOperand; - let DecoderMethod = "s12_0ImmDecoder"; } - def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand; - let DecoderMethod = "s11_0ImmDecoder"; } - def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand; - let DecoderMethod = "s11_1ImmDecoder"; } - def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand; - let DecoderMethod = "s11_2ImmDecoder"; } - def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand; - let DecoderMethod = "s11_3ImmDecoder"; } - def s10_0Ext : Operand<i32> { let ParserMatchClass = s10_0ExtOperand; - let DecoderMethod = "s10_0ImmDecoder"; } - def s9_0Ext : Operand<i32> { let ParserMatchClass = s9_0ExtOperand; - let DecoderMethod = "s9_0ImmDecoder"; } - def s8_0Ext : Operand<i32> { let ParserMatchClass = s8_0ExtOperand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s7_0Ext : Operand<i32> { let ParserMatchClass = s7_0ExtOperand; } - def s6_0Ext : Operand<i32> { let ParserMatchClass = s6_0ExtOperand; - let DecoderMethod = "s6_0ImmDecoder"; } - def u7_0Ext : Operand<i32> { let ParserMatchClass = u7_0ExtOperand; } - def u8_0Ext : Operand<i32> { let ParserMatchClass = u8_0ExtOperand; } - def u9_0Ext : Operand<i32> { let ParserMatchClass = u9_0ExtOperand; } - def u10_0Ext : Operand<i32> { let ParserMatchClass = u10_0ExtOperand; } - def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; } - def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; } - def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; } - def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; } - def u32_0MustExt : Operand<i32> { let ParserMatchClass = u32_0MustExtOperand; } -} - +def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; let RenderMethod = "addImmOperands"; } +def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; } +def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; } +def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; } // This complex pattern exists only to create a machine instruction operand // of type "frame index". There doesn't seem to be a way to do that directly @@ -305,28 +40,6 @@ def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>; def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>; -// Address operands. - -let PrintMethod = "printGlobalOperand" in { - def globaladdress : Operand<i32>; - def globaladdressExt : Operand<i32>; -} - -let PrintMethod = "printJumpTable" in -def jumptablebase : Operand<i32>; - -def brtarget : Operand<OtherVT> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} -def brtargetExt : Operand<OtherVT> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} -def calltarget : Operand<i32> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} def bblabel : Operand<i32>; def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">; diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td index ad81287007e..20ffc238ec9 100644 --- a/lib/Target/Hexagon/HexagonPatterns.td +++ b/lib/Target/Hexagon/HexagonPatterns.td @@ -153,8 +153,12 @@ def: Pat<(sub s32_0ImmPred:$s10, IntRegs:$Rs), def: Pat<(not I32:$src1), (A2_subri -1, IntRegs:$src1)>; +def TruncI64ToI32: SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); +}]>; + def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; -def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi imm:$s8)>; +def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs), (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; @@ -274,7 +278,7 @@ def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; -def: Pat<(br bb:$dst), (J2_jump brtarget:$dst)>; +def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; def: Pat<(brcond I1:$src1, bb:$block), (J2_jumpt PredRegs:$src1, bb:$block)>; def: Pat<(brind I32:$dst), (J2_jumpr IntRegs:$dst)>; @@ -695,8 +699,8 @@ def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; // Map TLS addressses to A2_tfrsi. -def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16_0Ext:$addr)>; -def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16_0Ext:$label)>; +def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s32_0Imm:$addr)>; +def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s32_0Imm:$label)>; def: Pat<(i64 imm:$v), (CONST64 imm:$v)>; def: Pat<(i1 0), (PS_false)>; @@ -2718,17 +2722,6 @@ def unalignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [ }]>; -def s4_6ImmPred: PatLeaf<(i32 imm), [{ - int64_t V = N->getSExtValue(); - return isShiftedInt<4,6>(V); -}]>; - -def s4_7ImmPred: PatLeaf<(i32 imm), [{ - int64_t V = N->getSExtValue(); - return isShiftedInt<4,7>(V); -}]>; - - multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> { // Aligned stores def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), @@ -3253,8 +3246,8 @@ def vmpyh: OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 (i32 $Rs), (i32 $Rt))>; def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), - (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)), - (v2i32 (vmpyh V2I16:$Rs, V2I16:$Rt))))>; + (LoReg (S2_vtrunewh (A2_combineii 0, 0), + (vmpyh V2I16:$Rs, V2I16:$Rt)))>; // Multiplies two v4i16 vectors. def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), diff --git a/lib/Target/Hexagon/HexagonPseudo.td b/lib/Target/Hexagon/HexagonPseudo.td new file mode 100644 index 00000000000..1ef31c55cc6 --- /dev/null +++ b/lib/Target/Hexagon/HexagonPseudo.td @@ -0,0 +1,538 @@ +//===--- HexagonPseudo.td -------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +let PrintMethod = "printGlobalOperand" in { + def globaladdress : Operand<i32>; + def globaladdressExt : Operand<i32>; +} + +let isPseudo = 1 in { +let isCodeGenOnly = 0 in +def A2_iconst : Pseudo<(outs IntRegs:$Rd32), (ins s23_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">; +def DUPLEX_Pseudo : InstHexagon<(outs), (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>; +} + +let isExtendable = 1, opExtendable = 1, opExtentBits = 6, + isAsmParserOnly = 1 in +def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), + (ins s32_0Imm:$src1, s8_0Imm:$src2), + "$dst=combine(#$src1,#$src2)">; + +// HI/LO Instructions +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, + hasNewValue = 1, opNewValue = 0 in +class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp> + : InstHexagon<(outs IntRegs:$dst), + (ins u16_0Imm:$imm_value), + "$dst"#RegHalf#"=#$imm_value", [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, OpcodeHexagon { + bits<5> dst; + bits<32> imm_value; + + let Inst{27} = Rs; + let Inst{26-24} = MajOp; + let Inst{21} = MinOp; + let Inst{20-16} = dst; + let Inst{23-22} = imm_value{15-14}; + let Inst{13-0} = imm_value{13-0}; +} + +let isAsmParserOnly = 1 in { + def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>; + def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>; +} + +let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in { + def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v), + "$Rd = CONST32(#$v)", []>; + def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v), + "$Rd = CONST64(#$v)", []>; +} + +let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, + isCodeGenOnly = 1 in +def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>; + +let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, + isCodeGenOnly = 1 in +def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>; + +let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), + ".error \"should not emit\" ", []>; + +let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in +def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + ".error \"should not emit\" ", []>; + + +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, + Defs = [PC, LC0], Uses = [SA0, LC0] in { +def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset), + ":endloop0", + []>; +} + +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, + Defs = [PC, LC1], Uses = [SA1, LC1] in { +def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset), + ":endloop1", + []>; +} + +let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, + opExtendable = 0, hasSideEffects = 0 in +class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> + : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2), + #mnemonic#"($offset,#$src2)", + [], "" , CR_tc_3x_SLOT3> { + bits<9> offset; + bits<10> src2; + + let IClass = 0b0110; + + let Inst{27-22} = 0b100100; + let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); + let Inst{20-16} = src2{9-5}; + let Inst{12-8} = offset{8-4}; + let Inst{7-5} = src2{4-2}; + let Inst{4-3} = offset{3-2}; + let Inst{1-0} = src2{1-0}; +} + +let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, + opExtendable = 0, hasSideEffects = 0 in +class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> + : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), + #mnemonic#"($offset,$src2)", + [], "" ,CR_tc_3x_SLOT3> { + bits<9> offset; + bits<5> src2; + + let IClass = 0b0110; + + let Inst{27-22} = 0b000000; + let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); + let Inst{20-16} = src2; + let Inst{12-8} = offset{8-4}; + let Inst{4-3} = offset{3-2}; + } + +multiclass LOOP_ri<string mnemonic> { + let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { + def iext: LOOP_iBase<mnemonic, b30_2Imm, 1>; + def rext: LOOP_rBase<mnemonic, b30_2Imm, 1>; + } +} + + +let Defs = [SA0, LC0, USR] in +defm J2_loop0 : LOOP_ri<"loop0">; + +// Interestingly only loop0's appear to set usr.lpcfg +let Defs = [SA1, LC1] in +defm J2_loop1 : LOOP_ri<"loop1">; + +let isCall = 1, hasSideEffects = 1, isPredicable = 0, + isExtended = 0, isExtendable = 1, opExtendable = 0, + isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in +class T_Call<bit CSR, string ExtStr> + : JInst<(outs), (ins a30_2Imm:$dst), + "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> { + let BaseOpcode = "call"; + bits<24> dst; + + let Defs = !if (CSR, VolatileV3.Regs, []); + let IClass = 0b0101; + let Inst{27-25} = 0b101; + let Inst{24-16,13-1} = dst{23-2}; + let Inst{0} = 0b0; +} + +let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16], + isPredicable = 0 in +def CALLProfile : T_Call<1, "">; + +let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, + Defs = [PC, R31, R6, R7, P0] in +def PS_call_stk : T_Call<0, "">; + +let isCall = 1, hasSideEffects = 1, cofMax1 = 1 in +class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, + dag InputDag = (ins IntRegs:$Rs)> + : JInst<(outs), InputDag, + !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", + "if ($Pu) callr $Rs"), + "callr $Rs"), + [], "", J_tc_2early_SLOT2> { + bits<5> Rs; + bits<2> Pu; + let isPredicated = isPred; + let isPredicatedFalse = isPredNot; + + let IClass = 0b0101; + let Inst{27-25} = 0b000; + let Inst{24-23} = !if (isPred, 0b10, 0b01); + let Inst{22} = 0; + let Inst{21} = isPredNot; + let Inst{9-8} = !if (isPred, Pu, 0b00); + let Inst{20-16} = Rs; + + } + +let isCodeGenOnly = 1, Defs = VolatileV3.Regs in { + def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. +} + +let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, + isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1, + BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2, + Itinerary = J_tc_2early_SLOT23 in +class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops> + : Pseudo<(outs), iops, "">, PredRel { + bits<2> Pu; + bits<17> dst; + let opExtentBits = nbits; + let isPredicable = 0; // !if(isPred, 0, 1); + let isPredicated = 0; // isPred; + let isPredicatedFalse = isFalse; +} + +def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii)>; +//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst)>; +//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst)>; + +let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], + isPredicable = 1, hasSideEffects = 0, InputType = "reg", + cofMax1 = 1 in +class T_JMPr + : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [], + "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon { + bits<5> dst; + + let IClass = 0b0101; + let Inst{27-21} = 0b0010100; + let Inst{20-16} = dst; +} + +// A return through builtin_eh_return. +let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, + isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in +def EH_RETURN_JMPR : T_JMPr; + +// Indirect tail-call. +let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, + isTerminator = 1, isCodeGenOnly = 1 in +def PS_tailcall_r : T_JMPr; + +// +// Direct tail-calls. +let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, + isTerminator = 1, isCodeGenOnly = 1 in +def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>; + +let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in +def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>; + +// Generate frameindex addresses. The main reason for the offset operand is +// that every instruction that is allowed to have frame index as an operand +// will then have that operand followed by an immediate operand (the offset). +// This simplifies the frame-index elimination code. +// +let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, + isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { + def PS_fi : Pseudo<(outs IntRegs:$Rd), + (ins IntRegs:$fi, s32_0Imm:$off), "">; + def PS_fia : Pseudo<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">; +} + +class CondStr<string CReg, bit True, bit New> { + string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; +} +class JumpOpcStr<string Mnemonic, bit New, bit Taken> { + string S = Mnemonic # !if(Taken, ":t", ":nt"); +} +let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, + hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in +class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> + : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst), + CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # + JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", + [], "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon { + + let isTaken = isTak; + let isPredicatedFalse = PredNot; + let isPredicatedNew = isPredNew; + bits<2> src; + bits<5> dst; + + let IClass = 0b0101; + + let Inst{27-22} = 0b001101; + let Inst{21} = PredNot; + let Inst{20-16} = dst; + let Inst{12} = isTak; + let Inst{11} = isPredNew; + let Inst{9-8} = src; +} +multiclass JMPR_Pred<bit PredNot> { + def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken + // Predicate new + def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken + def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken +} +multiclass JMPR_base<string BaseOp> { + let BaseOpcode = BaseOp in { + def NAME : T_JMPr; + defm t : JMPR_Pred<0>; + defm f : JMPR_Pred<1>; + } +} +let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in +defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel; + +//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>; + +// The reason for the custom inserter is to record all ALLOCA instructions +// in MachineFunctionInfo. +let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in +def PS_alloca: InstHexagon<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, u32_0Imm:$A), "", + [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>; + +// Load predicate. +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def LDriw_pred : LDInst<(outs PredRegs:$dst), + (ins IntRegs:$addr, s32_0Imm:$off), + ".error \"should not emit\"", []>; + +// Load modifier. +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def LDriw_mod : LDInst<(outs ModRegs:$dst), + (ins IntRegs:$addr, s32_0Imm:$off), + ".error \"should not emit\"", []>; + +// Vector load +let Predicates = [HasV60T, UseHVX] in +let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in + class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VM_LD, + IType type = TypeCVI_VM_LD> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +// Vector store +let Predicates = [HasV60T, UseHVX] in +let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in +class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VM_ST, + IType type = TypeCVI_VM_ST> +: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +let isCodeGenOnly = 1, isPseudo = 1 in +def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd), + (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), + ".error \"should not emit\" ", []>; + +let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, + isPredicable = 1, + isExtendable = 1, opExtendable = 0, isExtentSigned = 1, + opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in +class T_JMP<string ExtStr> + : JInst_CJUMP_UCJUMP<(outs), (ins b30_2Imm:$dst), + "jump " # ExtStr # "$dst", + [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> { + bits<24> dst; + let IClass = 0b0101; + + let Inst{27-25} = 0b100; + let Inst{24-16} = dst{23-15}; + let Inst{13-1} = dst{14-2}; +} + +// Restore registers and dealloc return function call. +let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, + Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in { + def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">; + + let Defs = [R14, R15, R28, R29, R30, R31, PC] in { + def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">; + } +} + +// Restore registers and dealloc frame before a tail call. +let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in { + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel; + + let Defs = [R14, R15, R28, R29, R30, R31, PC] in { + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel; + } +} + +// Save registers function call. +let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { + def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel; + + let Defs = [P0] in + def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel; + + let Defs = [P0], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel; + + let Defs = [R14, R15, R28] in + def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel; + + let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel; + + let Defs = [R14, R15, R28, P0] in + def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel; + + let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel; +} + +// Vector load/store pseudos + +let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +class STrivv_template<RegisterClass RC> + : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; + +def PS_vstorerw_ai: STrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vstorerwu_ai: STrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; +def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; + + +let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +class LDrivv_template<RegisterClass RC> + : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; + +def PS_vloadrw_ai: LDrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; +def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; + +// Store vector predicate pseudo. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { + def PS_vstorerq_ai : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXSgl]>; + + def PS_vstorerq_ai_128B : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXSgl]>; + + def PS_vloadrq_ai : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXDbl]>; + + def PS_vloadrq_ai_128B : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXDbl]>; +} + +class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VA_DV, + IType type = TypeCVI_VA_DV> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { + def PS_vselect: VSELInst<(outs VectorRegs:$dst), + (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>, + Requires<[HasV60T,UseHVXSgl]>; + def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), + (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), + "", []>, Requires<[HasV60T,UseHVXDbl]>; + def PS_wselect: VSELInst<(outs VecDblRegs:$dst), + (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>, + Requires<[HasV60T,UseHVXSgl]>; + def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), + (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), + "", []>, Requires<[HasV60T,UseHVXDbl]>; +} + +// Store predicate. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def STriw_pred : STInst<(outs), + (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1), + ".error \"should not emit\"", []>; +// Store modifier. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def STriw_mod : STInst<(outs), + (ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1), + ".error \"should not emit\"", []>; + +let isExtendable = 1, opExtendable = 1, opExtentBits = 6, + isAsmParserOnly = 1 in +def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1), + "$dst = #$src1">; + +// Hexagon doesn't have a vector multiply with C semantics. +// Instead, generate a pseudo instruction that gets expaneded into two +// scalar MPYI instructions. +// This is expanded by ExpandPostRAPseudos. +let isPseudo = 1 in +def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>; + +let isPseudo = 1 in +def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [], + "$Rd = $Rx">; + +def DuplexIClass0: InstDuplex < 0 >; +def DuplexIClass1: InstDuplex < 1 >; +def DuplexIClass2: InstDuplex < 2 >; +let isExtendable = 1 in { + def DuplexIClass3: InstDuplex < 3 >; + def DuplexIClass4: InstDuplex < 4 >; + def DuplexIClass5: InstDuplex < 5 >; + def DuplexIClass6: InstDuplex < 6 >; + def DuplexIClass7: InstDuplex < 7 >; +} +def DuplexIClass8: InstDuplex < 8 >; +def DuplexIClass9: InstDuplex < 9 >; +def DuplexIClassA: InstDuplex < 0xA >; +def DuplexIClassB: InstDuplex < 0xB >; +def DuplexIClassC: InstDuplex < 0xC >; +def DuplexIClassD: InstDuplex < 0xD >; +def DuplexIClassE: InstDuplex < 0xE >; +def DuplexIClassF: InstDuplex < 0xF >; diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index 582ab7289f3..3ab0fb9c7fd 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -221,6 +221,10 @@ def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, } // Registers are listed in reverse order for allocation preference reasons. +def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, + (add R23, R22, R21, R20, R19, R18, R17, + R16, R7, R6, R5, R4, R3, R2, R1, R0)>; + def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, (add R7, R6, R5, R4, R3, R2, R1, R0)> ; @@ -228,6 +232,10 @@ def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; +def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, + (add D11, D10, D9, D8, D3, D2, D1, + D0)>; + def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, (add (sequence "V%u", 0, 31))>; diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index 6e4987b7e4e..bce090fb9cf 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -21,4 +21,3 @@ include "HexagonScheduleV55.td" //===----------------------------------------------------------------------===// include "HexagonScheduleV60.td" - diff --git a/lib/Target/Hexagon/HexagonScheduleV4.td b/lib/Target/Hexagon/HexagonScheduleV4.td index 7416baab392..880cc0a02b6 100644 --- a/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/lib/Target/Hexagon/HexagonScheduleV4.td @@ -61,15 +61,21 @@ def J_tc_2early_SLOT23 : InstrItinClass; def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass; def J_tc_2early_SLOT2 : InstrItinClass; def LD_tc_ld_SLOT01 : InstrItinClass; +def LD_tc_ld_pi_SLOT01 : InstrItinClass; def LD_tc_ld_SLOT0 : InstrItinClass; def LD_tc_3or4stall_SLOT0 : InstrItinClass; def M_tc_2_SLOT23 : InstrItinClass; +def M_tc_2_acc_SLOT23 : InstrItinClass; def M_tc_3_SLOT23 : InstrItinClass; def M_tc_1_SLOT23 : InstrItinClass; def M_tc_3x_SLOT23 : InstrItinClass; +def M_tc_3x_acc_SLOT23 : InstrItinClass; def M_tc_3or4x_SLOT23 : InstrItinClass; +def M_tc_3or4x_acc_SLOT23 : InstrItinClass; def ST_tc_st_SLOT01 : InstrItinClass; +def ST_tc_st_pi_SLOT01 : InstrItinClass; def ST_tc_st_SLOT0 : InstrItinClass; +def ST_tc_st_pi_SLOT0 : InstrItinClass; def ST_tc_ld_SLOT0 : InstrItinClass; def ST_tc_3stall_SLOT0 : InstrItinClass; def S_2op_tc_1_SLOT23 : InstrItinClass; @@ -131,21 +137,27 @@ def HexagonItinerariesV4 : //Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, // M InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, // Store // ST InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<ST_tc_st_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, // ST0 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, // S diff --git a/lib/Target/Hexagon/HexagonScheduleV55.td b/lib/Target/Hexagon/HexagonScheduleV55.td index b2a75f7200d..06cbcb16abb 100644 --- a/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/lib/Target/Hexagon/HexagonScheduleV55.td @@ -88,6 +88,8 @@ def HexagonItinerariesV55 : // Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [2, 1]>, InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>, @@ -96,21 +98,30 @@ def HexagonItinerariesV55 : [1, 1, 1]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, + InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, // Store InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]>, InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>, InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, // S InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], diff --git a/lib/Target/Hexagon/HexagonScheduleV60.td b/lib/Target/Hexagon/HexagonScheduleV60.td index dc2ce43b057..63784710f52 100644 --- a/lib/Target/Hexagon/HexagonScheduleV60.td +++ b/lib/Target/Hexagon/HexagonScheduleV60.td @@ -19,6 +19,8 @@ def CVI_LD : FuncUnit; def CVI_XLSHF : FuncUnit; def CVI_MPY01 : FuncUnit; def CVI_ALL : FuncUnit; +def CVI_XLMPY0 : FuncUnit; +def CVI_SHFMPY1: FuncUnit; // Combined functional unit data. def HexagonComboFuncsV60 : @@ -26,7 +28,9 @@ def HexagonComboFuncsV60 : ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>, ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>, ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT, - CVI_MPY0, CVI_MPY1, CVI_LD]> + CVI_MPY0, CVI_MPY1, CVI_LD]>, + ComboFuncData<CVI_XLMPY0 , [CVI_XLANE, CVI_MPY0]>, + ComboFuncData<CVI_SHFMPY1 , [CVI_SHIFT, CVI_MPY1]> ]>; // Note: When adding additional vector scheduling classes, add the @@ -39,6 +43,7 @@ def CVI_VX : InstrItinClass; def CVI_VX_DV_LONG : InstrItinClass; def CVI_VX_DV : InstrItinClass; def CVI_VX_DV_SLOT2 : InstrItinClass; +def CVI_VX_DV_SLOT2_LONG_EARLY : InstrItinClass; def CVI_VP : InstrItinClass; def CVI_VP_LONG : InstrItinClass; def CVI_VP_VS_EARLY : InstrItinClass; @@ -150,22 +155,28 @@ def HexagonItinerariesV60 : // Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, // M InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, // Store InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>, InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>, // S InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index f2b9cdaad1a..a9a11ca2f74 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -38,9 +38,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool ModeIEEERndNear; public: - enum HexagonArchEnum { - V4, V5, V55, V60 - }; +#include "HexagonDepArch.h" HexagonArchEnum HexagonArchVersion; /// True if the target should use Back-Skip-Back scheduling. This is the diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index f6fff226c0c..9c80312b790 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -17,6 +17,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H +#include "HexagonDepITypes.h" #include "HexagonMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" #include <stdint.h> @@ -27,48 +28,8 @@ namespace llvm { /// instruction info tracks. /// namespace HexagonII { - // *** The code below must match HexagonInstrFormat*.td *** // - - // Insn types. - // *** Must match HexagonInstrFormat*.td *** - enum Type { - TypePSEUDO = 0, - TypeCR = 2, - TypeJ = 4, - TypeLD = 5, - TypeST = 6, - TypeV4LDST = 9, - TypeNCJ = 10, - TypeDUPLEX = 11, - TypeCJ = 12, - TypeCVI_FIRST = 13, - TypeCVI_VA = TypeCVI_FIRST, - TypeCVI_VA_DV = 14, - TypeCVI_VX = 15, - TypeCVI_VX_DV = 16, - TypeCVI_VP = 17, - TypeCVI_VP_VS = 18, - TypeCVI_VS = 19, - TypeCVI_VINLANESAT= 20, - TypeCVI_VM_LD = 21, - TypeCVI_VM_TMP_LD = 22, - TypeCVI_VM_CUR_LD = 23, - TypeCVI_VM_VP_LDU = 24, - TypeCVI_VM_ST = 25, - TypeCVI_VM_NEW_ST = 26, - TypeCVI_VM_STU = 27, - TypeCVI_HIST = 28, - TypeCVI_LAST = TypeCVI_HIST, - TypeEXTENDER = 39, - TypeENDLOOP = 40, - TypeS_2op = 41, - TypeS_3op = 42, - TypeALU64 = 43, - TypeM = 44, - TypeALU32_2op = 45, - TypeALU32_3op = 46, - TypeALU32_ADDI = 47 - }; + unsigned const TypeCVI_FIRST = TypeCVI_HIST; + unsigned const TypeCVI_LAST = TypeCVI_VX_DV; enum SubTarget { HasV4SubT = 0x3f, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 35f59c67ece..553ffba508a 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -362,7 +362,6 @@ int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII, unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI) { - const InstrItinerary *II = STI.getSchedModel().InstrItineraries; int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); @@ -758,22 +757,8 @@ void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) { bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI) { - if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) - return false; - - unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); - switch (SchedClass) { - case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123: - case Hexagon::Sched::ALU64_tc_2_SLOT23: - case Hexagon::Sched::ALU64_tc_3x_SLOT23: - case Hexagon::Sched::M_tc_2_SLOT23: - case Hexagon::Sched::M_tc_3x_SLOT23: - case Hexagon::Sched::S_2op_tc_2_SLOT23: - case Hexagon::Sched::S_3op_tc_2_SLOT23: - case Hexagon::Sched::S_3op_tc_3x_SLOT23: - return true; - } - return false; + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask; } void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB, diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 3db645b5769..529a5fd5ed8 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -34,7 +34,7 @@ void HexagonMCShuffler::init(MCInst &MCB) { // Copy the bundle for the shuffling. for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst &MI = *const_cast<MCInst *>(I.getInst()); - DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode())); + DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n'); assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); if (!HexagonMCInstrInfo::isImmext(MI)) { diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index c6aa3ec0e92..8c939155483 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -22,6 +22,7 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "HexagonShuffler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -363,6 +364,21 @@ bool HexagonShuffler::check() { foundBranches.push_back(ISJ); } break; + case HexagonII::TypeV2LDST: + if(HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { + ++loads; + ++memory; + if (ISJ->Core.getUnits() == slotSingleLoad || + HexagonMCInstrInfo::getType(MCII,ID) == + HexagonII::TypeCVI_VM_VP_LDU) + ++load0; + } + else { + assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()); + ++memory; + ++stores; + } + break; case HexagonII::TypeCR: // Legacy conditional branch predicated on a register. case HexagonII::TypeCJ: diff --git a/test/CodeGen/Hexagon/BranchPredict.ll b/test/CodeGen/Hexagon/BranchPredict.ll index 17d169974e5..40791c98148 100644 --- a/test/CodeGen/Hexagon/BranchPredict.ll +++ b/test/CodeGen/Hexagon/BranchPredict.ll @@ -9,7 +9,7 @@ @j = external global i32 define i32 @foo(i32 %a) nounwind { -; CHECK: if{{ *}}(!p{{[0-3]}}.new) jump:nt +; CHECK: if (!p{{[0-3]}}.new) jump:nt entry: %tobool = icmp eq i32 %a, 0 br i1 %tobool, label %if.else, label %if.then, !prof !0 @@ -31,7 +31,7 @@ return: ; preds = %if.else, %if.then declare i32 @foobar(...) define i32 @bar(i32 %a) nounwind { -; CHECK: if{{ *}}(p{{[0-3]}}.new) jump:nt +; CHECK: if (p{{[0-3]}}.new) jump:nt entry: %tobool = icmp eq i32 %a, 0 br i1 %tobool, label %if.else, label %if.then, !prof !1 @@ -51,7 +51,7 @@ return: ; preds = %if.else, %if.then } define i32 @foo_bar(i32 %a, i16 signext %b) nounwind { -; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt +; CHECK: if (!cmp.eq(r{{[0-9]*}}.new,#0)) jump:nt entry: %0 = load i32, i32* @j, align 4 %tobool = icmp eq i32 %0, 0 diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll index 43ddb4307ef..67594ad03be 100644 --- a/test/CodeGen/Hexagon/adde.ll +++ b/test/CodeGen/Hexagon/adde.ll @@ -1,17 +1,17 @@ ; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0) -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0) +; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { diff --git a/test/CodeGen/Hexagon/addh-sext-trunc.ll b/test/CodeGen/Hexagon/addh-sext-trunc.ll index 7f219944436..ec5dc611105 100644 --- a/test/CodeGen/Hexagon/addh-sext-trunc.ll +++ b/test/CodeGen/Hexagon/addh-sext-trunc.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{H|h}}) +; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{H|h}}) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon-unknown-none" diff --git a/test/CodeGen/Hexagon/addh-shifted.ll b/test/CodeGen/Hexagon/addh-shifted.ll index eb263521b42..697a5c5c69b 100644 --- a/test/CodeGen/Hexagon/addh-shifted.ll +++ b/test/CodeGen/Hexagon/addh-shifted.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{L|l}}):<<16 +; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}):<<16 define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone { entry: diff --git a/test/CodeGen/Hexagon/addh.ll b/test/CodeGen/Hexagon/addh.ll index c2b536c4669..8217d6753cb 100644 --- a/test/CodeGen/Hexagon/addh.ll +++ b/test/CodeGen/Hexagon/addh.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}}, r{{[0-9]+}}.{{L|l}}) +; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}}) define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone { entry: diff --git a/test/CodeGen/Hexagon/alu64.ll b/test/CodeGen/Hexagon/alu64.ll index f986f135937..453b40a6ee8 100644 --- a/test/CodeGen/Hexagon/alu64.ll +++ b/test/CodeGen/Hexagon/alu64.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s ; CHECK-LABEL: @test00 -; CHECK: = cmp.eq(r1:0, r3:2) +; CHECK: = cmp.eq(r1:0,r3:2) define i32 @test00(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt) @@ -9,7 +9,7 @@ entry: } ; CHECK-LABEL: @test01 -; CHECK: = cmp.gt(r1:0, r3:2) +; CHECK: = cmp.gt(r1:0,r3:2) define i32 @test01(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt) @@ -17,7 +17,7 @@ entry: } ; CHECK-LABEL: @test02 -; CHECK: = cmp.gtu(r1:0, r3:2) +; CHECK: = cmp.gtu(r1:0,r3:2) define i32 @test02(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt) @@ -25,7 +25,7 @@ entry: } ; CHECK-LABEL: @test10 -; CHECK: = cmp.eq(r0, r1) +; CHECK: = cmp.eq(r0,r1) define i32 @test10(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt) @@ -33,7 +33,7 @@ entry: } ; CHECK-LABEL: @test11 -; CHECK: = !cmp.eq(r0, r1) +; CHECK: = !cmp.eq(r0,r1) define i32 @test11(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt) @@ -41,7 +41,7 @@ entry: } ; CHECK-LABEL: @test12 -; CHECK: = cmp.eq(r0, #23) +; CHECK: = cmp.eq(r0,#23) define i32 @test12(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23) @@ -49,7 +49,7 @@ entry: } ; CHECK-LABEL: @test13 -; CHECK: = !cmp.eq(r0, #47) +; CHECK: = !cmp.eq(r0,#47) define i32 @test13(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47) @@ -57,7 +57,7 @@ entry: } ; CHECK-LABEL: @test20 -; CHECK: = cmpb.eq(r0, r1) +; CHECK: = cmpb.eq(r0,r1) define i32 @test20(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt) @@ -65,7 +65,7 @@ entry: } ; CHECK-LABEL: @test21 -; CHECK: = cmpb.gt(r0, r1) +; CHECK: = cmpb.gt(r0,r1) define i32 @test21(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt) @@ -73,7 +73,7 @@ entry: } ; CHECK-LABEL: @test22 -; CHECK: = cmpb.gtu(r0, r1) +; CHECK: = cmpb.gtu(r0,r1) define i32 @test22(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt) @@ -81,7 +81,7 @@ entry: } ; CHECK-LABEL: @test23 -; CHECK: = cmpb.eq(r0, #56) +; CHECK: = cmpb.eq(r0,#56) define i32 @test23(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56) @@ -89,7 +89,7 @@ entry: } ; CHECK-LABEL: @test24 -; CHECK: = cmpb.gt(r0, #29) +; CHECK: = cmpb.gt(r0,#29) define i32 @test24(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29) @@ -97,7 +97,7 @@ entry: } ; CHECK-LABEL: @test25 -; CHECK: = cmpb.gtu(r0, #111) +; CHECK: = cmpb.gtu(r0,#111) define i32 @test25(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111) @@ -105,7 +105,7 @@ entry: } ; CHECK-LABEL: @test30 -; CHECK: = cmph.eq(r0, r1) +; CHECK: = cmph.eq(r0,r1) define i32 @test30(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt) @@ -113,7 +113,7 @@ entry: } ; CHECK-LABEL: @test31 -; CHECK: = cmph.gt(r0, r1) +; CHECK: = cmph.gt(r0,r1) define i32 @test31(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt) @@ -121,7 +121,7 @@ entry: } ; CHECK-LABEL: @test32 -; CHECK: = cmph.gtu(r0, r1) +; CHECK: = cmph.gtu(r0,r1) define i32 @test32(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt) @@ -129,7 +129,7 @@ entry: } ; CHECK-LABEL: @test33 -; CHECK: = cmph.eq(r0, #-123) +; CHECK: = cmph.eq(r0,#-123) define i32 @test33(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123) @@ -137,7 +137,7 @@ entry: } ; CHECK-LABEL: @test34 -; CHECK: = cmph.gt(r0, #-3) +; CHECK: = cmph.gt(r0,#-3) define i32 @test34(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3) @@ -145,7 +145,7 @@ entry: } ; CHECK-LABEL: @test35 -; CHECK: = cmph.gtu(r0, #13) +; CHECK: = cmph.gtu(r0,#13) define i32 @test35(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13) @@ -153,7 +153,7 @@ entry: } ; CHECK-LABEL: @test40 -; CHECK: = vmux(p0, r3:2, r5:4) +; CHECK: = vmux(p0,r3:2,r5:4) define i64 @test40(i32 %Pu, i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt) @@ -161,7 +161,7 @@ entry: } ; CHECK-LABEL: @test41 -; CHECK: = any8(vcmpb.eq(r1:0, r3:2)) +; CHECK: = any8(vcmpb.eq(r1:0,r3:2)) define i32 @test41(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt) @@ -169,7 +169,7 @@ entry: } ; CHECK-LABEL: @test50 -; CHECK: = add(r1:0, r3:2) +; CHECK: = add(r1:0,r3:2) define i64 @test50(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt) @@ -177,7 +177,7 @@ entry: } ; CHECK-LABEL: @test51 -; CHECK: = add(r1:0, r3:2):sat +; CHECK: = add(r1:0,r3:2):sat define i64 @test51(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt) @@ -185,7 +185,7 @@ entry: } ; CHECK-LABEL: @test52 -; CHECK: = sub(r1:0, r3:2) +; CHECK: = sub(r1:0,r3:2) define i64 @test52(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt) @@ -193,7 +193,7 @@ entry: } ; CHECK-LABEL: @test53 -; CHECK: = add(r1:0, r3:2):raw: +; CHECK: = add(r1:0,r3:2):raw: define i64 @test53(i32 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt) @@ -201,7 +201,7 @@ entry: } ; CHECK-LABEL: @test54 -; CHECK: = and(r1:0, r3:2) +; CHECK: = and(r1:0,r3:2) define i64 @test54(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt) @@ -209,7 +209,7 @@ entry: } ; CHECK-LABEL: @test55 -; CHECK: = or(r1:0, r3:2) +; CHECK: = or(r1:0,r3:2) define i64 @test55(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt) @@ -217,7 +217,7 @@ entry: } ; CHECK-LABEL: @test56 -; CHECK: = xor(r1:0, r3:2) +; CHECK: = xor(r1:0,r3:2) define i64 @test56(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt) @@ -225,7 +225,7 @@ entry: } ; CHECK-LABEL: @test57 -; CHECK: = and(r1:0, ~r3:2) +; CHECK: = and(r1:0,~r3:2) define i64 @test57(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt) @@ -233,7 +233,7 @@ entry: } ; CHECK-LABEL: @test58 -; CHECK: = or(r1:0, ~r3:2) +; CHECK: = or(r1:0,~r3:2) define i64 @test58(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt) @@ -241,7 +241,7 @@ entry: } ; CHECK-LABEL: @test60 -; CHECK: = add(r0.l, r1.l) +; CHECK: = add(r0.l,r1.l) define i32 @test60(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt) @@ -249,7 +249,7 @@ entry: } ; CHECK-LABEL: @test61 -; CHECK: = add(r0.l, r1.h) +; CHECK: = add(r0.l,r1.h) define i32 @test61(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt) @@ -257,7 +257,7 @@ entry: } ; CHECK-LABEL: @test62 -; CHECK: = add(r0.l, r1.l):sat +; CHECK: = add(r0.l,r1.l):sat define i32 @test62(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt) @@ -265,7 +265,7 @@ entry: } ; CHECK-LABEL: @test63 -; CHECK: = add(r0.l, r1.h):sat +; CHECK: = add(r0.l,r1.h):sat define i32 @test63(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt) @@ -273,7 +273,7 @@ entry: } ; CHECK-LABEL: @test64 -; CHECK: = add(r0.l, r1.l):<<16 +; CHECK: = add(r0.l,r1.l):<<16 define i32 @test64(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt) @@ -281,7 +281,7 @@ entry: } ; CHECK-LABEL: @test65 -; CHECK: = add(r0.l, r1.h):<<16 +; CHECK: = add(r0.l,r1.h):<<16 define i32 @test65(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt) @@ -289,7 +289,7 @@ entry: } ; CHECK-LABEL: @test66 -; CHECK: = add(r0.h, r1.l):<<16 +; CHECK: = add(r0.h,r1.l):<<16 define i32 @test66(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt) @@ -297,7 +297,7 @@ entry: } ; CHECK-LABEL: @test67 -; CHECK: = add(r0.h, r1.h):<<16 +; CHECK: = add(r0.h,r1.h):<<16 define i32 @test67(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt) @@ -305,7 +305,7 @@ entry: } ; CHECK-LABEL: @test68 -; CHECK: = add(r0.l, r1.l):sat:<<16 +; CHECK: = add(r0.l,r1.l):sat:<<16 define i32 @test68(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt) @@ -313,7 +313,7 @@ entry: } ; CHECK-LABEL: @test69 -; CHECK: = add(r0.l, r1.h):sat:<<16 +; CHECK: = add(r0.l,r1.h):sat:<<16 define i32 @test69(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt) @@ -321,7 +321,7 @@ entry: } ; CHECK-LABEL: @test6A -; CHECK: = add(r0.h, r1.l):sat:<<16 +; CHECK: = add(r0.h,r1.l):sat:<<16 define i32 @test6A(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt) @@ -329,7 +329,7 @@ entry: } ; CHECK-LABEL: @test6B -; CHECK: = add(r0.h, r1.h):sat:<<16 +; CHECK: = add(r0.h,r1.h):sat:<<16 define i32 @test6B(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt) @@ -337,7 +337,7 @@ entry: } ; CHECK-LABEL: @test70 -; CHECK: = sub(r0.l, r1.l) +; CHECK: = sub(r0.l,r1.l) define i32 @test70(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt) @@ -345,7 +345,7 @@ entry: } ; CHECK-LABEL: @test71 -; CHECK: = sub(r0.l, r1.h) +; CHECK: = sub(r0.l,r1.h) define i32 @test71(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt) @@ -353,7 +353,7 @@ entry: } ; CHECK-LABEL: @test72 -; CHECK: = sub(r0.l, r1.l):sat +; CHECK: = sub(r0.l,r1.l):sat define i32 @test72(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt) @@ -361,7 +361,7 @@ entry: } ; CHECK-LABEL: @test73 -; CHECK: = sub(r0.l, r1.h):sat +; CHECK: = sub(r0.l,r1.h):sat define i32 @test73(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt) @@ -369,7 +369,7 @@ entry: } ; CHECK-LABEL: @test74 -; CHECK: = sub(r0.l, r1.l):<<16 +; CHECK: = sub(r0.l,r1.l):<<16 define i32 @test74(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt) @@ -377,7 +377,7 @@ entry: } ; CHECK-LABEL: @test75 -; CHECK: = sub(r0.l, r1.h):<<16 +; CHECK: = sub(r0.l,r1.h):<<16 define i32 @test75(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt) @@ -385,7 +385,7 @@ entry: } ; CHECK-LABEL: @test76 -; CHECK: = sub(r0.h, r1.l):<<16 +; CHECK: = sub(r0.h,r1.l):<<16 define i32 @test76(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt) @@ -393,7 +393,7 @@ entry: } ; CHECK-LABEL: @test77 -; CHECK: = sub(r0.h, r1.h):<<16 +; CHECK: = sub(r0.h,r1.h):<<16 define i32 @test77(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt) @@ -401,7 +401,7 @@ entry: } ; CHECK-LABEL: @test78 -; CHECK: = sub(r0.l, r1.l):sat:<<16 +; CHECK: = sub(r0.l,r1.l):sat:<<16 define i32 @test78(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt) @@ -409,7 +409,7 @@ entry: } ; CHECK-LABEL: @test79 -; CHECK: = sub(r0.l, r1.h):sat:<<16 +; CHECK: = sub(r0.l,r1.h):sat:<<16 define i32 @test79(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt) @@ -417,7 +417,7 @@ entry: } ; CHECK-LABEL: @test7A -; CHECK: = sub(r0.h, r1.l):sat:<<16 +; CHECK: = sub(r0.h,r1.l):sat:<<16 define i32 @test7A(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt) @@ -425,7 +425,7 @@ entry: } ; CHECK-LABEL: @test7B -; CHECK: = sub(r0.h, r1.h):sat:<<16 +; CHECK: = sub(r0.h,r1.h):sat:<<16 define i32 @test7B(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt) @@ -433,7 +433,7 @@ entry: } ; CHECK-LABEL: @test90 -; CHECK: = and(#1, asl(r0, #2)) +; CHECK: = and(#1,asl(r0,#2)) define i32 @test90(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2) @@ -441,7 +441,7 @@ entry: } ; CHECK-LABEL: @test91 -; CHECK: = or(#1, asl(r0, #2)) +; CHECK: = or(#1,asl(r0,#2)) define i32 @test91(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2) @@ -449,7 +449,7 @@ entry: } ; CHECK-LABEL: @test92 -; CHECK: = add(#1, asl(r0, #2)) +; CHECK: = add(#1,asl(r0,#2)) define i32 @test92(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2) @@ -457,7 +457,7 @@ entry: } ; CHECK-LABEL: @test93 -; CHECK: = sub(#1, asl(r0, #2)) +; CHECK: = sub(#1,asl(r0,#2)) define i32 @test93(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2) @@ -465,7 +465,7 @@ entry: } ; CHECK-LABEL: @test94 -; CHECK: = and(#1, lsr(r0, #2)) +; CHECK: = and(#1,lsr(r0,#2)) define i32 @test94(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2) @@ -473,7 +473,7 @@ entry: } ; CHECK-LABEL: @test95 -; CHECK: = or(#1, lsr(r0, #2)) +; CHECK: = or(#1,lsr(r0,#2)) define i32 @test95(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2) @@ -481,7 +481,7 @@ entry: } ; CHECK-LABEL: @test96 -; CHECK: = add(#1, lsr(r0, #2)) +; CHECK: = add(#1,lsr(r0,#2)) define i32 @test96(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2) @@ -489,7 +489,7 @@ entry: } ; CHECK-LABEL: @test97 -; CHECK: = sub(#1, lsr(r0, #2)) +; CHECK: = sub(#1,lsr(r0,#2)) define i32 @test97(i32 %Rs) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2) @@ -497,7 +497,7 @@ entry: } ; CHECK-LABEL: @test100 -; CHECK: = bitsplit(r0, r1) +; CHECK: = bitsplit(r0,r1) define i64 @test100(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt) @@ -505,7 +505,7 @@ entry: } ; CHECK-LABEL: @test101 -; CHECK: = modwrap(r0, r1) +; CHECK: = modwrap(r0,r1) define i32 @test101(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt) @@ -513,7 +513,7 @@ entry: } ; CHECK-LABEL: @test102 -; CHECK: = parity(r1:0, r3:2) +; CHECK: = parity(r1:0,r3:2) define i32 @test102(i64 %Rs, i64 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt) @@ -521,7 +521,7 @@ entry: } ; CHECK-LABEL: @test103 -; CHECK: = parity(r0, r1) +; CHECK: = parity(r0,r1) define i32 @test103(i32 %Rs, i32 %Rt) #0 { entry: %0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt) diff --git a/test/CodeGen/Hexagon/args.ll b/test/CodeGen/Hexagon/args.ll index 3bfb8b15955..a1c7bc3230d 100644 --- a/test/CodeGen/Hexagon/args.ll +++ b/test/CodeGen/Hexagon/args.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK: r5:4 = combine(#6, #5) -; CHECK: r3:2 = combine(#4, #3) -; CHECK: r1:0 = combine(#2, #1) -; CHECK: memw(r29+#0)=#7 +; CHECK: r5:4 = combine(#6,#5) +; CHECK: r3:2 = combine(#4,#3) +; CHECK: r1:0 = combine(#2,#1) +; CHECK: memw(r29+#0) = #7 define void @foo() nounwind { diff --git a/test/CodeGen/Hexagon/bit-eval.ll b/test/CodeGen/Hexagon/bit-eval.ll index 1d2be5bfc19..5b0111dfcd1 100644 --- a/test/CodeGen/Hexagon/bit-eval.ll +++ b/test/CodeGen/Hexagon/bit-eval.ll @@ -20,7 +20,7 @@ entry: } ; CHECK-LABEL: test3: -; CHECK: r1:0 = combine(#0, #1) +; CHECK: r1:0 = combine(#0,#1) define i64 @test3() #0 { entry: %0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63) diff --git a/test/CodeGen/Hexagon/bit-skip-byval.ll b/test/CodeGen/Hexagon/bit-skip-byval.ll index d6c1aad9400..9ee4014ae34 100644 --- a/test/CodeGen/Hexagon/bit-skip-byval.ll +++ b/test/CodeGen/Hexagon/bit-skip-byval.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; ; Either and or zxtb. -; CHECK: r0 = and(r1, #255) +; CHECK: r0 = and(r1,#255) %struct.t0 = type { i32 } diff --git a/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll b/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll index a56680bd439..e09f7986621 100644 --- a/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll +++ b/test/CodeGen/Hexagon/branchfolder-keep-impdef.ll @@ -3,7 +3,7 @@ ; Check that the testcase compiles successfully. Expect that if-conversion ; took place. ; CHECK-LABEL: fred: -; CHECK: if (!p0) r1 = memw(r0 + #0) +; CHECK: if (!p0) r1 = memw(r0+#0) target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/brev_ld.ll b/test/CodeGen/Hexagon/brev_ld.ll index a2914296ec4..861da32b981 100644 --- a/test/CodeGen/Hexagon/brev_ld.ll +++ b/test/CodeGen/Hexagon/brev_ld.ll @@ -29,7 +29,7 @@ entry: %1 = bitcast i64* %inputLR to i8* %sub = sub i32 13, %shr1 %shl = shl i32 1, %sub -; CHECK: = memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev) %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl) %3 = bitcast i8* %1 to i64* %4 = load i64, i64* %3, align 8, !tbaa !0 @@ -49,7 +49,7 @@ entry: %1 = bitcast i32* %inputLR to i8* %sub = sub i32 14, %shr1 %shl = shl i32 1, %sub -; CHECK: = memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev) %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl) %3 = bitcast i8* %1 to i32* %4 = load i32, i32* %3, align 4, !tbaa !2 @@ -69,7 +69,7 @@ entry: %1 = bitcast i16* %inputLR to i8* %sub = sub i32 15, %shr1 %shl = shl i32 1, %sub -; CHECK: = memh(r{{[0-9]*}} ++ m0:brev) +; CHECK: = memh(r{{[0-9]*}}++m0:brev) %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl) %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !3 @@ -89,7 +89,7 @@ entry: %1 = bitcast i16* %inputLR to i8* %sub = sub i32 15, %shr1 %shl = shl i32 1, %sub -; CHECK: = memuh(r{{[0-9]*}} ++ m0:brev) +; CHECK: = memuh(r{{[0-9]*}}++m0:brev) %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl) %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !3 @@ -108,7 +108,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub nsw i32 16, %shr1 %shl = shl i32 1, %sub -; CHECK: = memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev) %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl) %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 @@ -126,7 +126,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub nsw i32 16, %shr1 %shl = shl i32 1, %sub -; CHECK: = memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev) %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl) %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 diff --git a/test/CodeGen/Hexagon/brev_st.ll b/test/CodeGen/Hexagon/brev_st.ll index 6c55681a683..cee5f52e3e4 100644 --- a/test/CodeGen/Hexagon/brev_st.ll +++ b/test/CodeGen/Hexagon/brev_st.ll @@ -26,7 +26,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub i32 13, %shr2 %shl = shl i32 1, %sub -; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl) ret i64 0 } @@ -42,7 +42,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub i32 14, %shr1 %shl = shl i32 1, %sub -; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl) ret i32 0 } @@ -58,7 +58,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub i32 15, %shr2 %shl = shl i32 1, %sub -; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl) ret i16 0 } @@ -74,7 +74,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub i32 15, %shr2 %shl = shl i32 1, %sub -; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h +; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl) ret i16 0 } @@ -89,7 +89,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %sub = sub nsw i32 16, %shr2 - ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + ; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev) %shl = shl i32 1, %sub %1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl) ret i8 0 diff --git a/test/CodeGen/Hexagon/cext-valid-packet1.ll b/test/CodeGen/Hexagon/cext-valid-packet1.ll index 36abc59f5e3..b0aa3c16f86 100644 --- a/test/CodeGen/Hexagon/cext-valid-packet1.ll +++ b/test/CodeGen/Hexagon/cext-valid-packet1.ll @@ -3,8 +3,8 @@ ; Check that the packetizer generates valid packets with constant ; extended instructions. ; CHECK: { -; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) -; CHECK-NEXT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}, ##{{[0-9]+}}) +; CHECK-NEXT: r{{[0-9]+}} = add(r{{[0-9]+}},##{{[0-9]+}}) +; CHECK-NEXT: r{{[0-9]+}} = add(r{{[0-9]+}},##{{[0-9]+}}) ; CHECK-NEXT: } define i32 @check-packet1(i32 %a, i32 %b, i32 %c) nounwind readnone { diff --git a/test/CodeGen/Hexagon/circ_ld.ll b/test/CodeGen/Hexagon/circ_ld.ll index ffa5f2cd222..a9b367e9c4e 100644 --- a/test/CodeGen/Hexagon/circ_ld.ll +++ b/test/CodeGen/Hexagon/circ_ld.ll @@ -26,7 +26,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr1, 33554432 -; CHECK: = memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) +; CHECK: = memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}})) %1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1) %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 @@ -45,7 +45,7 @@ entry: %1 = bitcast i64* %inputLR to i8* %shl = shl nuw nsw i32 %shr1, 3 %or = or i32 %shl, 83886080 -; CHECK: = memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}})) +; CHECK: = memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8) %3 = bitcast i8* %1 to i64* %4 = load i64, i64* %3, align 8, !tbaa !0 @@ -64,7 +64,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %1 = bitcast i16* %inputLR to i8* %or = or i32 %shr1, 50331648 -; CHECK: = memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) +; CHECK: = memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2) %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !2 @@ -82,7 +82,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr1, 33554432 -; CHECK: = memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) +; CHECK: = memub(r{{[0-9]*}}++#-1:circ(m{{[0-1]}})) %1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1) %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 @@ -100,7 +100,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %1 = bitcast i16* %inputLR to i8* %or = or i32 %shr1, 50331648 -; CHECK: = memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) +; CHECK: = memuh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2) %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !2 @@ -120,7 +120,7 @@ entry: %1 = bitcast i32* %inputLR to i8* %shl = shl nuw nsw i32 %shr1, 2 %or = or i32 %shl, 67108864 -; CHECK: = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}})) +; CHECK: = memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4) %3 = bitcast i8* %1 to i32* %4 = load i32, i32* %3, align 4, !tbaa !3 diff --git a/test/CodeGen/Hexagon/circ_ldw.ll b/test/CodeGen/Hexagon/circ_ldw.ll index 4511a9cf69d..abfb0886c68 100644 --- a/test/CodeGen/Hexagon/circ_ldw.ll +++ b/test/CodeGen/Hexagon/circ_ldw.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s -; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m0)) +; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}++#-4:circ(m0)) %union.vect64 = type { i64 } diff --git a/test/CodeGen/Hexagon/circ_st.ll b/test/CodeGen/Hexagon/circ_st.ll index 4b54afbc611..c8fa256ad48 100644 --- a/test/CodeGen/Hexagon/circ_st.ll +++ b/test/CodeGen/Hexagon/circ_st.ll @@ -23,7 +23,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr2, 33554432 -; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}})) +; CHECK: memb(r{{[0-9]*}}++#-1:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1) ret i8 0 } @@ -39,7 +39,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %shl = shl nuw nsw i32 %shr1, 3 %or = or i32 %shl, 83886080 -; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}})) +; CHECK: memd(r{{[0-9]*}}++#-8:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8) ret i64 0 } @@ -54,7 +54,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr2, 50331648 -; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})) +; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2) ret i16 0 } @@ -69,7 +69,7 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr2, 50331648 -; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h +; CHECK: memh(r{{[0-9]*}}++#-2:circ(m{{[0-1]}})) = r{{[0-9]*}}.h %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2) ret i16 0 } @@ -85,7 +85,7 @@ entry: %0 = bitcast i16* %arrayidx to i8* %shl = shl nuw nsw i32 %shr1, 2 %or = or i32 %shl, 67108864 -; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}})) +; CHECK: memw(r{{[0-9]*}}++#-4:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4) ret i32 0 } diff --git a/test/CodeGen/Hexagon/clr_set_toggle.ll b/test/CodeGen/Hexagon/clr_set_toggle.ll index 19e3ed0cf89..4e983831652 100644 --- a/test/CodeGen/Hexagon/clr_set_toggle.ll +++ b/test/CodeGen/Hexagon/clr_set_toggle.ll @@ -4,7 +4,7 @@ define i32 @my_clrbit(i32 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -15,7 +15,7 @@ entry: define i64 @my_clrbit2(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit2 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -26,7 +26,7 @@ entry: define i64 @my_clrbit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit3 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -37,7 +37,7 @@ entry: define i32 @my_clrbit4(i32 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit4 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -48,7 +48,7 @@ entry: define i64 @my_clrbit5(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit5 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -59,7 +59,7 @@ entry: define i64 @my_clrbit6(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit6 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#27) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -70,7 +70,7 @@ entry: define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind { entry: ; CHECK-LABEL: my_setbit -; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}){{ *}}={{ *}}setbit(#15) +; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 %0 = load i16, i16* %crc.addr, align 2 @@ -85,7 +85,7 @@ entry: define i32 @my_setbit2(i32 %x) nounwind { entry: ; CHECK-LABEL: my_setbit2 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -96,7 +96,7 @@ entry: define i64 @my_setbit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_setbit3 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -107,7 +107,7 @@ entry: define i32 @my_setbit4(i32 %x) nounwind { entry: ; CHECK-LABEL: my_setbit4 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -118,7 +118,7 @@ entry: define i64 @my_setbit5(i64 %x) nounwind { entry: ; CHECK-LABEL: my_setbit5 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -129,7 +129,7 @@ entry: define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind { entry: ; CHECK-LABEL: my_togglebit -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 %0 = load i16, i16* %crc.addr, align 2 @@ -144,7 +144,7 @@ entry: define i32 @my_togglebit2(i32 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit2 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -155,7 +155,7 @@ entry: define i64 @my_togglebit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit3 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -166,7 +166,7 @@ entry: define i64 @my_togglebit4(i64 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit4 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#20) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 diff --git a/test/CodeGen/Hexagon/cmp.ll b/test/CodeGen/Hexagon/cmp.ll index c274a787249..a0bb90de1c2 100644 --- a/test/CodeGen/Hexagon/cmp.ll +++ b/test/CodeGen/Hexagon/cmp.ll @@ -9,7 +9,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpeq(i32 %0, i32 1) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},r{{[0-9]}}) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpeq(i32, i32) #1 @@ -23,7 +23,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgt(i32 %0, i32 2) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},r{{[0-9]}}) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgt(i32, i32) #1 @@ -37,7 +37,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgtu(i32 %0, i32 3) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},r{{[0-9]}}) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgtu(i32, i32) #1 @@ -51,7 +51,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},r{{[0-9]}}) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1 @@ -65,7 +65,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpltu(i32 %0, i32 5) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},r{{[0-9]}}) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpltu(i32, i32) #1 @@ -79,7 +79,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpeqi(i32 %0, i32 10) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, {{.*}}#10) +; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},#10) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpeqi(i32, i32) #1 @@ -93,7 +93,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgti(i32 %0, i32 20) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#20) +; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},#20) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgti(i32, i32) #1 @@ -107,7 +107,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgtui(i32 %0, i32 40) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#40) +; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},#40) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgtui(i32, i32) #1 @@ -121,7 +121,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgei(i32 %0, i32 3) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#2) +; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}},#2) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgei(i32, i32) #1 @@ -135,7 +135,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 3) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#2) +; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}},#2) ; Function Attrs: nounwind readnone declare i32 @llvm.hexagon.C2.cmpgeui(i32, i32) #1 @@ -149,7 +149,7 @@ entry: %1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 0) ret i32 %1 } -; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}}) +; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}},r{{[0-9]}}) attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Hexagon/combine.ll b/test/CodeGen/Hexagon/combine.ll index 04a080fdf42..5b71b366566 100644 --- a/test/CodeGen/Hexagon/combine.ll +++ b/test/CodeGen/Hexagon/combine.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s -; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}}) @j = external global i32 @k = external global i64 diff --git a/test/CodeGen/Hexagon/constp-combine-neg.ll b/test/CodeGen/Hexagon/constp-combine-neg.ll index 18f0e81076a..089d9f6a998 100644 --- a/test/CodeGen/Hexagon/constp-combine-neg.ll +++ b/test/CodeGen/Hexagon/constp-combine-neg.ll @@ -19,9 +19,9 @@ entry: ; The instructions seem to be in a different order in the .s file than ; the corresponding values in the .ll file, so just run the test three ; times and each time test for a different instruction. -; CHECK-TEST1: combine(#-2, #3) -; CHECK-TEST2: combine(#6, #-4) -; CHECK-TEST3: combine(#-10, #-8) +; CHECK-TEST1: combine(#-2,#3) +; CHECK-TEST2: combine(#6,#-4) +; CHECK-TEST3: combine(#-10,#-8) attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll b/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll index b8f483298f8..c8b1b0a2ca0 100644 --- a/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll +++ b/test/CodeGen/Hexagon/ctlz-cttz-ctpop.ll @@ -4,7 +4,7 @@ ; CHECK-DAG: cl0({{r[0-9]*:[0-9]*}}) ; CHECK-DAG: ct0({{r[0-9]*}}) ; CHECK-DAG: cl0({{r[0-9]*}}) -; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4) +; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}},#4) define i32 @foo(i64 %a, i32 %b) nounwind { entry: diff --git a/test/CodeGen/Hexagon/dead-store-stack.ll b/test/CodeGen/Hexagon/dead-store-stack.ll index 93d324baad9..0d8124e76b9 100644 --- a/test/CodeGen/Hexagon/dead-store-stack.ll +++ b/test/CodeGen/Hexagon/dead-store-stack.ll @@ -1,6 +1,6 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s ; CHECK: ParseFunc: -; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]] + #[[OFFSET:[0-9]+]]) +; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] @.str.3 = external unnamed_addr constant [8 x i8], align 1 diff --git a/test/CodeGen/Hexagon/eh_return.ll b/test/CodeGen/Hexagon/eh_return.ll index 67649a07afc..1596ade24c8 100644 --- a/test/CodeGen/Hexagon/eh_return.ll +++ b/test/CodeGen/Hexagon/eh_return.ll @@ -4,7 +4,7 @@ ; CHECK: deallocframe ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r29 = add(r29, r28) +; CHECK-NEXT: r29 = add(r29,r28) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll index c492343d791..c7a386a664b 100644 --- a/test/CodeGen/Hexagon/extload-combine.ll +++ b/test/CodeGen/Hexagon/extload-combine.ll @@ -15,8 +15,8 @@ ; Function Attrs: nounwind define i64 @short_test1() #0 { -; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(## -; CHECK: combine(#0, [[VAR]]) +; CHECK: [[VAR:r[0-9]+]] = memuh(## +; CHECK: combine(#0,[[VAR]]) entry: store i16 0, i16* @a, align 2 %0 = load i16, i16* @b, align 2 @@ -26,7 +26,7 @@ entry: ; Function Attrs: nounwind define i64 @short_test2() #0 { -; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(## +; CHECK: [[VAR1:r[0-9]+]] = memh(## ; CHECK: sxtw([[VAR1]]) entry: store i16 0, i16* @a, align 2 @@ -37,8 +37,8 @@ entry: ; Function Attrs: nounwind define i64 @char_test1() #0 { -; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(## -; CHECK: combine(#0, [[VAR2]]) +; CHECK: [[VAR2:r[0-9]+]] = memub(## +; CHECK: combine(#0,[[VAR2]]) entry: store i8 0, i8* @char_a, align 1 %0 = load i8, i8* @char_b, align 1 @@ -48,7 +48,7 @@ entry: ; Function Attrs: nounwind define i64 @char_test2() #0 { -; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(## +; CHECK: [[VAR3:r[0-9]+]] = memb(## ; CHECK: sxtw([[VAR3]]) entry: store i8 0, i8* @char_a, align 1 @@ -59,8 +59,8 @@ entry: ; Function Attrs: nounwind define i64 @int_test1() #0 { -; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(## -; CHECK: combine(#0, [[VAR4]]) +; CHECK: [[VAR4:r[0-9]+]] = memw(## +; CHECK: combine(#0,[[VAR4]]) entry: store i32 0, i32* @int_a, align 4 %0 = load i32, i32* @int_b, align 4 @@ -70,7 +70,7 @@ entry: ; Function Attrs: nounwind define i64 @int_test2() #0 { -; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(## +; CHECK: [[VAR5:r[0-9]+]] = memw(## ; CHECK: sxtw([[VAR5]]) entry: store i32 0, i32* @int_a, align 4 diff --git a/test/CodeGen/Hexagon/extract-basic.ll b/test/CodeGen/Hexagon/extract-basic.ll index c75125cedd3..ad118dea0ab 100644 --- a/test/CodeGen/Hexagon/extract-basic.ll +++ b/test/CodeGen/Hexagon/extract-basic.ll @@ -1,8 +1,8 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s -; CHECK-DAG: extractu(r{{[0-9]*}}, #3, #4) -; CHECK-DAG: extractu(r{{[0-9]*}}, #8, #7) -; CHECK-DAG: extractu(r{{[0-9]*}}, #8, #16) +; CHECK-DAG: extractu(r{{[0-9]*}},#3,#4) +; CHECK-DAG: extractu(r{{[0-9]*}},#8,#7) +; CHECK-DAG: extractu(r{{[0-9]*}},#8,#16) ; C source: ; typedef struct { diff --git a/test/CodeGen/Hexagon/fadd.ll b/test/CodeGen/Hexagon/fadd.ll index 6cf0fbbccf7..0418c1724f5 100644 --- a/test/CodeGen/Hexagon/fadd.ll +++ b/test/CodeGen/Hexagon/fadd.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate sp floating point add in V5. -; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}},r{{[0-9]+}}) define i32 @main() nounwind { entry: diff --git a/test/CodeGen/Hexagon/float-amode.ll b/test/CodeGen/Hexagon/float-amode.ll index 5f13e048f9c..d770582ecab 100644 --- a/test/CodeGen/Hexagon/float-amode.ll +++ b/test/CodeGen/Hexagon/float-amode.ll @@ -12,9 +12,9 @@ @a = common global float 0.000000e+00, align 4 ; CHECK-LABEL: test1 -; CHECK: [[REG11:(r[0-9]+)]]{{ *}}={{ *}}memw(r{{[0-9]+}} + r{{[0-9]+}}<<#2) +; CHECK: [[REG11:(r[0-9]+)]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2) ; CHECK: [[REG12:(r[0-9]+)]] += sfmpy({{.*}}[[REG11]] -; CHECK: memw(r{{[0-9]+}} + r{{[0-9]+}}<<#2) = [[REG12]].new +; CHECK: memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2) = [[REG12]].new ; Function Attrs: norecurse nounwind define void @test1(%struct.matrix_params* nocapture readonly %params, i32 %col1) { @@ -35,7 +35,7 @@ entry: } ; CHECK-LABEL: test2 -; CHECK: [[REG21:(r[0-9]+)]]{{ *}}={{ *}}memw(##globB+92) +; CHECK: [[REG21:(r[0-9]+)]] = memw(##globB+92) ; CHECK: [[REG22:(r[0-9]+)]] = sfadd({{.*}}[[REG21]] ; CHECK: memw(##globA+84) = [[REG22]] @@ -54,7 +54,7 @@ entry: } ; CHECK-LABEL: test3 -; CHECK: [[REG31:(r[0-9]+)]]{{ *}}={{ *}}memw(gp+#b) +; CHECK: [[REG31:(r[0-9]+)]] = memw(gp+#b) ; CHECK: [[REG32:(r[0-9]+)]] = sfadd({{.*}}[[REG31]] ; CHECK: memw(gp+#a) = [[REG32]] @@ -73,9 +73,9 @@ entry: } ; CHECK-LABEL: test4 -; CHECK: [[REG41:(r[0-9]+)]]{{ *}}={{ *}}memw(r0<<#2 + ##globB+52) +; CHECK: [[REG41:(r[0-9]+)]] = memw(r0<<#2+##globB+52) ; CHECK: [[REG42:(r[0-9]+)]] = sfadd({{.*}}[[REG41]] -; CHECK: memw(r0<<#2 + ##globA+60) = [[REG42]] +; CHECK: memw(r0<<#2+##globA+60) = [[REG42]] ; Function Attrs: noinline norecurse nounwind define void @test4(i32 %col1) { entry: diff --git a/test/CodeGen/Hexagon/fmul.ll b/test/CodeGen/Hexagon/fmul.ll index 4f55d0bec47..552f98ec7a5 100644 --- a/test/CodeGen/Hexagon/fmul.ll +++ b/test/CodeGen/Hexagon/fmul.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate single precision floating point multiply in V5. -; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = sfmpy(r{{[0-9]+}},r{{[0-9]+}}) define i32 @main() nounwind { diff --git a/test/CodeGen/Hexagon/fsel.ll b/test/CodeGen/Hexagon/fsel.ll index 247249da50b..a2f0b4a47f1 100644 --- a/test/CodeGen/Hexagon/fsel.ll +++ b/test/CodeGen/Hexagon/fsel.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s ; CHECK-LABEL: danny: -; CHECK: mux(p0, r1, ##1065353216) +; CHECK: mux(p0,r1,##1065353216) define float @danny(i32 %x, float %f) #0 { %t = icmp sgt i32 %x, 0 @@ -10,7 +10,7 @@ define float @danny(i32 %x, float %f) #0 { } ; CHECK-LABEL: sammy: -; CHECK: mux(p0, ##1069547520, r1) +; CHECK: mux(p0,##1069547520,r1) define float @sammy(i32 %x, float %f) #0 { %t = icmp sgt i32 %x, 0 diff --git a/test/CodeGen/Hexagon/fsub.ll b/test/CodeGen/Hexagon/fsub.ll index ca7bdc4d0b3..d7b0e2f65b3 100644 --- a/test/CodeGen/Hexagon/fsub.ll +++ b/test/CodeGen/Hexagon/fsub.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that we generate sp floating point subtract in V5. -; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = sfsub(r{{[0-9]+}},r{{[0-9]+}}) define i32 @main() nounwind { entry: diff --git a/test/CodeGen/Hexagon/fusedandshift.ll b/test/CodeGen/Hexagon/fusedandshift.ll index 414574aec40..0310d440ffe 100644 --- a/test/CodeGen/Hexagon/fusedandshift.ll +++ b/test/CodeGen/Hexagon/fusedandshift.ll @@ -2,7 +2,7 @@ ; Check that we generate fused logical and with shift instruction. ; Disable "extract" generation, since it may eliminate the and/lsr. -; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = and(#15,lsr(r{{[0-9]+}},#{{[0-9]+}}) define i32 @main(i16* %a, i16* %b) nounwind { entry: diff --git a/test/CodeGen/Hexagon/hwloop-cleanup.ll b/test/CodeGen/Hexagon/hwloop-cleanup.ll index c04966a5a4b..56a6fedf81e 100644 --- a/test/CodeGen/Hexagon/hwloop-cleanup.ll +++ b/test/CodeGen/Hexagon/hwloop-cleanup.ll @@ -5,7 +5,7 @@ ; Bug 6685. ; CHECK: loop0 -; CHECK-NOT: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#-1) +; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1) ; CHECK-NOT: cmp.eq ; CHECK: endloop0 @@ -39,7 +39,7 @@ for.end: ; This test checks that that initial loop count value is removed. ; CHECK-NOT: ={{.}}#40 ; CHECK: loop0 -; CHECK-NOT: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#-1) +; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1) ; CHECK-NOT: cmp.eq ; CHECK: endloop0 @@ -64,7 +64,7 @@ for.end: ; This test checks that we don't remove the induction variable since it's used. ; CHECK: loop0 -; CHECK: r{{[0-9]+}}{{.}}={{.}}add(r{{[0-9]+}},{{.}}#1) +; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},#1) ; CHECK-NOT: cmp.eq ; CHECK: endloop0 define i32 @test3(i32* nocapture %b) nounwind { diff --git a/test/CodeGen/Hexagon/hwloop-loop1.ll b/test/CodeGen/Hexagon/hwloop-loop1.ll index 238d34e7ea1..7508b947f1c 100644 --- a/test/CodeGen/Hexagon/hwloop-loop1.ll +++ b/test/CodeGen/Hexagon/hwloop-loop1.ll @@ -2,8 +2,8 @@ ; ; Generate loop1 instruction for double loop sequence. -; CHECK: loop1(.LBB{{.}}_{{.}}, #100) -; CHECK: loop0(.LBB{{.}}_{{.}}, #100) +; CHECK: loop1(.LBB{{.}}_{{.}},#100) +; CHECK: loop0(.LBB{{.}}_{{.}},#100) ; CHECK: endloop0 ; CHECK: endloop1 diff --git a/test/CodeGen/Hexagon/hwloop1.ll b/test/CodeGen/Hexagon/hwloop1.ll index 68af3b34eee..7a805d951b9 100644 --- a/test/CodeGen/Hexagon/hwloop1.ll +++ b/test/CodeGen/Hexagon/hwloop1.ll @@ -3,7 +3,7 @@ ; Case 1 : Loop with a constant number of iterations. ; CHECK-LABEL: @hwloop1 -; CHECK: loop0(.LBB{{.}}_{{.}}, #10) +; CHECK: loop0(.LBB{{.}}_{{.}},#10) ; CHECK: endloop0 @a = common global [10 x i32] zeroinitializer, align 4 @@ -23,7 +23,7 @@ for.end: ; Case 2 : Loop with a run-time number of iterations. ; CHECK-LABEL: @hwloop2 -; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) +; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}}) ; CHECK: endloop0 define i32 @hwloop2(i32 %n, i32* nocapture %b) nounwind { @@ -54,8 +54,8 @@ for.end: ; Case 3 : Induction variable increment more than 1. ; CHECK-LABEL: @hwloop3 -; CHECK: lsr(r{{[0-9]+}}, #2) -; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) +; CHECK: lsr(r{{[0-9]+}},#2) +; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}}) ; CHECK: endloop0 define i32 @hwloop3(i32 %n, i32* nocapture %b) nounwind { @@ -86,7 +86,7 @@ for.end: ; Case 4 : Loop exit compare uses register instead of immediate value. ; CHECK-LABEL: @hwloop4 -; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) +; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}}) ; CHECK: endloop0 define i32 @hwloop4(i32 %n, i32* nocapture %b) nounwind { @@ -114,7 +114,7 @@ for.end: ; Case 5: After LSR, the initial value is 100 and the iv decrements to 0. ; CHECK-LABEL: @hwloop5 -; CHECK: loop0(.LBB{{.}}_{{.}}, #100) +; CHECK: loop0(.LBB{{.}}_{{.}},#100) ; CHECK: endloop0 define void @hwloop5(i32* nocapture %a, i32* nocapture %res) nounwind { @@ -138,8 +138,8 @@ for.end: ; Case 6: Large immediate offset ; CHECK-LABEL: @hwloop6 -; CHECK-NOT: loop0(.LBB{{.}}_{{.}}, #1024) -; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) +; CHECK-NOT: loop0(.LBB{{.}}_{{.}},#1024) +; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}}) ; CHECK: endloop0 define void @hwloop6(i32* nocapture %a, i32* nocapture %res) nounwind { diff --git a/test/CodeGen/Hexagon/hwloop2.ll b/test/CodeGen/Hexagon/hwloop2.ll index d411d979904..ba3de1f1a2a 100644 --- a/test/CodeGen/Hexagon/hwloop2.ll +++ b/test/CodeGen/Hexagon/hwloop2.ll @@ -2,7 +2,7 @@ ; Test for multiple phis with induction variables. -; CHECK: loop0(.LBB{{.}}_{{.}}, r{{[0-9]+}}) +; CHECK: loop0(.LBB{{.}}_{{.}},r{{[0-9]+}}) ; CHECK: endloop0 define i32 @hwloop4(i32* nocapture %s, i32* nocapture %a, i32 %n) { diff --git a/test/CodeGen/Hexagon/hwloop4.ll b/test/CodeGen/Hexagon/hwloop4.ll index d159c45e3fb..b8cea4c7772 100644 --- a/test/CodeGen/Hexagon/hwloop4.ll +++ b/test/CodeGen/Hexagon/hwloop4.ll @@ -2,9 +2,9 @@ ; ; Remove the unnecessary 'add' instruction used for the hardware loop setup. -; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]] -; CHECK-NOT: add([[OP0]], #[[OP2]]) -; CHECK: lsr([[OP1]], #{{[0-9]+}}) +; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]],#-[[OP2:[0-9]+]] +; CHECK-NOT: add([[OP0]],#[[OP2]]) +; CHECK: lsr([[OP1]],#{{[0-9]+}}) ; CHECK: loop0 define void @matrix_mul_matrix(i32 %N, i32* nocapture %C, i16* nocapture readnone %A, i16* nocapture readnone %B) #0 { diff --git a/test/CodeGen/Hexagon/hwloop5.ll b/test/CodeGen/Hexagon/hwloop5.ll index 0886b03cc75..f4990dabebb 100644 --- a/test/CodeGen/Hexagon/hwloop5.ll +++ b/test/CodeGen/Hexagon/hwloop5.ll @@ -2,9 +2,9 @@ ; ; Generate hardware loop when unknown trip count loop is vectorized. -; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}}) +; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}},r{{[0-9]+}}) ; CHECK: endloop0 -; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}}) +; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}},r{{[0-9]+}}) ; CHECK: endloop0 @A = common global [1000 x i32] zeroinitializer, align 8 diff --git a/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll b/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll index 68a5dc16ecf..cbc1c327e69 100644 --- a/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll +++ b/test/CodeGen/Hexagon/ifcvt-diamond-bug-2016-08-26.ll @@ -15,7 +15,7 @@ entry: br i1 %cmp199, label %if.then200, label %if.else201 ; CHECK-DAG: [[R4:r[0-9]+]] = #4 -; CHECK: p0 = cmp.eq(r0, #0) +; CHECK: p0 = cmp.eq(r0,#0) ; CHECK: if (!p0.new) [[R3:r[0-9]+]] = #3 ; CHECK-DAG: if (!p0) memh(##t) = [[R3]] ; CHECK-DAG: if (p0) memh(##t) = [[R4]] diff --git a/test/CodeGen/Hexagon/insert-basic.ll b/test/CodeGen/Hexagon/insert-basic.ll index e941c063d9e..14ee735abd7 100644 --- a/test/CodeGen/Hexagon/insert-basic.ll +++ b/test/CodeGen/Hexagon/insert-basic.ll @@ -1,8 +1,8 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s -; CHECK-DAG: insert(r{{[0-9]*}}, #17, #0) -; CHECK-DAG: insert(r{{[0-9]*}}, #18, #0) -; CHECK-DAG: insert(r{{[0-9]*}}, #22, #0) -; CHECK-DAG: insert(r{{[0-9]*}}, #12, #0) +; CHECK-DAG: insert(r{{[0-9]*}},#17,#0) +; CHECK-DAG: insert(r{{[0-9]*}},#18,#0) +; CHECK-DAG: insert(r{{[0-9]*}},#22,#0) +; CHECK-DAG: insert(r{{[0-9]*}},#12,#0) ; C source: ; typedef struct { diff --git a/test/CodeGen/Hexagon/insert4.ll b/test/CodeGen/Hexagon/insert4.ll index c4d575dd406..3bc8e9e5798 100644 --- a/test/CodeGen/Hexagon/insert4.ll +++ b/test/CodeGen/Hexagon/insert4.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; ; Check that we no longer generate 4 inserts. -; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l) -; CHECK: combine(r{{[0-9]+}}.l, r{{[0-9]+}}.l) +; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.l) +; CHECK: combine(r{{[0-9]+}}.l,r{{[0-9]+}}.l) ; CHECK-NOT: insert target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll b/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll index fcf80b08181..abdd4cba7c5 100644 --- a/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll +++ b/test/CodeGen/Hexagon/intrinsics/alu32_alu.ll @@ -10,21 +10,21 @@ define i32 @A2_addi(i32 %a) { %z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0) ret i32 %z } -; CHECK: = add({{.*}}, #0) +; CHECK: = add({{.*}},#0) declare i32 @llvm.hexagon.A2.add(i32, i32) define i32 @A2_add(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}, {{.*}}) +; CHECK: = add({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.addsat(i32, i32) define i32 @A2_addsat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}, {{.*}}):sat +; CHECK: = add({{.*}},{{.*}}):sat ; Logical operations declare i32 @llvm.hexagon.A2.and(i32, i32) @@ -32,35 +32,35 @@ define i32 @A2_and(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b) ret i32 %z } -; CHECK: = and({{.*}}, {{.*}}) +; CHECK: = and({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.or(i32, i32) define i32 @A2_or(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b) ret i32 %z } -; CHECK: = or({{.*}}, {{.*}}) +; CHECK: = or({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.xor(i32, i32) define i32 @A2_xor(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b) ret i32 %z } -; CHECK: = xor({{.*}}, {{.*}}) +; CHECK: = xor({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.andn(i32, i32) define i32 @A4_andn(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b) ret i32 %z } -; CHECK: = and({{.*}}, ~{{.*}}) +; CHECK: = and({{.*}},~{{.*}}) declare i32 @llvm.hexagon.A4.orn(i32, i32) define i32 @A4_orn(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b) ret i32 %z } -; CHECK: = or({{.*}}, ~{{.*}}) +; CHECK: = or({{.*}},~{{.*}}) ; Subtract declare i32 @llvm.hexagon.A2.sub(i32, i32) @@ -68,14 +68,14 @@ define i32 @A2_sub(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}, {{.*}}) +; CHECK: = sub({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.subsat(i32, i32) define i32 @A2_subsat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subsat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}, {{.*}}):sat +; CHECK: = sub({{.*}},{{.*}}):sat ; Sign extend declare i32 @llvm.hexagon.A2.sxtb(i32) @@ -128,21 +128,21 @@ define i32 @A2_svaddh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svaddh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vaddh({{.*}}, {{.*}}) +; CHECK: = vaddh({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.svaddhs(i32, i32) define i32 @A2_svaddhs(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svaddhs(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vaddh({{.*}}, {{.*}}):sat +; CHECK: = vaddh({{.*}},{{.*}}):sat declare i32 @llvm.hexagon.A2.svadduhs(i32, i32) define i32 @A2_svadduhs(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svadduhs(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vadduh({{.*}}, {{.*}}):sat +; CHECK: = vadduh({{.*}},{{.*}}):sat ; Vector average halfwords declare i32 @llvm.hexagon.A2.svavgh(i32, i32) @@ -150,21 +150,21 @@ define i32 @A2_svavgh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svavgh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vavgh({{.*}}, {{.*}}) +; CHECK: = vavgh({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.svavghs(i32, i32) define i32 @A2_svavghs(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svavghs(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vavgh({{.*}}, {{.*}}):rnd +; CHECK: = vavgh({{.*}},{{.*}}):rnd declare i32 @llvm.hexagon.A2.svnavgh(i32, i32) define i32 @A2_svnavgh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svnavgh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vnavgh({{.*}}, {{.*}}) +; CHECK: = vnavgh({{.*}},{{.*}}) ; Vector subtract halfwords declare i32 @llvm.hexagon.A2.svsubh(i32, i32) @@ -172,21 +172,21 @@ define i32 @A2_svsubh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svsubh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vsubh({{.*}}, {{.*}}) +; CHECK: = vsubh({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.svsubhs(i32, i32) define i32 @A2_svsubhs(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svsubhs(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vsubh({{.*}}, {{.*}}):sat +; CHECK: = vsubh({{.*}},{{.*}}):sat declare i32 @llvm.hexagon.A2.svsubuhs(i32, i32) define i32 @A2_svsubuhs(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.svsubuhs(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vsubuh({{.*}}, {{.*}}):sat +; CHECK: = vsubuh({{.*}},{{.*}}):sat ; Zero extend declare i32 @llvm.hexagon.A2.zxth(i32) diff --git a/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll b/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll index c9fb0afe078..554dac4563d 100644 --- a/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll +++ b/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll @@ -10,56 +10,56 @@ define i64 @A4_combineri(i32 %a) { %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0) ret i64 %z } -; CHECK: = combine({{.*}}, #0) +; CHECK: = combine({{.*}},#0) declare i64 @llvm.hexagon.A4.combineir(i32, i32) define i64 @A4_combineir(i32 %a) { %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a) ret i64 %z } -; CHECK: = combine(#0, {{.*}}) +; CHECK: = combine(#0,{{.*}}) declare i64 @llvm.hexagon.A2.combineii(i32, i32) define i64 @A2_combineii() { %z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0) ret i64 %z } -; CHECK: = combine(#0, #0) +; CHECK: = combine(#0,#0) declare i32 @llvm.hexagon.A2.combine.hh(i32, i32) define i32 @A2_combine_hh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.combine.hh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = combine({{.*}}, {{.*}}) +; CHECK: = combine({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.combine.hl(i32, i32) define i32 @A2_combine_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.combine.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = combine({{.*}}, {{.*}}) +; CHECK: = combine({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.combine.lh(i32, i32) define i32 @A2_combine_lh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.combine.lh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = combine({{.*}}, {{.*}}) +; CHECK: = combine({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) define i32 @A2_combine_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.combine.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = combine({{.*}}, {{.*}}) +; CHECK: = combine({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.combinew(i32, i32) define i64 @A2_combinew(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.A2.combinew(i32 %a, i32 %b) ret i64 %z } -; CHECK: = combine({{.*}}, {{.*}}) +; CHECK: = combine({{.*}},{{.*}}) ; Mux declare i32 @llvm.hexagon.C2.muxri(i32, i32, i32) @@ -67,21 +67,21 @@ define i32 @C2_muxri(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C2.muxri(i32 %a, i32 0, i32 %b) ret i32 %z } -; CHECK: = mux({{.*}}, #0, {{.*}}) +; CHECK: = mux({{.*}},#0,{{.*}}) declare i32 @llvm.hexagon.C2.muxir(i32, i32, i32) define i32 @C2_muxir(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C2.muxir(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: = mux({{.*}}, {{.*}}, #0) +; CHECK: = mux({{.*}},{{.*}},#0) declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) define i32 @C2_mux(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = mux({{.*}}, {{.*}}, {{.*}}) +; CHECK: = mux({{.*}},{{.*}},{{.*}}) ; Shift word by 16 declare i32 @llvm.hexagon.A2.aslh(i32) @@ -104,4 +104,4 @@ define i64 @S2_packhl(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.packhl(i32 %a, i32 %b) ret i64 %z } -; CHECK: = packhl({{.*}}, {{.*}}) +; CHECK: = packhl({{.*}},{{.*}}) diff --git a/test/CodeGen/Hexagon/intrinsics/cr.ll b/test/CodeGen/Hexagon/intrinsics/cr.ll index f308ef8e566..4c0fcb3707c 100644 --- a/test/CodeGen/Hexagon/intrinsics/cr.ll +++ b/test/CodeGen/Hexagon/intrinsics/cr.ll @@ -10,14 +10,14 @@ define i32 @C4_fastcorner9(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b) ret i32 %z } -; CHECK: = fastcorner9({{.*}}, {{.*}}) +; CHECK: = fastcorner9({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32) define i32 @C4_fastcorner9_not(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b) ret i32 %z } -; CHECK: = !fastcorner9({{.*}}, {{.*}}) +; CHECK: = !fastcorner9({{.*}},{{.*}}) ; Logical reductions on predicates declare i32 @llvm.hexagon.C2.any8(i32) @@ -41,70 +41,70 @@ define i32 @C2_and(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.and(i32 %a, i32 %b) ret i32 %z } -; CHECK: = and({{.*}}, {{.*}}) +; CHECK: = and({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = and({{.*}}, and({{.*}}, {{.*}})) +; CHECK: = and({{.*}},and({{.*}},{{.*}})) declare i32 @llvm.hexagon.C2.or(i32, i32) define i32 @C2_or(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.or(i32 %a, i32 %b) ret i32 %z } -; CHECK: = or({{.*}}, {{.*}}) +; CHECK: = or({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32) define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = and({{.*}}, or({{.*}}, {{.*}})) +; CHECK: = and({{.*}},or({{.*}},{{.*}})) declare i32 @llvm.hexagon.C2.xor(i32, i32) define i32 @C2_xor(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.xor(i32 %a, i32 %b) ret i32 %z } -; CHECK: = xor({{.*}}, {{.*}}) +; CHECK: = xor({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32) define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = or({{.*}}, and({{.*}}, {{.*}})) +; CHECK: = or({{.*}},and({{.*}},{{.*}})) declare i32 @llvm.hexagon.C2.andn(i32, i32) define i32 @C2_andn(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.andn(i32 %a, i32 %b) ret i32 %z } -; CHECK: = and({{.*}}, !{{.*}}) +; CHECK: = and({{.*}},!{{.*}}) declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32) define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = or({{.*}}, or({{.*}}, {{.*}})) +; CHECK: = or({{.*}},or({{.*}},{{.*}})) declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32) define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = and({{.*}}, and({{.*}}, !{{.*}})) +; CHECK: = and({{.*}},and({{.*}},!{{.*}})) declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32) define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = and({{.*}}, or({{.*}}, !{{.*}})) +; CHECK: = and({{.*}},or({{.*}},!{{.*}})) declare i32 @llvm.hexagon.C2.not(i32) define i32 @C2_not(i32 %a) { @@ -118,18 +118,18 @@ define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = or({{.*}}, and({{.*}}, !{{.*}})) +; CHECK: = or({{.*}},and({{.*}},!{{.*}})) declare i32 @llvm.hexagon.C2.orn(i32, i32) define i32 @C2_orn(i32 %a, i32 %b) { %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b) ret i32 %z } -; CHECK: = or({{.*}}, !{{.*}}) +; CHECK: = or({{.*}},!{{.*}}) declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32) define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) { %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = or({{.*}}, or({{.*}}, !{{.*}})) +; CHECK: = or({{.*}},or({{.*}},!{{.*}})) diff --git a/test/CodeGen/Hexagon/intrinsics/system_user.ll b/test/CodeGen/Hexagon/intrinsics/system_user.ll index dad4effb0a1..ac4c53e221d 100644 --- a/test/CodeGen/Hexagon/intrinsics/system_user.ll +++ b/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -10,4 +10,4 @@ define void @prefetch(i8* %a) { call void @llvm.hexagon.prefetch(i8* %a) ret void } -; CHECK: dcfetch({{.*}} + #0) +; CHECK: dcfetch({{.*}}+#0) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll b/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll index c5c23c22bde..4d630c62005 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll @@ -34,42 +34,42 @@ define i32 @S4_addaddi(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: = add({{.*}}, add({{.*}}, #0)) +; CHECK: = add({{.*}},add({{.*}},#0)) declare i32 @llvm.hexagon.S4.subaddi(i32, i32, i32) define i32 @S4_subaddi(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.subaddi(i32 %a, i32 0, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}, sub(#0, {{.*}})) +; CHECK: = add({{.*}},sub(#0,{{.*}})) declare i32 @llvm.hexagon.M2.accii(i32, i32, i32) define i32 @M2_accii(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.accii(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: += add({{.*}}, #0) +; CHECK: += add({{.*}},#0) declare i32 @llvm.hexagon.M2.naccii(i32, i32, i32) define i32 @M2_naccii(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.naccii(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: -= add({{.*}}, #0) +; CHECK: -= add({{.*}},#0) declare i32 @llvm.hexagon.M2.acci(i32, i32, i32) define i32 @M2_acci(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.acci(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += add({{.*}}, {{.*}}) +; CHECK: += add({{.*}},{{.*}}) declare i32 @llvm.hexagon.M2.nacci(i32, i32, i32) define i32 @M2_nacci(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.nacci(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= add({{.*}}, {{.*}}) +; CHECK: -= add({{.*}},{{.*}}) ; Add doublewords declare i64 @llvm.hexagon.A2.addp(i64, i64) @@ -77,14 +77,14 @@ define i64 @A2_addp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.addp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = add({{.*}}, {{.*}}) +; CHECK: = add({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.addpsat(i64, i64) define i64 @A2_addpsat(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.addpsat(i64 %a, i64 %b) ret i64 %z } -; CHECK: = add({{.*}}, {{.*}}):sat +; CHECK: = add({{.*}},{{.*}}):sat ; Add halfword declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32) @@ -92,84 +92,84 @@ define i32 @A2_addh_l16_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.l) +; CHECK: = add({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32) define i32 @A2_addh_l16_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.h) +; CHECK: = add({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) define i32 @A2_addh_l16_sat.ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.l):sat +; CHECK: = add({{.*}}.l,{{.*}}.l):sat declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32) define i32 @A2_addh_l16_sat.hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.h):sat +; CHECK: = add({{.*}}.l,{{.*}}.h):sat declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32) define i32 @A2_addh_h16_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.l):<<16 +; CHECK: = add({{.*}}.l,{{.*}}.l):<<16 declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32) define i32 @A2_addh_h16_lh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.h):<<16 +; CHECK: = add({{.*}}.l,{{.*}}.h):<<16 declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32) define i32 @A2_addh_h16_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.h, {{.*}}.l):<<16 +; CHECK: = add({{.*}}.h,{{.*}}.l):<<16 declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32) define i32 @A2_addh_h16_hh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.h, {{.*}}.h):<<16 +; CHECK: = add({{.*}}.h,{{.*}}.h):<<16 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32) define i32 @A2_addh_h16_sat_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.l):sat:<<16 +; CHECK: = add({{.*}}.l,{{.*}}.l):sat:<<16 declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32) define i32 @A2_addh_h16_sat_lh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.l, {{.*}}.h):sat:<<16 +; CHECK: = add({{.*}}.l,{{.*}}.h):sat:<<16 declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32) define i32 @A2_addh_h16_sat_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.h, {{.*}}.l):sat:<<16 +; CHECK: = add({{.*}}.h,{{.*}}.l):sat:<<16 declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32) define i32 @A2_addh_h16_sat_hh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}.h, {{.*}}.h):sat:<<16 +; CHECK: = add({{.*}}.h,{{.*}}.h):sat:<<16 ; Logical doublewords declare i64 @llvm.hexagon.A2.notp(i64) @@ -184,35 +184,35 @@ define i64 @A2_andp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.andp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = and({{.*}}, {{.*}}) +; CHECK: = and({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.andnp(i64, i64) define i64 @A2_andnp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A4.andnp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = and({{.*}}, ~{{.*}}) +; CHECK: = and({{.*}},~{{.*}}) declare i64 @llvm.hexagon.A2.orp(i64, i64) define i64 @A2_orp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.orp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = or({{.*}}, {{.*}}) +; CHECK: = or({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.ornp(i64, i64) define i64 @A2_ornp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A4.ornp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = or({{.*}}, ~{{.*}}) +; CHECK: = or({{.*}},~{{.*}}) declare i64 @llvm.hexagon.A2.xorp(i64, i64) define i64 @A2_xorp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.xorp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = xor({{.*}}, {{.*}}) +; CHECK: = xor({{.*}},{{.*}}) ; Logical-logical doublewords declare i64 @llvm.hexagon.M4.xor.xacc(i64, i64, i64) @@ -220,7 +220,7 @@ define i64 @M4_xor_xacc(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M4.xor.xacc(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: ^= xor({{.*}}, {{.*}}) +; CHECK: ^= xor({{.*}},{{.*}}) ; Logical-logical words declare i32 @llvm.hexagon.S4.or.andi(i32, i32, i32) @@ -228,91 +228,91 @@ define i32 @S4_or_andi(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.or.andi(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: |= and({{.*}}, #0) +; CHECK: |= and({{.*}},#0) declare i32 @llvm.hexagon.S4.or.andix(i32, i32, i32) define i32 @S4_or_andix(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.or.andix(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: = or({{.*}}, and({{.*}}, #0)) +; CHECK: = or({{.*}},and({{.*}},#0)) declare i32 @llvm.hexagon.M4.or.andn(i32, i32, i32) define i32 @M4_or_andn(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.or.andn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= and({{.*}}, ~{{.*}}) +; CHECK: |= and({{.*}},~{{.*}}) declare i32 @llvm.hexagon.M4.and.andn(i32, i32, i32) define i32 @M4_and_andn(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.and.andn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= and({{.*}}, ~{{.*}}) +; CHECK: &= and({{.*}},~{{.*}}) declare i32 @llvm.hexagon.M4.xor.andn(i32, i32, i32) define i32 @M4_xor_andn(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.xor.andn(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: ^= and({{.*}}, ~{{.*}}) +; CHECK: ^= and({{.*}},~{{.*}}) declare i32 @llvm.hexagon.M4.and.and(i32, i32, i32) define i32 @M4_and_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.and.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= and({{.*}}, {{.*}}) +; CHECK: &= and({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.and.or(i32, i32, i32) define i32 @M4_and_or(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.and.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= or({{.*}}, {{.*}}) +; CHECK: &= or({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.and.xor(i32, i32, i32) define i32 @M4_and_xor(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.and.xor(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= xor({{.*}}, {{.*}}) +; CHECK: &= xor({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.or.and(i32, i32, i32) define i32 @M4_or_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.or.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= and({{.*}}, {{.*}}) +; CHECK: |= and({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.or.or(i32, i32, i32) define i32 @M4_or_or(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.or.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= or({{.*}}, {{.*}}) +; CHECK: |= or({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.or.xor(i32, i32, i32) define i32 @M4_or_xor(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.or.xor(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= xor({{.*}}, {{.*}}) +; CHECK: |= xor({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.xor.and(i32, i32, i32) define i32 @M4_xor_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.xor.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: ^= and({{.*}}, {{.*}}) +; CHECK: ^= and({{.*}},{{.*}}) declare i32 @llvm.hexagon.M4.xor.or(i32, i32, i32) define i32 @M4_xor_or(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.xor.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: ^= or({{.*}}, {{.*}}) +; CHECK: ^= or({{.*}},{{.*}}) ; Maximum words declare i32 @llvm.hexagon.A2.max(i32, i32) @@ -320,14 +320,14 @@ define i32 @A2_max(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.max(i32 %a, i32 %b) ret i32 %z } -; CHECK: = max({{.*}}, {{.*}}) +; CHECK: = max({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.maxu(i32, i32) define i32 @A2_maxu(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.maxu(i32 %a, i32 %b) ret i32 %z } -; CHECK: = maxu({{.*}}, {{.*}}) +; CHECK: = maxu({{.*}},{{.*}}) ; Maximum doublewords declare i64 @llvm.hexagon.A2.maxp(i64, i64) @@ -335,14 +335,14 @@ define i64 @A2_maxp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.maxp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = max({{.*}}, {{.*}}) +; CHECK: = max({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.maxup(i64, i64) define i64 @A2_maxup(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.maxup(i64 %a, i64 %b) ret i64 %z } -; CHECK: = maxu({{.*}}, {{.*}}) +; CHECK: = maxu({{.*}},{{.*}}) ; Minimum words declare i32 @llvm.hexagon.A2.min(i32, i32) @@ -350,14 +350,14 @@ define i32 @A2_min(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.min(i32 %a, i32 %b) ret i32 %z } -; CHECK: = min({{.*}}, {{.*}}) +; CHECK: = min({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.minu(i32, i32) define i32 @A2_minu(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.minu(i32 %a, i32 %b) ret i32 %z } -; CHECK: = minu({{.*}}, {{.*}}) +; CHECK: = minu({{.*}},{{.*}}) ; Minimum doublewords declare i64 @llvm.hexagon.A2.minp(i64, i64) @@ -365,14 +365,14 @@ define i64 @A2_minp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.minp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = min({{.*}}, {{.*}}) +; CHECK: = min({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.minup(i64, i64) define i64 @A2_minup(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.minup(i64 %a, i64 %b) ret i64 %z } -; CHECK: = minu({{.*}}, {{.*}}) +; CHECK: = minu({{.*}},{{.*}}) ; Module wrap declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) @@ -380,7 +380,7 @@ define i32 @A4_modwrapu(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.modwrapu(i32 %a, i32 %b) ret i32 %z } -; CHECK: = modwrap({{.*}}, {{.*}}) +; CHECK: = modwrap({{.*}},{{.*}}) ; Negate declare i64 @llvm.hexagon.A2.negp(i64) @@ -410,42 +410,42 @@ define i32 @A4_cround_ri(i32 %a) { %z = call i32 @llvm.hexagon.A4.cround.ri(i32 %a, i32 0) ret i32 %z } -; CHECK: = cround({{.*}}, #0) +; CHECK: = cround({{.*}},#0) declare i32 @llvm.hexagon.A4.round.ri(i32, i32) define i32 @A4_round_ri(i32 %a) { %z = call i32 @llvm.hexagon.A4.round.ri(i32 %a, i32 0) ret i32 %z } -; CHECK: = round({{.*}}, #0) +; CHECK: = round({{.*}},#0) declare i32 @llvm.hexagon.A4.round.ri.sat(i32, i32) define i32 @A4_round_ri_sat(i32 %a) { %z = call i32 @llvm.hexagon.A4.round.ri.sat(i32 %a, i32 0) ret i32 %z } -; CHECK: = round({{.*}}, #0):sat +; CHECK: = round({{.*}},#0):sat declare i32 @llvm.hexagon.A4.cround.rr(i32, i32) define i32 @A4_cround_rr(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cround.rr(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cround({{.*}}, {{.*}}) +; CHECK: = cround({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.round.rr(i32, i32) define i32 @A4_round_rr(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.round.rr(i32 %a, i32 %b) ret i32 %z } -; CHECK: = round({{.*}}, {{.*}}) +; CHECK: = round({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.round.rr.sat(i32, i32) define i32 @A4_round_rr_sat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.round.rr.sat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = round({{.*}}, {{.*}}):sat +; CHECK: = round({{.*}},{{.*}}):sat ; Subtract doublewords declare i64 @llvm.hexagon.A2.subp(i64, i64) @@ -453,7 +453,7 @@ define i64 @A2_subp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.subp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = sub({{.*}}, {{.*}}) +; CHECK: = sub({{.*}},{{.*}}) ; Subtract and accumulate declare i32 @llvm.hexagon.M2.subacc(i32, i32, i32) @@ -461,7 +461,7 @@ define i32 @M2_subacc(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.subacc(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += sub({{.*}}, {{.*}}) +; CHECK: += sub({{.*}},{{.*}}) ; Subtract halfwords declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32) @@ -469,84 +469,84 @@ define i32 @A2_subh_l16_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.l) +; CHECK: = sub({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32) define i32 @A2_subh_l16_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.h) +; CHECK: = sub({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) define i32 @A2_subh_l16_sat.ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.l):sat +; CHECK: = sub({{.*}}.l,{{.*}}.l):sat declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32) define i32 @A2_subh_l16_sat.hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.h):sat +; CHECK: = sub({{.*}}.l,{{.*}}.h):sat declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32) define i32 @A2_subh_h16_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.l):<<16 +; CHECK: = sub({{.*}}.l,{{.*}}.l):<<16 declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32) define i32 @A2_subh_h16_lh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.h):<<16 +; CHECK: = sub({{.*}}.l,{{.*}}.h):<<16 declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32) define i32 @A2_subh_h16_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.h, {{.*}}.l):<<16 +; CHECK: = sub({{.*}}.h,{{.*}}.l):<<16 declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32) define i32 @A2_subh_h16_hh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.h, {{.*}}.h):<<16 +; CHECK: = sub({{.*}}.h,{{.*}}.h):<<16 declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32) define i32 @A2_subh_h16_sat_ll(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.l):sat:<<16 +; CHECK: = sub({{.*}}.l,{{.*}}.l):sat:<<16 declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32) define i32 @A2_subh_h16_sat_lh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.l, {{.*}}.h):sat:<<16 +; CHECK: = sub({{.*}}.l,{{.*}}.h):sat:<<16 declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32) define i32 @A2_subh_h16_sat_hl(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.h, {{.*}}.l):sat:<<16 +; CHECK: = sub({{.*}}.h,{{.*}}.l):sat:<<16 declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32) define i32 @A2_subh_h16_sat_hh(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %a, i32 %b) ret i32 %z } -; CHECK: = sub({{.*}}.h, {{.*}}.h):sat:<<16 +; CHECK: = sub({{.*}}.h,{{.*}}.h):sat:<<16 ; Sign extend word to doubleword declare i64 @llvm.hexagon.A2.sxtw(i32) @@ -592,7 +592,7 @@ define i64 @M2_vabsdiffh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vabsdiffh({{.*}}, {{.*}}) +; CHECK: = vabsdiffh({{.*}},{{.*}}) ; Vector absolute difference words declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64) @@ -600,7 +600,7 @@ define i64 @M2_vabsdiffw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vabsdiffw({{.*}}, {{.*}}) +; CHECK: = vabsdiffw({{.*}},{{.*}}) ; Vector add halfwords declare i64 @llvm.hexagon.A2.vaddh(i64, i64) @@ -608,21 +608,21 @@ define i64 @A2_vaddh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddh({{.*}}, {{.*}}) +; CHECK: = vaddh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vaddhs(i64, i64) define i64 @A2_vaddhs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddhs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddh({{.*}}, {{.*}}):sat +; CHECK: = vaddh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.A2.vadduhs(i64, i64) define i64 @A2_vadduhs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vadduhs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vadduh({{.*}}, {{.*}}):sat +; CHECK: = vadduh({{.*}},{{.*}}):sat ; Vector add halfwords with saturate and pack to unsigned bytes declare i32 @llvm.hexagon.A5.vaddhubs(i64, i64) @@ -630,7 +630,7 @@ define i32 @A5_vaddhubs(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A5.vaddhubs(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vaddhub({{.*}}, {{.*}}):sat +; CHECK: = vaddhub({{.*}},{{.*}}):sat ; Vector reduce add unsigned bytes declare i64 @llvm.hexagon.A2.vraddub(i64, i64) @@ -638,14 +638,14 @@ define i64 @A2_vraddub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vraddub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vraddub({{.*}}, {{.*}}) +; CHECK: = vraddub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64) define i64 @A2_vraddub_acc(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.A2.vraddub.acc(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vraddub({{.*}}, {{.*}}) +; CHECK: += vraddub({{.*}},{{.*}}) ; Vector reduce add halfwords declare i32 @llvm.hexagon.M2.vradduh(i64, i64) @@ -653,14 +653,14 @@ define i32 @M2_vradduh(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.M2.vradduh(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vradduh({{.*}}, {{.*}}) +; CHECK: = vradduh({{.*}},{{.*}}) declare i32 @llvm.hexagon.M2.vraddh(i64, i64) define i32 @M2_vraddh(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.M2.vraddh(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vraddh({{.*}}, {{.*}}) +; CHECK: = vraddh({{.*}},{{.*}}) ; Vector add bytes declare i64 @llvm.hexagon.A2.vaddub(i64, i64) @@ -668,14 +668,14 @@ define i64 @A2_vaddub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddub({{.*}}, {{.*}}) +; CHECK: = vaddub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vaddubs(i64, i64) define i64 @A2_vaddubs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddubs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddub({{.*}}, {{.*}}):sat +; CHECK: = vaddub({{.*}},{{.*}}):sat ; Vector add words declare i64 @llvm.hexagon.A2.vaddw(i64, i64) @@ -683,14 +683,14 @@ define i64 @A2_vaddw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddw({{.*}}, {{.*}}) +; CHECK: = vaddw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vaddws(i64, i64) define i64 @A2_vaddws(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vaddws(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vaddw({{.*}}, {{.*}}):sat +; CHECK: = vaddw({{.*}},{{.*}}):sat ; Vector average halfwords declare i64 @llvm.hexagon.A2.vavgh(i64, i64) @@ -698,56 +698,56 @@ define i64 @A2_vavgh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgh({{.*}}, {{.*}}) +; CHECK: = vavgh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vavghr(i64, i64) define i64 @A2_vavghr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavghr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgh({{.*}}, {{.*}}):rnd +; CHECK: = vavgh({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vavghcr(i64, i64) define i64 @A2_vavghcr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavghcr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgh({{.*}}, {{.*}}):crnd +; CHECK: = vavgh({{.*}},{{.*}}):crnd declare i64 @llvm.hexagon.A2.vavguh(i64, i64) define i64 @A2_vavguh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavguh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavguh({{.*}}, {{.*}}) +; CHECK: = vavguh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vavguhr(i64, i64) define i64 @A2_vavguhr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavguhr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavguh({{.*}}, {{.*}}):rnd +; CHECK: = vavguh({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vnavgh(i64, i64) define i64 @A2_vnavgh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavgh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgh({{.*}}, {{.*}}) +; CHECK: = vnavgh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vnavghr(i64, i64) define i64 @A2_vnavghr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavghr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgh({{.*}}, {{.*}}):rnd +; CHECK: = vnavgh({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vnavghcr(i64, i64) define i64 @A2_vnavghcr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavghcr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgh({{.*}}, {{.*}}):crnd +; CHECK: = vnavgh({{.*}},{{.*}}):crnd ; Vector average unsigned bytes declare i64 @llvm.hexagon.A2.vavgub(i64, i64) @@ -755,14 +755,14 @@ define i64 @A2_vavgub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgub(i64 %a, i64 %b) ret i64 %z } -; CHECK: vavgub({{.*}}, {{.*}}) +; CHECK: vavgub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vavgubr(i64, i64) define i64 @A2_vavgubr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgubr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgub({{.*}}, {{.*}}):rnd +; CHECK: = vavgub({{.*}},{{.*}}):rnd ; Vector average words declare i64 @llvm.hexagon.A2.vavgw(i64, i64) @@ -770,56 +770,56 @@ define i64 @A2_vavgw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgw({{.*}}, {{.*}}) +; CHECK: = vavgw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vavgwr(i64, i64) define i64 @A2_vavgwr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgwr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgw({{.*}}, {{.*}}):rnd +; CHECK: = vavgw({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vavgwcr(i64, i64) define i64 @A2_vavgwcr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavgwcr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavgw({{.*}}, {{.*}}):crnd +; CHECK: = vavgw({{.*}},{{.*}}):crnd declare i64 @llvm.hexagon.A2.vavguw(i64, i64) define i64 @A2_vavguw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavguw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavguw({{.*}}, {{.*}}) +; CHECK: = vavguw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vavguwr(i64, i64) define i64 @A2_vavguwr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vavguwr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vavguw({{.*}}, {{.*}}):rnd +; CHECK: = vavguw({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vnavgw(i64, i64) define i64 @A2_vnavgw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavgw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgw({{.*}}, {{.*}}) +; CHECK: = vnavgw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vnavgwr(i64, i64) define i64 @A2_vnavgwr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavgwr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgw({{.*}}, {{.*}}):rnd +; CHECK: = vnavgw({{.*}},{{.*}}):rnd declare i64 @llvm.hexagon.A2.vnavgwcr(i64, i64) define i64 @A2_vnavgwcr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vnavgwcr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vnavgw({{.*}}, {{.*}}):crnd +; CHECK: = vnavgw({{.*}},{{.*}}):crnd ; Vector conditional negate declare i64 @llvm.hexagon.S2.vcnegh(i64, i32) @@ -827,14 +827,14 @@ define i64 @S2_vcnegh(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.vcnegh(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vcnegh({{.*}}, {{.*}}) +; CHECK: = vcnegh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.vrcnegh(i64, i64, i32) define i64 @S2_vrcnegh(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.vrcnegh(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: += vrcnegh({{.*}}, {{.*}}) +; CHECK: += vrcnegh({{.*}},{{.*}}) ; Vector maximum bytes declare i64 @llvm.hexagon.A2.vmaxub(i64, i64) @@ -842,14 +842,14 @@ define i64 @A2_vmaxub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vmaxub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmaxub({{.*}}, {{.*}}) +; CHECK: = vmaxub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vmaxb(i64, i64) define i64 @A2_vmaxb(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vmaxb(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmaxb({{.*}}, {{.*}}) +; CHECK: = vmaxb({{.*}},{{.*}}) ; Vector maximum halfwords declare i64 @llvm.hexagon.A2.vmaxh(i64, i64) @@ -857,14 +857,14 @@ define i64 @A2_vmaxh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vmaxh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmaxh({{.*}}, {{.*}}) +; CHECK: = vmaxh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vmaxuh(i64, i64) define i64 @A2_vmaxuh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vmaxuh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmaxuh({{.*}}, {{.*}}) +; CHECK: = vmaxuh({{.*}},{{.*}}) ; Vector reduce maximum halfwords declare i64 @llvm.hexagon.A4.vrmaxh(i64, i64, i32) @@ -872,14 +872,14 @@ define i64 @A4_vrmaxh(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrmaxh(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrmaxh({{.*}}, {{.*}}) +; CHECK: = vrmaxh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.vrmaxuh(i64, i64, i32) define i64 @A4_vrmaxuh(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrmaxuh(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrmaxuh({{.*}}, {{.*}}) +; CHECK: = vrmaxuh({{.*}},{{.*}}) ; Vector reduce maximum words declare i64 @llvm.hexagon.A4.vrmaxw(i64, i64, i32) @@ -887,14 +887,14 @@ define i64 @A4_vrmaxw(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrmaxw(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrmaxw({{.*}}, {{.*}}) +; CHECK: = vrmaxw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.vrmaxuw(i64, i64, i32) define i64 @A4_vrmaxuw(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrmaxuw(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: vrmaxuw({{.*}}, {{.*}}) +; CHECK: vrmaxuw({{.*}},{{.*}}) ; Vector minimum bytes declare i64 @llvm.hexagon.A2.vminub(i64, i64) @@ -902,14 +902,14 @@ define i64 @A2_vminub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vminub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vminub({{.*}}, {{.*}}) +; CHECK: = vminub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vminb(i64, i64) define i64 @A2_vminb(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vminb(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vminb({{.*}}, {{.*}}) +; CHECK: = vminb({{.*}},{{.*}}) ; Vector minimum halfwords declare i64 @llvm.hexagon.A2.vminh(i64, i64) @@ -917,14 +917,14 @@ define i64 @A2_vminh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vminh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vminh({{.*}}, {{.*}}) +; CHECK: = vminh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vminuh(i64, i64) define i64 @A2_vminuh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vminuh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vminuh({{.*}}, {{.*}}) +; CHECK: = vminuh({{.*}},{{.*}}) ; Vector reduce minimum halfwords declare i64 @llvm.hexagon.A4.vrminh(i64, i64, i32) @@ -932,14 +932,14 @@ define i64 @A4_vrminh(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrminh(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrminh({{.*}}, {{.*}}) +; CHECK: = vrminh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.vrminuh(i64, i64, i32) define i64 @A4_vrminuh(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrminuh(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrminuh({{.*}}, {{.*}}) +; CHECK: = vrminuh({{.*}},{{.*}}) ; Vector reduce minimum words declare i64 @llvm.hexagon.A4.vrminw(i64, i64, i32) @@ -947,14 +947,14 @@ define i64 @A4_vrminw(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrminw(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrminw({{.*}}, {{.*}}) +; CHECK: = vrminw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A4.vrminuw(i64, i64, i32) define i64 @A4_vrminuw(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.A4.vrminuw(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vrminuw({{.*}}, {{.*}}) +; CHECK: = vrminuw({{.*}},{{.*}}) ; Vector sum of absolute differences unsigned bytes declare i64 @llvm.hexagon.A2.vrsadub(i64, i64) @@ -962,14 +962,14 @@ define i64 @A2_vrsadub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vrsadub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrsadub({{.*}}, {{.*}}) +; CHECK: = vrsadub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64) define i64 @A2_vrsadub_acc(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrsadub({{.*}}, {{.*}}) +; CHECK: += vrsadub({{.*}},{{.*}}) ; Vector subtract halfwords declare i64 @llvm.hexagon.A2.vsubh(i64, i64) @@ -977,21 +977,21 @@ define i64 @A2_vsubh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubh({{.*}}, {{.*}}) +; CHECK: = vsubh({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) define i64 @A2_vsubhs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubhs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubh({{.*}}, {{.*}}):sat +; CHECK: = vsubh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.A2.vsubuhs(i64, i64) define i64 @A2_vsubuhs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubuhs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubuh({{.*}}, {{.*}}):sat +; CHECK: = vsubuh({{.*}},{{.*}}):sat ; Vector subtract bytes declare i64 @llvm.hexagon.A2.vsubub(i64, i64) @@ -999,14 +999,14 @@ define i64 @A2_vsubub(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubub(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubub({{.*}}, {{.*}}) +; CHECK: = vsubub({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vsububs(i64, i64) define i64 @A2_vsububs(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsububs(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubub({{.*}}, {{.*}}):sat +; CHECK: = vsubub({{.*}},{{.*}}):sat ; Vector subtract words declare i64 @llvm.hexagon.A2.vsubw(i64, i64) @@ -1014,11 +1014,11 @@ define i64 @A2_vsubw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubw({{.*}}, {{.*}}) +; CHECK: = vsubw({{.*}},{{.*}}) declare i64 @llvm.hexagon.A2.vsubws(i64, i64) define i64 @A2_vsubws(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.A2.vsubws(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vsubw({{.*}}, {{.*}}):sat +; CHECK: = vsubw({{.*}},{{.*}}):sat diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll b/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll index e8f83d01820..ec7613e3ef2 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_bit.ll @@ -38,14 +38,14 @@ define i32 @S4_clbpaddi(i64 %a) { %z = call i32 @llvm.hexagon.S4.clbpaddi(i64 %a, i32 0) ret i32 %z } -; CHECK: = add(clb({{.*}}), #0) +; CHECK: = add(clb({{.*}}),#0) declare i32 @llvm.hexagon.S4.clbaddi(i32, i32) define i32 @S4_clbaddi(i32 %a) { %z = call i32 @llvm.hexagon.S4.clbaddi(i32 %a, i32 0) ret i32 %z } -; CHECK: = add(clb({{.*}}), #0) +; CHECK: = add(clb({{.*}}),#0) declare i32 @llvm.hexagon.S2.cl0(i32) define i32 @S2_cl0(i32 %a) { @@ -111,56 +111,56 @@ define i64 @S2_extractup(i64 %a) { %z = call i64 @llvm.hexagon.S2.extractup(i64 %a, i32 0, i32 0) ret i64 %z } -; CHECK: = extractu({{.*}}, #0, #0) +; CHECK: = extractu({{.*}},#0,#0) declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32) define i64 @S2_extractp(i64 %a) { %z = call i64 @llvm.hexagon.S4.extractp(i64 %a, i32 0, i32 0) ret i64 %z } -; CHECK: = extract({{.*}}, #0, #0) +; CHECK: = extract({{.*}},#0,#0) declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32) define i32 @S2_extractu(i32 %a) { %z = call i32 @llvm.hexagon.S2.extractu(i32 %a, i32 0, i32 0) ret i32 %z } -; CHECK: = extractu({{.*}}, #0, #0) +; CHECK: = extractu({{.*}},#0,#0) declare i32 @llvm.hexagon.S4.extract(i32, i32, i32) define i32 @S2_extract(i32 %a) { %z = call i32 @llvm.hexagon.S4.extract(i32 %a, i32 0, i32 0) ret i32 %z } -; CHECK: = extract({{.*}}, #0, #0) +; CHECK: = extract({{.*}},#0,#0) declare i64 @llvm.hexagon.S2.extractup.rp(i64, i64) define i64 @S2_extractup_rp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.extractup.rp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = extractu({{.*}}, {{.*}}) +; CHECK: = extractu({{.*}},{{.*}}) declare i64 @llvm.hexagon.S4.extractp.rp(i64, i64) define i64 @S4_extractp_rp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.extractp.rp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = extract({{.*}}, {{.*}}) +; CHECK: = extract({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.extractu.rp(i32, i64) define i32 @S2_extractu_rp(i32 %a, i64 %b) { %z = call i32 @llvm.hexagon.S2.extractu.rp(i32 %a, i64 %b) ret i32 %z } -; CHECK: = extractu({{.*}}, {{.*}}) +; CHECK: = extractu({{.*}},{{.*}}) declare i32 @llvm.hexagon.S4.extract.rp(i32, i64) define i32 @S4_extract_rp(i32 %a, i64 %b) { %z = call i32 @llvm.hexagon.S4.extract.rp(i32 %a, i64 %b) ret i32 %z } -; CHECK: = extract({{.*}}, {{.*}}) +; CHECK: = extract({{.*}},{{.*}}) ; Insert bitfield declare i64 @llvm.hexagon.S2.insertp(i64, i64, i32, i32) @@ -168,28 +168,28 @@ define i64 @S2_insertp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.insertp(i64 %a, i64 %b, i32 0, i32 0) ret i64 %z } -; CHECK: = insert({{.*}}, #0, #0) +; CHECK: = insert({{.*}},#0,#0) declare i32 @llvm.hexagon.S2.insert(i32, i32, i32, i32) define i32 @S2_insert(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.insert(i32 %a, i32 %b, i32 0, i32 0) ret i32 %z } -; CHECK: = insert({{.*}}, #0, #0) +; CHECK: = insert({{.*}},#0,#0) declare i32 @llvm.hexagon.S2.insert.rp(i32, i32, i64) define i32 @S2_insert_rp(i32 %a, i32 %b, i64 %c) { %z = call i32 @llvm.hexagon.S2.insert.rp(i32 %a, i32 %b, i64 %c) ret i32 %z } -; CHECK: = insert({{.*}}, {{.*}}) +; CHECK: = insert({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.insertp.rp(i64, i64, i64) define i64 @S2_insertp_rp(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.S2.insertp.rp(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: = insert({{.*}}, r5:4) +; CHECK: = insert({{.*}},r5:4) ; Interleave/deinterleave declare i64 @llvm.hexagon.S2.deinterleave(i64) @@ -212,7 +212,7 @@ define i64 @S2_lfsp(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lfsp(i64 %a, i64 %b) ret i64 %z } -; CHECK: = lfs({{.*}}, {{.*}}) +; CHECK: = lfs({{.*}},{{.*}}) ; Masked parity declare i32 @llvm.hexagon.S2.parityp(i64, i64) @@ -220,14 +220,14 @@ define i32 @S2_parityp(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.S2.parityp(i64 %a, i64 %b) ret i32 %z } -; CHECK: = parity({{.*}}, {{.*}}) +; CHECK: = parity({{.*}},{{.*}}) declare i32 @llvm.hexagon.S4.parity(i32, i32) define i32 @S4_parity(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.parity(i32 %a, i32 %b) ret i32 %z } -; CHECK: = parity({{.*}}, {{.*}}) +; CHECK: = parity({{.*}},{{.*}}) ; Bit reverse declare i64 @llvm.hexagon.S2.brevp(i64) @@ -250,42 +250,42 @@ define i32 @S2_setbit_i(i32 %a) { %z = call i32 @llvm.hexagon.S2.setbit.i(i32 %a, i32 0) ret i32 %z } -; CHECK: = setbit({{.*}}, #0) +; CHECK: = setbit({{.*}},#0) declare i32 @llvm.hexagon.S2.clrbit.i(i32, i32) define i32 @S2_clrbit_i(i32 %a) { %z = call i32 @llvm.hexagon.S2.clrbit.i(i32 %a, i32 0) ret i32 %z } -; CHECK: = clrbit({{.*}}, #0) +; CHECK: = clrbit({{.*}},#0) declare i32 @llvm.hexagon.S2.togglebit.i(i32, i32) define i32 @S2_togglebit_i(i32 %a) { %z = call i32 @llvm.hexagon.S2.togglebit.i(i32 %a, i32 0) ret i32 %z } -; CHECK: = togglebit({{.*}}, #0) +; CHECK: = togglebit({{.*}},#0) declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) define i32 @S2_setbit_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.setbit.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = setbit({{.*}}, {{.*}}) +; CHECK: = setbit({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.clrbit.r(i32, i32) define i32 @S2_clrbit_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.clrbit.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = clrbit({{.*}}, {{.*}}) +; CHECK: = clrbit({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.togglebit.r(i32, i32) define i32 @S2_togglebit_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.togglebit.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = togglebit({{.*}}, {{.*}}) +; CHECK: = togglebit({{.*}},{{.*}}) ; Split bitfield declare i64 @llvm.hexagon.A4.bitspliti(i32, i32) @@ -293,14 +293,14 @@ define i64 @A4_bitspliti(i32 %a) { %z = call i64 @llvm.hexagon.A4.bitspliti(i32 %a, i32 0) ret i64 %z } -; CHECK: = bitsplit({{.*}}, #0) +; CHECK: = bitsplit({{.*}},#0) declare i64 @llvm.hexagon.A4.bitsplit(i32, i32) define i64 @A4_bitsplit(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.A4.bitsplit(i32 %a, i32 %b) ret i64 %z } -; CHECK: = bitsplit({{.*}}, {{.*}}) +; CHECK: = bitsplit({{.*}},{{.*}}) ; Table index declare i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32, i32, i32, i32) @@ -308,25 +308,25 @@ define i32 @S2_tableidxb_goodsyntax(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.tableidxb.goodsyntax(i32 %a, i32 %b, i32 0, i32 0) ret i32 %z } -; CHECK: = tableidxb({{.*}}, #0, #0) +; CHECK: = tableidxb({{.*}},#0,#0) declare i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32, i32, i32, i32) define i32 @S2_tableidxh_goodsyntax(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.tableidxh.goodsyntax(i32 %a, i32 %b, i32 0, i32 0) ret i32 %z } -; CHECK: = tableidxh({{.*}}, #0, #-1) +; CHECK: = tableidxh({{.*}},#0,#-1) declare i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32, i32, i32, i32) define i32 @S2_tableidxw_goodsyntax(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.tableidxw.goodsyntax(i32 %a, i32 %b, i32 0, i32 0) ret i32 %z } -; CHECK: = tableidxw({{.*}}, #0, #-2) +; CHECK: = tableidxw({{.*}},#0,#-2) declare i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32, i32, i32, i32) define i32 @S2_tableidxd_goodsyntax(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.tableidxd.goodsyntax(i32 %a, i32 %b, i32 0, i32 0) ret i32 %z } -; CHECK: = tableidxd({{.*}}, #0, #-3) +; CHECK: = tableidxd({{.*}},#0,#-3) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll b/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll index 0087883573e..254b928aa98 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_complex.ll @@ -10,28 +10,28 @@ define i64 @S4_vxaddsubh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxaddsubh({{.*}}, {{.*}}):sat +; CHECK: = vxaddsubh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64) define i64 @S4_vxsubaddh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxsubaddh({{.*}}, {{.*}}):sat +; CHECK: = vxsubaddh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64) define i64 @S4_vxaddsubhr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxaddsubh({{.*}}, {{.*}}):rnd:>>1:sat +; CHECK: = vxaddsubh({{.*}},{{.*}}):rnd:>>1:sat declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64) define i64 @S4_vxsubaddhr(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxsubaddh({{.*}}, {{.*}}):rnd:>>1:sat +; CHECK: = vxsubaddh({{.*}},{{.*}}):rnd:>>1:sat ; Complex add/sub words declare i64 @llvm.hexagon.S4.vxaddsubw(i64, i64) @@ -39,14 +39,14 @@ define i64 @S4_vxaddsubw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxaddsubw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxaddsubw({{.*}}, {{.*}}):sat +; CHECK: = vxaddsubw({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.S4.vxsubaddw(i64, i64) define i64 @S4_vxsubaddw(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S4.vxsubaddw(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vxsubaddw({{.*}}, {{.*}}):sat +; CHECK: = vxsubaddw({{.*}},{{.*}}):sat ; Complex multiply declare i64 @llvm.hexagon.M2.cmpys.s0(i32, i32) @@ -54,84 +54,84 @@ define i64 @M2_cmpys_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpys.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpy({{.*}}, {{.*}}):sat +; CHECK: = cmpy({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.cmpys.s1(i32, i32) define i64 @M2_cmpys_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpys.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpy({{.*}}, {{.*}}):<<1:sat +; CHECK: = cmpy({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.cmpysc.s0(i32, i32) define i64 @M2_cmpysc_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpysc.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpy({{.*}}, {{.*}}*):sat +; CHECK: = cmpy({{.*}},{{.*}}*):sat declare i64 @llvm.hexagon.M2.cmpysc.s1(i32, i32) define i64 @M2_cmpysc_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpysc.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:sat +; CHECK: = cmpy({{.*}},{{.*}}*):<<1:sat declare i64 @llvm.hexagon.M2.cmacs.s0(i64, i32, i32) define i64 @M2_cmacs_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmacs.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpy({{.*}}, {{.*}}):sat +; CHECK: += cmpy({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.cmacs.s1(i64, i32, i32) define i64 @M2_cmacs_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmacs.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpy({{.*}}, {{.*}}):<<1:sat +; CHECK: += cmpy({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.cnacs.s0(i64, i32, i32) define i64 @M2_cnacs_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cnacs.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= cmpy({{.*}}, {{.*}}):sat +; CHECK: -= cmpy({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.cnacs.s1(i64, i32, i32) define i64 @M2_cnacs_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cnacs.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= cmpy({{.*}}, {{.*}}):<<1:sat +; CHECK: -= cmpy({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.cmacsc.s0(i64, i32, i32) define i64 @M2_cmacsc_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmacsc.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpy({{.*}}, {{.*}}*):sat +; CHECK: += cmpy({{.*}},{{.*}}*):sat declare i64 @llvm.hexagon.M2.cmacsc.s1(i64, i32, i32) define i64 @M2_cmacsc_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmacsc.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpy({{.*}}, {{.*}}*):<<1:sat +; CHECK: += cmpy({{.*}},{{.*}}*):<<1:sat declare i64 @llvm.hexagon.M2.cnacsc.s0(i64, i32, i32) define i64 @M2_cnacsc_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cnacsc.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= cmpy({{.*}}, {{.*}}*):sat +; CHECK: -= cmpy({{.*}},{{.*}}*):sat declare i64 @llvm.hexagon.M2.cnacsc.s1(i64, i32, i32) define i64 @M2_cnacsc_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cnacsc.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= cmpy({{.*}}, {{.*}}*):<<1:sat +; CHECK: -= cmpy({{.*}},{{.*}}*):<<1:sat ; Complex multiply real or imaginary declare i64 @llvm.hexagon.M2.cmpyi.s0(i32, i32) @@ -139,28 +139,28 @@ define i64 @M2_cmpyi_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpyi.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpyi({{.*}}, {{.*}}) +; CHECK: = cmpyi({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.cmpyr.s0(i32, i32) define i64 @M2_cmpyr_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.cmpyr.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = cmpyr({{.*}}, {{.*}}) +; CHECK: = cmpyr({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.cmaci.s0(i64, i32, i32) define i64 @M2_cmaci_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmaci.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpyi({{.*}}, {{.*}}) +; CHECK: += cmpyi({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.cmacr.s0(i64, i32, i32) define i64 @M2_cmacr_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.cmacr.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += cmpyr({{.*}}, {{.*}}) +; CHECK: += cmpyr({{.*}},{{.*}}) ; Complex multiply with round and pack declare i32 @llvm.hexagon.M2.cmpyrs.s0(i32, i32) @@ -168,28 +168,28 @@ define i32 @M2_cmpyrs_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.cmpyrs.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpy({{.*}}, {{.*}}):rnd:sat +; CHECK: = cmpy({{.*}},{{.*}}):rnd:sat declare i32 @llvm.hexagon.M2.cmpyrs.s1(i32, i32) define i32 @M2_cmpyrs_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.cmpyrs.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpy({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = cmpy({{.*}},{{.*}}):<<1:rnd:sat declare i32 @llvm.hexagon.M2.cmpyrsc.s0(i32, i32) define i32 @M2_cmpyrsc_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.cmpyrsc.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpy({{.*}}, {{.*}}*):rnd:sat +; CHECK: = cmpy({{.*}},{{.*}}*):rnd:sat declare i32 @llvm.hexagon.M2.cmpyrsc.s1(i32, i32) define i32 @M2_cmpyrsc_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.cmpyrsc.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:rnd:sat +; CHECK: = cmpy({{.*}},{{.*}}*):<<1:rnd:sat ; Complex multiply 32x16 declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32) @@ -197,28 +197,28 @@ define i32 @M4_cmpyi_wh(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 %a, i32 %b) ret i32 %z } -; CHECK: = cmpyiwh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = cmpyiwh({{.*}},{{.*}}):<<1:rnd:sat declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) define i32 @M4_cmpyi_whc(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 %a, i32 %b) ret i32 %z } -; CHECK: = cmpyiwh({{.*}}, {{.*}}*):<<1:rnd:sat +; CHECK: = cmpyiwh({{.*}},{{.*}}*):<<1:rnd:sat declare i32 @llvm.hexagon.M4.cmpyr.wh(i64, i32) define i32 @M4_cmpyr_wh(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.cmpyr.wh(i64 %a, i32 %b) ret i32 %z } -; CHECK: = cmpyrwh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = cmpyrwh({{.*}},{{.*}}):<<1:rnd:sat declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) define i32 @M4_cmpyr_whc(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 %a, i32 %b) ret i32 %z } -; CHECK: = cmpyrwh({{.*}}, {{.*}}*):<<1:rnd:sat +; CHECK: = cmpyrwh({{.*}},{{.*}}*):<<1:rnd:sat ; Vector complex multiply real or imaginary declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64, i64) @@ -226,42 +226,42 @@ define i64 @M2_vcmpy_s0_sat_r(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vcmpyr({{.*}}, {{.*}}):sat +; CHECK: = vcmpyr({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64, i64) define i64 @M2_vcmpy_s1_sat_r(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vcmpyr({{.*}}, {{.*}}):<<1:sat +; CHECK: = vcmpyr({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64, i64) define i64 @M2_vcmpy_s0_sat_i(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vcmpyi({{.*}}, {{.*}}):sat +; CHECK: = vcmpyi({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64, i64) define i64 @M2_vcmpy_s1_sat_i(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vcmpyi({{.*}}, {{.*}}):<<1:sat +; CHECK: = vcmpyi({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64, i64, i64) define i64 @M2_vcmac_s0_sat_r(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vcmpyr({{.*}}, r5:4):sat +; CHECK: += vcmpyr({{.*}},r5:4):sat declare i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64, i64, i64) define i64 @M2_vcmac_s0_sat_i(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vcmpyi({{.*}}, r5:4):sat +; CHECK: += vcmpyi({{.*}},r5:4):sat ; Vector complex conjugate declare i64 @llvm.hexagon.A2.vconj(i64) @@ -277,7 +277,7 @@ define i64 @S2_vcrotate(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.vcrotate(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vcrotate({{.*}}, {{.*}}) +; CHECK: = vcrotate({{.*}},{{.*}}) ; Vector reduce complex multiply real or imaginary declare i64 @llvm.hexagon.M2.vrcmpyi.s0(i64, i64) @@ -285,56 +285,56 @@ define i64 @M2_vrcmpyi_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vrcmpyi.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrcmpyi({{.*}}, {{.*}}) +; CHECK: = vrcmpyi({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.vrcmpyr.s0(i64, i64) define i64 @M2_vrcmpyr_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vrcmpyr.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrcmpyr({{.*}}, {{.*}}) +; CHECK: = vrcmpyr({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64, i64) define i64 @M2_vrcmpyi_s0c(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrcmpyi({{.*}}, {{.*}}*) +; CHECK: = vrcmpyi({{.*}},{{.*}}*) declare i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64, i64) define i64 @M2_vrcmpyr_s0c(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrcmpyr({{.*}}, {{.*}}*) +; CHECK: = vrcmpyr({{.*}},{{.*}}*) declare i64 @llvm.hexagon.M2.vrcmaci.s0(i64, i64, i64) define i64 @M2_vrcmaci_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vrcmaci.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrcmpyi({{.*}}, r5:4) +; CHECK: += vrcmpyi({{.*}},r5:4) declare i64 @llvm.hexagon.M2.vrcmacr.s0(i64, i64, i64) define i64 @M2_vrcmacr_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vrcmacr.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrcmpyr({{.*}}, r5:4) +; CHECK: += vrcmpyr({{.*}},r5:4) declare i64 @llvm.hexagon.M2.vrcmaci.s0c(i64, i64, i64) define i64 @M2_vrcmaci_s0c(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vrcmaci.s0c(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrcmpyi({{.*}}, r5:4*) +; CHECK: += vrcmpyi({{.*}},r5:4*) declare i64 @llvm.hexagon.M2.vrcmacr.s0c(i64, i64, i64) define i64 @M2_vrcmacr_s0c(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vrcmacr.s0c(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrcmpyr({{.*}}, r5:4*) +; CHECK: += vrcmpyr({{.*}},r5:4*) ; Vector reduce complex rotate declare i64 @llvm.hexagon.S4.vrcrotate(i64, i32, i32) @@ -342,11 +342,11 @@ define i64 @S4_vrcrotate(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S4.vrcrotate(i64 %a, i32 %b, i32 0) ret i64 %z } -; CHECK: = vrcrotate({{.*}}, {{.*}}, #0) +; CHECK: = vrcrotate({{.*}},{{.*}},#0) declare i64 @llvm.hexagon.S4.vrcrotate.acc(i64, i64, i32, i32) define i64 @S4_vrcrotate_acc(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S4.vrcrotate.acc(i64 %a, i64 %b, i32 %c, i32 0) ret i64 %z } -; CHECK: += vrcrotate({{.*}}, {{.*}}, #0) +; CHECK: += vrcrotate({{.*}},{{.*}},#0) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll index 598d0a83206..ee56e905162 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll @@ -11,7 +11,7 @@ define float @F2_sfadd(float %a, float %b) { %z = call float @llvm.hexagon.F2.sfadd(float %a, float %b) ret float %z } -; CHECK: = sfadd({{.*}}, {{.*}}) +; CHECK: = sfadd({{.*}},{{.*}}) ; Classify floating-point value declare i32 @llvm.hexagon.F2.sfclass(float, i32) @@ -19,14 +19,14 @@ define i32 @F2_sfclass(float %a) { %z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0) ret i32 %z } -; CHECK: = sfclass({{.*}}, #0) +; CHECK: = sfclass({{.*}},#0) declare i32 @llvm.hexagon.F2.dfclass(double, i32) define i32 @F2_dfclass(double %a) { %z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0) ret i32 %z } -; CHECK: = dfclass({{.*}}, #0) +; CHECK: = dfclass({{.*}},#0) ; Compare floating-point value declare i32 @llvm.hexagon.F2.sfcmpge(float, float) @@ -34,56 +34,56 @@ define i32 @F2_sfcmpge(float %a, float %b) { %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b) ret i32 %z } -; CHECK: = sfcmp.ge({{.*}}, {{.*}}) +; CHECK: = sfcmp.ge({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.sfcmpuo(float, float) define i32 @F2_sfcmpuo(float %a, float %b) { %z = call i32 @llvm.hexagon.F2.sfcmpuo(float %a, float %b) ret i32 %z } -; CHECK: = sfcmp.uo({{.*}}, {{.*}}) +; CHECK: = sfcmp.uo({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.sfcmpeq(float, float) define i32 @F2_sfcmpeq(float %a, float %b) { %z = call i32 @llvm.hexagon.F2.sfcmpeq(float %a, float %b) ret i32 %z } -; CHECK: = sfcmp.eq({{.*}}, {{.*}}) +; CHECK: = sfcmp.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.sfcmpgt(float, float) define i32 @F2_sfcmpgt(float %a, float %b) { %z = call i32 @llvm.hexagon.F2.sfcmpgt(float %a, float %b) ret i32 %z } -; CHECK: = sfcmp.gt({{.*}}, {{.*}}) +; CHECK: = sfcmp.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.dfcmpge(double, double) define i32 @F2_dfcmpge(double %a, double %b) { %z = call i32 @llvm.hexagon.F2.dfcmpge(double %a, double %b) ret i32 %z } -; CHECK: = dfcmp.ge({{.*}}, {{.*}}) +; CHECK: = dfcmp.ge({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.dfcmpuo(double, double) define i32 @F2_dfcmpuo(double %a, double %b) { %z = call i32 @llvm.hexagon.F2.dfcmpuo(double %a, double %b) ret i32 %z } -; CHECK: = dfcmp.uo({{.*}}, {{.*}}) +; CHECK: = dfcmp.uo({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.dfcmpeq(double, double) define i32 @F2_dfcmpeq(double %a, double %b) { %z = call i32 @llvm.hexagon.F2.dfcmpeq(double %a, double %b) ret i32 %z } -; CHECK: = dfcmp.eq({{.*}}, {{.*}}) +; CHECK: = dfcmp.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.F2.dfcmpgt(double, double) define i32 @F2_dfcmpgt(double %a, double %b) { %z = call i32 @llvm.hexagon.F2.dfcmpgt(double %a, double %b) ret i32 %z } -; CHECK: = dfcmp.gt({{.*}}, {{.*}}) +; CHECK: = dfcmp.gt({{.*}},{{.*}}) ; Convert floating-point value to other format declare double @llvm.hexagon.F2.conv.sf2df(float) @@ -283,14 +283,14 @@ define float @F2_sffixupn(float %a, float %b) { %z = call float @llvm.hexagon.F2.sffixupn(float %a, float %b) ret float %z } -; CHECK: = sffixupn({{.*}}, {{.*}}) +; CHECK: = sffixupn({{.*}},{{.*}}) declare float @llvm.hexagon.F2.sffixupd(float, float) define float @F2_sffixupd(float %a, float %b) { %z = call float @llvm.hexagon.F2.sffixupd(float %a, float %b) ret float %z } -; CHECK: = sffixupd({{.*}}, {{.*}}) +; CHECK: = sffixupd({{.*}},{{.*}}) ; Floating point fused multiply-add declare float @llvm.hexagon.F2.sffma(float, float, float) @@ -298,14 +298,14 @@ define float @F2_sffma(float %a, float %b, float %c) { %z = call float @llvm.hexagon.F2.sffma(float %a, float %b, float %c) ret float %z } -; CHECK: += sfmpy({{.*}}, {{.*}}) +; CHECK: += sfmpy({{.*}},{{.*}}) declare float @llvm.hexagon.F2.sffms(float, float, float) define float @F2_sffms(float %a, float %b, float %c) { %z = call float @llvm.hexagon.F2.sffms(float %a, float %b, float %c) ret float %z } -; CHECK: -= sfmpy({{.*}}, {{.*}}) +; CHECK: -= sfmpy({{.*}},{{.*}}) ; Floating point fused multiply-add with scaling declare float @llvm.hexagon.F2.sffma.sc(float, float, float, i32) @@ -313,7 +313,7 @@ define float @F2_sffma_sc(float %a, float %b, float %c, i32 %d) { %z = call float @llvm.hexagon.F2.sffma.sc(float %a, float %b, float %c, i32 %d) ret float %z } -; CHECK: += sfmpy({{.*}}, {{.*}}, {{.*}}):scale +; CHECK: += sfmpy({{.*}},{{.*}},{{.*}}):scale ; Floating point fused multiply-add for library routines declare float @llvm.hexagon.F2.sffma.lib(float, float, float) @@ -321,14 +321,14 @@ define float @F2_sffma_lib(float %a, float %b, float %c) { %z = call float @llvm.hexagon.F2.sffma.lib(float %a, float %b, float %c) ret float %z } -; CHECK: += sfmpy({{.*}}, {{.*}}):lib +; CHECK: += sfmpy({{.*}},{{.*}}):lib declare float @llvm.hexagon.F2.sffms.lib(float, float, float) define float @F2_sffms_lib(float %a, float %b, float %c) { %z = call float @llvm.hexagon.F2.sffms.lib(float %a, float %b, float %c) ret float %z } -; CHECK: -= sfmpy({{.*}}, {{.*}}):lib +; CHECK: -= sfmpy({{.*}},{{.*}}):lib ; Create floating-point constant declare float @llvm.hexagon.F2.sfimm.p(i32) @@ -365,7 +365,7 @@ define float @F2_sfmax(float %a, float %b) { %z = call float @llvm.hexagon.F2.sfmax(float %a, float %b) ret float %z } -; CHECK: = sfmax({{.*}}, {{.*}}) +; CHECK: = sfmax({{.*}},{{.*}}) ; Floating point minimum declare float @llvm.hexagon.F2.sfmin(float, float) @@ -373,7 +373,7 @@ define float @F2_sfmin(float %a, float %b) { %z = call float @llvm.hexagon.F2.sfmin(float %a, float %b) ret float %z } -; CHECK: = sfmin({{.*}}, {{.*}}) +; CHECK: = sfmin({{.*}},{{.*}}) ; Floating point multiply declare float @llvm.hexagon.F2.sfmpy(float, float) @@ -381,7 +381,7 @@ define float @F2_sfmpy(float %a, float %b) { %z = call float @llvm.hexagon.F2.sfmpy(float %a, float %b) ret float %z } -; CHECK: = sfmpy({{.*}}, {{.*}}) +; CHECK: = sfmpy({{.*}},{{.*}}) ; Floating point subtraction declare float @llvm.hexagon.F2.sfsub(float, float) @@ -389,4 +389,4 @@ define float @F2_sfsub(float %a, float %b) { %z = call float @llvm.hexagon.F2.sfsub(float %a, float %b) ret float %z } -; CHECK: = sfsub({{.*}}, {{.*}}) +; CHECK: = sfsub({{.*}},{{.*}}) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll b/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll index a1490499fbf..4da4a8a6393 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_mpy.ll @@ -11,35 +11,35 @@ define i32 @M4_mpyrr_addi(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b) ret i32 %z } -; CHECK: = add(#0, mpyi({{.*}}, {{.*}})) +; CHECK: = add(#0,mpyi({{.*}},{{.*}})) declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32) define i32 @M4_mpyri_addi(i32 %a) { %z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = add(#0, mpyi({{.*}}, #0)) +; CHECK: = add(#0,mpyi({{.*}},#0)) declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32) define i32 @M4_mpyri_addr_u2(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b) ret i32 %z } -; CHECK: = add({{.*}}, mpyi(#0, {{.*}})) +; CHECK: = add({{.*}},mpyi(#0,{{.*}})) declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32) define i32 @M4_mpyri_addr(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: = add({{.*}}, mpyi({{.*}}, #0)) +; CHECK: = add({{.*}},mpyi({{.*}},#0)) declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32) define i32 @M4_mpyrr_addr(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.mpyrr.addr(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: = add({{.*}}, mpyi({{.*}}, {{.*}})) +; CHECK: = add({{.*}},mpyi({{.*}},{{.*}})) ; Vector multiply word by signed half (32x16) declare i64 @llvm.hexagon.M2.mmpyl.s0(i64, i64) @@ -47,56 +47,56 @@ define i64 @M2_mmpyl_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyl.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweh({{.*}}, {{.*}}):sat +; CHECK: = vmpyweh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) define i64 @M2_mmpyl_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpyweh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.mmpyh.s0(i64, i64) define i64 @M2_mmpyh_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyh.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywoh({{.*}}, {{.*}}):sat +; CHECK: = vmpywoh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.mmpyh.s1(i64, i64) define i64 @M2_mmpyh_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyh.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpywoh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.mmpyl.rs0(i64, i64) define i64 @M2_mmpyl_rs0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyl.rs0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweh({{.*}}, {{.*}}):rnd:sat +; CHECK: = vmpyweh({{.*}},{{.*}}):rnd:sat declare i64 @llvm.hexagon.M2.mmpyl.rs1(i64, i64) define i64 @M2_mmpyl_rs1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyl.rs1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = vmpyweh({{.*}},{{.*}}):<<1:rnd:sat declare i64 @llvm.hexagon.M2.mmpyh.rs0(i64, i64) define i64 @M2_mmpyh_rs0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyh.rs0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywoh({{.*}}, {{.*}}):rnd:sat +; CHECK: = vmpywoh({{.*}},{{.*}}):rnd:sat declare i64 @llvm.hexagon.M2.mmpyh.rs1(i64, i64) define i64 @M2_mmpyh_rs1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyh.rs1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = vmpywoh({{.*}},{{.*}}):<<1:rnd:sat ; Vector multiply word by unsigned half (32x16) declare i64 @llvm.hexagon.M2.mmpyul.s0(i64, i64) @@ -104,56 +104,56 @@ define i64 @M2_mmpyul_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyul.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweuh({{.*}}, {{.*}}):sat +; CHECK: = vmpyweuh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.mmpyul.s1(i64, i64) define i64 @M2_mmpyul_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyul.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpyweuh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.mmpyuh.s0(i64, i64) define i64 @M2_mmpyuh_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyuh.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywouh({{.*}}, {{.*}}):sat +; CHECK: = vmpywouh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.mmpyuh.s1(i64, i64) define i64 @M2_mmpyuh_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyuh.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywouh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpywouh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.mmpyul.rs0(i64, i64) define i64 @M2_mmpyul_rs0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyul.rs0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweuh({{.*}}, {{.*}}):rnd:sat +; CHECK: = vmpyweuh({{.*}},{{.*}}):rnd:sat declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) define i64 @M2_mmpyul_rs1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = vmpyweuh({{.*}},{{.*}}):<<1:rnd:sat declare i64 @llvm.hexagon.M2.mmpyuh.rs0(i64, i64) define i64 @M2_mmpyuh_rs0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyuh.rs0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywouh({{.*}}, {{.*}}):rnd:sat +; CHECK: = vmpywouh({{.*}},{{.*}}):rnd:sat declare i64 @llvm.hexagon.M2.mmpyuh.rs1(i64, i64) define i64 @M2_mmpyuh_rs1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.mmpyuh.rs1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpywouh({{.*}}, {{.*}}):<<1:rnd:sat +; CHECK: = vmpywouh({{.*}},{{.*}}):<<1:rnd:sat ; Multiply signed halfwords declare i64 @llvm.hexagon.M2.mpyd.ll.s0(i32, i32) @@ -161,616 +161,616 @@ define i64 @M2_mpyd_ll_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.ll.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l) +; CHECK: = mpy({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) define i64 @M2_mpyd_ll_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.lh.s0(i32, i32) define i64 @M2_mpyd_lh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.lh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h) +; CHECK: = mpy({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.lh.s1(i32, i32) define i64 @M2_mpyd_lh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.lh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyd.hl.s0(i32, i32) define i64 @M2_mpyd_hl_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.hl.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l) +; CHECK: = mpy({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.hl.s1(i32, i32) define i64 @M2_mpyd_hl_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.hl.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.hh.s0(i32, i32) define i64 @M2_mpyd_hh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.hh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h) +; CHECK: = mpy({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.hh.s1(i32, i32) define i64 @M2_mpyd_hh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.hh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32, i32) define i64 @M2_mpyd_rnd_ll_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):rnd +; CHECK: = mpy({{.*}}.l,{{.*}}.l):rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32, i32) define i64 @M2_mpyd_rnd_ll_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:rnd +; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32, i32) define i64 @M2_mpyd_rnd_lh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):rnd +; CHECK: = mpy({{.*}}.l,{{.*}}.h):rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32, i32) define i64 @M2_mpyd_rnd_lh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:rnd +; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32, i32) define i64 @M2_mpyd_rnd_hl_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):rnd +; CHECK: = mpy({{.*}}.h,{{.*}}.l):rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32, i32) define i64 @M2_mpyd_rnd_hl_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:rnd +; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32, i32) define i64 @M2_mpyd_rnd_hh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):rnd +; CHECK: = mpy({{.*}}.h,{{.*}}.h):rnd declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32, i32) define i64 @M2_mpyd_rnd_hh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:rnd +; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:rnd declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64, i32, i32) define i64 @M2_mpyd_acc_ll_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l) +; CHECK: += mpy({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64, i32, i32) define i64 @M2_mpyd_acc_ll_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64, i32, i32) define i64 @M2_mpyd_acc_lh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h) +; CHECK: += mpy({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64, i32, i32) define i64 @M2_mpyd_acc_lh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64, i32, i32) define i64 @M2_mpyd_acc_hl_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l) +; CHECK: += mpy({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64, i32, i32) define i64 @M2_mpyd_acc_hl_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64, i32, i32) define i64 @M2_mpyd_acc_hh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h) +; CHECK: += mpy({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64, i32, i32) define i64 @M2_mpyd_acc_hh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64, i32, i32) define i64 @M2_mpyd_nac_ll_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l) +; CHECK: -= mpy({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64, i32, i32) define i64 @M2_mpyd_nac_ll_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64, i32, i32) define i64 @M2_mpyd_nac_lh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h) +; CHECK: -= mpy({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64, i32, i32) define i64 @M2_mpyd_nac_lh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64, i32, i32) define i64 @M2_mpyd_nac_hl_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l) +; CHECK: -= mpy({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64, i32, i32) define i64 @M2_mpyd_nac_hl_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64, i32, i32) define i64 @M2_mpyd_nac_hh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h) +; CHECK: -= mpy({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64, i32, i32) define i64 @M2_mpyd_nac_hh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) define i32 @M2_mpy_ll_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l) +; CHECK: = mpy({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.ll.s1(i32, i32) define i32 @M2_mpy_ll_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.ll.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.lh.s0(i32, i32) define i32 @M2_mpy_lh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.lh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h) +; CHECK: = mpy({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.lh.s1(i32, i32) define i32 @M2_mpy_lh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.lh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.hl.s0(i32, i32) define i32 @M2_mpy_hl_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.hl.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l) +; CHECK: = mpy({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.hl.s1(i32, i32) define i32 @M2_mpy_hl_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.hl.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.hh.s0(i32, i32) define i32 @M2_mpy_hh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.hh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h) +; CHECK: = mpy({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.hh.s1(i32, i32) define i32 @M2_mpy_hh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.hh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32, i32) define i32 @M2_mpy_sat_ll_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):sat +; CHECK: = mpy({{.*}}.l,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) define i32 @M2_mpy_sat_ll_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32, i32) define i32 @M2_mpy_sat_lh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):sat +; CHECK: = mpy({{.*}}.l,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32, i32) define i32 @M2_mpy_sat_lh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32, i32) define i32 @M2_mpy_sat_hl_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):sat +; CHECK: = mpy({{.*}}.h,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32, i32) define i32 @M2_mpy_sat_hl_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32, i32) define i32 @M2_mpy_sat_hh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):sat +; CHECK: = mpy({{.*}}.h,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32, i32) define i32 @M2_mpy_sat_hh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32, i32) define i32 @M2_mpy_sat_rnd_ll_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):rnd:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.l):rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32, i32) define i32 @M2_mpy_sat_rnd_ll_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.l):<<1:rnd:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.l):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32, i32) define i32 @M2_mpy_sat_rnd_lh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):rnd:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.h):rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32, i32) define i32 @M2_mpy_sat_rnd_lh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.l, {{.*}}.h):<<1:rnd:sat +; CHECK: = mpy({{.*}}.l,{{.*}}.h):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32, i32) define i32 @M2_mpy_sat_rnd_hl_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):rnd:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.l):rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32, i32) define i32 @M2_mpy_sat_rnd_hl_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.l):<<1:rnd:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.l):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32, i32) define i32 @M2_mpy_sat_rnd_hh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):rnd:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.h):rnd:sat declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32, i32) define i32 @M2_mpy_sat_rnd_hh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}.h, {{.*}}.h):<<1:rnd:sat +; CHECK: = mpy({{.*}}.h,{{.*}}.h):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32, i32, i32) define i32 @M2_mpy_acc_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l) +; CHECK: += mpy({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32, i32, i32) define i32 @M2_mpy_acc_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32, i32, i32) define i32 @M2_mpy_acc_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h) +; CHECK: += mpy({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32, i32, i32) define i32 @M2_mpy_acc_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32, i32, i32) define i32 @M2_mpy_acc_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l) +; CHECK: += mpy({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32, i32, i32) define i32 @M2_mpy_acc_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32, i32, i32) define i32 @M2_mpy_acc_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h) +; CHECK: += mpy({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32, i32, i32) define i32 @M2_mpy_acc_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) define i32 @M2_mpy_acc_sat_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l):sat +; CHECK: += mpy({{.*}}.l,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) define i32 @M2_mpy_acc_sat_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.l):<<1:sat +; CHECK: += mpy({{.*}}.l,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32, i32, i32) define i32 @M2_mpy_acc_sat_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h):sat +; CHECK: += mpy({{.*}}.l,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32, i32, i32) define i32 @M2_mpy_acc_sat_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.l, {{.*}}.h):<<1:sat +; CHECK: += mpy({{.*}}.l,{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32, i32, i32) define i32 @M2_mpy_acc_sat_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l):sat +; CHECK: += mpy({{.*}}.h,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32, i32, i32) define i32 @M2_mpy_acc_sat_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.l):<<1:sat +; CHECK: += mpy({{.*}}.h,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32, i32, i32) define i32 @M2_mpy_acc_sat_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h):sat +; CHECK: += mpy({{.*}}.h,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32, i32, i32) define i32 @M2_mpy_acc_sat_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.acc.sat.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}.h, {{.*}}.h):<<1:sat +; CHECK: += mpy({{.*}}.h,{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32, i32, i32) define i32 @M2_mpy_nac_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l) +; CHECK: -= mpy({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32, i32, i32) define i32 @M2_mpy_nac_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1 +; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32, i32, i32) define i32 @M2_mpy_nac_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h) +; CHECK: -= mpy({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32, i32, i32) define i32 @M2_mpy_nac_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1 +; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32, i32, i32) define i32 @M2_mpy_nac_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l) +; CHECK: -= mpy({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32, i32, i32) define i32 @M2_mpy_nac_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1 +; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32, i32, i32) define i32 @M2_mpy_nac_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h) +; CHECK: -= mpy({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32, i32, i32) define i32 @M2_mpy_nac_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1 +; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32, i32, i32) define i32 @M2_mpy_nac_sat_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l):sat +; CHECK: -= mpy({{.*}}.l,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32, i32, i32) define i32 @M2_mpy_nac_sat_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.l):<<1:sat +; CHECK: -= mpy({{.*}}.l,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32, i32, i32) define i32 @M2_mpy_nac_sat_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h):sat +; CHECK: -= mpy({{.*}}.l,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32, i32, i32) define i32 @M2_mpy_nac_sat_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.l, {{.*}}.h):<<1:sat +; CHECK: -= mpy({{.*}}.l,{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32, i32, i32) define i32 @M2_mpy_nac_sat_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l):sat +; CHECK: -= mpy({{.*}}.h,{{.*}}.l):sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32, i32, i32) define i32 @M2_mpy_nac_sat_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.l):<<1:sat +; CHECK: -= mpy({{.*}}.h,{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32, i32, i32) define i32 @M2_mpy_nac_sat_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h):sat +; CHECK: -= mpy({{.*}}.h,{{.*}}.h):sat declare i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32, i32, i32) define i32 @M2_mpy_nac_sat_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpy.nac.sat.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}.h, {{.*}}.h):<<1:sat +; CHECK: -= mpy({{.*}}.h,{{.*}}.h):<<1:sat ; Multiply unsigned halfwords declare i64 @llvm.hexagon.M2.mpyud.ll.s0(i32, i32) @@ -778,336 +778,336 @@ define i64 @M2_mpyud_ll_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.ll.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.l) +; CHECK: = mpyu({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.ll.s1(i32, i32) define i64 @M2_mpyud_ll_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.ll.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: = mpyu({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.lh.s0(i32, i32) define i64 @M2_mpyud_lh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.lh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.h) +; CHECK: = mpyu({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.lh.s1(i32, i32) define i64 @M2_mpyud_lh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.lh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: = mpyu({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyud.hl.s0(i32, i32) define i64 @M2_mpyud_hl_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.hl.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.l) +; CHECK: = mpyu({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.hl.s1(i32, i32) define i64 @M2_mpyud_hl_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.hl.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: = mpyu({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.hh.s0(i32, i32) define i64 @M2_mpyud_hh_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.hh.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.h) +; CHECK: = mpyu({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.hh.s1(i32, i32) define i64 @M2_mpyud_hh_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.mpyud.hh.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: = mpyu({{.*}}.h,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64, i32, i32) define i64 @M2_mpyud_acc_ll_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.l) +; CHECK: += mpyu({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64, i32, i32) define i64 @M2_mpyud_acc_ll_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: += mpyu({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64, i32, i32) define i64 @M2_mpyud_acc_lh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.h) +; CHECK: += mpyu({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64, i32, i32) define i64 @M2_mpyud_acc_lh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: += mpyu({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64, i32, i32) define i64 @M2_mpyud_acc_hl_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.l) +; CHECK: += mpyu({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64, i32, i32) define i64 @M2_mpyud_acc_hl_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: += mpyu({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64, i32, i32) define i64 @M2_mpyud_acc_hh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.h) +; CHECK: += mpyu({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64, i32, i32) define i64 @M2_mpyud_acc_hh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: += mpyu({{.*}}.h,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64, i32, i32) define i64 @M2_mpyud_nac_ll_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.l) +; CHECK: -= mpyu({{.*}}.l,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64, i32, i32) define i64 @M2_mpyud_nac_ll_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: -= mpyu({{.*}}.l,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64, i32, i32) define i64 @M2_mpyud_nac_lh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.h) +; CHECK: -= mpyu({{.*}}.l,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64, i32, i32) define i64 @M2_mpyud_nac_lh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: -= mpyu({{.*}}.l,{{.*}}.h):<<1 declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64, i32, i32) define i64 @M2_mpyud_nac_hl_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.l) +; CHECK: -= mpyu({{.*}}.h,{{.*}}.l) declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64, i32, i32) define i64 @M2_mpyud_nac_hl_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: -= mpyu({{.*}}.h,{{.*}}.l):<<1 declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64, i32, i32) define i64 @M2_mpyud_nac_hh_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.h) +; CHECK: -= mpyu({{.*}}.h,{{.*}}.h) declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64, i32, i32) define i64 @M2_mpyud_nac_hh_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: -= mpyu({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.ll.s0(i32, i32) define i32 @M2_mpyu_ll_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.ll.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.l) +; CHECK: = mpyu({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.ll.s1(i32, i32) define i32 @M2_mpyu_ll_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.ll.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: = mpyu({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.lh.s0(i32, i32) define i32 @M2_mpyu_lh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.lh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.h) +; CHECK: = mpyu({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.lh.s1(i32, i32) define i32 @M2_mpyu_lh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.lh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: = mpyu({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.hl.s0(i32, i32) define i32 @M2_mpyu_hl_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.hl.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.l) +; CHECK: = mpyu({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.hl.s1(i32, i32) define i32 @M2_mpyu_hl_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.hl.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: = mpyu({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.hh.s0(i32, i32) define i32 @M2_mpyu_hh_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.hh.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.h) +; CHECK: = mpyu({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.hh.s1(i32, i32) define i32 @M2_mpyu_hh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.hh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: = mpyu({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32, i32, i32) define i32 @M2_mpyu_acc_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.l) +; CHECK: += mpyu({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32, i32, i32) define i32 @M2_mpyu_acc_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: += mpyu({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32, i32, i32) define i32 @M2_mpyu_acc_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.h) +; CHECK: += mpyu({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32, i32, i32) define i32 @M2_mpyu_acc_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: += mpyu({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32, i32, i32) define i32 @M2_mpyu_acc_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.l) +; CHECK: += mpyu({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32, i32, i32) define i32 @M2_mpyu_acc_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: += mpyu({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32, i32, i32) define i32 @M2_mpyu_acc_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.h) +; CHECK: += mpyu({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32, i32, i32) define i32 @M2_mpyu_acc_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.acc.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: += mpyu({{.*}}.h,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) define i32 @M2_mpyu_nac_ll_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.l) +; CHECK: -= mpyu({{.*}}.l,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32, i32, i32) define i32 @M2_mpyu_nac_ll_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.ll.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.l):<<1 +; CHECK: -= mpyu({{.*}}.l,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32, i32, i32) define i32 @M2_mpyu_nac_lh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.h) +; CHECK: -= mpyu({{.*}}.l,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32, i32, i32) define i32 @M2_mpyu_nac_lh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.lh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.l, {{.*}}.h):<<1 +; CHECK: -= mpyu({{.*}}.l,{{.*}}.h):<<1 declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32, i32, i32) define i32 @M2_mpyu_nac_hl_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.l) +; CHECK: -= mpyu({{.*}}.h,{{.*}}.l) declare i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32, i32, i32) define i32 @M2_mpyu_nac_hl_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.hl.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.l):<<1 +; CHECK: -= mpyu({{.*}}.h,{{.*}}.l):<<1 declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32, i32, i32) define i32 @M2_mpyu_nac_hh_s0(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s0(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.h) +; CHECK: -= mpyu({{.*}}.h,{{.*}}.h) declare i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32, i32, i32) define i32 @M2_mpyu_nac_hh_s1(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M2.mpyu.nac.hh.s1(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpyu({{.*}}.h, {{.*}}.h):<<1 +; CHECK: -= mpyu({{.*}}.h,{{.*}}.h):<<1 ; Polynomial multiply words declare i64 @llvm.hexagon.M4.pmpyw(i32, i32) @@ -1115,14 +1115,14 @@ define i64 @M4_pmpyw(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M4.pmpyw(i32 %a, i32 %b) ret i64 %z } -; CHECK: = pmpyw({{.*}}, {{.*}}) +; CHECK: = pmpyw({{.*}},{{.*}}) declare i64 @llvm.hexagon.M4.pmpyw.acc(i64, i32, i32) define i64 @M4_pmpyw_acc(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M4.pmpyw.acc(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: ^= pmpyw({{.*}}, {{.*}}) +; CHECK: ^= pmpyw({{.*}},{{.*}}) ; Vector reduce multiply word by signed half declare i64 @llvm.hexagon.M4.vrmpyoh.s0(i64, i64) @@ -1130,56 +1130,56 @@ define i64 @M4_vrmpyoh_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M4.vrmpyoh.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpywoh({{.*}}, {{.*}}) +; CHECK: = vrmpywoh({{.*}},{{.*}}) declare i64 @llvm.hexagon.M4.vrmpyoh.s1(i64, i64) define i64 @M4_vrmpyoh_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M4.vrmpyoh.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpywoh({{.*}}, {{.*}}):<<1 +; CHECK: = vrmpywoh({{.*}},{{.*}}):<<1 declare i64 @llvm.hexagon.M4.vrmpyeh.s0(i64, i64) define i64 @M4_vrmpyeh_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M4.vrmpyeh.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpyweh({{.*}}, {{.*}}) +; CHECK: = vrmpyweh({{.*}},{{.*}}) declare i64 @llvm.hexagon.M4.vrmpyeh.s1(i64, i64) define i64 @M4_vrmpyeh_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M4.vrmpyeh.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpyweh({{.*}}, {{.*}}):<<1 +; CHECK: = vrmpyweh({{.*}},{{.*}}):<<1 declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64, i64, i64) define i64 @M4_vrmpyoh_acc_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpywoh({{.*}}, r5:4) +; CHECK: += vrmpywoh({{.*}},r5:4) declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64, i64, i64) define i64 @M4_vrmpyoh_acc_s1(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpywoh({{.*}}, r5:4):<<1 +; CHECK: += vrmpywoh({{.*}},r5:4):<<1 declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64, i64, i64) define i64 @M4_vrmpyeh_acc_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpyweh({{.*}}, r5:4) +; CHECK: += vrmpyweh({{.*}},r5:4) declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64, i64, i64) define i64 @M4_vrmpyeh_acc_s1(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpyweh({{.*}}, r5:4):<<1 +; CHECK: += vrmpyweh({{.*}},r5:4):<<1 ; Multiply and use upper result declare i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32, i32) @@ -1187,84 +1187,84 @@ define i32 @M2_dpmpyss_rnd_s0(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.dpmpyss.rnd.s0(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}):rnd +; CHECK: = mpy({{.*}},{{.*}}):rnd declare i32 @llvm.hexagon.M2.mpyu.up(i32, i32) define i32 @M2_mpyu_up(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpyu.up(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpyu({{.*}}, {{.*}}) +; CHECK: = mpyu({{.*}},{{.*}}) declare i32 @llvm.hexagon.M2.mpysu.up(i32, i32) define i32 @M2_mpysu_up(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpysu.up(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpysu({{.*}}, {{.*}}) +; CHECK: = mpysu({{.*}},{{.*}}) declare i32 @llvm.hexagon.M2.hmmpyh.s1(i32, i32) define i32 @M2_hmmpyh_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.hmmpyh.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}.h):<<1:sat +; CHECK: = mpy({{.*}},{{.*}}.h):<<1:sat declare i32 @llvm.hexagon.M2.hmmpyl.s1(i32, i32) define i32 @M2_hmmpyl_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}.l):<<1:sat +; CHECK: = mpy({{.*}},{{.*}}.l):<<1:sat declare i32 @llvm.hexagon.M2.hmmpyh.rs1(i32, i32) define i32 @M2_hmmpyh_rs1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.hmmpyh.rs1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}.h):<<1:rnd:sat +; CHECK: = mpy({{.*}},{{.*}}.h):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32, i32) define i32 @M2_mpy_up_s1_sat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.up.s1.sat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}):<<1:sat +; CHECK: = mpy({{.*}},{{.*}}):<<1:sat declare i32 @llvm.hexagon.M2.hmmpyl.rs1(i32, i32) define i32 @M2_hmmpyl_rs1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.hmmpyl.rs1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}.l):<<1:rnd:sat +; CHECK: = mpy({{.*}},{{.*}}.l):<<1:rnd:sat declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) define i32 @M2_mpy_up(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.up(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}) +; CHECK: = mpy({{.*}},{{.*}}) declare i32 @llvm.hexagon.M2.mpy.up.s1(i32, i32) define i32 @M2_mpy_up_s1(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.M2.mpy.up.s1(i32 %a, i32 %b) ret i32 %z } -; CHECK: = mpy({{.*}}, {{.*}}):<<1 +; CHECK: = mpy({{.*}},{{.*}}):<<1 declare i32 @llvm.hexagon.M4.mac.up.s1.sat(i32, i32, i32) define i32 @M4_mac_up_s1_sat(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.mac.up.s1.sat(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += mpy({{.*}}, {{.*}}):<<1:sat +; CHECK: += mpy({{.*}},{{.*}}):<<1:sat declare i32 @llvm.hexagon.M4.nac.up.s1.sat(i32, i32, i32) define i32 @M4_nac_up_s1_sat(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.M4.nac.up.s1.sat(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= mpy({{.*}}, {{.*}}):<<1:sat +; CHECK: -= mpy({{.*}},{{.*}}):<<1:sat ; Multiply and use full result declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) @@ -1272,42 +1272,42 @@ define i64 @M2_dpmpyss_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpy({{.*}}, {{.*}}) +; CHECK: = mpy({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.dpmpyuu.s0(i32, i32) define i64 @M2_dpmpyuu_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.dpmpyuu.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = mpyu({{.*}}, {{.*}}) +; CHECK: = mpyu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64, i32, i32) define i64 @M2_dpmpyss_acc_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.dpmpyss.acc.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpy({{.*}}, {{.*}}) +; CHECK: += mpy({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64, i32, i32) define i64 @M2_dpmpyss_nac_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.dpmpyss.nac.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpy({{.*}}, {{.*}}) +; CHECK: -= mpy({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64, i32, i32) define i64 @M2_dpmpyuu_acc_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.dpmpyuu.acc.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += mpyu({{.*}}, {{.*}}) +; CHECK: += mpyu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64, i32, i32) define i64 @M2_dpmpyuu_nac_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.dpmpyuu.nac.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: -= mpyu({{.*}}, {{.*}}) +; CHECK: -= mpyu({{.*}},{{.*}}) ; Vector dual multiply declare i64 @llvm.hexagon.M2.vdmpys.s0(i64, i64) @@ -1315,14 +1315,14 @@ define i64 @M2_vdmpys_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vdmpys.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vdmpy({{.*}}, {{.*}}):sat +; CHECK: = vdmpy({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vdmpys.s1(i64, i64) define i64 @M2_vdmpys_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vdmpys.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vdmpy({{.*}}, {{.*}}):<<1:sat +; CHECK: = vdmpy({{.*}},{{.*}}):<<1:sat ; Vector reduce multiply bytes declare i64 @llvm.hexagon.M5.vrmpybuu(i64, i64) @@ -1330,28 +1330,28 @@ define i64 @M5_vrmpybuu(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M5.vrmpybuu(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpybu({{.*}}, {{.*}}) +; CHECK: = vrmpybu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M5.vrmpybsu(i64, i64) define i64 @M5_vrmpybsu(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M5.vrmpybsu(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpybsu({{.*}}, {{.*}}) +; CHECK: = vrmpybsu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M5.vrmacbuu(i64, i64, i64) define i64 @M5_vrmacbuu(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M5.vrmacbuu(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpybu({{.*}}, r5:4) +; CHECK: += vrmpybu({{.*}},r5:4) declare i64 @llvm.hexagon.M5.vrmacbsu(i64, i64, i64) define i64 @M5_vrmacbsu(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M5.vrmacbsu(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpybsu({{.*}}, r5:4) +; CHECK: += vrmpybsu({{.*}},r5:4) ; Vector dual multiply signed by unsigned bytes declare i64 @llvm.hexagon.M5.vdmpybsu(i64, i64) @@ -1359,14 +1359,14 @@ define i64 @M5_vdmpybsu(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M5.vdmpybsu(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vdmpybsu({{.*}}, {{.*}}):sat +; CHECK: = vdmpybsu({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M5.vdmacbsu(i64, i64, i64) define i64 @M5_vdmacbsu(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M5.vdmacbsu(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vdmpybsu({{.*}}, r5:4):sat +; CHECK: += vdmpybsu({{.*}},r5:4):sat ; Vector multiply even halfwords declare i64 @llvm.hexagon.M2.vmpy2es.s0(i64, i64) @@ -1374,35 +1374,35 @@ define i64 @M2_vmpy2es_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2es.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyeh({{.*}}, {{.*}}):sat +; CHECK: = vmpyeh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vmpy2es.s1(i64, i64) define i64 @M2_vmpy2es_s1(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2es.s1(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vmpyeh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpyeh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.vmac2es(i64, i64, i64) define i64 @M2_vmac2es(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vmac2es(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vmpyeh({{.*}}, r5:4) +; CHECK: += vmpyeh({{.*}},r5:4) declare i64 @llvm.hexagon.M2.vmac2es.s0(i64, i64, i64) define i64 @M2_vmac2es_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vmac2es.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vmpyeh({{.*}}, r5:4):sat +; CHECK: += vmpyeh({{.*}},r5:4):sat declare i64 @llvm.hexagon.M2.vmac2es.s1(i64, i64, i64) define i64 @M2_vmac2es_s1(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vmac2es.s1(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vmpyeh({{.*}}, r5:4):<<1:sat +; CHECK: += vmpyeh({{.*}},r5:4):<<1:sat ; Vector multiply halfwords declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) @@ -1410,35 +1410,35 @@ define i64 @M2_vmpy2s_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpyh({{.*}}, {{.*}}):sat +; CHECK: = vmpyh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vmpy2s.s1(i32, i32) define i64 @M2_vmpy2s_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2s.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpyh({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpyh({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.vmac2(i64, i32, i32) define i64 @M2_vmac2(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.vmac2(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpyh({{.*}}, {{.*}}) +; CHECK: += vmpyh({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) define i64 @M2_vmac2s_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpyh({{.*}}, {{.*}}):sat +; CHECK: += vmpyh({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vmac2s.s1(i64, i32, i32) define i64 @M2_vmac2s_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.vmac2s.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpyh({{.*}}, {{.*}}):<<1:sat +; CHECK: += vmpyh({{.*}},{{.*}}):<<1:sat ; Vector multiply halfwords signed by unsigned declare i64 @llvm.hexagon.M2.vmpy2su.s0(i32, i32) @@ -1446,28 +1446,28 @@ define i64 @M2_vmpy2su_s0(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2su.s0(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpyhsu({{.*}}, {{.*}}):sat +; CHECK: = vmpyhsu({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vmpy2su.s1(i32, i32) define i64 @M2_vmpy2su_s1(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M2.vmpy2su.s1(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpyhsu({{.*}}, {{.*}}):<<1:sat +; CHECK: = vmpyhsu({{.*}},{{.*}}):<<1:sat declare i64 @llvm.hexagon.M2.vmac2su.s0(i64, i32, i32) define i64 @M2_vmac2su_s0(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.vmac2su.s0(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpyhsu({{.*}}, {{.*}}):sat +; CHECK: += vmpyhsu({{.*}},{{.*}}):sat declare i64 @llvm.hexagon.M2.vmac2su.s1(i64, i32, i32) define i64 @M2_vmac2su_s1(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M2.vmac2su.s1(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpyhsu({{.*}}, {{.*}}):<<1:sat +; CHECK: += vmpyhsu({{.*}},{{.*}}):<<1:sat ; Vector reduce multiply halfwords declare i64 @llvm.hexagon.M2.vrmpy.s0(i64, i64) @@ -1475,14 +1475,14 @@ define i64 @M2_vrmpy_s0(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.M2.vrmpy.s0(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vrmpyh({{.*}}, {{.*}}) +; CHECK: = vrmpyh({{.*}},{{.*}}) declare i64 @llvm.hexagon.M2.vrmac.s0(i64, i64, i64) define i64 @M2_vrmac_s0(i64 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.M2.vrmac.s0(i64 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: += vrmpyh({{.*}}, r5:4) +; CHECK: += vrmpyh({{.*}},r5:4) ; Vector multiply bytes declare i64 @llvm.hexagon.M5.vmpybsu(i32, i32) @@ -1490,28 +1490,28 @@ define i64 @M2_vmpybsu(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M5.vmpybsu(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpybsu({{.*}}, {{.*}}) +; CHECK: = vmpybsu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M5.vmpybuu(i32, i32) define i64 @M2_vmpybuu(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M5.vmpybuu(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vmpybu({{.*}}, {{.*}}) +; CHECK: = vmpybu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M5.vmacbuu(i64, i32, i32) define i64 @M2_vmacbuu(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M5.vmacbuu(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpybu({{.*}}, {{.*}}) +; CHECK: += vmpybu({{.*}},{{.*}}) declare i64 @llvm.hexagon.M5.vmacbsu(i64, i32, i32) define i64 @M2_vmacbsu(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M5.vmacbsu(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: += vmpybsu({{.*}}, {{.*}}) +; CHECK: += vmpybsu({{.*}},{{.*}}) ; Vector polynomial multiply halfwords declare i64 @llvm.hexagon.M4.vpmpyh(i32, i32) @@ -1519,11 +1519,11 @@ define i64 @M4_vpmpyh(i32 %a, i32 %b) { %z = call i64 @llvm.hexagon.M4.vpmpyh(i32 %a, i32 %b) ret i64 %z } -; CHECK: = vpmpyh({{.*}}, {{.*}}) +; CHECK: = vpmpyh({{.*}},{{.*}}) declare i64 @llvm.hexagon.M4.vpmpyh.acc(i64, i32, i32) define i64 @M4_vpmpyh_acc(i64 %a, i32 %b, i32 %c) { %z = call i64 @llvm.hexagon.M4.vpmpyh.acc(i64 %a, i32 %b, i32 %c) ret i64 %z } -; CHECK: ^= vpmpyh({{.*}}, {{.*}}) +; CHECK: ^= vpmpyh({{.*}},{{.*}}) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll index 3e044e3838d..9260790e33a 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_perm.ll @@ -141,28 +141,28 @@ define i64 @S2_shuffeb(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.shuffeb(i64 %a, i64 %b) ret i64 %z } -; CHECK: = shuffeb({{.*}}, {{.*}}) +; CHECK: = shuffeb({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.shuffob(i64, i64) define i64 @S2_shuffob(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.shuffob(i64 %a, i64 %b) ret i64 %z } -; CHECK: = shuffob({{.*}}, {{.*}}) +; CHECK: = shuffob({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.shuffeh(i64, i64) define i64 @S2_shuffeh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.shuffeh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = shuffeh({{.*}}, {{.*}}) +; CHECK: = shuffeh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.shuffoh(i64, i64) define i64 @S2_shuffoh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.shuffoh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = shuffoh({{.*}}, {{.*}}) +; CHECK: = shuffoh({{.*}},{{.*}}) ; Vector splat bytes declare i32 @llvm.hexagon.S2.vsplatrb(i32) @@ -186,14 +186,14 @@ define i64 @S2_vspliceib(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.vspliceib(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: = vspliceb({{.*}}, {{.*}}, #0) +; CHECK: = vspliceb({{.*}},{{.*}},#0) declare i64 @llvm.hexagon.S2.vsplicerb(i64, i64, i32) define i64 @S2_vsplicerb(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.vsplicerb(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: = vspliceb({{.*}}, {{.*}}, {{.*}}) +; CHECK: = vspliceb({{.*}},{{.*}},{{.*}}) ; Vector sign extend declare i64 @llvm.hexagon.S2.vsxtbh(i32) @@ -230,14 +230,14 @@ define i64 @S2_vtrunowh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.vtrunowh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vtrunowh({{.*}}, {{.*}}) +; CHECK: = vtrunowh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64) define i64 @S2_vtrunewh(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.vtrunewh(i64 %a, i64 %b) ret i64 %z } -; CHECK: = vtrunewh({{.*}}, {{.*}}) +; CHECK: = vtrunewh({{.*}},{{.*}}) ; Vector zero extend declare i64 @llvm.hexagon.S2.vzxtbh(i32) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll index f06339b9a85..506dc88d3c1 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll @@ -10,42 +10,42 @@ define i32 @A4_cmpbgt(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpb.gt({{.*}}, {{.*}}) +; CHECK: = cmpb.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) define i32 @A4_cmpbeq(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpb.eq({{.*}}, {{.*}}) +; CHECK: = cmpb.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) define i32 @A4_cmpbgtu(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmpb.gtu({{.*}}, {{.*}}) +; CHECK: = cmpb.gtu({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) define i32 @A4_cmpbgti(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmpb.gt({{.*}}, #0) +; CHECK: = cmpb.gt({{.*}},#0) declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) define i32 @A4_cmpbeqi(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmpbeqi(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmpb.eq({{.*}}, #0) +; CHECK: = cmpb.eq({{.*}},#0) declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) define i32 @A4_cmpbgtui(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmpbgtui(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmpb.gtu({{.*}}, #0) +; CHECK: = cmpb.gtu({{.*}},#0) ; Compare half declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) @@ -53,42 +53,42 @@ define i32 @A4_cmphgt(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmphgt(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmph.gt({{.*}}, {{.*}}) +; CHECK: = cmph.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) define i32 @A4_cmpheq(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmpheq(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmph.eq({{.*}}, {{.*}}) +; CHECK: = cmph.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) define i32 @A4_cmphgtu(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.cmphgtu(i32 %a, i32 %b) ret i32 %z } -; CHECK: = cmph.gtu({{.*}}, {{.*}}) +; CHECK: = cmph.gtu({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) define i32 @A4_cmphgti(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmphgti(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmph.gt({{.*}}, #0) +; CHECK: = cmph.gt({{.*}},#0) declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) define i32 @A4_cmpheqi(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmpheqi(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmph.eq({{.*}}, #0) +; CHECK: = cmph.eq({{.*}},#0) declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) define i32 @A4_cmphgtui(i32 %a) { %z = call i32 @llvm.hexagon.A4.cmphgtui(i32 %a, i32 0) ret i32 %z } -; CHECK: = cmph.gtu({{.*}}, #0) +; CHECK: = cmph.gtu({{.*}},#0) ; Compare doublewords declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) @@ -96,21 +96,21 @@ define i32 @C2_cmpgtp(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.C2.cmpgtp(i64 %a, i64 %b) ret i32 %z } -; CHECK: = cmp.gt({{.*}}, {{.*}}) +; CHECK: = cmp.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) define i32 @C2_cmpeqp(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.C2.cmpeqp(i64 %a, i64 %b) ret i32 %z } -; CHECK: = cmp.eq({{.*}}, {{.*}}) +; CHECK: = cmp.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) define i32 @C2_cmpgtup(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.C2.cmpgtup(i64 %a, i64 %b) ret i32 %z } -; CHECK: = cmp.gtu({{.*}}, {{.*}}) +; CHECK: = cmp.gtu({{.*}},{{.*}}) ; Compare bitmask declare i32 @llvm.hexagon.C2.bitsclri(i32, i32) @@ -118,42 +118,42 @@ define i32 @C2_bitsclri(i32 %a) { %z = call i32 @llvm.hexagon.C2.bitsclri(i32 %a, i32 0) ret i32 %z } -; CHECK: = bitsclr({{.*}}, #0) +; CHECK: = bitsclr({{.*}},#0) declare i32 @llvm.hexagon.C4.nbitsclri(i32, i32) define i32 @C4_nbitsclri(i32 %a) { %z = call i32 @llvm.hexagon.C4.nbitsclri(i32 %a, i32 0) ret i32 %z } -; CHECK: = !bitsclr({{.*}}, #0) +; CHECK: = !bitsclr({{.*}},#0) declare i32 @llvm.hexagon.C2.bitsset(i32, i32) define i32 @C2_bitsset(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C2.bitsset(i32 %a, i32 %b) ret i32 %z } -; CHECK: = bitsset({{.*}}, {{.*}}) +; CHECK: = bitsset({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.nbitsset(i32, i32) define i32 @C4_nbitsset(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C4.nbitsset(i32 %a, i32 %b) ret i32 %z } -; CHECK: = !bitsset({{.*}}, {{.*}}) +; CHECK: = !bitsset({{.*}},{{.*}}) declare i32 @llvm.hexagon.C2.bitsclr(i32, i32) define i32 @C2_bitsclr(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C2.bitsclr(i32 %a, i32 %b) ret i32 %z } -; CHECK: = bitsclr({{.*}}, {{.*}}) +; CHECK: = bitsclr({{.*}},{{.*}}) declare i32 @llvm.hexagon.C4.nbitsclr(i32, i32) define i32 @C4_nbitsclr(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C4.nbitsclr(i32 %a, i32 %b) ret i32 %z } -; CHECK: = !bitsclr({{.*}}, {{.*}}) +; CHECK: = !bitsclr({{.*}},{{.*}}) ; Mask generate from predicate declare i64 @llvm.hexagon.C2.mask(i32) @@ -169,7 +169,7 @@ define i32 @A4_tlbmatch(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.A4.tlbmatch(i64 %a, i32 %b) ret i32 %z } -; CHECK: = tlbmatch({{.*}}, {{.*}}) +; CHECK: = tlbmatch({{.*}},{{.*}}) ; Test bit declare i32 @llvm.hexagon.S2.tstbit.i(i32, i32) @@ -177,28 +177,28 @@ define i32 @S2_tstbit_i(i32 %a) { %z = call i32 @llvm.hexagon.S2.tstbit.i(i32 %a, i32 0) ret i32 %z } -; CHECK: = tstbit({{.*}}, #0) +; CHECK: = tstbit({{.*}},#0) declare i32 @llvm.hexagon.S4.ntstbit.i(i32, i32) define i32 @S4_ntstbit_i(i32 %a) { %z = call i32 @llvm.hexagon.S4.ntstbit.i(i32 %a, i32 0) ret i32 %z } -; CHECK: = !tstbit({{.*}}, #0) +; CHECK: = !tstbit({{.*}},#0) declare i32 @llvm.hexagon.S2.tstbit.r(i32, i32) define i32 @S2_tstbit_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.tstbit.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = tstbit({{.*}}, {{.*}}) +; CHECK: = tstbit({{.*}},{{.*}}) declare i32 @llvm.hexagon.S4.ntstbit.r(i32, i32) define i32 @S4_ntstbit_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S4.ntstbit.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = !tstbit({{.*}}, {{.*}}) +; CHECK: = !tstbit({{.*}},{{.*}}) ; Vector compare halfwords declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64) @@ -206,42 +206,42 @@ define i32 @A2_vcmpheq(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmph.eq({{.*}}, {{.*}}) +; CHECK: = vcmph.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64) define i32 @A2_vcmphgt(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmph.gt({{.*}}, {{.*}}) +; CHECK: = vcmph.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64) define i32 @A2_vcmphgtu(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmph.gtu({{.*}}, {{.*}}) +; CHECK: = vcmph.gtu({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32) define i32 @A4_vcmpheqi(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmph.eq({{.*}}, #0) +; CHECK: = vcmph.eq({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32) define i32 @A4_vcmphgti(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmph.gt({{.*}}, #0) +; CHECK: = vcmph.gt({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32) define i32 @A4_vcmphgtui(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmph.gtu({{.*}}, #0) +; CHECK: = vcmph.gtu({{.*}},#0) ; Vector compare bytes for any match declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) @@ -249,7 +249,7 @@ define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b) ret i32 %z } -; CHECK: = any8(vcmpb.eq({{.*}}, {{.*}})) +; CHECK: = any8(vcmpb.eq({{.*}},{{.*}})) ; Vector compare bytes declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64) @@ -257,42 +257,42 @@ define i32 @A2_vcmpbeq(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpb.eq({{.*}}, {{.*}}) +; CHECK: = vcmpb.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64) define i32 @A2_vcmpbgtu(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpb.gtu({{.*}}, {{.*}}) +; CHECK: = vcmpb.gtu({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64) define i32 @A4_vcmpbgt(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpb.gt({{.*}}, {{.*}}) +; CHECK: = vcmpb.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32) define i32 @A4_vcmpbeqi(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpb.eq({{.*}}, #0) +; CHECK: = vcmpb.eq({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32) define i32 @A4_vcmpbgti(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpb.gt({{.*}}, #0) +; CHECK: = vcmpb.gt({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32) define i32 @A4_vcmpbgtui(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpb.gtu({{.*}}, #0) +; CHECK: = vcmpb.gtu({{.*}},#0) ; Vector compare words declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64) @@ -300,42 +300,42 @@ define i32 @A2_vcmpweq(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpw.eq({{.*}}, {{.*}}) +; CHECK: = vcmpw.eq({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64) define i32 @A2_vcmpwgt(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpw.gt({{.*}}, {{.*}}) +; CHECK: = vcmpw.gt({{.*}},{{.*}}) declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64) define i32 @A2_vcmpwgtu(i64 %a, i64 %b) { %z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b) ret i32 %z } -; CHECK: = vcmpw.gtu({{.*}}, {{.*}}) +; CHECK: = vcmpw.gtu({{.*}},{{.*}}) declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32) define i32 @A4_vcmpweqi(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpw.eq({{.*}}, #0) +; CHECK: = vcmpw.eq({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32) define i32 @A4_vcmpwgti(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpw.gt({{.*}}, #0) +; CHECK: = vcmpw.gt({{.*}},#0) declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32) define i32 @A4_vcmpwgtui(i64 %a) { %z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0) ret i32 %z } -; CHECK: = vcmpw.gtu({{.*}}, #0) +; CHECK: = vcmpw.gtu({{.*}},#0) ; Viterbi pack even and odd predicate bitsclr declare i32 @llvm.hexagon.C2.vitpack(i32, i32) @@ -343,7 +343,7 @@ define i32 @C2_vitpack(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b) ret i32 %z } -; CHECK: = vitpack({{.*}}, {{.*}}) +; CHECK: = vitpack({{.*}},{{.*}}) ; Vector mux declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) @@ -351,4 +351,4 @@ define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) { %z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c) ret i64 %z } -; CHECK: = vmux({{.*}}, {{.*}}, {{.*}}) +; CHECK: = vmux({{.*}},{{.*}},{{.*}}) diff --git a/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll b/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll index 1a65f44c195..8809baf3551 100644 --- a/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll +++ b/test/CodeGen/Hexagon/intrinsics/xtype_shift.ll @@ -10,42 +10,42 @@ define i64 @S2_asr_i_p(i64 %a) { %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0) ret i64 %z } -; CHECK: = asr({{.*}}, #0) +; CHECK: = asr({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32) define i64 @S2_lsr_i_p(i64 %a) { %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0) ret i64 %z } -; CHECK: = lsr({{.*}}, #0) +; CHECK: = lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32) define i64 @S2_asl_i_p(i64 %a) { %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0) ret i64 %z } -; CHECK: = asl({{.*}}, #0) +; CHECK: = asl({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32) define i32 @S2_asr_i_r(i32 %a) { %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0) ret i32 %z } -; CHECK: = asr({{.*}}, #0) +; CHECK: = asr({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r(i32, i32) define i32 @S2_lsr_i_r(i32 %a) { %z = call i32 @llvm.hexagon.S2.lsr.i.r(i32 %a, i32 0) ret i32 %z } -; CHECK: = lsr({{.*}}, #0) +; CHECK: = lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r(i32, i32) define i32 @S2_asl_i_r(i32 %a) { %z = call i32 @llvm.hexagon.S2.asl.i.r(i32 %a, i32 0) ret i32 %z } -; CHECK: = asl({{.*}}, #0) +; CHECK: = asl({{.*}},#0) ; Shift by immediate and accumulate declare i64 @llvm.hexagon.S2.asr.i.p.nac(i64, i64, i32) @@ -53,84 +53,84 @@ define i64 @S2_asr_i_p_nac(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asr.i.p.nac(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: -= asr({{.*}}, #0) +; CHECK: -= asr({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p.nac(i64, i64, i32) define i64 @S2_lsr_i_p_nac(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lsr.i.p.nac(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: -= lsr({{.*}}, #0) +; CHECK: -= lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p.nac(i64, i64, i32) define i64 @S2_asl_i_p_nac(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asl.i.p.nac(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: -= asl({{.*}}, #0) +; CHECK: -= asl({{.*}},#0) declare i64 @llvm.hexagon.S2.asr.i.p.acc(i64, i64, i32) define i64 @S2_asr_i_p_acc(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asr.i.p.acc(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: += asr({{.*}}, #0) +; CHECK: += asr({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p.acc(i64, i64, i32) define i64 @S2_lsr_i_p_acc(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lsr.i.p.acc(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: += lsr({{.*}}, #0) +; CHECK: += lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p.acc(i64, i64, i32) define i64 @S2_asl_i_p_acc(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asl.i.p.acc(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: += asl({{.*}}, #0) +; CHECK: += asl({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.i.r.nac(i32, i32, i32) define i32 @S2_asr_i_r_nac(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.i.r.nac(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: -= asr({{.*}}, #0) +; CHECK: -= asr({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r.nac(i32, i32, i32) define i32 @S2_lsr_i_r_nac(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.i.r.nac(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: -= lsr({{.*}}, #0) +; CHECK: -= lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r.nac(i32, i32, i32) define i32 @S2_asl_i_r_nac(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.i.r.nac(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: -= asl({{.*}}, #0) +; CHECK: -= asl({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.i.r.acc(i32, i32, i32) define i32 @S2_asr_i_r_acc(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.i.r.acc(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: += asr({{.*}}, #0) +; CHECK: += asr({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r.acc(i32, i32, i32) define i32 @S2_lsr_i_r_acc(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.i.r.acc(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: += lsr({{.*}}, #0) +; CHECK: += lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r.acc(i32, i32, i32) define i32 @S2_asl_i_r_acc(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.i.r.acc(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: += asl({{.*}}, #0) +; CHECK: += asl({{.*}},#0) ; Shift by immediate and add declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32) @@ -138,35 +138,35 @@ define i32 @S4_addi_asl_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.addi.asl.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = add(#0, asl({{.*}}, #0)) +; CHECK: = add(#0,asl({{.*}},#0)) declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32) define i32 @S4_subi_asl_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.subi.asl.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = sub(#0, asl({{.*}}, #0)) +; CHECK: = sub(#0,asl({{.*}},#0)) declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32) define i32 @S4_addi_lsr_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = add(#0, lsr({{.*}}, #0)) +; CHECK: = add(#0,lsr({{.*}},#0)) declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) define i32 @S4_subi_lsr_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = sub(#0, lsr({{.*}}, #0)) +; CHECK: = sub(#0,lsr({{.*}},#0)) declare i32 @llvm.hexagon.S2.addasl.rrri(i32, i32, i32) define i32 @S2_addasl_rrri(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.addasl.rrri(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: = addasl({{.*}}, {{.*}}, #0) +; CHECK: = addasl({{.*}},{{.*}},#0) ; Shift by immediate and logical declare i64 @llvm.hexagon.S2.asr.i.p.and(i64, i64, i32) @@ -174,140 +174,140 @@ define i64 @S2_asr_i_p_and(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asr.i.p.and(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: &= asr({{.*}}, #0) +; CHECK: &= asr({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p.and(i64, i64, i32) define i64 @S2_lsr_i_p_and(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lsr.i.p.and(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: {{.*}} &= lsr({{.*}}, #0) +; CHECK: {{.*}} &= lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p.and(i64, i64, i32) define i64 @S2_asl_i_p_and(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asl.i.p.and(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: &= asl({{.*}}, #0) +; CHECK: &= asl({{.*}},#0) declare i64 @llvm.hexagon.S2.asr.i.p.or(i64, i64, i32) define i64 @S2_asr_i_p_or(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asr.i.p.or(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: |= asr({{.*}}, #0) +; CHECK: |= asr({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p.or(i64, i64, i32) define i64 @S2_lsr_i_p_or(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lsr.i.p.or(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: |= lsr({{.*}}, #0) +; CHECK: |= lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p.or(i64, i64, i32) define i64 @S2_asl_i_p_or(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asl.i.p.or(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: |= asl({{.*}}, #0) +; CHECK: |= asl({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64, i64, i32) define i64 @S2_lsr_i_p_xacc(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.lsr.i.p.xacc(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: ^= lsr({{.*}}, #0) +; CHECK: ^= lsr({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.p.xacc(i64, i64, i32) define i64 @S2_asl_i_p_xacc(i64 %a, i64 %b) { %z = call i64 @llvm.hexagon.S2.asl.i.p.xacc(i64 %a, i64 %b, i32 0) ret i64 %z } -; CHECK: ^= asl({{.*}}, #0) +; CHECK: ^= asl({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.i.r.and(i32, i32, i32) define i32 @S2_asr_i_r_and(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.i.r.and(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: &= asr({{.*}}, #0) +; CHECK: &= asr({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r.and(i32, i32, i32) define i32 @S2_lsr_i_r_and(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.i.r.and(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: &= lsr({{.*}}, #0) +; CHECK: &= lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r.and(i32, i32, i32) define i32 @S2_asl_i_r_and(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.i.r.and(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: &= asl({{.*}}, #0) +; CHECK: &= asl({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.i.r.or(i32, i32, i32) define i32 @S2_asr_i_r_or(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.i.r.or(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: |= asr({{.*}}, #0) +; CHECK: |= asr({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r.or(i32, i32, i32) define i32 @S2_lsr_i_r_or(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.i.r.or(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: |= lsr({{.*}}, #0) +; CHECK: |= lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r.or(i32, i32, i32) define i32 @S2_asl_i_r_or(i32%a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.i.r.or(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: |= asl({{.*}}, #0) +; CHECK: |= asl({{.*}},#0) declare i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32, i32, i32) define i32 @S2_lsr_i_r_xacc(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.i.r.xacc(i32%a, i32 %b, i32 0) ret i32 %z } -; CHECK: ^= lsr({{.*}}, #0) +; CHECK: ^= lsr({{.*}},#0) declare i32 @llvm.hexagon.S2.asl.i.r.xacc(i32, i32, i32) define i32 @S2_asl_i_r_xacc(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.i.r.xacc(i32 %a, i32 %b, i32 0) ret i32 %z } -; CHECK: ^= asl({{.*}}, #0) +; CHECK: ^= asl({{.*}},#0) declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) define i32 @S4_andi_asl_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.andi.asl.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = and(#0, asl({{.*}}, #0)) +; CHECK: = and(#0,asl({{.*}},#0)) declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) define i32 @S4_ori_asl_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.ori.asl.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = or(#0, asl({{.*}}, #0)) +; CHECK: = or(#0,asl({{.*}},#0)) declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32) define i32 @S4_andi_lsr_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = and(#0, lsr({{.*}}, #0)) +; CHECK: = and(#0,lsr({{.*}},#0)) declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32) define i32 @S4_ori_lsr_ri(i32 %a) { %z = call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 0, i32 %a, i32 0) ret i32 %z } -; CHECK: = or(#0, lsr({{.*}}, #0)) +; CHECK: = or(#0,lsr({{.*}},#0)) ; Shift right by immediate with rounding declare i64 @llvm.hexagon.S2.asr.i.p.rnd(i64, i32) @@ -315,14 +315,14 @@ define i64 @S2_asr_i_p_rnd(i64 %a) { %z = call i64 @llvm.hexagon.S2.asr.i.p.rnd(i64 %a, i32 0) ret i64 %z } -; CHECK: = asr({{.*}}, #0):rnd +; CHECK: = asr({{.*}},#0):rnd declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32) define i32 @S2_asr_i_r_rnd(i32 %a) { %z = call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 %a, i32 0) ret i32 %z } -; CHECK: = asr({{.*}}, #0):rnd +; CHECK: = asr({{.*}},#0):rnd ; Shift left by immediate with saturation declare i32 @llvm.hexagon.S2.asl.i.r.sat(i32, i32) @@ -330,7 +330,7 @@ define i32 @S2_asl_i_r_sat(i32 %a) { %z = call i32 @llvm.hexagon.S2.asl.i.r.sat(i32 %a, i32 0) ret i32 %z } -; CHECK: = asl({{.*}}, #0):sat +; CHECK: = asl({{.*}},#0):sat ; Shift by register declare i64 @llvm.hexagon.S2.asr.r.p(i64, i32) @@ -338,63 +338,63 @@ define i64 @S2_asr_r_p(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.asr.r.p(i64 %a, i32 %b) ret i64 %z } -; CHECK: = asr({{.*}}, {{.*}}) +; CHECK: = asr({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.lsr.r.p(i64, i32) define i64 @S2_lsr_r_p(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.lsr.r.p(i64 %a, i32 %b) ret i64 %z } -; CHECK: = lsr({{.*}}, {{.*}}) +; CHECK: = lsr({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) define i64 @S2_asl_r_p(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.asl.r.p(i64 %a, i32 %b) ret i64 %z } -; CHECK: = asl({{.*}}, {{.*}}) +; CHECK: = asl({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.lsl.r.p(i64, i32) define i64 @S2_lsl_r_p(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.lsl.r.p(i64 %a, i32 %b) ret i64 %z } -; CHECK: = lsl({{.*}}, {{.*}}) +; CHECK: = lsl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asr.r.r(i32, i32) define i32 @S2_asr_r_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.r.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = asr({{.*}}, {{.*}}) +; CHECK: = asr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) define i32 @S2_lsr_r_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsr.r.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = lsr({{.*}}, {{.*}}) +; CHECK: = lsr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) define i32 @S2_asl_r_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.r.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = asl({{.*}}, {{.*}}) +; CHECK: = asl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsl.r.r(i32, i32) define i32 @S2_lsl_r_r(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.lsl.r.r(i32 %a, i32 %b) ret i32 %z } -; CHECK: = lsl({{.*}}, {{.*}}) +; CHECK: = lsl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S4.lsli(i32, i32) define i32 @S4_lsli(i32 %a) { %z = call i32 @llvm.hexagon.S4.lsli(i32 0, i32 %a) ret i32 %z } -; CHECK: = lsl(#0, {{.*}}) +; CHECK: = lsl(#0,{{.*}}) ; Shift by register and accumulate declare i64 @llvm.hexagon.S2.asr.r.p.nac(i64, i64, i32) @@ -402,112 +402,112 @@ define i64 @S2_asr_r_p_nac(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asr.r.p.nac(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: -= asr({{.*}}, r4) +; CHECK: -= asr({{.*}},r4) declare i64 @llvm.hexagon.S2.lsr.r.p.nac(i64, i64, i32) define i64 @S2_lsr_r_p_nac(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsr.r.p.nac(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: -= lsr({{.*}}, r4) +; CHECK: -= lsr({{.*}},r4) declare i64 @llvm.hexagon.S2.asl.r.p.nac(i64, i64, i32) define i64 @S2_asl_r_p_nac(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asl.r.p.nac(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: -= asl({{.*}}, r4) +; CHECK: -= asl({{.*}},r4) declare i64 @llvm.hexagon.S2.lsl.r.p.nac(i64, i64, i32) define i64 @S2_lsl_r_p_nac(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsl.r.p.nac(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: -= lsl({{.*}}, r4) +; CHECK: -= lsl({{.*}},r4) declare i64 @llvm.hexagon.S2.asr.r.p.acc(i64, i64, i32) define i64 @S2_asr_r_p_acc(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asr.r.p.acc(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: += asr({{.*}}, r4) +; CHECK: += asr({{.*}},r4) declare i64 @llvm.hexagon.S2.lsr.r.p.acc(i64, i64, i32) define i64 @S2_lsr_r_p_acc(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsr.r.p.acc(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: += lsr({{.*}}, r4) +; CHECK: += lsr({{.*}},r4) declare i64 @llvm.hexagon.S2.asl.r.p.acc(i64, i64, i32) define i64 @S2_asl_r_p_acc(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asl.r.p.acc(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: += asl({{.*}}, r4) +; CHECK: += asl({{.*}},r4) declare i64 @llvm.hexagon.S2.lsl.r.p.acc(i64, i64, i32) define i64 @S2_lsl_r_p_acc(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsl.r.p.acc(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: += lsl({{.*}}, r4) +; CHECK: += lsl({{.*}},r4) declare i32 @llvm.hexagon.S2.asr.r.r.nac(i32, i32, i32) define i32 @S2_asr_r_r_nac(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asr.r.r.nac(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= asr({{.*}}, {{.*}}) +; CHECK: -= asr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsr.r.r.nac(i32, i32, i32) define i32 @S2_lsr_r_r_nac(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsr.r.r.nac(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= lsr({{.*}}, {{.*}}) +; CHECK: -= lsr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asl.r.r.nac(i32, i32, i32) define i32 @S2_asl_r_r_nac(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asl.r.r.nac(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= asl({{.*}}, {{.*}}) +; CHECK: -= asl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsl.r.r.nac(i32, i32, i32) define i32 @S2_lsl_r_r_nac(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsl.r.r.nac(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: -= lsl({{.*}}, {{.*}}) +; CHECK: -= lsl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asr.r.r.acc(i32, i32, i32) define i32 @S2_asr_r_r_acc(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asr.r.r.acc(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += asr({{.*}}, {{.*}}) +; CHECK: += asr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsr.r.r.acc(i32, i32, i32) define i32 @S2_lsr_r_r_acc(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsr.r.r.acc(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += lsr({{.*}}, {{.*}}) +; CHECK: += lsr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asl.r.r.acc(i32, i32, i32) define i32 @S2_asl_r_r_acc(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asl.r.r.acc(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += asl({{.*}}, {{.*}}) +; CHECK: += asl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsl.r.r.acc(i32, i32, i32) define i32 @S2_lsl_r_r_acc(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsl.r.r.acc(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: += lsl({{.*}}, {{.*}}) +; CHECK: += lsl({{.*}},{{.*}}) ; Shift by register and logical declare i64 @llvm.hexagon.S2.asr.r.p.or(i64, i64, i32) @@ -515,112 +515,112 @@ define i64 @S2_asr_r_p_or(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asr.r.p.or(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: |= asr({{.*}}, r4) +; CHECK: |= asr({{.*}},r4) declare i64 @llvm.hexagon.S2.lsr.r.p.or(i64, i64, i32) define i64 @S2_lsr_r_p_or(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsr.r.p.or(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: |= lsr({{.*}}, r4) +; CHECK: |= lsr({{.*}},r4) declare i64 @llvm.hexagon.S2.asl.r.p.or(i64, i64, i32) define i64 @S2_asl_r_p_or(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asl.r.p.or(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: |= asl({{.*}}, r4) +; CHECK: |= asl({{.*}},r4) declare i64 @llvm.hexagon.S2.lsl.r.p.or(i64, i64, i32) define i64 @S2_lsl_r_p_or(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsl.r.p.or(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: |= lsl({{.*}}, r4) +; CHECK: |= lsl({{.*}},r4) declare i64 @llvm.hexagon.S2.asr.r.p.and(i64, i64, i32) define i64 @S2_asr_r_p_and(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asr.r.p.and(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: &= asr({{.*}}, r4) +; CHECK: &= asr({{.*}},r4) declare i64 @llvm.hexagon.S2.lsr.r.p.and(i64, i64, i32) define i64 @S2_lsr_r_p_and(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsr.r.p.and(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: &= lsr({{.*}}, r4) +; CHECK: &= lsr({{.*}},r4) declare i64 @llvm.hexagon.S2.asl.r.p.and(i64, i64, i32) define i64 @S2_asl_r_p_and(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.asl.r.p.and(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: &= asl({{.*}}, r4) +; CHECK: &= asl({{.*}},r4) declare i64 @llvm.hexagon.S2.lsl.r.p.and(i64, i64, i32) define i64 @S2_lsl_r_p_and(i64 %a, i64 %b, i32 %c) { %z = call i64 @llvm.hexagon.S2.lsl.r.p.and(i64 %a, i64 %b, i32 %c) ret i64 %z } -; CHECK: &= lsl({{.*}}, r4) +; CHECK: &= lsl({{.*}},r4) declare i32 @llvm.hexagon.S2.asr.r.r.or(i32, i32, i32) define i32 @S2_asr_r_r_or(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asr.r.r.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= asr({{.*}}, {{.*}}) +; CHECK: |= asr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsr.r.r.or(i32, i32, i32) define i32 @S2_lsr_r_r_or(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsr.r.r.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= lsr({{.*}}, {{.*}}) +; CHECK: |= lsr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asl.r.r.or(i32, i32, i32) define i32 @S2_asl_r_r_or(i32%a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asl.r.r.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= asl({{.*}}, {{.*}}) +; CHECK: |= asl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsl.r.r.or(i32, i32, i32) define i32 @S2_lsl_r_r_or(i32%a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsl.r.r.or(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: |= lsl({{.*}}, {{.*}}) +; CHECK: |= lsl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asr.r.r.and(i32, i32, i32) define i32 @S2_asr_r_r_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asr.r.r.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= asr({{.*}}, {{.*}}) +; CHECK: &= asr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsr.r.r.and(i32, i32, i32) define i32 @S2_lsr_r_r_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsr.r.r.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= lsr({{.*}}, {{.*}}) +; CHECK: &= lsr({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.asl.r.r.and(i32, i32, i32) define i32 @S2_asl_r_r_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.asl.r.r.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= asl({{.*}}, {{.*}}) +; CHECK: &= asl({{.*}},{{.*}}) declare i32 @llvm.hexagon.S2.lsl.r.r.and(i32, i32, i32) define i32 @S2_lsl_r_r_and(i32 %a, i32 %b, i32 %c) { %z = call i32 @llvm.hexagon.S2.lsl.r.r.and(i32 %a, i32 %b, i32 %c) ret i32 %z } -; CHECK: &= lsl({{.*}}, {{.*}}) +; CHECK: &= lsl({{.*}},{{.*}}) ; Shift by register with saturation declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) @@ -628,14 +628,14 @@ define i32 @S2_asr_r_r_sat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = asr({{.*}}, {{.*}}):sat +; CHECK: = asr({{.*}},{{.*}}):sat declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) define i32 @S2_asl_r_r_sat(i32 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %a, i32 %b) ret i32 %z } -; CHECK: = asl({{.*}}, {{.*}}):sat +; CHECK: = asl({{.*}},{{.*}}):sat ; Vector shift halfwords by immediate declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) @@ -643,21 +643,21 @@ define i64 @S2_asr_i_vh(i64 %a) { %z = call i64 @llvm.hexagon.S2.asr.i.vh(i64 %a, i32 0) ret i64 %z } -; CHECK: = vasrh({{.*}}, #0) +; CHECK: = vasrh({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) define i64 @S2_lsr_i_vh(i64 %a) { %z = call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %a, i32 0) ret i64 %z } -; CHECK: = vlsrh({{.*}}, #0) +; CHECK: = vlsrh({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) define i64 @S2_asl_i_vh(i64 %a) { %z = call i64 @llvm.hexagon.S2.asl.i.vh(i64 %a, i32 0) ret i64 %z } -; CHECK: = vaslh({{.*}}, #0) +; CHECK: = vaslh({{.*}},#0) ; Vector shift halfwords by register declare i64 @llvm.hexagon.S2.asr.r.vh(i64, i32) @@ -665,28 +665,28 @@ define i64 @S2_asr_r_vh(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.asr.r.vh(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vasrh({{.*}}, {{.*}}) +; CHECK: = vasrh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.lsr.r.vh(i64, i32) define i64 @S2_lsr_r_vh(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.lsr.r.vh(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vlsrh({{.*}}, {{.*}}) +; CHECK: = vlsrh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.asl.r.vh(i64, i32) define i64 @S2_asl_r_vh(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.asl.r.vh(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vaslh({{.*}}, {{.*}}) +; CHECK: = vaslh({{.*}},{{.*}}) declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32) define i64 @S2_lsl_r_vh(i64 %a, i32 %b) { %z = call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %a, i32 %b) ret i64 %z } -; CHECK: = vlslh({{.*}}, {{.*}}) +; CHECK: = vlslh({{.*}},{{.*}}) ; Vector shift words by immediate declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) @@ -694,21 +694,21 @@ define i64 @S2_asr_i_vw(i64 %a) { %z = call i64 @llvm.hexagon.S2.asr.i.vw(i64 %a, i32 0) ret i64 %z } -; CHECK: = vasrw({{.*}}, #0) +; CHECK: = vasrw({{.*}},#0) declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) define i64 @S2_lsr_i_vw(i64 %a) { %z = call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %a, i32 0) ret i64 %z } -; CHECK: = vlsrw({{.*}}, #0) +; CHECK: = vlsrw({{.*}},#0) declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) define i64 @S2_asl_i_vw(i64 %a) { %z = call i64 @llvm.hexagon.S2.asl.i.vw(i64 %a, i32 0) ret i64 %z } -; CHECK: = vaslw({{.*}}, #0) +; CHECK: = vaslw({{.*}},#0) ; Vector shift words by with truncate and pack declare i32 @llvm.hexagon.S2.asr.i.svw.trun(i64, i32) @@ -716,11 +716,11 @@ define i32 @S2_asr_i_svw_trun(i64 %a) { %z = call i32 @llvm.hexagon.S2.asr.i.svw.trun(i64 %a, i32 0) ret i32 %z } -; CHECK: = vasrw({{.*}}, #0) +; CHECK: = vasrw({{.*}},#0) declare i32 @llvm.hexagon.S2.asr.r.svw.trun(i64, i32) define i32 @S2_asr_r_svw_trun(i64 %a, i32 %b) { %z = call i32 @llvm.hexagon.S2.asr.r.svw.trun(i64 %a, i32 %b) ret i32 %z } -; CHECK: = vasrw({{.*}}, {{.*}}) +; CHECK: = vasrw({{.*}},{{.*}}) diff --git a/test/CodeGen/Hexagon/newvalueSameReg.ll b/test/CodeGen/Hexagon/newvalueSameReg.ll index 0fc4df22eb3..39f32fb2f9d 100644 --- a/test/CodeGen/Hexagon/newvalueSameReg.ll +++ b/test/CodeGen/Hexagon/newvalueSameReg.ll @@ -12,8 +12,8 @@ ; Test that we don't generate a new value compare if the operands are ; the same register. -; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new, [[REG0]]) -; CHECK: cmp.eq([[REG1:(r[0-9]+)]], [[REG1]]) +; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]]) +; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]]) ; Function Attrs: nounwind declare void @fprintf(%struct._Dnk_filet.1* nocapture, i8* nocapture readonly, ...) #1 diff --git a/test/CodeGen/Hexagon/newvaluejump.ll b/test/CodeGen/Hexagon/newvaluejump.ll index 3e1ee179573..e1437f369c8 100644 --- a/test/CodeGen/Hexagon/newvaluejump.ll +++ b/test/CodeGen/Hexagon/newvaluejump.ll @@ -6,7 +6,7 @@ define i32 @foo(i32 %a) nounwind { entry: -; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}} +; CHECK: if (cmp.eq(r{{[0-9]+}}.new,#0)) jump{{.}} %addr1 = alloca i32, align 4 %addr2 = alloca i32, align 4 %0 = load i32, i32* @i, align 4 diff --git a/test/CodeGen/Hexagon/newvaluejump2.ll b/test/CodeGen/Hexagon/newvaluejump2.ll index a812a7d9665..4c897f0830f 100644 --- a/test/CodeGen/Hexagon/newvaluejump2.ll +++ b/test/CodeGen/Hexagon/newvaluejump2.ll @@ -6,7 +6,7 @@ @Reg = common global i32 0, align 4 define i32 @main() nounwind { entry: -; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}} +; CHECK: if (cmp.gt(r{{[0-9]+}},r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}} %Reg2 = alloca i32, align 4 %0 = load i32, i32* %Reg2, align 4 %1 = load i32, i32* @Reg, align 4 diff --git a/test/CodeGen/Hexagon/opt-addr-mode.ll b/test/CodeGen/Hexagon/opt-addr-mode.ll index 7cb437c327c..705cd045ea3 100644 --- a/test/CodeGen/Hexagon/opt-addr-mode.ll +++ b/test/CodeGen/Hexagon/opt-addr-mode.ll @@ -2,10 +2,10 @@ ; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE ; CHECK-NO-AMODE: [[REG0:(r[0-9]+)]] = ##global_2 -; CHECK-NO-AMODE: memw([[REG0]] + {{.*}}<<#2) = +; CHECK-NO-AMODE: memw([[REG0]]+{{.*}}<<#2) = ; CHECK-AMODE: [[REG1:(r[0-9]+)]] = memw(##global_1) -; CHECK-AMODE: memw([[REG1]]<<#2 + ##global_2) = +; CHECK-AMODE: memw([[REG1]]<<#2+##global_2) = @global_1 = external global i32, align 4 @global_2 = external global [128 x i32], align 8 diff --git a/test/CodeGen/Hexagon/opt-fabs.ll b/test/CodeGen/Hexagon/opt-fabs.ll index 2ecbce310ad..9c94f853ba5 100644 --- a/test/CodeGen/Hexagon/opt-fabs.ll +++ b/test/CodeGen/Hexagon/opt-fabs.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=hexagon-unknown-elf -mcpu=hexagonv5 -hexagon-bit=0 < %s | FileCheck %s ; Optimize fabsf to clrbit in V5. -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) define float @my_fabsf(float %x) nounwind { entry: diff --git a/test/CodeGen/Hexagon/opt-fneg.ll b/test/CodeGen/Hexagon/opt-fneg.ll index 97895786586..da496c58801 100644 --- a/test/CodeGen/Hexagon/opt-fneg.ll +++ b/test/CodeGen/Hexagon/opt-fneg.ll @@ -3,7 +3,7 @@ define float @foo(float %x) nounwind { entry: -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31) %x.addr = alloca float, align 4 store float %x, float* %x.addr, align 4 %0 = load float, float* %x.addr, align 4 @@ -13,14 +13,14 @@ entry: define float @bar(float %x) nounwind { entry: -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31) %sub = fsub float -0.000000e+00, %x ret float %sub } define float @baz(float %x) nounwind { entry: -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#31) %conv1 = fmul float %x, -1.000000e+00 ret float %conv1 } diff --git a/test/CodeGen/Hexagon/opt-spill-volatile.ll b/test/CodeGen/Hexagon/opt-spill-volatile.ll index 99dd4646d74..4f50a9a28a3 100644 --- a/test/CodeGen/Hexagon/opt-spill-volatile.ll +++ b/test/CodeGen/Hexagon/opt-spill-volatile.ll @@ -6,7 +6,7 @@ target triple = "hexagon" ; CHECK-LABEL: foo ; CHECK: memw(r29+#4) = -; CHECK: = memw(r29 + #4) +; CHECK: = memw(r29+#4) define i32 @foo(i32 %a) #0 { entry: %x = alloca i32, align 4 diff --git a/test/CodeGen/Hexagon/pic-local.ll b/test/CodeGen/Hexagon/pic-local.ll index 48b0096aa65..6544b3d3216 100644 --- a/test/CodeGen/Hexagon/pic-local.ll +++ b/test/CodeGen/Hexagon/pic-local.ll @@ -9,11 +9,11 @@ define internal void @f2() { } define void()* @get_f1() { - ; CHECK: r0 = add(pc, ##.Lf1@PCREL) + ; CHECK: r0 = add(pc,##.Lf1@PCREL) ret void()* @f1 } define void()* @get_f2() { - ; CHECK: r0 = add(pc, ##f2@PCREL) + ; CHECK: r0 = add(pc,##f2@PCREL) ret void()* @f2 } diff --git a/test/CodeGen/Hexagon/pic-simple.ll b/test/CodeGen/Hexagon/pic-simple.ll index 46d95204f2e..aeb21ef7de1 100644 --- a/test/CodeGen/Hexagon/pic-simple.ll +++ b/test/CodeGen/Hexagon/pic-simple.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=hexagon-- -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s -; CHECK: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_@PCREL) -; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##src@GOT) -; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##dst@GOT) +; CHECK: r{{[0-9]+}} = add({{pc|PC}},##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##src@GOT) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##dst@GOT) @dst = external global i32 @src = external global i32 diff --git a/test/CodeGen/Hexagon/pic-static.ll b/test/CodeGen/Hexagon/pic-static.ll index 66d7734f2cf..95da5f060d7 100644 --- a/test/CodeGen/Hexagon/pic-static.ll +++ b/test/CodeGen/Hexagon/pic-static.ll @@ -1,8 +1,8 @@ ; RUN: llc -mtriple=hexagon-- -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s -; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_@PCREL) -; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##x@PCREL) -; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##bar@GOT) +; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}},##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}},##x@PCREL) +; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+##bar@GOT) @x = internal global i32 9, align 4 @bar = external global i32* diff --git a/test/CodeGen/Hexagon/predicate-logical.ll b/test/CodeGen/Hexagon/predicate-logical.ll index be2bcb03d6a..e3ba4d8643d 100644 --- a/test/CodeGen/Hexagon/predicate-logical.ll +++ b/test/CodeGen/Hexagon/predicate-logical.ll @@ -1,5 +1,5 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s -; CHECK: p{{[0-9]}} = or(p{{[0-9]}}, and(p{{[0-9]}}, p{{[0-9]}})) +; CHECK: p{{[0-9]}} = or(p{{[0-9]}},and(p{{[0-9]}},p{{[0-9]}})) target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/predicate-rcmp.ll b/test/CodeGen/Hexagon/predicate-rcmp.ll index 45daa88d716..78991e0dbe7 100644 --- a/test/CodeGen/Hexagon/predicate-rcmp.ll +++ b/test/CodeGen/Hexagon/predicate-rcmp.ll @@ -1,5 +1,5 @@ ; RUN: llc -O2 -march=hexagon < %s | FileCheck %s -; CHECK: cmp.eq(r{{[0-9]+}}, #0) +; CHECK: cmp.eq(r{{[0-9]+}},#0) ; Check that the result of the builtin is not stored directly, i.e. that ; there is an instruction that converts it to {0,1} from {0,-1}. Right now ; the instruction is "r4 = !cmp.eq(r0, #0)". diff --git a/test/CodeGen/Hexagon/ret-struct-by-val.ll b/test/CodeGen/Hexagon/ret-struct-by-val.ll index 26ed2ff36f7..60a97bcccfc 100644 --- a/test/CodeGen/Hexagon/ret-struct-by-val.ll +++ b/test/CodeGen/Hexagon/ret-struct-by-val.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK: r0 = add(r0, r1) +; CHECK: r0 = add(r0,r1) ; Allow simple structures to be returned by value. diff --git a/test/CodeGen/Hexagon/signed_immediates.ll b/test/CodeGen/Hexagon/signed_immediates.ll index a4766313cc6..ad4aa259660 100644 --- a/test/CodeGen/Hexagon/signed_immediates.ll +++ b/test/CodeGen/Hexagon/signed_immediates.ll @@ -33,7 +33,7 @@ define i64* @foo4(i64* %a, i64 %b) { } ; s6Ext -; CHECK: if (p0.new) memw(r0+#0)=#-1 +; CHECK: if (p0.new) memw(r0+#0) = #-1 define void @foo5(i32* %a, i1 %b) { br i1 %b, label %x, label %y x: @@ -44,7 +44,7 @@ y: } ; s10Ext -; CHECK: p0 = cmp.eq(r0, #-1) +; CHECK: p0 = cmp.eq(r0,#-1) define i1 @foo7(i32 %a) { %b = icmp eq i32 %a, -1 ret i1 %b @@ -96,4 +96,4 @@ y: ; CHECK: r0 = #-2 define i32 @foo13() { ret i32 -2 -}
\ No newline at end of file +} diff --git a/test/CodeGen/Hexagon/stack-align1.ll b/test/CodeGen/Hexagon/stack-align1.ll index 4efa70f5985..aefd16594f0 100644 --- a/test/CodeGen/Hexagon/stack-align1.ll +++ b/test/CodeGen/Hexagon/stack-align1.ll @@ -1,7 +1,7 @@ ; RUN: llc -O0 -march=hexagon < %s | FileCheck %s -; CHECK: and(r29, #-32) -; CHECK-DAG: add(r29, #0) -; CHECK-DAG: add(r29, #28) +; CHECK: and(r29,#-32) +; CHECK-DAG: add(r29,#0) +; CHECK-DAG: add(r29,#28) target triple = "hexagon-unknown-unknown" diff --git a/test/CodeGen/Hexagon/stack-align2.ll b/test/CodeGen/Hexagon/stack-align2.ll index 1bbd5782032..042e4097c56 100644 --- a/test/CodeGen/Hexagon/stack-align2.ll +++ b/test/CodeGen/Hexagon/stack-align2.ll @@ -1,9 +1,9 @@ ; RUN: llc -O0 -march=hexagon < %s | FileCheck %s -; CHECK: and(r29, #-128) -; CHECK-DAG: add(r29, #0) -; CHECK-DAG: add(r29, #64) -; CHECK-DAG: add(r29, #96) -; CHECK-DAG: add(r29, #124) +; CHECK: and(r29,#-128) +; CHECK-DAG: add(r29,#0) +; CHECK-DAG: add(r29,#64) +; CHECK-DAG: add(r29,#96) +; CHECK-DAG: add(r29,#124) target triple = "hexagon-unknown-unknown" diff --git a/test/CodeGen/Hexagon/stack-alloca1.ll b/test/CodeGen/Hexagon/stack-alloca1.ll index 00e9e051aeb..b38b8846d26 100644 --- a/test/CodeGen/Hexagon/stack-alloca1.ll +++ b/test/CodeGen/Hexagon/stack-alloca1.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -march=hexagon < %s | FileCheck %s -; CHECK: sub(r29, r[[REG:[0-9]+]]) +; CHECK: sub(r29,r[[REG:[0-9]+]]) ; CHECK: r29 = r[[REG]] target triple = "hexagon-unknown-unknown" diff --git a/test/CodeGen/Hexagon/stack-alloca2.ll b/test/CodeGen/Hexagon/stack-alloca2.ll index ad5e13166aa..b211be0c0ff 100644 --- a/test/CodeGen/Hexagon/stack-alloca2.ll +++ b/test/CodeGen/Hexagon/stack-alloca2.ll @@ -1,8 +1,8 @@ ; RUN: llc -O0 -march=hexagon < %s | FileCheck %s -; CHECK-DAG: r[[AP:[0-9]+]] = and(r30, #-32) -; CHECK-DAG: r1 = add(r[[AP]], #-32) +; CHECK-DAG: r[[AP:[0-9]+]] = and(r30,#-32) +; CHECK-DAG: r1 = add(r[[AP]],#-32) -; CHECK-DAG: sub(r29, r[[SP:[0-9]+]]) +; CHECK-DAG: sub(r29,r[[SP:[0-9]+]]) ; CHECK-DAG: r29 = r[[SP]] target triple = "hexagon-unknown-unknown" diff --git a/test/CodeGen/Hexagon/store-shift.ll b/test/CodeGen/Hexagon/store-shift.ll index 866930990ba..981071a0181 100644 --- a/test/CodeGen/Hexagon/store-shift.ll +++ b/test/CodeGen/Hexagon/store-shift.ll @@ -1,12 +1,12 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK-DAG: r[[BASE:[0-9]+]] += add -; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2, #5) -; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2, #6) -; CHECK-DAG: memw(r0 + r[[IDX0]]<<#2) = r3 -; CHECK-DAG: memw(r0 + r[[IDX1]]<<#2) = r3 -; CHECK-DAG: memw(r[[BASE]] + r[[IDX0]]<<#2) = r[[IDX0]] -; CHECK-DAG: memw(r[[BASE]] + r[[IDX1]]<<#2) = r[[IDX0]] +; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2,#5) +; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2,#6) +; CHECK-DAG: memw(r0+r[[IDX0]]<<#2) = r3 +; CHECK-DAG: memw(r0+r[[IDX1]]<<#2) = r3 +; CHECK-DAG: memw(r[[BASE]]+r[[IDX0]]<<#2) = r[[IDX0]] +; CHECK-DAG: memw(r[[BASE]]+r[[IDX1]]<<#2) = r[[IDX0]] target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll index 7bc00759303..861f361a2c5 100644 --- a/test/CodeGen/Hexagon/sube.ll +++ b/test/CodeGen/Hexagon/sube.ll @@ -1,13 +1,13 @@ ; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1) -; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#0) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0,#1) +; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}},r{{[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}},r{{[0-9]+}}) define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { entry: diff --git a/test/CodeGen/Hexagon/subi-asl.ll b/test/CodeGen/Hexagon/subi-asl.ll index f0b27e828f5..d7610ceb62a 100644 --- a/test/CodeGen/Hexagon/subi-asl.ll +++ b/test/CodeGen/Hexagon/subi-asl.ll @@ -3,11 +3,11 @@ ; Check if S4_subi_asl_ri is being generated correctly. ; CHECK-LABEL: yes_sub_asl -; CHECK: [[REG1:(r[0-9]+)]] = sub(#0, asl([[REG1]], #1)) +; CHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1)) ; CHECK-LABEL: no_sub_asl -; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}}, #1) -; CHECK: r{{[0-9]+}} = sub([[REG2]], r{{[0-9]+}}) +; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1) +; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}}) %struct.rtx_def = type { i16, i8 } diff --git a/test/CodeGen/Hexagon/swp-const-tc.ll b/test/CodeGen/Hexagon/swp-const-tc.ll index 3113094d2ba..c07d23623eb 100644 --- a/test/CodeGen/Hexagon/swp-const-tc.ll +++ b/test/CodeGen/Hexagon/swp-const-tc.ll @@ -4,7 +4,7 @@ ; of computing a new LC0 value. ; CHECK-LABEL: @test -; CHECK: loop0(.LBB0_1, #998) +; CHECK: loop0(.LBB0_1,#998) define i32 @test(i32* %A, i32* %B, i32 %count) { entry: diff --git a/test/CodeGen/Hexagon/swp-matmul-bitext.ll b/test/CodeGen/Hexagon/swp-matmul-bitext.ll index db5bb96d0bc..9c425ae6a09 100644 --- a/test/CodeGen/Hexagon/swp-matmul-bitext.ll +++ b/test/CodeGen/Hexagon/swp-matmul-bitext.ll @@ -11,7 +11,7 @@ ; CHECK: [[REG0:(r[0-9]+)]] = memh ; CHECK: [[REG1:(r[0-9]+)]] = memh ; CHECK: += mpyi -; CHECK: [[REG2]] = mpyi([[REG0]], [[REG1]]) +; CHECK: [[REG2]] = mpyi([[REG0]],[[REG1]]) ; CHECK: endloop0 %union_h2_sem_t = type { i32 } diff --git a/test/CodeGen/Hexagon/swp-max.ll b/test/CodeGen/Hexagon/swp-max.ll index 038138ff256..26238ea6fb3 100644 --- a/test/CodeGen/Hexagon/swp-max.ll +++ b/test/CodeGen/Hexagon/swp-max.ll @@ -15,8 +15,8 @@ for.body.preheader: ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: [[REG1:(r[0-9]+)]] = max(r{{[0-9]+}}, [[REG1]]) -; CHECK: [[REG0:(r[0-9]+)]] = add([[REG2:(r[0-9]+)]], [[REG0]]) +; CHECK: [[REG1:(r[0-9]+)]] = max(r{{[0-9]+}},[[REG1]]) +; CHECK: [[REG0:(r[0-9]+)]] = add([[REG2:(r[0-9]+)]],[[REG0]]) ; CHECK: [[REG2]] = memw ; CHECK: endloop0 diff --git a/test/CodeGen/Hexagon/swp-multi-loops.ll b/test/CodeGen/Hexagon/swp-multi-loops.ll index 56e8c651100..fc2576af8ac 100644 --- a/test/CodeGen/Hexagon/swp-multi-loops.ll +++ b/test/CodeGen/Hexagon/swp-multi-loops.ll @@ -5,15 +5,15 @@ ; Check if the first loop is pipelined. ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: add(r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK-NEXT: memw(r{{[0-9]+}}{{.*}}++{{.*}}#4) +; CHECK: add(r{{[0-9]+}},r{{[0-9]+}}) +; CHECK-NEXT: memw(r{{[0-9]+}}++#4) ; CHECK-NEXT: endloop0 ; Check if the second loop is pipelined. ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: add(r{{[0-9]+}}, r{{[0-9]+}}) -; CHECK-NEXT: memw(r{{[0-9]+}}{{.*}}++{{.*}}#4) +; CHECK: add(r{{[0-9]+}},r{{[0-9]+}}) +; CHECK-NEXT: memw(r{{[0-9]+}}++#4) ; CHECK-NEXT: endloop0 define i32 @test(i32* %a, i32 %n, i32 %l) { diff --git a/test/CodeGen/Hexagon/swp-stages4.ll b/test/CodeGen/Hexagon/swp-stages4.ll index cdd09845ba5..f58e8320315 100644 --- a/test/CodeGen/Hexagon/swp-stages4.ll +++ b/test/CodeGen/Hexagon/swp-stages4.ll @@ -6,8 +6,8 @@ ; CHECK: = and ; CHECK: = and ; CHECK: = and -; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]], #255) -; CHECK-NOT: [[REG0]] = and([[REG1]], #255) +; CHECK: [[REG0:(r[0-9]+)]] = and([[REG1:(r[0-9]+)]],#255) +; CHECK-NOT: [[REG0]] = and([[REG1]],#255) ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: ; CHECK: [[REG0]] += add diff --git a/test/CodeGen/Hexagon/swp-stages5.ll b/test/CodeGen/Hexagon/swp-stages5.ll index f83aa32ae0a..fdfb2101cd3 100644 --- a/test/CodeGen/Hexagon/swp-stages5.ll +++ b/test/CodeGen/Hexagon/swp-stages5.ll @@ -7,7 +7,7 @@ ; CHECK-DAG: [[REG0:(r[0-9]+)]] = memub(r{{[0-9]+}}++#1) ; CHECK-DAG: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: = and([[REG0]], #255) +; CHECK: = and([[REG0]],#255) ; CHECK: [[REG0]]{{[:0-9]*}} = ; CHECK: endloop diff --git a/test/CodeGen/Hexagon/swp-vmult.ll b/test/CodeGen/Hexagon/swp-vmult.ll index 9018405274c..7c53248f47f 100644 --- a/test/CodeGen/Hexagon/swp-vmult.ll +++ b/test/CodeGen/Hexagon/swp-vmult.ll @@ -2,10 +2,10 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s ; Multiply and accumulate -; CHECK: mpyi([[REG0:r([0-9]+)]], [[REG1:r([0-9]+)]]) -; CHECK-NEXT: add(r{{[0-9]+}}, #4) -; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0) -; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0) +; CHECK: mpyi([[REG0:r([0-9]+)]],[[REG1:r([0-9]+)]]) +; CHECK-NEXT: add(r{{[0-9]+}},#4) +; CHECK-NEXT: [[REG0]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) +; CHECK-NEXT: [[REG1]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) ; CHECK-NEXT: endloop0 define i32 @foo(i32* %a, i32* %b, i32 %n) { diff --git a/test/CodeGen/Hexagon/swp-vsum.ll b/test/CodeGen/Hexagon/swp-vsum.ll index 4756c644709..3561997450d 100644 --- a/test/CodeGen/Hexagon/swp-vsum.ll +++ b/test/CodeGen/Hexagon/swp-vsum.ll @@ -4,9 +4,9 @@ ; Simple vector total. ; CHECK: loop0(.LBB0_[[LOOP:.]], ; CHECK: .LBB0_[[LOOP]]: -; CHECK: add([[REG:r([0-9]+)]], r{{[0-9]+}}) -; CHECK-NEXT: add(r{{[0-9]+}}, #4) -; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}} + r{{[0-9]+}}<<#0) +; CHECK: add([[REG:r([0-9]+)]],r{{[0-9]+}}) +; CHECK-NEXT: add(r{{[0-9]+}},#4) +; CHECK-NEXT: [[REG]] = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#0) ; CHECK-NEXT: endloop0 define i32 @foo(i32* %a, i32 %n) { diff --git a/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll index 08dadeb9aaa..1b11d087832 100644 --- a/test/CodeGen/Hexagon/tail-dup-subreg-map.ll +++ b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll @@ -5,7 +5,7 @@ ; subregisters were dropped by the tail duplicator, resulting in invalid ; COPY instructions being generated. -; CHECK: = extractu(r{{[0-9]+}}, #15, #17) +; CHECK: = extractu(r{{[0-9]+}},#15,#17) target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/tfr-to-combine.ll b/test/CodeGen/Hexagon/tfr-to-combine.ll index 1b82f3e4562..50879ffe582 100644 --- a/test/CodeGen/Hexagon/tfr-to-combine.ll +++ b/test/CodeGen/Hexagon/tfr-to-combine.ll @@ -8,7 +8,7 @@ ; Function Attrs: nounwind define i64 @test1() #0 { -; CHECK: combine(#10, #0) +; CHECK: combine(#10,#0) entry: store i16 0, i16* @a, align 2 store i16 10, i16* @b, align 2 @@ -17,7 +17,7 @@ entry: ; Function Attrs: nounwind define i64 @test2() #0 { -; CHECK: combine(#0, r{{[0-9]+}}) +; CHECK: combine(#0,r{{[0-9]+}}) entry: store i16 0, i16* @a, align 2 %0 = load i16, i16* @c, align 2 @@ -27,7 +27,7 @@ entry: ; Function Attrs: nounwind define i64 @test4() #0 { -; CHECK: combine(#0, #100) +; CHECK: combine(#0,#100) entry: store i16 100, i16* @b, align 2 store i16 0, i16* @a, align 2 diff --git a/test/CodeGen/Hexagon/tls_pic.ll b/test/CodeGen/Hexagon/tls_pic.ll index 190e1d71d39..2c2be0dc384 100644 --- a/test/CodeGen/Hexagon/tls_pic.ll +++ b/test/CodeGen/Hexagon/tls_pic.ll @@ -4,7 +4,7 @@ @src_ie = thread_local(initialexec) global i32 0, align 4 ; CHECK-LABEL: test_initial_exec -; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK-DAG: = add(pc,##_GLOBAL_OFFSET_TABLE_@PCREL) ; CHECK-DAG: = ##src_ie@IEGOT ; CHECK-DAG: = ##dst_ie@IEGOT ; CHECK-NOT: call @@ -22,7 +22,7 @@ entry: ; general-dynamic model. ; CHECK-LABEL: test_dynamic -; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK-DAG: = add(pc,##_GLOBAL_OFFSET_TABLE_@PCREL) ; CHECK-DAG: = ##src_gd@GDGOT ; CHECK-DAG: = ##dst_gd@GDGOT ; CHECK-DAG: call src_gd@GDPLT diff --git a/test/CodeGen/Hexagon/two-crash.ll b/test/CodeGen/Hexagon/two-crash.ll index 0ab02cda8a0..7e79cb3be91 100644 --- a/test/CodeGen/Hexagon/two-crash.ll +++ b/test/CodeGen/Hexagon/two-crash.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; This testcase crashed, because we propagated a reg:sub into a tied use. ; The two-address pass rewrote it in a way that generated incorrect code. -; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #16) +; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}},#16) target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/vaddh.ll b/test/CodeGen/Hexagon/vaddh.ll index 88194b750ad..a4fb33de4ac 100644 --- a/test/CodeGen/Hexagon/vaddh.ll +++ b/test/CodeGen/Hexagon/vaddh.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}}) +; CHECK: vaddh(r{{[0-9]+}},r{{[0-9]+}}) @j = external global i32 @k = external global i32 diff --git a/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll index 70c4aeb4bac..4bba134a40c 100644 --- a/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll +++ b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; This one should generate a combine with two immediates. -; CHECK: combine(#7, #7) +; CHECK: combine(#7,#7) @B = common global [400 x i32] zeroinitializer, align 8 @A = common global [400 x i32] zeroinitializer, align 8 @C = common global [400 x i32] zeroinitializer, align 8 diff --git a/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll index 91b32652400..f49a1e24a1b 100644 --- a/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll +++ b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; Check that store is post-incremented. -; CHECK: memuh(r{{[0-9]+}} + {{ *}}#6{{ *}}) -; CHECK: combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}{{ *}}) +; CHECK: memuh(r{{[0-9]+}}+#6) +; CHECK: combine(r{{[0-9]+}},r{{[0-9]+}}) ; CHECK: vaddh target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/test/CodeGen/Hexagon/vect/vect-shift-imm.ll b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll index 4861181d412..a4d6afa40bc 100644 --- a/test/CodeGen/Hexagon/vect/vect-shift-imm.ll +++ b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll @@ -6,12 +6,12 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH ; ; Make sure that the instructions with immediate operands are generated. -; CHECK-ASLW: vaslw({{.*}}, #9) -; CHECK-ASRW: vasrw({{.*}}, #8) -; CHECK-LSRW: vlsrw({{.*}}, #7) -; CHECK-ASLH: vaslh({{.*}}, #6) -; CHECK-ASRH: vasrh({{.*}}, #5) -; CHECK-LSRH: vlsrh({{.*}}, #4) +; CHECK-ASLW: vaslw({{.*}},#9) +; CHECK-ASRW: vasrw({{.*}},#8) +; CHECK-LSRW: vlsrw({{.*}},#7) +; CHECK-ASLH: vaslh({{.*}},#6) +; CHECK-ASRH: vasrh({{.*}},#5) +; CHECK-LSRH: vlsrh({{.*}},#4) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/vect/vect-vshifts.ll b/test/CodeGen/Hexagon/vect/vect-vshifts.ll index 49ff812601a..9d3cbe6e113 100644 --- a/test/CodeGen/Hexagon/vect/vect-vshifts.ll +++ b/test/CodeGen/Hexagon/vect/vect-vshifts.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Check that store is post-incremented. -; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}}) -; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}},r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}},r{{[0-9]+}}) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/vect/vect-xor.ll b/test/CodeGen/Hexagon/vect/vect-xor.ll index 96719e68341..8864ab5c5cb 100644 --- a/test/CodeGen/Hexagon/vect/vect-xor.ll +++ b/test/CodeGen/Hexagon/vect/vect-xor.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s ; Check that the parsing succeeded. -; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}},r{{[0-9]+:[0-9]+}}) target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt index 26b320ecde0..e75a9982abd 100644 --- a/test/MC/Disassembler/Hexagon/alu32_alu.txt +++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt @@ -3,27 +3,27 @@ # Add 0xf1 0xc3 0x15 0xb0 -# CHECK: r17 = add(r21, #31) +# CHECK: r17 = add(r21,#31) 0x11 0xdf 0x15 0xf3 -# CHECK: r17 = add(r21, r31) +# CHECK: r17 = add(r21,r31) 0x11 0xdf 0x55 0xf6 -# CHECK: r17 = add(r21, r31):sat +# CHECK: r17 = add(r21,r31):sat # And 0xf1 0xc3 0x15 0x76 -# CHECK: r17 = and(r21, #31) +# CHECK: r17 = and(r21,#31) 0xf1 0xc3 0x95 0x76 -# CHECK: r17 = or(r21, #31) +# CHECK: r17 = or(r21,#31) 0x11 0xdf 0x15 0xf1 -# CHECK: r17 = and(r21, r31) +# CHECK: r17 = and(r21,r31) 0x11 0xdf 0x35 0xf1 -# CHECK: r17 = or(r21, r31) +# CHECK: r17 = or(r21,r31) 0x11 0xdf 0x75 0xf1 -# CHECK: r17 = xor(r21, r31) +# CHECK: r17 = xor(r21,r31) 0x11 0xd5 0x9f 0xf1 -# CHECK: r17 = and(r21, ~r31) +# CHECK: r17 = and(r21,~r31) 0x11 0xd5 0xbf 0xf1 -# CHECK: r17 = or(r21, ~r31) +# CHECK: r17 = or(r21,~r31) # Nop 0x00 0xc0 0x00 0x7f @@ -31,11 +31,11 @@ # Subtract 0xb1 0xc2 0x5f 0x76 -# CHECK: r17 = sub(#21, r31) +# CHECK: r17 = sub(#21,r31) 0x11 0xdf 0x35 0xf3 -# CHECK: r17 = sub(r31, r21) +# CHECK: r17 = sub(r31,r21) 0x11 0xdf 0xd5 0xf6 -# CHECK: r17 = sub(r31, r21):sat +# CHECK: r17 = sub(r31,r21):sat # Sign extend 0x11 0xc0 0xbf 0x70 @@ -57,27 +57,27 @@ # Vector add halfwords 0x11 0xdf 0x15 0xf6 -# CHECK: r17 = vaddh(r21, r31) +# CHECK: r17 = vaddh(r21,r31) 0x11 0xdf 0x35 0xf6 -# CHECK: r17 = vaddh(r21, r31):sat +# CHECK: r17 = vaddh(r21,r31):sat 0x11 0xdf 0x75 0xf6 -# CHECK: r17 = vadduh(r21, r31):sat +# CHECK: r17 = vadduh(r21,r31):sat # Vector average halfwords 0x11 0xdf 0x15 0xf7 -# CHECK: r17 = vavgh(r21, r31) +# CHECK: r17 = vavgh(r21,r31) 0x11 0xdf 0x35 0xf7 -# CHECK: r17 = vavgh(r21, r31):rnd +# CHECK: r17 = vavgh(r21,r31):rnd 0x11 0xdf 0x75 0xf7 -# CHECK: r17 = vnavgh(r31, r21) +# CHECK: r17 = vnavgh(r31,r21) # Vector subtract halfwords 0x11 0xdf 0x95 0xf6 -# CHECK: r17 = vsubh(r31, r21) +# CHECK: r17 = vsubh(r31,r21) 0x11 0xdf 0xb5 0xf6 -# CHECK: r17 = vsubh(r31, r21):sat +# CHECK: r17 = vsubh(r31,r21):sat 0x11 0xdf 0xf5 0xf6 -# CHECK: r17 = vsubuh(r31, r21):sat +# CHECK: r17 = vsubuh(r31,r21):sat # Zero extend 0x11 0xc0 0xd5 0x70 diff --git a/test/MC/Disassembler/Hexagon/alu32_perm.txt b/test/MC/Disassembler/Hexagon/alu32_perm.txt index a2953506c59..c4b1ab97963 100644 --- a/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -3,31 +3,31 @@ # Combine words in to doublewords 0x11 0xdf 0x95 0xf3 -# CHECK: r17 = combine(r31.h, r21.h) +# CHECK: r17 = combine(r31.h,r21.h) 0x11 0xdf 0xb5 0xf3 -# CHECK: r17 = combine(r31.h, r21.l) +# CHECK: r17 = combine(r31.h,r21.l) 0x11 0xdf 0xd5 0xf3 -# CHECK: r17 = combine(r31.l, r21.h) +# CHECK: r17 = combine(r31.l,r21.h) 0x11 0xdf 0xf5 0xf3 -# CHECK: r17 = combine(r31.l, r21.l) +# CHECK: r17 = combine(r31.l,r21.l) 0xb0 0xe2 0x0f 0x7c -# CHECK: r17:16 = combine(#21, #31) +# CHECK: r17:16 = combine(#21,#31) 0xb0 0xe2 0x3f 0x73 -# CHECK: r17:16 = combine(#21, r31) +# CHECK: r17:16 = combine(#21,r31) 0xf0 0xe3 0x15 0x73 -# CHECK: r17:16 = combine(r21, #31) +# CHECK: r17:16 = combine(r21,#31) 0x10 0xdf 0x15 0xf5 -# CHECK: r17:16 = combine(r21, r31) +# CHECK: r17:16 = combine(r21,r31) # Mux 0xf1 0xc3 0x75 0x73 -# CHECK: r17 = mux(p3, r21, #31) +# CHECK: r17 = mux(p3,r21,#31) 0xb1 0xc2 0xff 0x73 -# CHECK: r17 = mux(p3, #21, r31) +# CHECK: r17 = mux(p3,#21,r31) 0xb1 0xe2 0x8f 0x7b -# CHECK: r17 = mux(p3, #21, #31) +# CHECK: r17 = mux(p3,#21,#31) 0x71 0xdf 0x15 0xf4 -# CHECK: r17 = mux(p3, r21, r31) +# CHECK: r17 = mux(p3,r21,r31) # Shift word by 16 0x11 0xc0 0x15 0x70 @@ -37,4 +37,4 @@ # Pack high and low halfwords 0x10 0xdf 0x95 0xf5 -# CHECK: r17:16 = packhl(r21, r31) +# CHECK: r17:16 = packhl(r21,r31) diff --git a/test/MC/Disassembler/Hexagon/alu32_pred.txt b/test/MC/Disassembler/Hexagon/alu32_pred.txt index 084b39d8cbf..b9e111364e6 100644 --- a/test/MC/Disassembler/Hexagon/alu32_pred.txt +++ b/test/MC/Disassembler/Hexagon/alu32_pred.txt @@ -3,25 +3,25 @@ # Conditional add 0xf1 0xc3 0x75 0x74 -# CHECK: if (p3) r17 = add(r21, #31) +# CHECK: if (p3) r17 = add(r21,#31) 0x03 0x40 0x45 0x85 0xf1 0xe3 0x75 0x74 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = add(r21, #31) +# CHECK-NEXT: if (p3.new) r17 = add(r21,#31) 0xf1 0xc3 0xf5 0x74 -# CHECK: if (!p3) r17 = add(r21, #31) +# CHECK: if (!p3) r17 = add(r21,#31) 0x03 0x40 0x45 0x85 0xf1 0xe3 0xf5 0x74 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = add(r21, #31) +# CHECK-NEXT: if (!p3.new) r17 = add(r21,#31) 0x71 0xdf 0x15 0xfb -# CHECK: if (p3) r17 = add(r21, r31) +# CHECK: if (p3) r17 = add(r21,r31) 0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xfb # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = add(r21, r31) +# CHECK-NEXT: if (p3.new) r17 = add(r21,r31) 0xf1 0xdf 0x15 0xfb -# CHECK: if (!p3) r17 = add(r21, r31) +# CHECK: if (!p3) r17 = add(r21,r31) 0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xfb # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = add(r21, r31) +# CHECK-NEXT: if (!p3.new) r17 = add(r21,r31) # Conditional shift halfword 0x11 0xe3 0x15 0x70 @@ -47,59 +47,59 @@ # Conditional combine 0x70 0xdf 0x15 0xfd -# CHECK: if (p3) r17:16 = combine(r21, r31) +# CHECK: if (p3) r17:16 = combine(r21,r31) 0xf0 0xdf 0x15 0xfd -# CHECK: if (!p3) r17:16 = combine(r21, r31) +# CHECK: if (!p3) r17:16 = combine(r21,r31) 0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31) +# CHECK-NEXT: if (p3.new) r17:16 = combine(r21,r31) 0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31) +# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21,r31) # Conditional logical operations 0x71 0xdf 0x15 0xf9 -# CHECK: if (p3) r17 = and(r21, r31) +# CHECK: if (p3) r17 = and(r21,r31) 0xf1 0xdf 0x15 0xf9 -# CHECK: if (!p3) r17 = and(r21, r31) +# CHECK: if (!p3) r17 = and(r21,r31) 0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = and(r21, r31) +# CHECK-NEXT: if (p3.new) r17 = and(r21,r31) 0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = and(r21, r31) +# CHECK-NEXT: if (!p3.new) r17 = and(r21,r31) 0x71 0xdf 0x35 0xf9 -# CHECK: if (p3) r17 = or(r21, r31) +# CHECK: if (p3) r17 = or(r21,r31) 0xf1 0xdf 0x35 0xf9 -# CHECK: if (!p3) r17 = or(r21, r31) +# CHECK: if (!p3) r17 = or(r21,r31) 0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = or(r21, r31) +# CHECK-NEXT: if (p3.new) r17 = or(r21,r31) 0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = or(r21, r31) +# CHECK-NEXT: if (!p3.new) r17 = or(r21,r31) 0x71 0xdf 0x75 0xf9 -# CHECK: if (p3) r17 = xor(r21, r31) +# CHECK: if (p3) r17 = xor(r21,r31) 0xf1 0xdf 0x75 0xf9 -# CHECK: if (!p3) r17 = xor(r21, r31) +# CHECK: if (!p3) r17 = xor(r21,r31) 0x03 0x40 0x45 0x85 0x71 0xff 0x75 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = xor(r21, r31) +# CHECK-NEXT: if (p3.new) r17 = xor(r21,r31) 0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0xf9 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = xor(r21, r31) +# CHECK-NEXT: if (!p3.new) r17 = xor(r21,r31) # Conditional subtract 0x71 0xdf 0x35 0xfb -# CHECK: if (p3) r17 = sub(r31, r21) +# CHECK: if (p3) r17 = sub(r31,r21) 0xf1 0xdf 0x35 0xfb -# CHECK: if (!p3) r17 = sub(r31, r21) +# CHECK: if (!p3) r17 = sub(r31,r21) 0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xfb # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = sub(r31, r21) +# CHECK-NEXT: if (p3.new) r17 = sub(r31,r21) 0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xfb # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = sub(r31, r21) +# CHECK-NEXT: if (!p3.new) r17 = sub(r31,r21) # Conditional sign extend 0x11 0xe3 0xb5 0x70 @@ -159,36 +159,36 @@ # Compare 0xe3 0xc3 0x15 0x75 -# CHECK: p3 = cmp.eq(r21, #31) +# CHECK: p3 = cmp.eq(r21,#31) 0xf3 0xc3 0x15 0x75 -# CHECK: p3 = !cmp.eq(r21, #31) +# CHECK: p3 = !cmp.eq(r21,#31) 0xe3 0xc3 0x55 0x75 -# CHECK: p3 = cmp.gt(r21, #31) +# CHECK: p3 = cmp.gt(r21,#31) 0xf3 0xc3 0x55 0x75 -# CHECK: p3 = !cmp.gt(r21, #31) +# CHECK: p3 = !cmp.gt(r21,#31) 0xe3 0xc3 0x95 0x75 -# CHECK: p3 = cmp.gtu(r21, #31) +# CHECK: p3 = cmp.gtu(r21,#31) 0xf3 0xc3 0x95 0x75 -# CHECK: p3 = !cmp.gtu(r21, #31) +# CHECK: p3 = !cmp.gtu(r21,#31) 0x03 0xdf 0x15 0xf2 -# CHECK: p3 = cmp.eq(r21, r31) +# CHECK: p3 = cmp.eq(r21,r31) 0x13 0xdf 0x15 0xf2 -# CHECK: p3 = !cmp.eq(r21, r31) +# CHECK: p3 = !cmp.eq(r21,r31) 0x03 0xdf 0x55 0xf2 -# CHECK: p3 = cmp.gt(r21, r31) +# CHECK: p3 = cmp.gt(r21,r31) 0x13 0xdf 0x55 0xf2 -# CHECK: p3 = !cmp.gt(r21, r31) +# CHECK: p3 = !cmp.gt(r21,r31) 0x03 0xdf 0x75 0xf2 -# CHECK: p3 = cmp.gtu(r21, r31) +# CHECK: p3 = cmp.gtu(r21,r31) 0x13 0xdf 0x75 0xf2 -# CHECK: p3 = !cmp.gtu(r21, r31) +# CHECK: p3 = !cmp.gtu(r21,r31) # Compare to general register 0xf1 0xe3 0x55 0x73 -# CHECK: r17 = cmp.eq(r21, #31) +# CHECK: r17 = cmp.eq(r21,#31) 0xf1 0xe3 0x75 0x73 -# CHECK: r17 = !cmp.eq(r21, #31) +# CHECK: r17 = !cmp.eq(r21,#31) 0x11 0xdf 0x55 0xf3 -# CHECK: r17 = cmp.eq(r21, r31) +# CHECK: r17 = cmp.eq(r21,r31) 0x11 0xdf 0x75 0xf3 -# CHECK: r17 = !cmp.eq(r21, r31) +# CHECK: r17 = !cmp.eq(r21,r31) diff --git a/test/MC/Disassembler/Hexagon/cr.txt b/test/MC/Disassembler/Hexagon/cr.txt index 6cf2b5fda39..8e505299d96 100644 --- a/test/MC/Disassembler/Hexagon/cr.txt +++ b/test/MC/Disassembler/Hexagon/cr.txt @@ -3,9 +3,9 @@ # Corner detection acceleration 0x93 0xe1 0x12 0x6b -# CHECK: p3 = !fastcorner9(p2, p1) +# CHECK: p3 = !fastcorner9(p2,p1) 0x91 0xe3 0x02 0x6b -# CHECK: p1 = fastcorner9(p2, p3) +# CHECK: p1 = fastcorner9(p2,p3) # Logical reductions on predicates 0x01 0xc0 0x82 0x6b @@ -25,7 +25,7 @@ # Add to PC 0x91 0xca 0x49 0x6a -# CHECK: r17 = add(pc, #21) +# CHECK: r17 = add(pc,#21) # Pipelined loop instructions 0x08 0xc4 0xb5 0x60 @@ -43,33 +43,33 @@ # Logical operations on predicates 0x01 0xc3 0x02 0x6b -# CHECK: p1 = and(p3, p2) +# CHECK: p1 = and(p3,p2) 0xc1 0xc3 0x12 0x6b -# CHECK: p1 = and(p2, and(p3, p3)) +# CHECK: p1 = and(p2,and(p3,p3)) 0x01 0xc3 0x22 0x6b -# CHECK: p1 = or(p3, p2) +# CHECK: p1 = or(p3,p2) 0xc1 0xc3 0x32 0x6b -# CHECK: p1 = and(p2, or(p3, p3)) +# CHECK: p1 = and(p2,or(p3,p3)) 0x01 0xc3 0x42 0x6b -# CHECK: p1 = xor(p2, p3) +# CHECK: p1 = xor(p2,p3) 0xc1 0xc3 0x52 0x6b -# CHECK: p1 = or(p2, and(p3, p3)) +# CHECK: p1 = or(p2,and(p3,p3)) 0x01 0xc2 0x63 0x6b -# CHECK: p1 = and(p2, !p3) +# CHECK: p1 = and(p2,!p3) 0xc1 0xc3 0x72 0x6b -# CHECK: p1 = or(p2, or(p3, p3)) +# CHECK: p1 = or(p2,or(p3,p3)) 0xc1 0xc3 0x92 0x6b -# CHECK: p1 = and(p2, and(p3, !p3)) +# CHECK: p1 = and(p2,and(p3,!p3)) 0xc1 0xc3 0xb2 0x6b -# CHECK: p1 = and(p2, or(p3, !p3)) +# CHECK: p1 = and(p2,or(p3,!p3)) 0x01 0xc0 0xc2 0x6b # CHECK: p1 = not(p2) 0xc1 0xc3 0xd2 0x6b -# CHECK: p1 = or(p2, and(p3, !p3)) +# CHECK: p1 = or(p2,and(p3,!p3)) 0x01 0xc2 0xe3 0x6b -# CHECK: p1 = or(p2, !p3) +# CHECK: p1 = or(p2,!p3) 0xc1 0xc3 0xf2 0x6b -# CHECK: p1 = or(p2, or(p3, !p3)) +# CHECK: p1 = or(p2,or(p3,!p3)) # User control register transfer 0x0d 0xc0 0x35 0x62 diff --git a/test/MC/Disassembler/Hexagon/j.txt b/test/MC/Disassembler/Hexagon/j.txt index 661670e2a61..c3d16386393 100644 --- a/test/MC/Disassembler/Hexagon/j.txt +++ b/test/MC/Disassembler/Hexagon/j.txt @@ -15,145 +15,145 @@ 0x00 0xc1 0x89 0x11 # CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:nt 0x00 0xc3 0x89 0x11 -# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:nt +# CHECK: p0 = tstbit(r17,#0); if (p0.new) jump:nt 0x00 0xe0 0x89 0x11 # CHECK: p0 = cmp.eq(r17,#-1); if (p0.new) jump:t 0x00 0xe1 0x89 0x11 # CHECK: p0 = cmp.gt(r17,#-1); if (p0.new) jump:t 0x00 0xe3 0x89 0x11 -# CHECK: p0 = tstbit(r17, #0); if (p0.new) jump:t +# CHECK: p0 = tstbit(r17,#0); if (p0.new) jump:t 0x00 0xc0 0xc9 0x11 # CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:nt 0x00 0xc1 0xc9 0x11 # CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:nt 0x00 0xc3 0xc9 0x11 -# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:nt +# CHECK: p0 = tstbit(r17,#0); if (!p0.new) jump:nt 0x00 0xe0 0xc9 0x11 # CHECK: p0 = cmp.eq(r17,#-1); if (!p0.new) jump:t 0x00 0xe1 0xc9 0x11 # CHECK: p0 = cmp.gt(r17,#-1); if (!p0.new) jump:t 0x00 0xe3 0xc9 0x11 -# CHECK: p0 = tstbit(r17, #0); if (!p0.new) jump:t +# CHECK: p0 = tstbit(r17,#0); if (!p0.new) jump:t 0x00 0xd5 0x09 0x10 -# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:nt +# CHECK: p0 = cmp.eq(r17,#21); if (p0.new) jump:nt 0x00 0xf5 0x09 0x10 -# CHECK: p0 = cmp.eq(r17, #21); if (p0.new) jump:t +# CHECK: p0 = cmp.eq(r17,#21); if (p0.new) jump:t 0x00 0xd5 0x49 0x10 -# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.eq(r17,#21); if (!p0.new) jump:nt 0x00 0xf5 0x49 0x10 -# CHECK: p0 = cmp.eq(r17, #21); if (!p0.new) jump:t +# CHECK: p0 = cmp.eq(r17,#21); if (!p0.new) jump:t 0x00 0xd5 0x89 0x10 -# CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:nt +# CHECK: p0 = cmp.gt(r17,#21); if (p0.new) jump:nt 0x00 0xf5 0x89 0x10 -# CHECK: p0 = cmp.gt(r17, #21); if (p0.new) jump:t +# CHECK: p0 = cmp.gt(r17,#21); if (p0.new) jump:t 0x00 0xd5 0xc9 0x10 -# CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.gt(r17,#21); if (!p0.new) jump:nt 0x00 0xf5 0xc9 0x10 -# CHECK: p0 = cmp.gt(r17, #21); if (!p0.new) jump:t +# CHECK: p0 = cmp.gt(r17,#21); if (!p0.new) jump:t 0x00 0xd5 0x09 0x11 -# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:nt +# CHECK: p0 = cmp.gtu(r17,#21); if (p0.new) jump:nt 0x00 0xf5 0x09 0x11 -# CHECK: p0 = cmp.gtu(r17, #21); if (p0.new) jump:t +# CHECK: p0 = cmp.gtu(r17,#21); if (p0.new) jump:t 0x00 0xd5 0x49 0x11 -# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.gtu(r17,#21); if (!p0.new) jump:nt 0x00 0xf5 0x49 0x11 -# CHECK: p0 = cmp.gtu(r17, #21); if (!p0.new) jump:t +# CHECK: p0 = cmp.gtu(r17,#21); if (!p0.new) jump:t 0x00 0xc0 0x89 0x13 # CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:nt 0x00 0xc1 0x89 0x13 # CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:nt 0x00 0xc3 0x89 0x13 -# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:nt +# CHECK: p1 = tstbit(r17,#0); if (p1.new) jump:nt 0x00 0xe0 0x89 0x13 # CHECK: p1 = cmp.eq(r17,#-1); if (p1.new) jump:t 0x00 0xe1 0x89 0x13 # CHECK: p1 = cmp.gt(r17,#-1); if (p1.new) jump:t 0x00 0xe3 0x89 0x13 -# CHECK: p1 = tstbit(r17, #0); if (p1.new) jump:t +# CHECK: p1 = tstbit(r17,#0); if (p1.new) jump:t 0x00 0xc0 0xc9 0x13 # CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:nt 0x00 0xc1 0xc9 0x13 # CHECK: p1 = cmp.gt(r17,#-1); if (!p1.new) jump:nt 0x00 0xc3 0xc9 0x13 -# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:nt +# CHECK: p1 = tstbit(r17,#0); if (!p1.new) jump:nt 0x00 0xe0 0xc9 0x13 # CHECK: p1 = cmp.eq(r17,#-1); if (!p1.new) jump:t 0x00 0xe1 0xc9 0x13 # CHECK: p1 = cmp.gt(r17,#-1); if (!p1.new) jump:t 0x00 0xe3 0xc9 0x13 -# CHECK: p1 = tstbit(r17, #0); if (!p1.new) jump:t +# CHECK: p1 = tstbit(r17,#0); if (!p1.new) jump:t 0x00 0xd5 0x09 0x12 -# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:nt +# CHECK: p1 = cmp.eq(r17,#21); if (p1.new) jump:nt 0x00 0xf5 0x09 0x12 -# CHECK: p1 = cmp.eq(r17, #21); if (p1.new) jump:t +# CHECK: p1 = cmp.eq(r17,#21); if (p1.new) jump:t 0x00 0xd5 0x49 0x12 -# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.eq(r17,#21); if (!p1.new) jump:nt 0x00 0xf5 0x49 0x12 -# CHECK: p1 = cmp.eq(r17, #21); if (!p1.new) jump:t +# CHECK: p1 = cmp.eq(r17,#21); if (!p1.new) jump:t 0x00 0xd5 0x89 0x12 -# CHECK: p1 = cmp.gt(r17, #21); if (p1.new) jump:nt +# CHECK: p1 = cmp.gt(r17,#21); if (p1.new) jump:nt 0x00 0xf5 0x89 0x12 -# CHECK: p1 = cmp.gt(r17, #21); if (p1.new) jump:t +# CHECK: p1 = cmp.gt(r17,#21); if (p1.new) jump:t 0x00 0xd5 0xc9 0x12 -# CHECK: p1 = cmp.gt(r17, #21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.gt(r17,#21); if (!p1.new) jump:nt 0x00 0xf5 0xc9 0x12 -# CHECK: p1 = cmp.gt(r17, #21); if (!p1.new) jump:t +# CHECK: p1 = cmp.gt(r17,#21); if (!p1.new) jump:t 0x00 0xd5 0x09 0x13 -# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:nt +# CHECK: p1 = cmp.gtu(r17,#21); if (p1.new) jump:nt 0x00 0xf5 0x09 0x13 -# CHECK: p1 = cmp.gtu(r17, #21); if (p1.new) jump:t +# CHECK: p1 = cmp.gtu(r17,#21); if (p1.new) jump:t 0x00 0xd5 0x49 0x13 -# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.gtu(r17,#21); if (!p1.new) jump:nt 0x00 0xf5 0x49 0x13 -# CHECK: p1 = cmp.gtu(r17, #21); if (!p1.new) jump:t +# CHECK: p1 = cmp.gtu(r17,#21); if (!p1.new) jump:t 0x00 0xcd 0x09 0x14 -# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:nt +# CHECK: p0 = cmp.eq(r17,r21); if (p0.new) jump:nt 0x00 0xdd 0x09 0x14 -# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:nt +# CHECK: p1 = cmp.eq(r17,r21); if (p1.new) jump:nt 0x00 0xed 0x09 0x14 -# CHECK: p0 = cmp.eq(r17, r21); if (p0.new) jump:t +# CHECK: p0 = cmp.eq(r17,r21); if (p0.new) jump:t 0x00 0xfd 0x09 0x14 -# CHECK: p1 = cmp.eq(r17, r21); if (p1.new) jump:t +# CHECK: p1 = cmp.eq(r17,r21); if (p1.new) jump:t 0x00 0xcd 0x49 0x14 -# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.eq(r17,r21); if (!p0.new) jump:nt 0x00 0xdd 0x49 0x14 -# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.eq(r17,r21); if (!p1.new) jump:nt 0x00 0xed 0x49 0x14 -# CHECK: p0 = cmp.eq(r17, r21); if (!p0.new) jump:t +# CHECK: p0 = cmp.eq(r17,r21); if (!p0.new) jump:t 0x00 0xfd 0x49 0x14 -# CHECK: p1 = cmp.eq(r17, r21); if (!p1.new) jump:t +# CHECK: p1 = cmp.eq(r17,r21); if (!p1.new) jump:t 0x00 0xcd 0x89 0x14 -# CHECK: p0 = cmp.gt(r17, r21); if (p0.new) jump:nt +# CHECK: p0 = cmp.gt(r17,r21); if (p0.new) jump:nt 0x00 0xdd 0x89 0x14 -# CHECK: p1 = cmp.gt(r17, r21); if (p1.new) jump:nt +# CHECK: p1 = cmp.gt(r17,r21); if (p1.new) jump:nt 0x00 0xed 0x89 0x14 -# CHECK: p0 = cmp.gt(r17, r21); if (p0.new) jump:t +# CHECK: p0 = cmp.gt(r17,r21); if (p0.new) jump:t 0x00 0xfd 0x89 0x14 -# CHECK: p1 = cmp.gt(r17, r21); if (p1.new) jump:t +# CHECK: p1 = cmp.gt(r17,r21); if (p1.new) jump:t 0x00 0xcd 0xc9 0x14 -# CHECK: p0 = cmp.gt(r17, r21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.gt(r17,r21); if (!p0.new) jump:nt 0x00 0xdd 0xc9 0x14 -# CHECK: p1 = cmp.gt(r17, r21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.gt(r17,r21); if (!p1.new) jump:nt 0x00 0xed 0xc9 0x14 -# CHECK: p0 = cmp.gt(r17, r21); if (!p0.new) jump:t +# CHECK: p0 = cmp.gt(r17,r21); if (!p0.new) jump:t 0x00 0xfd 0xc9 0x14 -# CHECK: p1 = cmp.gt(r17, r21); if (!p1.new) jump:t +# CHECK: p1 = cmp.gt(r17,r21); if (!p1.new) jump:t 0x00 0xcd 0x09 0x15 -# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:nt +# CHECK: p0 = cmp.gtu(r17,r21); if (p0.new) jump:nt 0x00 0xdd 0x09 0x15 -# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:nt +# CHECK: p1 = cmp.gtu(r17,r21); if (p1.new) jump:nt 0x00 0xed 0x09 0x15 -# CHECK: p0 = cmp.gtu(r17, r21); if (p0.new) jump:t +# CHECK: p0 = cmp.gtu(r17,r21); if (p0.new) jump:t 0x00 0xfd 0x09 0x15 -# CHECK: p1 = cmp.gtu(r17, r21); if (p1.new) jump:t +# CHECK: p1 = cmp.gtu(r17,r21); if (p1.new) jump:t 0x00 0xcd 0x49 0x15 -# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:nt +# CHECK: p0 = cmp.gtu(r17,r21); if (!p0.new) jump:nt 0x00 0xdd 0x49 0x15 -# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:nt +# CHECK: p1 = cmp.gtu(r17,r21); if (!p1.new) jump:nt 0x00 0xed 0x49 0x15 -# CHECK: p0 = cmp.gtu(r17, r21); if (!p0.new) jump:t +# CHECK: p0 = cmp.gtu(r17,r21); if (!p0.new) jump:t 0x00 0xfd 0x49 0x15 -# CHECK: p1 = cmp.gtu(r17, r21); if (!p1.new) jump:t +# CHECK: p1 = cmp.gtu(r17,r21); if (!p1.new) jump:t # Jump to address 0x22 0xc0 0x00 0x58 diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt index 91bb250733f..66e014fea59 100644 --- a/test/MC/Disassembler/Hexagon/ld.txt +++ b/test/MC/Disassembler/Hexagon/ld.txt @@ -3,25 +3,25 @@ # Load doubleword 0x90 0xff 0xd5 0x3a -# CHECK: r17:16 = memd(r21 + r31<<#3) +# CHECK: r17:16 = memd(r21+r31<<#3) 0xb0 0xc2 0xc0 0x49 # CHECK: r17:16 = memd(gp+#168) 0x02 0x40 0x00 0x00 0x10 0xc5 0xc0 0x49 # CHECK: r17:16 = memd(##168) 0xd0 0xc0 0xd5 0x91 -# CHECK: r17:16 = memd(r21 + #48) +# CHECK: r17:16 = memd(r21+#48) 0xb0 0xe0 0xd5 0x99 -# CHECK: r17:16 = memd(r21 ++ #40:circ(m1)) +# CHECK: r17:16 = memd(r21++#40:circ(m1)) 0x10 0xe2 0xd5 0x99 -# CHECK: r17:16 = memd(r21 ++ I:circ(m1)) +# CHECK: r17:16 = memd(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x70 0xd7 0xd5 0x9b -# CHECK: r17:16 = memd(r21 = ##31) +# CHECK: r17:16 = memd(r21=##31) 0xb0 0xc0 0xd5 0x9b # CHECK: r17:16 = memd(r21++#40) 0x10 0xe0 0xd5 0x9d # CHECK: r17:16 = memd(r21++m1) 0x10 0xe0 0xd5 0x9f -# CHECK: r17:16 = memd(r21 ++ m1:brev) +# CHECK: r17:16 = memd(r21++m1:brev) # Load doubleword conditionally 0xf0 0xff 0xd5 0x30 @@ -35,15 +35,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+r31<<#3) 0x70 0xd8 0xd5 0x41 -# CHECK: if (p3) r17:16 = memd(r21 + #24) +# CHECK: if (p3) r17:16 = memd(r21+#24) 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17:16 = memd(r21 + #24) +# CHECK-NEXT: if (p3.new) r17:16 = memd(r21+#24) 0x70 0xd8 0xd5 0x45 -# CHECK: if (!p3) r17:16 = memd(r21 + #24) +# CHECK: if (!p3) r17:16 = memd(r21+#24) 0x03 0x40 0x45 0x85 0x70 0xd8 0xd5 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21 + #24) +# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21+#24) 0xb0 0xe6 0xd5 0x9b # CHECK: if (p3) r17:16 = memd(r21++#40) 0xb0 0xee 0xd5 0x9b @@ -57,25 +57,25 @@ # Load byte 0x91 0xff 0x15 0x3a -# CHECK: r17 = memb(r21 + r31<<#3) +# CHECK: r17 = memb(r21+r31<<#3) 0xb1 0xc2 0x00 0x49 # CHECK: r17 = memb(gp+#21) 0x00 0x40 0x00 0x00 0xb1 0xc2 0x00 0x49 # CHECK: r17 = memb(##21) 0xf1 0xc3 0x15 0x91 -# CHECK: r17 = memb(r21 + #31) +# CHECK: r17 = memb(r21+#31) 0xb1 0xe0 0x15 0x99 -# CHECK: r17 = memb(r21 ++ #5:circ(m1)) +# CHECK: r17 = memb(r21++#5:circ(m1)) 0x11 0xe2 0x15 0x99 -# CHECK: r17 = memb(r21 ++ I:circ(m1)) +# CHECK: r17 = memb(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x15 0x9b -# CHECK: r17 = memb(r21 = ##31) +# CHECK: r17 = memb(r21=##31) 0xb1 0xc0 0x15 0x9b # CHECK: r17 = memb(r21++#5) 0x11 0xe0 0x15 0x9d # CHECK: r17 = memb(r21++m1) 0x11 0xe0 0x15 0x9f -# CHECK: r17 = memb(r21 ++ m1:brev) +# CHECK: r17 = memb(r21++m1:brev) # Load byte conditionally 0xf1 0xff 0x15 0x30 @@ -89,15 +89,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memb(r21+r31<<#3) 0x91 0xdd 0x15 0x41 -# CHECK: if (p3) r17 = memb(r21 + #44) +# CHECK: if (p3) r17 = memb(r21+#44) 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = memb(r21 + #44) +# CHECK-NEXT: if (p3.new) r17 = memb(r21+#44) 0x91 0xdd 0x15 0x45 -# CHECK: if (!p3) r17 = memb(r21 + #44) +# CHECK: if (!p3) r17 = memb(r21+#44) 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44) +# CHECK-NEXT: if (!p3.new) r17 = memb(r21+#44) 0xb1 0xe6 0x15 0x9b # CHECK: if (p3) r17 = memb(r21++#5) 0xb1 0xee 0x15 0x9b @@ -111,41 +111,41 @@ # Load byte into shifted vector 0xf0 0xc3 0x95 0x90 -# CHECK: r17:16 = memb_fifo(r21 + #31) +# CHECK: r17:16 = memb_fifo(r21+#31) 0xb0 0xe0 0x95 0x98 -# CHECK: r17:16 = memb_fifo(r21 ++ #5:circ(m1)) +# CHECK: r17:16 = memb_fifo(r21++#5:circ(m1)) 0x10 0xe2 0x95 0x98 -# CHECK: r17:16 = memb_fifo(r21 ++ I:circ(m1)) +# CHECK: r17:16 = memb_fifo(r21++I:circ(m1)) # Load half into shifted vector 0xf0 0xc3 0x55 0x90 -# CHECK: r17:16 = memh_fifo(r21 + #62) +# CHECK: r17:16 = memh_fifo(r21+#62) 0xb0 0xe0 0x55 0x98 -# CHECK: r17:16 = memh_fifo(r21 ++ #10:circ(m1)) +# CHECK: r17:16 = memh_fifo(r21++#10:circ(m1)) 0x10 0xe2 0x55 0x98 -# CHECK: r17:16 = memh_fifo(r21 ++ I:circ(m1)) +# CHECK: r17:16 = memh_fifo(r21++I:circ(m1)) # Load halfword 0x91 0xff 0x55 0x3a -# CHECK: r17 = memh(r21 + r31<<#3) +# CHECK: r17 = memh(r21+r31<<#3) 0xb1 0xc2 0x40 0x49 # CHECK: r17 = memh(gp+#42) 0x00 0x40 0x00 0x00 0x51 0xc5 0x40 0x49 # CHECK: r17 = memh(##42) 0xf1 0xc3 0x55 0x91 -# CHECK: r17 = memh(r21 + #62) +# CHECK: r17 = memh(r21+#62) 0xb1 0xe0 0x55 0x99 -# CHECK: r17 = memh(r21 ++ #10:circ(m1)) +# CHECK: r17 = memh(r21++#10:circ(m1)) 0x11 0xe2 0x55 0x99 -# CHECK: r17 = memh(r21 ++ I:circ(m1)) +# CHECK: r17 = memh(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x55 0x9b -# CHECK: r17 = memh(r21 = ##31) +# CHECK: r17 = memh(r21=##31) 0xb1 0xc0 0x55 0x9b # CHECK: r17 = memh(r21++#10) 0x11 0xe0 0x55 0x9d # CHECK: r17 = memh(r21++m1) 0x11 0xe0 0x55 0x9f -# CHECK: r17 = memh(r21 ++ m1:brev) +# CHECK: r17 = memh(r21++m1:brev) # Load halfword conditionally 0xf1 0xff 0x55 0x30 @@ -169,37 +169,37 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10) 0xf1 0xdb 0x55 0x41 -# CHECK: if (p3) r17 = memh(r21 + #62) +# CHECK: if (p3) r17 = memh(r21+#62) 0xf1 0xdb 0x55 0x45 -# CHECK: if (!p3) r17 = memh(r21 + #62) +# CHECK: if (!p3) r17 = memh(r21+#62) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = memh(r21 + #62) +# CHECK-NEXT: if (p3.new) r17 = memh(r21+#62) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x55 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = memh(r21 + #62) +# CHECK-NEXT: if (!p3.new) r17 = memh(r21+#62) # Load unsigned byte 0x91 0xff 0x35 0x3a -# CHECK: r17 = memub(r21 + r31<<#3) +# CHECK: r17 = memub(r21+r31<<#3) 0xb1 0xc2 0x20 0x49 # CHECK: r17 = memub(gp+#21) 0x00 0x40 0x00 0x00 0xb1 0xc2 0x20 0x49 # CHECK: r17 = memub(##21) 0xf1 0xc3 0x35 0x91 -# CHECK: r17 = memub(r21 + #31) +# CHECK: r17 = memub(r21+#31) 0xb1 0xe0 0x35 0x99 -# CHECK: r17 = memub(r21 ++ #5:circ(m1)) +# CHECK: r17 = memub(r21++#5:circ(m1)) 0x11 0xe2 0x35 0x99 -# CHECK: r17 = memub(r21 ++ I:circ(m1)) +# CHECK: r17 = memub(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9b -# CHECK: r17 = memub(r21 = ##31) +# CHECK: r17 = memub(r21=##31) 0xb1 0xc0 0x35 0x9b # CHECK: r17 = memub(r21++#5) 0x11 0xe0 0x35 0x9d # CHECK: r17 = memub(r21++m1) 0x11 0xe0 0x35 0x9f -# CHECK: r17 = memub(r21 ++ m1:brev) +# CHECK: r17 = memub(r21++m1:brev) # Load unsigned byte conditionally 0xf1 0xff 0x35 0x30 @@ -213,15 +213,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memub(r21+r31<<#3) 0xf1 0xdb 0x35 0x41 -# CHECK: if (p3) r17 = memub(r21 + #31) +# CHECK: if (p3) r17 = memub(r21+#31) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = memub(r21 + #31) +# CHECK-NEXT: if (p3.new) r17 = memub(r21+#31) 0xf1 0xdb 0x35 0x45 -# CHECK: if (!p3) r17 = memub(r21 + #31) +# CHECK: if (!p3) r17 = memub(r21+#31) 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31) +# CHECK-NEXT: if (!p3.new) r17 = memub(r21+#31) 0xb1 0xe6 0x35 0x9b # CHECK: if (p3) r17 = memub(r21++#5) 0xb1 0xee 0x35 0x9b @@ -235,25 +235,25 @@ # Load unsigned halfword 0x91 0xff 0x75 0x3a -# CHECK: r17 = memuh(r21 + r31<<#3) +# CHECK: r17 = memuh(r21+r31<<#3) 0xb1 0xc2 0x60 0x49 # CHECK: r17 = memuh(gp+#42) 0x00 0x40 0x00 0x00 0x51 0xc5 0x60 0x49 # CHECK: r17 = memuh(##42) 0xb1 0xc2 0x75 0x91 -# CHECK: r17 = memuh(r21 + #42) +# CHECK: r17 = memuh(r21+#42) 0xb1 0xe0 0x75 0x99 -# CHECK: r17 = memuh(r21 ++ #10:circ(m1)) +# CHECK: r17 = memuh(r21++#10:circ(m1)) 0x11 0xe2 0x75 0x99 -# CHECK: r17 = memuh(r21 ++ I:circ(m1)) +# CHECK: r17 = memuh(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9b -# CHECK: r17 = memuh(r21 = ##31) +# CHECK: r17 = memuh(r21=##31) 0xb1 0xc0 0x75 0x9b # CHECK: r17 = memuh(r21++#10) 0x11 0xe0 0x75 0x9d # CHECK: r17 = memuh(r21++m1) 0x11 0xe0 0x75 0x9f -# CHECK: r17 = memuh(r21 ++ m1:brev) +# CHECK: r17 = memuh(r21++m1:brev) # Load unsigned halfword conditionally 0xf1 0xff 0x75 0x30 @@ -267,15 +267,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21+r31<<#3) 0xb1 0xda 0x75 0x41 -# CHECK: if (p3) r17 = memuh(r21 + #42) +# CHECK: if (p3) r17 = memuh(r21+#42) 0xb1 0xda 0x75 0x45 -# CHECK: if (!p3) r17 = memuh(r21 + #42) +# CHECK: if (!p3) r17 = memuh(r21+#42) 0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = memuh(r21 + #42) +# CHECK-NEXT: if (p3.new) r17 = memuh(r21+#42) 0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42) +# CHECK-NEXT: if (!p3.new) r17 = memuh(r21+#42) 0xb1 0xe6 0x75 0x9b # CHECK: if (p3) r17 = memuh(r21++#10) 0xb1 0xee 0x75 0x9b @@ -289,25 +289,25 @@ # Load word 0x91 0xff 0x95 0x3a -# CHECK: r17 = memw(r21 + r31<<#3) +# CHECK: r17 = memw(r21+r31<<#3) 0xb1 0xc2 0x80 0x49 # CHECK: r17 = memw(gp+#84) 0x01 0x40 0x00 0x00 0x91 0xc2 0x80 0x49 # CHECK: r17 = memw(##84) 0xb1 0xc2 0x95 0x91 -# CHECK: r17 = memw(r21 + #84) +# CHECK: r17 = memw(r21+#84) 0xb1 0xe0 0x95 0x99 -# CHECK: r17 = memw(r21 ++ #20:circ(m1)) +# CHECK: r17 = memw(r21++#20:circ(m1)) 0x11 0xe2 0x95 0x99 -# CHECK: r17 = memw(r21 ++ I:circ(m1)) +# CHECK: r17 = memw(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x95 0x9b -# CHECK: r17 = memw(r21 = ##31) +# CHECK: r17 = memw(r21=##31) 0xb1 0xc0 0x95 0x9b # CHECK: r17 = memw(r21++#20) 0x11 0xe0 0x95 0x9d # CHECK: r17 = memw(r21++m1) 0x11 0xe0 0x95 0x9f -# CHECK: r17 = memw(r21 ++ m1:brev) +# CHECK: r17 = memw(r21++m1:brev) # Load word conditionally 0xf1 0xff 0x95 0x30 @@ -321,15 +321,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17 = memw(r21+r31<<#3) 0xb1 0xda 0x95 0x41 -# CHECK: if (p3) r17 = memw(r21 + #84) +# CHECK: if (p3) r17 = memw(r21+#84) 0xb1 0xda 0x95 0x45 -# CHECK: if (!p3) r17 = memw(r21 + #84) +# CHECK: if (!p3) r17 = memw(r21+#84) 0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x43 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = memw(r21 + #84) +# CHECK-NEXT: if (p3.new) r17 = memw(r21+#84) 0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x47 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = memw(r21 + #84) +# CHECK-NEXT: if (!p3.new) r17 = memw(r21+#84) 0xb1 0xe6 0x95 0x9b # CHECK: if (p3) r17 = memw(r21++#20) 0xb1 0xee 0x95 0x9b @@ -367,59 +367,59 @@ # Load and unpack bytes to halfwords 0xf1 0xc3 0x35 0x90 -# CHECK: r17 = membh(r21 + #62) +# CHECK: r17 = membh(r21+#62) 0xf1 0xc3 0x75 0x90 -# CHECK: r17 = memubh(r21 + #62) +# CHECK: r17 = memubh(r21+#62) 0xf0 0xc3 0xb5 0x90 -# CHECK: r17:16 = memubh(r21 + #124) +# CHECK: r17:16 = memubh(r21+#124) 0xf0 0xc3 0xf5 0x90 -# CHECK: r17:16 = membh(r21 + #124) +# CHECK: r17:16 = membh(r21+#124) 0xb1 0xe0 0x35 0x98 -# CHECK: r17 = membh(r21 ++ #10:circ(m1)) +# CHECK: r17 = membh(r21++#10:circ(m1)) 0x11 0xe2 0x35 0x98 -# CHECK: r17 = membh(r21 ++ I:circ(m1)) +# CHECK: r17 = membh(r21++I:circ(m1)) 0xb1 0xe0 0x75 0x98 -# CHECK: r17 = memubh(r21 ++ #10:circ(m1)) +# CHECK: r17 = memubh(r21++#10:circ(m1)) 0x11 0xe2 0x75 0x98 -# CHECK: r17 = memubh(r21 ++ I:circ(m1)) +# CHECK: r17 = memubh(r21++I:circ(m1)) 0xb0 0xe0 0xf5 0x98 -# CHECK: r17:16 = membh(r21 ++ #20:circ(m1)) +# CHECK: r17:16 = membh(r21++#20:circ(m1)) 0x10 0xe2 0xf5 0x98 -# CHECK: r17:16 = membh(r21 ++ I:circ(m1)) +# CHECK: r17:16 = membh(r21++I:circ(m1)) 0xb0 0xe0 0xb5 0x98 -# CHECK: r17:16 = memubh(r21 ++ #20:circ(m1)) +# CHECK: r17:16 = memubh(r21++#20:circ(m1)) 0x10 0xe2 0xb5 0x98 -# CHECK: r17:16 = memubh(r21 ++ I:circ(m1)) +# CHECK: r17:16 = memubh(r21++I:circ(m1)) 0x00 0x40 0x00 0x00 0x71 0xd7 0x35 0x9a -# CHECK: r17 = membh(r21 = ##31) +# CHECK: r17 = membh(r21=##31) 0xb1 0xc0 0x35 0x9a # CHECK: r17 = membh(r21++#10) 0x00 0x40 0x00 0x00 0x71 0xd7 0x75 0x9a -# CHECK: r17 = memubh(r21 = ##31) +# CHECK: r17 = memubh(r21=##31) 0xb1 0xc0 0x75 0x9a # CHECK: r17 = memubh(r21++#10) 0x00 0x40 0x00 0x00 0x70 0xd7 0xb5 0x9a -# CHECK: r17:16 = memubh(r21 = ##31) +# CHECK: r17:16 = memubh(r21=##31) 0xb0 0xc0 0xb5 0x9a # CHECK: r17:16 = memubh(r21++#20) 0x00 0x40 0x00 0x00 0x70 0xd7 0xf5 0x9a -# CHECK: r17:16 = membh(r21 = ##31) +# CHECK: r17:16 = membh(r21=##31) 0xb0 0xc0 0xf5 0x9a # CHECK: r17:16 = membh(r21++#20) 0x00 0x40 0x00 0x00 0xf1 0xf7 0x35 0x9c -# CHECK: r17 = membh(r21<<#3 + ##31) +# CHECK: r17 = membh(r21<<#3+##31) 0x11 0xe0 0x35 0x9c # CHECK: r17 = membh(r21++m1) 0x00 0x40 0x00 0x00 0xf1 0xf7 0x75 0x9c -# CHECK: r17 = memubh(r21<<#3 + ##31) +# CHECK: r17 = memubh(r21<<#3+##31) 0x11 0xe0 0x75 0x9c # CHECK: r17 = memubh(r21++m1) 0x00 0x40 0x00 0x00 0xf0 0xf7 0xf5 0x9c -# CHECK: r17:16 = membh(r21<<#3 + ##31) +# CHECK: r17:16 = membh(r21<<#3+##31) 0x10 0xe0 0xf5 0x9c # CHECK: r17:16 = membh(r21++m1) 0x00 0x40 0x00 0x00 0xf0 0xf7 0xb5 0x9c -# CHECK: r17:16 = memubh(r21<<#3 + ##31) +# CHECK: r17:16 = memubh(r21<<#3+##31) 0x11 0xe0 0x35 0x9c # CHECK: r17 = membh(r21++m1) 0x11 0xe0 0x75 0x9c @@ -429,10 +429,10 @@ 0x10 0xe0 0xb5 0x9c # CHECK: r17:16 = memubh(r21++m1) 0x11 0xe0 0x35 0x9e -# CHECK: r17 = membh(r21 ++ m1:brev) +# CHECK: r17 = membh(r21++m1:brev) 0x11 0xe0 0x75 0x9e -# CHECK: r17 = memubh(r21 ++ m1:brev) +# CHECK: r17 = memubh(r21++m1:brev) 0x10 0xe0 0xb5 0x9e -# CHECK: r17:16 = memubh(r21 ++ m1:brev) +# CHECK: r17:16 = memubh(r21++m1:brev) 0x10 0xe0 0xf5 0x9e -# CHECK: r17:16 = membh(r21 ++ m1:brev) +# CHECK: r17:16 = membh(r21++m1:brev) diff --git a/test/MC/Disassembler/Hexagon/nv_j.txt b/test/MC/Disassembler/Hexagon/nv_j.txt index 2135b5a039f..f3b7140f8a7 100644 --- a/test/MC/Disassembler/Hexagon/nv_j.txt +++ b/test/MC/Disassembler/Hexagon/nv_j.txt @@ -4,133 +4,133 @@ # Jump to address conditioned on new register value 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:nt +# CHECK-NEXT: if (cmp.eq(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.eq(r17.new, r21)) jump:t +# CHECK-NEXT: if (cmp.eq(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:nt +# CHECK-NEXT: if (!cmp.eq(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, r21)) jump:t +# CHECK-NEXT: if (!cmp.eq(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, r21)) jump:nt +# CHECK-NEXT: if (cmp.gt(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, r21)) jump:t +# CHECK-NEXT: if (cmp.gt(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, r21)) jump:nt +# CHECK-NEXT: if (!cmp.gt(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x20 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, r21)) jump:t +# CHECK-NEXT: if (!cmp.gt(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:nt +# CHECK-NEXT: if (cmp.gtu(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r17.new, r21)) jump:t +# CHECK-NEXT: if (cmp.gtu(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:nt +# CHECK-NEXT: if (!cmp.gtu(r17.new,r21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r17.new, r21)) jump:t +# CHECK-NEXT: if (!cmp.gtu(r17.new,r21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r21, r17.new)) jump:nt +# CHECK-NEXT: if (cmp.gt(r21,r17.new)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r21, r17.new)) jump:t +# CHECK-NEXT: if (cmp.gt(r21,r17.new)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r21, r17.new)) jump:nt +# CHECK-NEXT: if (!cmp.gt(r21,r17.new)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x21 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r21, r17.new)) jump:t +# CHECK-NEXT: if (!cmp.gt(r21,r17.new)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x22 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:nt +# CHECK-NEXT: if (cmp.gtu(r21,r17.new)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x22 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r21, r17.new)) jump:t +# CHECK-NEXT: if (cmp.gtu(r21,r17.new)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x22 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:nt +# CHECK-NEXT: if (!cmp.gtu(r21,r17.new)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x22 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r21, r17.new)) jump:t +# CHECK-NEXT: if (!cmp.gtu(r21,r17.new)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.eq(r17.new, #21)) jump:nt +# CHECK-NEXT: if (cmp.eq(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x24 # CHECK: r17 = r17 -# CHECK-NETX: if (cmp.eq(r17.new, #21)) jump:t +# CHECK-NETX: if (cmp.eq(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:nt +# CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, #21)) jump:t +# CHECK-NEXT: if (!cmp.eq(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x82 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, #21)) jump:nt +# CHECK-NEXT: if (cmp.gt(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x82 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, #21)) jump:t +# CHECK-NEXT: if (cmp.gt(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0xc2 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, #21)) jump:nt +# CHECK-NEXT: if (!cmp.gt(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0xc2 0x24 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, #21)) jump:t +# CHECK-NEXT: if (!cmp.gt(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:nt +# CHECK-NEXT: if (cmp.gtu(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x02 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gtu(r17.new, #21)) jump:t +# CHECK-NEXT: if (cmp.gtu(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xd5 0x42 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:nt +# CHECK-NEXT: if (!cmp.gtu(r17.new,#21)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xf5 0x42 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gtu(r17.new, #21)) jump:t +# CHECK-NEXT: if (!cmp.gtu(r17.new,#21)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:nt +# CHECK-NEXT: if (tstbit(r17.new,#0)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (tstbit(r17.new, #0)) jump:t +# CHECK-NEXT: if (tstbit(r17.new,#0)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:nt +# CHECK-NEXT: if (!tstbit(r17.new,#0)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x25 # CHECK: r17 = r17 -# CHECK-NEXT: if (!tstbit(r17.new, #0)) jump:t +# CHECK-NEXT: if (!tstbit(r17.new,#0)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0x02 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:nt +# CHECK-NEXT: if (cmp.eq(r17.new,#-1)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0x02 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.eq(r17.new, #-1)) jump:t +# CHECK-NEXT: if (cmp.eq(r17.new,#-1)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0x42 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:nt +# CHECK-NEXT: if (!cmp.eq(r17.new,#-1)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0x42 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.eq(r17.new, #-1)) jump:t +# CHECK-NEXT: if (!cmp.eq(r17.new,#-1)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0x82 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, #-1)) jump:nt +# CHECK-NEXT: if (cmp.gt(r17.new,#-1)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0x82 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (cmp.gt(r17.new, #-1)) jump:t +# CHECK-NEXT: if (cmp.gt(r17.new,#-1)) jump:t 0x11 0x40 0x71 0x70 0x92 0xc0 0xc2 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, #-1)) jump:nt +# CHECK-NEXT: if (!cmp.gt(r17.new,#-1)) jump:nt 0x11 0x40 0x71 0x70 0x92 0xe0 0xc2 0x26 # CHECK: r17 = r17 -# CHECK-NEXT: if (!cmp.gt(r17.new, #-1)) jump:t +# CHECK-NEXT: if (!cmp.gt(r17.new,#-1)) jump:t diff --git a/test/MC/Disassembler/Hexagon/nv_st.txt b/test/MC/Disassembler/Hexagon/nv_st.txt index 9e3f9a776b8..7b76cb56dd3 100644 --- a/test/MC/Disassembler/Hexagon/nv_st.txt +++ b/test/MC/Disassembler/Hexagon/nv_st.txt @@ -4,7 +4,7 @@ # Store new-value byte 0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b # CHECK: r31 = r31 -# CHECK-NEXT: memb(r17 + r21<<#3) = r31.new +# CHECK-NEXT: memb(r17+r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x11 0xc2 0xa0 0x48 # CHECK: r31 = r31 # CHECK-NEXT: memb(gp+#17) = r31.new @@ -13,10 +13,10 @@ # CHECK-NEXT: memb(r17+#21) = r31.new 0x1f 0x40 0x7f 0x70 0x02 0xe2 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memb(r17 ++ I:circ(m1)) = r31.new +# CHECK-NEXT: memb(r17++I:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xe2 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memb(r17 ++ #5:circ(m1)) = r31.new +# CHECK-NEXT: memb(r17++#5:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memb(r17++#5) = r31.new @@ -25,7 +25,7 @@ # CHECK-NEXT: memb(r17++m1) = r31.new 0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xaf # CHECK: r31 = r31 -# CHECK-NEXT: memb(r17 ++ m1:brev) = r31.new +# CHECK-NEXT: memb(r17++m1:brev) = r31.new # Store new-value byte conditionally 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 @@ -74,7 +74,7 @@ # Store new-value halfword 0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b # CHECK: r31 = r31 -# CHECK-NEXT: memh(r17 + r21<<#3) = r31.new +# CHECK-NEXT: memh(r17+r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xca 0xa0 0x48 # CHECK: r31 = r31 # CHECK-NEXT: memh(gp+#42) = r31.new @@ -83,10 +83,10 @@ # CHECK-NEXT: memh(r17+#42) = r31.new 0x1f 0x40 0x7f 0x70 0x02 0xea 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memh(r17 ++ I:circ(m1)) = r31.new +# CHECK-NEXT: memh(r17++I:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xea 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memh(r17 ++ #10:circ(m1)) = r31.new +# CHECK-NEXT: memh(r17++#10:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memh(r17++#10) = r31.new @@ -95,7 +95,7 @@ # CHECK-NEXT: memh(r17++m1) = r31.new 0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xaf # CHECK: r31 = r31 -# CHECK-NEXT: memh(r17 ++ m1:brev) = r31.new +# CHECK-NEXT: memh(r17++m1:brev) = r31.new # Store new-value halfword conditionally 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 @@ -144,7 +144,7 @@ # Store new-value word 0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b # CHECK: r31 = r31 -# CHECK-NEXT: memw(r17 + r21<<#3) = r31.new +# CHECK-NEXT: memw(r17+r21<<#3) = r31.new 0x1f 0x40 0x7f 0x70 0x15 0xd2 0xa0 0x48 # CHECK: r31 = r31 # CHECK-NEXT: memw(gp+#84) = r31.new @@ -153,10 +153,10 @@ # CHECK-NEXT: memw(r17+#84) = r31.new 0x1f 0x40 0x7f 0x70 0x02 0xf2 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memw(r17 ++ I:circ(m1)) = r31.new +# CHECK-NEXT: memw(r17++I:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xf2 0xb1 0xa9 # CHECK: r31 = r31 -# CHECK-NEXT: memw(r17 ++ #20:circ(m1)) = r31.new +# CHECK-NEXT: memw(r17++#20:circ(m1)) = r31.new 0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab # CHECK: r31 = r31 # CHECK-NEXT: memw(r17++#20) = r31.new @@ -165,7 +165,7 @@ # CHECK-NEXT: memw(r17++m1) = r31.new 0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xaf # CHECK: r31 = r31 -# CHECK-NEXT: memw(r17 ++ m1:brev) = r31.new +# CHECK-NEXT: memw(r17++m1:brev) = r31.new # Store new-value word conditionally 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 diff --git a/test/MC/Disassembler/Hexagon/st.txt b/test/MC/Disassembler/Hexagon/st.txt index 601047e88a2..0f936c267f5 100644 --- a/test/MC/Disassembler/Hexagon/st.txt +++ b/test/MC/Disassembler/Hexagon/st.txt @@ -3,7 +3,7 @@ # Store doubleword 0x9e 0xf5 0xd1 0x3b -# CHECK: memd(r17 + r21<<#3) = r31:30 +# CHECK: memd(r17+r21<<#3) = r31:30 0x28 0xd4 0xc0 0x48 # CHECK: memd(gp+#320) = r21:20 0x02 0x40 0x00 0x00 0x28 0xd4 0xc0 0x48 @@ -11,17 +11,17 @@ 0x15 0xd4 0xd1 0xa1 # CHECK: memd(r17+#168) = r21:20 0x02 0xf4 0xd1 0xa9 -# CHECK: memd(r17 ++ I:circ(m1)) = r21:20 +# CHECK: memd(r17++I:circ(m1)) = r21:20 0x28 0xf4 0xd1 0xa9 -# CHECK: memd(r17 ++ #40:circ(m1)) = r21:20 +# CHECK: memd(r17++#40:circ(m1)) = r21:20 0x28 0xd4 0xd1 0xab # CHECK: memd(r17++#40) = r21:20 0x00 0x40 0x00 0x00 0xd5 0xfe 0xd1 0xad -# CHECK: memd(r17<<#3 + ##21) = r31:30 +# CHECK: memd(r17<<#3+##21) = r31:30 0x00 0xf4 0xd1 0xad # CHECK: memd(r17++m1) = r21:20 0x00 0xf4 0xd1 0xaf -# CHECK: memd(r17 ++ m1:brev) = r21:20 +# CHECK: memd(r17++m1:brev) = r21:20 # Store doubleword conditionally 0xfe 0xf5 0xd1 0x34 @@ -67,9 +67,9 @@ # Store byte 0x9f 0xf5 0x11 0x3b -# CHECK: memb(r17 + r21<<#3) = r31 +# CHECK: memb(r17+r21<<#3) = r31 0x9f 0xca 0x11 0x3c -# CHECK: memb(r17+#21)=#31 +# CHECK: memb(r17+#21) = #31 0x15 0xd5 0x00 0x48 # CHECK: memb(gp+#21) = r21 0x00 0x40 0x00 0x00 0x15 0xd5 0x00 0x48 @@ -77,17 +77,17 @@ 0x15 0xd5 0x11 0xa1 # CHECK: memb(r17+#21) = r21 0x02 0xf5 0x11 0xa9 -# CHECK: memb(r17 ++ I:circ(m1)) = r21 +# CHECK: memb(r17++I:circ(m1)) = r21 0x28 0xf5 0x11 0xa9 -# CHECK: memb(r17 ++ #5:circ(m1)) = r21 +# CHECK: memb(r17++#5:circ(m1)) = r21 0x28 0xd5 0x11 0xab # CHECK: memb(r17++#5) = r21 0x00 0x40 0x00 0x00 0xd5 0xff 0x11 0xad -# CHECK: memb(r17<<#3 + ##21) = r31 +# CHECK: memb(r17<<#3+##21) = r31 0x00 0xf5 0x11 0xad # CHECK: memb(r17++m1) = r21 0x00 0xf5 0x11 0xaf -# CHECK: memb(r17 ++ m1:brev) = r21 +# CHECK: memb(r17++m1:brev) = r21 # Store byte conditionally 0xff 0xf5 0x11 0x34 @@ -101,15 +101,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memb(r17+r21<<#3) = r31 0xff 0xca 0x11 0x38 -# CHECK: if (p3) memb(r17+#21)=#31 +# CHECK: if (p3) memb(r17+#21) = #31 0xff 0xca 0x91 0x38 -# CHECK: if (!p3) memb(r17+#21)=#31 +# CHECK: if (!p3) memb(r17+#21) = #31 0x03 0x40 0x45 0x85 0xff 0xca 0x11 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) memb(r17+#21)=#31 +# CHECK-NEXT: if (p3.new) memb(r17+#21) = #31 0x03 0x40 0x45 0x85 0xff 0xca 0x91 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) memb(r17+#21)=#31 +# CHECK-NEXT: if (!p3.new) memb(r17+#21) = #31 0xab 0xdf 0x11 0x40 # CHECK: if (p3) memb(r17+#21) = r31 0xab 0xdf 0x11 0x44 @@ -143,11 +143,11 @@ # Store halfword 0x9f 0xf5 0x51 0x3b -# CHECK: memh(r17 + r21<<#3) = r31 +# CHECK: memh(r17+r21<<#3) = r31 0x9f 0xf5 0x71 0x3b -# CHECK: memh(r17 + r21<<#3) = r31.h +# CHECK: memh(r17+r21<<#3) = r31.h 0x95 0xcf 0x31 0x3c -# CHECK: memh(r17+#62)=#21 +# CHECK: memh(r17+#62) = #21 0x00 0x40 0x00 0x00 0x2a 0xd5 0x40 0x48 # CHECK: memh(##42) = r21 0x00 0x40 0x00 0x00 0x2a 0xd5 0x60 0x48 @@ -161,29 +161,29 @@ 0x15 0xdf 0x71 0xa1 # CHECK: memh(r17+#42) = r31.h 0x02 0xf5 0x51 0xa9 -# CHECK: memh(r17 ++ I:circ(m1)) = r21 +# CHECK: memh(r17++I:circ(m1)) = r21 0x28 0xf5 0x51 0xa9 -# CHECK: memh(r17 ++ #10:circ(m1)) = r21 +# CHECK: memh(r17++#10:circ(m1)) = r21 0x02 0xf5 0x71 0xa9 -# CHECK: memh(r17 ++ I:circ(m1)) = r21.h +# CHECK: memh(r17++I:circ(m1)) = r21.h 0x28 0xf5 0x71 0xa9 -# CHECK: memh(r17 ++ #10:circ(m1)) = r21.h +# CHECK: memh(r17++#10:circ(m1)) = r21.h 0x28 0xd5 0x51 0xab # CHECK: memh(r17++#10) = r21 0x00 0x40 0x00 0x00 0xd5 0xff 0x51 0xad -# CHECK: memh(r17<<#3 + ##21) = r31 +# CHECK: memh(r17<<#3+##21) = r31 0x28 0xd5 0x71 0xab # CHECK: memh(r17++#10) = r21.h 0x00 0x40 0x00 0x00 0xd5 0xff 0x71 0xad -# CHECK: memh(r17<<#3 + ##21) = r31.h +# CHECK: memh(r17<<#3+##21) = r31.h 0x00 0xf5 0x51 0xad # CHECK: memh(r17++m1) = r21 0x00 0xf5 0x71 0xad # CHECK: memh(r17++m1) = r21.h 0x00 0xf5 0x51 0xaf -# CHECK: memh(r17 ++ m1:brev) = r21 +# CHECK: memh(r17++m1:brev) = r21 0x00 0xf5 0x71 0xaf -# CHECK: memh(r17 ++ m1:brev) = r21.h +# CHECK: memh(r17++m1:brev) = r21.h # Store halfword conditionally 0xff 0xf5 0x51 0x34 @@ -207,15 +207,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memh(r17+r21<<#3) = r31.h 0xf5 0xcf 0x31 0x38 -# CHECK: if (p3) memh(r17+#62)=#21 +# CHECK: if (p3) memh(r17+#62) = #21 0xf5 0xcf 0xb1 0x38 -# CHECK: if (!p3) memh(r17+#62)=#21 +# CHECK: if (!p3) memh(r17+#62) = #21 0x03 0x40 0x45 0x85 0xf5 0xcf 0x31 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) memh(r17+#62)=#21 +# CHECK-NEXT: if (p3.new) memh(r17+#62) = #21 0x03 0x40 0x45 0x85 0xf5 0xcf 0xb1 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) memh(r17+#62)=#21 +# CHECK-NEXT: if (!p3.new) memh(r17+#62) = #21 0xfb 0xd5 0x51 0x40 # CHECK: if (p3) memh(r17+#62) = r21 0xfb 0xd5 0x71 0x40 @@ -279,29 +279,29 @@ # Store word 0x9f 0xf5 0x91 0x3b -# CHECK: memw(r17 + r21<<#3) = r31 +# CHECK: memw(r17+r21<<#3) = r31 0x9f 0xca 0x51 0x3c -# CHECK: memw(r17{{ *}}+{{ *}}#84)=#31 +# CHECK: memw(r17+#84) = #31 0x15 0xdf 0x80 0x48 # CHECK: memw(gp+#84) = r31 0x01 0x40 0x00 0x00 0x14 0xd5 0x80 0x48 # CHECK: memw(##84) = r21 0x9f 0xca 0x51 0x3c -# CHECK: memw(r17+#84)=#31 +# CHECK: memw(r17+#84) = #31 0x15 0xdf 0x91 0xa1 # CHECK: memw(r17+#84) = r31 0x02 0xf5 0x91 0xa9 -# CHECK: memw(r17 ++ I:circ(m1)) = r21 +# CHECK: memw(r17++I:circ(m1)) = r21 0x28 0xf5 0x91 0xa9 -# CHECK: memw(r17 ++ #20:circ(m1)) = r21 +# CHECK: memw(r17++#20:circ(m1)) = r21 0x28 0xd5 0x91 0xab # CHECK: memw(r17++#20) = r21 0x00 0x40 0x00 0x00 0xd5 0xff 0x91 0xad -# CHECK: memw(r17<<#3 + ##21) = r31 +# CHECK: memw(r17<<#3+##21) = r31 0x00 0xf5 0x91 0xad # CHECK: memw(r17++m1) = r21 0x00 0xf5 0x91 0xaf -# CHECK: memw(r17 ++ m1:brev) = r21 +# CHECK: memw(r17++m1:brev) = r21 # Store word conditionally 0xff 0xf5 0x91 0x34 @@ -315,15 +315,15 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) memw(r17+r21<<#3) = r31 0xff 0xca 0x51 0x38 -# CHECK: if (p3) memw(r17+#84)=#31 +# CHECK: if (p3) memw(r17+#84) = #31 0xff 0xca 0xd1 0x38 -# CHECK: if (!p3) memw(r17+#84)=#31 +# CHECK: if (!p3) memw(r17+#84) = #31 0x03 0x40 0x45 0x85 0xff 0xca 0x51 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (p3.new) memw(r17+#84)=#31 +# CHECK-NEXT: if (p3.new) memw(r17+#84) = #31 0x03 0x40 0x45 0x85 0xff 0xca 0xd1 0x39 # CHECK: p3 = r5 -# CHECK-NEXT: if (!p3.new) memw(r17+#84)=#31 +# CHECK-NEXT: if (!p3.new) memw(r17+#84) = #31 0xab 0xdf 0x91 0x40 # CHECK: if (p3) memw(r17+#84) = r31 0xab 0xdf 0x91 0x44 diff --git a/test/MC/Disassembler/Hexagon/system_user.txt b/test/MC/Disassembler/Hexagon/system_user.txt index d55a94e939b..f4d731059e0 100644 --- a/test/MC/Disassembler/Hexagon/system_user.txt +++ b/test/MC/Disassembler/Hexagon/system_user.txt @@ -9,9 +9,9 @@ # Store conditional 0x03 0xd5 0xb1 0xa0 -# CHECK: memw_locked(r17, p3) = r21 +# CHECK: memw_locked(r17,p3) = r21 0x03 0xd4 0xf1 0xa0 -# CHECK: memd_locked(r17, p3) = r21:20 +# CHECK: memd_locked(r17,p3) = r21:20 # Memory barrier 0x00 0xc0 0x00 0xa8 @@ -19,7 +19,7 @@ # Data cache prefetch 0x15 0xc0 0x11 0x94 -# CHECK: dcfetch(r17 + #168) +# CHECK: dcfetch(r17+#168) # Send value to ETM trace 0x00 0xc0 0x51 0x62 diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt index 03d0f0518a3..f05dafb3fce 100644 --- a/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -11,137 +11,137 @@ # Add and accumulate 0xff 0xd1 0x35 0xdb -# CHECK: r17 = add(r21, add(r31, #23)) +# CHECK: r17 = add(r21,add(r31,#23)) 0xff 0xd1 0xb5 0xdb -# CHECK: r17 = add(r21, sub(#23, r31)) +# CHECK: r17 = add(r21,sub(#23,r31)) 0xf1 0xc2 0x15 0xe2 -# CHECK: r17 += add(r21, #23) +# CHECK: r17 += add(r21,#23) 0xf1 0xc2 0x95 0xe2 -# CHECK: r17 -= add(r21, #23) +# CHECK: r17 -= add(r21,#23) 0x31 0xdf 0x15 0xef -# CHECK: r17 += add(r21, r31) +# CHECK: r17 += add(r21,r31) 0x31 0xdf 0x95 0xef -# CHECK: r17 -= add(r21, r31) +# CHECK: r17 -= add(r21,r31) # Add doublewords 0xf0 0xde 0x14 0xd3 -# CHECK: r17:16 = add(r21:20, r31:30) +# CHECK: r17:16 = add(r21:20,r31:30) 0xb0 0xde 0x74 0xd3 -# CHECK: r17:16 = add(r21:20, r31:30):sat +# CHECK: r17:16 = add(r21:20,r31:30):sat 0xd0 0xde 0x74 0xd3 -# CHECK: r17:16 = add(r21:20, r31:30):raw:lo +# CHECK: r17:16 = add(r21:20,r31:30):raw:lo 0xf0 0xde 0x74 0xd3 -# CHECK: r17:16 = add(r21:20, r31:30):raw:hi +# CHECK: r17:16 = add(r21:20,r31:30):raw:hi # Add halfword 0x11 0xd5 0x1f 0xd5 -# CHECK: r17 = add(r21.l, r31.l) +# CHECK: r17 = add(r21.l,r31.l) 0x51 0xd5 0x1f 0xd5 -# CHECK: r17 = add(r21.l, r31.h) +# CHECK: r17 = add(r21.l,r31.h) 0x91 0xd5 0x1f 0xd5 -# CHECK: r17 = add(r21.l, r31.l):sat +# CHECK: r17 = add(r21.l,r31.l):sat 0xd1 0xd5 0x1f 0xd5 -# CHECK: r17 = add(r21.l, r31.h):sat +# CHECK: r17 = add(r21.l,r31.h):sat 0x11 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.l, r31.l):<<16 +# CHECK: r17 = add(r21.l,r31.l):<<16 0x31 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.l, r31.h):<<16 +# CHECK: r17 = add(r21.l,r31.h):<<16 0x51 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.h, r31.l):<<16 +# CHECK: r17 = add(r21.h,r31.l):<<16 0x71 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.h, r31.h):<<16 +# CHECK: r17 = add(r21.h,r31.h):<<16 0x91 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.l, r31.l):sat:<<16 +# CHECK: r17 = add(r21.l,r31.l):sat:<<16 0xb1 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.l, r31.h):sat:<<16 +# CHECK: r17 = add(r21.l,r31.h):sat:<<16 0xd1 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.h, r31.l):sat:<<16 +# CHECK: r17 = add(r21.h,r31.l):sat:<<16 0xf1 0xd5 0x5f 0xd5 -# CHECK: r17 = add(r21.h, r31.h):sat:<<16 +# CHECK: r17 = add(r21.h,r31.h):sat:<<16 # Add or subtract doublewords with carry 0x70 0xde 0xd4 0xc2 -# CHECK: r17:16 = add(r21:20, r31:30, p3):carry +# CHECK: r17:16 = add(r21:20,r31:30,p3):carry 0x70 0xde 0xf4 0xc2 -# CHECK: r17:16 = sub(r21:20, r31:30, p3):carry +# CHECK: r17:16 = sub(r21:20,r31:30,p3):carry # Logical doublewords 0x90 0xc0 0x94 0x80 # CHECK: r17:16 = not(r21:20) 0x10 0xde 0xf4 0xd3 -# CHECK: r17:16 = and(r21:20, r31:30) +# CHECK: r17:16 = and(r21:20,r31:30) 0x30 0xd4 0xfe 0xd3 -# CHECK: r17:16 = and(r21:20, ~r31:30) +# CHECK: r17:16 = and(r21:20,~r31:30) 0x50 0xde 0xf4 0xd3 -# CHECK: r17:16 = or(r21:20, r31:30) +# CHECK: r17:16 = or(r21:20,r31:30) 0x70 0xd4 0xfe 0xd3 -# CHECK: r17:16 = or(r21:20, ~r31:30) +# CHECK: r17:16 = or(r21:20,~r31:30) 0x90 0xde 0xf4 0xd3 -# CHECK: r17:16 = xor(r21:20, r31:30) +# CHECK: r17:16 = xor(r21:20,r31:30) # Logical-logical doublewords 0x10 0xde 0x94 0xca -# CHECK: r17:16 ^= xor(r21:20, r31:30) +# CHECK: r17:16 ^= xor(r21:20,r31:30) # Logical-logical words 0xf1 0xc3 0x15 0xda -# CHECK: r17 |= and(r21, #31) +# CHECK: r17 |= and(r21,#31) 0xf5 0xc3 0x51 0xda -# CHECK: r17 = or(r21, and(r17, #31)) +# CHECK: r17 = or(r21,and(r17,#31)) 0xf1 0xc3 0x95 0xda -# CHECK: r17 |= or(r21, #31) +# CHECK: r17 |= or(r21,#31) 0x11 0xdf 0x35 0xef -# CHECK: r17 |= and(r21, ~r31) +# CHECK: r17 |= and(r21,~r31) 0x31 0xdf 0x35 0xef -# CHECK: r17 &= and(r21, ~r31) +# CHECK: r17 &= and(r21,~r31) 0x51 0xdf 0x35 0xef -# CHECK: r17 ^= and(r21, ~r31) +# CHECK: r17 ^= and(r21,~r31) 0x11 0xdf 0x55 0xef -# CHECK: r17 &= and(r21, r31) +# CHECK: r17 &= and(r21,r31) 0x31 0xdf 0x55 0xef -# CHECK: r17 &= or(r21, r31) +# CHECK: r17 &= or(r21,r31) 0x51 0xdf 0x55 0xef -# CHECK: r17 &= xor(r21, r31) +# CHECK: r17 &= xor(r21,r31) 0x71 0xdf 0x55 0xef -# CHECK: r17 |= and(r21, r31) +# CHECK: r17 |= and(r21,r31) 0x71 0xdf 0x95 0xef -# CHECK: r17 ^= xor(r21, r31) +# CHECK: r17 ^= xor(r21,r31) 0x11 0xdf 0xd5 0xef -# CHECK: r17 |= or(r21, r31) +# CHECK: r17 |= or(r21,r31) 0x31 0xdf 0xd5 0xef -# CHECK: r17 |= xor(r21, r31) +# CHECK: r17 |= xor(r21,r31) 0x51 0xdf 0xd5 0xef -# CHECK: r17 ^= and(r21, r31) +# CHECK: r17 ^= and(r21,r31) 0x71 0xdf 0xd5 0xef -# CHECK: r17 ^= or(r21, r31) +# CHECK: r17 ^= or(r21,r31) # Maximum words 0x11 0xdf 0xd5 0xd5 -# CHECK: r17 = max(r21, r31) +# CHECK: r17 = max(r21,r31) 0x91 0xdf 0xd5 0xd5 -# CHECK: r17 = maxu(r21, r31) +# CHECK: r17 = maxu(r21,r31) # Maximum doublewords 0x90 0xde 0xd4 0xd3 -# CHECK: r17:16 = max(r21:20, r31:30) +# CHECK: r17:16 = max(r21:20,r31:30) 0xb0 0xde 0xd4 0xd3 -# CHECK: r17:16 = maxu(r21:20, r31:30) +# CHECK: r17:16 = maxu(r21:20,r31:30) # Minimum words 0x11 0xd5 0xbf 0xd5 -# CHECK: r17 = min(r21, r31) +# CHECK: r17 = min(r21,r31) 0x91 0xd5 0xbf 0xd5 -# CHECK: r17 = minu(r21, r31) +# CHECK: r17 = minu(r21,r31) # Minimum doublewords 0xd0 0xd4 0xbe 0xd3 -# CHECK: r17:16 = min(r21:20, r31:30) +# CHECK: r17:16 = min(r21:20,r31:30) 0xf0 0xd4 0xbe 0xd3 -# CHECK: r17:16 = minu(r21:20, r31:30) +# CHECK: r17:16 = minu(r21:20,r31:30) # Module wrap 0xf1 0xdf 0xf5 0xd3 -# CHECK: r17 = modwrap(r21, r31) +# CHECK: r17 = modwrap(r21,r31) # Negate 0xb0 0xc0 0x94 0x80 @@ -153,51 +153,51 @@ 0x31 0xc0 0xd4 0x88 # CHECK: r17 = round(r21:20):sat 0x11 0xdf 0xf5 0x8c -# CHECK: r17 = cround(r21, #31) +# CHECK: r17 = cround(r21,#31) 0x91 0xdf 0xf5 0x8c -# CHECK: r17 = round(r21, #31) +# CHECK: r17 = round(r21,#31) 0xd1 0xdf 0xf5 0x8c -# CHECK: r17 = round(r21, #31):sat +# CHECK: r17 = round(r21,#31):sat 0x11 0xdf 0xd5 0xc6 -# CHECK: r17 = cround(r21, r31) +# CHECK: r17 = cround(r21,r31) 0x91 0xdf 0xd5 0xc6 -# CHECK: r17 = round(r21, r31) +# CHECK: r17 = round(r21,r31) 0xd1 0xdf 0xd5 0xc6 -# CHECK: r17 = round(r21, r31):sat +# CHECK: r17 = round(r21,r31):sat # Subtract doublewords 0xf0 0xd4 0x3e 0xd3 -# CHECK: r17:16 = sub(r21:20, r31:30) +# CHECK: r17:16 = sub(r21:20,r31:30) # Subtract and accumulate words 0x71 0xd5 0x1f 0xef -# CHECK: r17 += sub(r21, r31) +# CHECK: r17 += sub(r21,r31) # Subtract halfword 0x11 0xd5 0x3f 0xd5 -# CHECK: r17 = sub(r21.l, r31.l) +# CHECK: r17 = sub(r21.l,r31.l) 0x51 0xd5 0x3f 0xd5 -# CHECK: r17 = sub(r21.l, r31.h) +# CHECK: r17 = sub(r21.l,r31.h) 0x91 0xd5 0x3f 0xd5 -# CHECK: r17 = sub(r21.l, r31.l):sat +# CHECK: r17 = sub(r21.l,r31.l):sat 0xd1 0xd5 0x3f 0xd5 -# CHECK: r17 = sub(r21.l, r31.h):sat +# CHECK: r17 = sub(r21.l,r31.h):sat 0x11 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.l, r31.l):<<16 +# CHECK: r17 = sub(r21.l,r31.l):<<16 0x31 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.l, r31.h):<<16 +# CHECK: r17 = sub(r21.l,r31.h):<<16 0x51 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.h, r31.l):<<16 +# CHECK: r17 = sub(r21.h,r31.l):<<16 0x71 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.h, r31.h):<<16 +# CHECK: r17 = sub(r21.h,r31.h):<<16 0x91 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.l, r31.l):sat:<<16 +# CHECK: r17 = sub(r21.l,r31.l):sat:<<16 0xb1 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.l, r31.h):sat:<<16 +# CHECK: r17 = sub(r21.l,r31.h):sat:<<16 0xd1 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.h, r31.l):sat:<<16 +# CHECK: r17 = sub(r21.h,r31.l):sat:<<16 0xf1 0xd5 0x7f 0xd5 -# CHECK: r17 = sub(r21.h, r31.h):sat:<<16 +# CHECK: r17 = sub(r21.h,r31.h):sat:<<16 # Sign extend word to doubleword 0x10 0xc0 0x55 0x84 @@ -217,179 +217,179 @@ # Vector absolute difference halfwords 0x10 0xd4 0x7e 0xe8 -# CHECK: r17:16 = vabsdiffh(r21:20, r31:30) +# CHECK: r17:16 = vabsdiffh(r21:20,r31:30) # Vector absolute difference words 0x10 0xd4 0x3e 0xe8 -# CHECK: r17:16 = vabsdiffw(r21:20, r31:30) +# CHECK: r17:16 = vabsdiffw(r21:20,r31:30) # Vector add halfwords 0x50 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddh(r21:20, r31:30) +# CHECK: r17:16 = vaddh(r21:20,r31:30) 0x70 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddh(r21:20, r31:30):sat +# CHECK: r17:16 = vaddh(r21:20,r31:30):sat 0x90 0xde 0x14 0xd3 -# CHECK: r17:16 = vadduh(r21:20, r31:30):sat +# CHECK: r17:16 = vadduh(r21:20,r31:30):sat # Vector add halfwords with saturate and pack to unsigned bytes 0x31 0xde 0x54 0xc1 -# CHECK: r17 = vaddhub(r21:20, r31:30):sat +# CHECK: r17 = vaddhub(r21:20,r31:30):sat # Vector reduce add unsigned bytes 0x30 0xde 0x54 0xe8 -# CHECK: r17:16 = vraddub(r21:20, r31:30) +# CHECK: r17:16 = vraddub(r21:20,r31:30) 0x30 0xde 0x54 0xea -# CHECK: r17:16 += vraddub(r21:20, r31:30) +# CHECK: r17:16 += vraddub(r21:20,r31:30) # Vector reduce add halfwords 0x31 0xde 0x14 0xe9 -# CHECK: r17 = vradduh(r21:20, r31:30) +# CHECK: r17 = vradduh(r21:20,r31:30) 0xf1 0xde 0x34 0xe9 -# CHECK: r17 = vraddh(r21:20, r31:30) +# CHECK: r17 = vraddh(r21:20,r31:30) # Vector add bytes 0x10 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddub(r21:20, r31:30) +# CHECK: r17:16 = vaddub(r21:20,r31:30) 0x30 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddub(r21:20, r31:30):sat +# CHECK: r17:16 = vaddub(r21:20,r31:30):sat # Vector add words 0xb0 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddw(r21:20, r31:30) +# CHECK: r17:16 = vaddw(r21:20,r31:30) 0xd0 0xde 0x14 0xd3 -# CHECK: r17:16 = vaddw(r21:20, r31:30):sat +# CHECK: r17:16 = vaddw(r21:20,r31:30):sat # Vector average halfwords 0x50 0xde 0x54 0xd3 -# CHECK: r17:16 = vavgh(r21:20, r31:30) +# CHECK: r17:16 = vavgh(r21:20,r31:30) 0x70 0xde 0x54 0xd3 -# CHECK: r17:16 = vavgh(r21:20, r31:30):rnd +# CHECK: r17:16 = vavgh(r21:20,r31:30):rnd 0x90 0xde 0x54 0xd3 -# CHECK: r17:16 = vavgh(r21:20, r31:30):crnd +# CHECK: r17:16 = vavgh(r21:20,r31:30):crnd 0xb0 0xde 0x54 0xd3 -# CHECK: r17:16 = vavguh(r21:20, r31:30) +# CHECK: r17:16 = vavguh(r21:20,r31:30) 0xd0 0xde 0x54 0xd3 -# CHECK: r17:16 = vavguh(r21:20, r31:30):rnd +# CHECK: r17:16 = vavguh(r21:20,r31:30):rnd 0x10 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgh(r21:20, r31:30) +# CHECK: r17:16 = vnavgh(r21:20,r31:30) 0x30 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vnavgh(r21:20,r31:30):rnd:sat 0x50 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgh(r21:20, r31:30):crnd:sat +# CHECK: r17:16 = vnavgh(r21:20,r31:30):crnd:sat # Vector average unsigned bytes 0x10 0xde 0x54 0xd3 -# CHECK: r17:16 = vavgub(r21:20, r31:30) +# CHECK: r17:16 = vavgub(r21:20,r31:30) 0x30 0xde 0x54 0xd3 -# CHECK: r17:16 = vavgub(r21:20, r31:30):rnd +# CHECK: r17:16 = vavgub(r21:20,r31:30):rnd # Vector average words 0x10 0xde 0x74 0xd3 -# CHECK: r17:16 = vavgw(r21:20, r31:30) +# CHECK: r17:16 = vavgw(r21:20,r31:30) 0x30 0xde 0x74 0xd3 -# CHECK: r17:16 = vavgw(r21:20, r31:30):rnd +# CHECK: r17:16 = vavgw(r21:20,r31:30):rnd 0x50 0xde 0x74 0xd3 -# CHECK: r17:16 = vavgw(r21:20, r31:30):crnd +# CHECK: r17:16 = vavgw(r21:20,r31:30):crnd 0x70 0xde 0x74 0xd3 -# CHECK: r17:16 = vavguw(r21:20, r31:30) +# CHECK: r17:16 = vavguw(r21:20,r31:30) 0x90 0xde 0x74 0xd3 -# CHECK: r17:16 = vavguw(r21:20, r31:30):rnd +# CHECK: r17:16 = vavguw(r21:20,r31:30):rnd 0x70 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgw(r21:20, r31:30) +# CHECK: r17:16 = vnavgw(r21:20,r31:30) 0x90 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgw(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vnavgw(r21:20,r31:30):rnd:sat 0xd0 0xd4 0x9e 0xd3 -# CHECK: r17:16 = vnavgw(r21:20, r31:30):crnd:sat +# CHECK: r17:16 = vnavgw(r21:20,r31:30):crnd:sat # Vector conditional negate 0x50 0xdf 0xd4 0xc3 -# CHECK: r17:16 = vcnegh(r21:20, r31) +# CHECK: r17:16 = vcnegh(r21:20,r31) 0xf0 0xff 0x34 0xcb -# CHECK: r17:16 += vrcnegh(r21:20, r31) +# CHECK: r17:16 += vrcnegh(r21:20,r31) # Vector maximum bytes 0x10 0xd4 0xde 0xd3 -# CHECK: r17:16 = vmaxub(r21:20, r31:30) +# CHECK: r17:16 = vmaxub(r21:20,r31:30) 0xd0 0xd4 0xde 0xd3 -# CHECK: r17:16 = vmaxb(r21:20, r31:30) +# CHECK: r17:16 = vmaxb(r21:20,r31:30) # Vector maximum halfwords 0x30 0xd4 0xde 0xd3 -# CHECK: r17:16 = vmaxh(r21:20, r31:30) +# CHECK: r17:16 = vmaxh(r21:20,r31:30) 0x50 0xd4 0xde 0xd3 -# CHECK: r17:16 = vmaxuh(r21:20, r31:30) +# CHECK: r17:16 = vmaxuh(r21:20,r31:30) # Vector reduce maximum halfwords 0x3f 0xd0 0x34 0xcb -# CHECK: r17:16 = vrmaxh(r21:20, r31) +# CHECK: r17:16 = vrmaxh(r21:20,r31) 0x3f 0xf0 0x34 0xcb -# CHECK: r17:16 = vrmaxuh(r21:20, r31) +# CHECK: r17:16 = vrmaxuh(r21:20,r31) # Vector reduce maximum words 0x5f 0xd0 0x34 0xcb -# CHECK: r17:16 = vrmaxw(r21:20, r31) +# CHECK: r17:16 = vrmaxw(r21:20,r31) 0x5f 0xf0 0x34 0xcb -# CHECK: r17:16 = vrmaxuw(r21:20, r31) +# CHECK: r17:16 = vrmaxuw(r21:20,r31) # Vector maximum words 0xb0 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vmaxuw(r21:20, r31:30) +# CHECK: r17:16 = vmaxuw(r21:20,r31:30) 0x70 0xd4 0xde 0xd3 -# CHECK: r17:16 = vmaxw(r21:20, r31:30) +# CHECK: r17:16 = vmaxw(r21:20,r31:30) # Vector minimum bytes 0x10 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vminub(r21:20, r31:30) +# CHECK: r17:16 = vminub(r21:20,r31:30) 0xf0 0xd4 0xde 0xd3 -# CHECK: r17:16 = vminb(r21:20, r31:30) +# CHECK: r17:16 = vminb(r21:20,r31:30) # Vector minimum halfwords 0x30 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vminh(r21:20, r31:30) +# CHECK: r17:16 = vminh(r21:20,r31:30) 0x50 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vminuh(r21:20, r31:30) +# CHECK: r17:16 = vminuh(r21:20,r31:30) # Vector reduce minimum halfwords 0xbf 0xd0 0x34 0xcb -# CHECK: r17:16 = vrminh(r21:20, r31) +# CHECK: r17:16 = vrminh(r21:20,r31) 0xbf 0xf0 0x34 0xcb -# CHECK: r17:16 = vrminuh(r21:20, r31) +# CHECK: r17:16 = vrminuh(r21:20,r31) # Vector reduce minimum words 0xdf 0xd0 0x34 0xcb -# CHECK: r17:16 = vrminw(r21:20, r31) +# CHECK: r17:16 = vrminw(r21:20,r31) 0xdf 0xf0 0x34 0xcb -# CHECK: r17:16 = vrminuw(r21:20, r31) +# CHECK: r17:16 = vrminuw(r21:20,r31) # Vector minimum words 0x70 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vminw(r21:20, r31:30) +# CHECK: r17:16 = vminw(r21:20,r31:30) 0x90 0xd4 0xbe 0xd3 -# CHECK: r17:16 = vminuw(r21:20, r31:30) +# CHECK: r17:16 = vminuw(r21:20,r31:30) # Vector sum of absolute differences unsigned bytes 0x50 0xde 0x54 0xe8 -# CHECK: r17:16 = vrsadub(r21:20, r31:30) +# CHECK: r17:16 = vrsadub(r21:20,r31:30) 0x50 0xde 0x54 0xea -# CHECK: r17:16 += vrsadub(r21:20, r31:30) +# CHECK: r17:16 += vrsadub(r21:20,r31:30) # Vector subtract halfwords 0x50 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubh(r21:20, r31:30) +# CHECK: r17:16 = vsubh(r21:20,r31:30) 0x70 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubh(r21:20, r31:30):sat +# CHECK: r17:16 = vsubh(r21:20,r31:30):sat 0x90 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubuh(r21:20, r31:30):sat +# CHECK: r17:16 = vsubuh(r21:20,r31:30):sat # Vector subtract bytes 0x10 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubub(r21:20, r31:30) +# CHECK: r17:16 = vsubub(r21:20,r31:30) 0x30 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubub(r21:20, r31:30):sat +# CHECK: r17:16 = vsubub(r21:20,r31:30):sat # Vector subtract words 0xb0 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubw(r21:20, r31:30) +# CHECK: r17:16 = vsubw(r21:20,r31:30) 0xd0 0xd4 0x3e 0xd3 -# CHECK: r17:16 = vsubw(r21:20, r31:30):sat +# CHECK: r17:16 = vsubw(r21:20,r31:30):sat diff --git a/test/MC/Disassembler/Hexagon/xtype_bit.txt b/test/MC/Disassembler/Hexagon/xtype_bit.txt index 89b6906afa9..490a8bf8502 100644 --- a/test/MC/Disassembler/Hexagon/xtype_bit.txt +++ b/test/MC/Disassembler/Hexagon/xtype_bit.txt @@ -11,9 +11,9 @@ 0x11 0xc0 0x74 0x88 # CHECK: r17 = normamt(r21:20) 0x51 0xd7 0x74 0x88 -# CHECK: r17 = add(clb(r21:20), #23) +# CHECK: r17 = add(clb(r21:20),#23) 0x11 0xd7 0x35 0x8c -# CHECK: r17 = add(clb(r21), #23) +# CHECK: r17 = add(clb(r21),#23) 0x91 0xc0 0x15 0x8c # CHECK: r17 = clb(r21) 0xb1 0xc0 0x15 0x8c @@ -39,31 +39,31 @@ # Extract bitfield 0xf0 0xdf 0x54 0x81 -# CHECK: r17:16 = extractu(r21:20, #31, #23) +# CHECK: r17:16 = extractu(r21:20,#31,#23) 0xf0 0xdf 0x54 0x8a -# CHECK: r17:16 = extract(r21:20, #31, #23) +# CHECK: r17:16 = extract(r21:20,#31,#23) 0xf1 0xdf 0x55 0x8d -# CHECK: r17 = extractu(r21, #31, #23) +# CHECK: r17 = extractu(r21,#31,#23) 0xf1 0xdf 0xd5 0x8d -# CHECK: r17 = extract(r21, #31, #23) +# CHECK: r17 = extract(r21,#31,#23) 0x10 0xde 0x14 0xc1 -# CHECK: r17:16 = extractu(r21:20, r31:30) +# CHECK: r17:16 = extractu(r21:20,r31:30) 0x90 0xde 0xd4 0xc1 -# CHECK: r17:16 = extract(r21:20, r31:30) +# CHECK: r17:16 = extract(r21:20,r31:30) 0x11 0xde 0x15 0xc9 -# CHECK: r17 = extractu(r21, r31:30) +# CHECK: r17 = extractu(r21,r31:30) 0x51 0xde 0x15 0xc9 -# CHECK: r17 = extract(r21, r31:30) +# CHECK: r17 = extract(r21,r31:30) # Insert bitfield 0xf0 0xdf 0x54 0x83 -# CHECK: r17:16 = insert(r21:20, #31, #23) +# CHECK: r17:16 = insert(r21:20,#31,#23) 0xf1 0xdf 0x55 0x8f -# CHECK: r17 = insert(r21, #31, #23) +# CHECK: r17 = insert(r21,#31,#23) 0x11 0xde 0x15 0xc8 -# CHECK: r17 = insert(r21, r31:30) +# CHECK: r17 = insert(r21,r31:30) 0x10 0xde 0x14 0xca -# CHECK: r17:16 = insert(r21:20, r31:30) +# CHECK: r17:16 = insert(r21:20,r31:30) # Interleave/deinterleave 0x90 0xc0 0xd4 0x80 @@ -73,13 +73,13 @@ # Linear feedback-shift iteration 0xd0 0xde 0x94 0xc1 -# CHECK: r17:16 = lfs(r21:20, r31:30) +# CHECK: r17:16 = lfs(r21:20,r31:30) # Masked parity 0x11 0xde 0x14 0xd0 -# CHECK: r17 = parity(r21:20, r31:30) +# CHECK: r17 = parity(r21:20,r31:30) 0x11 0xdf 0xf5 0xd5 -# CHECK: r17 = parity(r21, r31) +# CHECK: r17 = parity(r21,r31) # Bit reverse 0xd0 0xc0 0xd4 0x80 @@ -89,30 +89,30 @@ # Set/clear/toggle bit 0x11 0xdf 0xd5 0x8c -# CHECK: r17 = setbit(r21, #31) +# CHECK: r17 = setbit(r21,#31) 0x31 0xdf 0xd5 0x8c -# CHECK: r17 = clrbit(r21, #31) +# CHECK: r17 = clrbit(r21,#31) 0x51 0xdf 0xd5 0x8c -# CHECK: r17 = togglebit(r21, #31) +# CHECK: r17 = togglebit(r21,#31) 0x11 0xdf 0x95 0xc6 -# CHECK: r17 = setbit(r21, r31) +# CHECK: r17 = setbit(r21,r31) 0x51 0xdf 0x95 0xc6 -# CHECK: r17 = clrbit(r21, r31) +# CHECK: r17 = clrbit(r21,r31) 0x91 0xdf 0x95 0xc6 -# CHECK: r17 = togglebit(r21, r31) +# CHECK: r17 = togglebit(r21,r31) # Split bitfield 0x90 0xdf 0xd5 0x88 -# CHECK: r17:16 = bitsplit(r21, #31) +# CHECK: r17:16 = bitsplit(r21,#31) 0x10 0xdf 0x35 0xd4 -# CHECK: r17:16 = bitsplit(r21, r31) +# CHECK: r17:16 = bitsplit(r21,r31) # Table index 0xf1 0xcd 0x15 0x87 -# CHECK: r17 = tableidxb(r21, #7, #13):raw +# CHECK: r17 = tableidxb(r21,#7,#13):raw 0xf1 0xcd 0x55 0x87 -# CHECK: r17 = tableidxh(r21, #7, #13):raw +# CHECK: r17 = tableidxh(r21,#7,#13):raw 0xf1 0xcd 0x95 0x87 -# CHECK: r17 = tableidxw(r21, #7, #13):raw +# CHECK: r17 = tableidxw(r21,#7,#13):raw 0xf1 0xcd 0xd5 0x87 -# CHECK: r17 = tableidxd(r21, #7, #13):raw +# CHECK: r17 = tableidxd(r21,#7,#13):raw diff --git a/test/MC/Disassembler/Hexagon/xtype_complex.txt b/test/MC/Disassembler/Hexagon/xtype_complex.txt index 2332082d835..2c604f37d2e 100644 --- a/test/MC/Disassembler/Hexagon/xtype_complex.txt +++ b/test/MC/Disassembler/Hexagon/xtype_complex.txt @@ -3,89 +3,89 @@ # Complex add/sub halfwords 0x90 0xde 0x54 0xc1 -# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat +# CHECK: r17:16 = vxaddsubh(r21:20,r31:30):sat 0xd0 0xde 0x54 0xc1 -# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat +# CHECK: r17:16 = vxsubaddh(r21:20,r31:30):sat 0x10 0xde 0xd4 0xc1 -# CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat +# CHECK: r17:16 = vxaddsubh(r21:20,r31:30):rnd:>>1:sat 0x50 0xde 0xd4 0xc1 -# CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat +# CHECK: r17:16 = vxsubaddh(r21:20,r31:30):rnd:>>1:sat # Complex add/sub words 0x10 0xde 0x54 0xc1 -# CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat +# CHECK: r17:16 = vxaddsubw(r21:20,r31:30):sat 0x50 0xde 0x54 0xc1 -# CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat +# CHECK: r17:16 = vxsubaddw(r21:20,r31:30):sat # Complex multiply 0xd0 0xdf 0x15 0xe5 -# CHECK: r17:16 = cmpy(r21, r31):sat +# CHECK: r17:16 = cmpy(r21,r31):sat 0xd0 0xdf 0x95 0xe5 -# CHECK: r17:16 = cmpy(r21, r31):<<1:sat +# CHECK: r17:16 = cmpy(r21,r31):<<1:sat 0xd0 0xdf 0x55 0xe5 -# CHECK: r17:16 = cmpy(r21, r31*):sat +# CHECK: r17:16 = cmpy(r21,r31*):sat 0xd0 0xdf 0xd5 0xe5 -# CHECK: r17:16 = cmpy(r21, r31*):<<1:sat +# CHECK: r17:16 = cmpy(r21,r31*):<<1:sat 0xd0 0xdf 0x15 0xe7 -# CHECK: r17:16 += cmpy(r21, r31):sat +# CHECK: r17:16 += cmpy(r21,r31):sat 0xd0 0xdf 0x95 0xe7 -# CHECK: r17:16 += cmpy(r21, r31):<<1:sat +# CHECK: r17:16 += cmpy(r21,r31):<<1:sat 0xf0 0xdf 0x15 0xe7 -# CHECK: r17:16 -= cmpy(r21, r31):sat +# CHECK: r17:16 -= cmpy(r21,r31):sat 0xf0 0xdf 0x95 0xe7 -# CHECK: r17:16 -= cmpy(r21, r31):<<1:sat +# CHECK: r17:16 -= cmpy(r21,r31):<<1:sat 0xd0 0xdf 0x55 0xe7 -# CHECK: r17:16 += cmpy(r21, r31*):sat +# CHECK: r17:16 += cmpy(r21,r31*):sat 0xd0 0xdf 0xd5 0xe7 -# CHECK: r17:16 += cmpy(r21, r31*):<<1:sat +# CHECK: r17:16 += cmpy(r21,r31*):<<1:sat 0xf0 0xdf 0x55 0xe7 -# CHECK: r17:16 -= cmpy(r21, r31*):sat +# CHECK: r17:16 -= cmpy(r21,r31*):sat 0xf0 0xdf 0xd5 0xe7 -# CHECK: r17:16 -= cmpy(r21, r31*):<<1:sat +# CHECK: r17:16 -= cmpy(r21,r31*):<<1:sat # Complex multiply real or imaginary 0x30 0xdf 0x15 0xe5 -# CHECK: r17:16 = cmpyi(r21, r31) +# CHECK: r17:16 = cmpyi(r21,r31) 0x50 0xdf 0x15 0xe5 -# CHECK: r17:16 = cmpyr(r21, r31) +# CHECK: r17:16 = cmpyr(r21,r31) 0x30 0xdf 0x15 0xe7 -# CHECK: r17:16 += cmpyi(r21, r31) +# CHECK: r17:16 += cmpyi(r21,r31) 0x50 0xdf 0x15 0xe7 -# CHECK: r17:16 += cmpyr(r21, r31) +# CHECK: r17:16 += cmpyr(r21,r31) # Complex multiply with round and pack 0xd1 0xdf 0x35 0xed -# CHECK: r17 = cmpy(r21, r31):rnd:sat +# CHECK: r17 = cmpy(r21,r31):rnd:sat 0xd1 0xdf 0xb5 0xed -# CHECK: r17 = cmpy(r21, r31):<<1:rnd:sat +# CHECK: r17 = cmpy(r21,r31):<<1:rnd:sat 0xd1 0xdf 0x75 0xed -# CHECK: r17 = cmpy(r21, r31*):rnd:sat +# CHECK: r17 = cmpy(r21,r31*):rnd:sat 0xd1 0xdf 0xf5 0xed -# CHECK: r17 = cmpy(r21, r31*):<<1:rnd:sat +# CHECK: r17 = cmpy(r21,r31*):<<1:rnd:sat # Complex multiply 32x16 0x91 0xdf 0x14 0xc5 -# CHECK: r17 = cmpyiwh(r21:20, r31):<<1:rnd:sat +# CHECK: r17 = cmpyiwh(r21:20,r31):<<1:rnd:sat 0xb1 0xdf 0x14 0xc5 -# CHECK: r17 = cmpyiwh(r21:20, r31*):<<1:rnd:sat +# CHECK: r17 = cmpyiwh(r21:20,r31*):<<1:rnd:sat 0xd1 0xdf 0x14 0xc5 -# CHECK: r17 = cmpyrwh(r21:20, r31):<<1:rnd:sat +# CHECK: r17 = cmpyrwh(r21:20,r31):<<1:rnd:sat 0xf1 0xdf 0x14 0xc5 -# CHECK: r17 = cmpyrwh(r21:20, r31*):<<1:rnd:sat +# CHECK: r17 = cmpyrwh(r21:20,r31*):<<1:rnd:sat # Vector complex multiply real or imaginary 0xd0 0xde 0x34 0xe8 -# CHECK: r17:16 = vcmpyr(r21:20, r31:30):sat +# CHECK: r17:16 = vcmpyr(r21:20,r31:30):sat 0xd0 0xde 0xb4 0xe8 -# CHECK: r17:16 = vcmpyr(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vcmpyr(r21:20,r31:30):<<1:sat 0xd0 0xde 0x54 0xe8 -# CHECK: r17:16 = vcmpyi(r21:20, r31:30):sat +# CHECK: r17:16 = vcmpyi(r21:20,r31:30):sat 0xd0 0xde 0xd4 0xe8 -# CHECK: r17:16 = vcmpyi(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vcmpyi(r21:20,r31:30):<<1:sat 0x90 0xde 0x34 0xea -# CHECK: r17:16 += vcmpyr(r21:20, r31:30):sat +# CHECK: r17:16 += vcmpyr(r21:20,r31:30):sat 0x90 0xde 0x54 0xea -# CHECK: r17:16 += vcmpyi(r21:20, r31:30):sat +# CHECK: r17:16 += vcmpyi(r21:20,r31:30):sat # Vector complex conjugate 0xf0 0xc0 0x94 0x80 @@ -93,36 +93,36 @@ # Vector complex rotate 0x10 0xdf 0xd4 0xc3 -# CHECK: r17:16 = vcrotate(r21:20, r31) +# CHECK: r17:16 = vcrotate(r21:20,r31) # Vector reduce complex multiply real or imaginary 0x10 0xde 0x14 0xe8 -# CHECK: r17:16 = vrcmpyi(r21:20, r31:30) +# CHECK: r17:16 = vrcmpyi(r21:20,r31:30) 0x30 0xde 0x14 0xe8 -# CHECK: r17:16 = vrcmpyr(r21:20, r31:30) +# CHECK: r17:16 = vrcmpyr(r21:20,r31:30) 0x10 0xde 0x54 0xe8 -# CHECK: r17:16 = vrcmpyi(r21:20, r31:30*) +# CHECK: r17:16 = vrcmpyi(r21:20,r31:30*) 0x30 0xde 0x74 0xe8 -# CHECK: r17:16 = vrcmpyr(r21:20, r31:30*) +# CHECK: r17:16 = vrcmpyr(r21:20,r31:30*) # Vector reduce complex multiply by scalar 0x90 0xde 0xb4 0xe8 -# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:hi +# CHECK: r17:16 = vrcmpys(r21:20,r31:30):<<1:sat:raw:hi 0x90 0xde 0xf4 0xe8 -# CHECK: r17:16 = vrcmpys(r21:20, r31:30):<<1:sat:raw:lo +# CHECK: r17:16 = vrcmpys(r21:20,r31:30):<<1:sat:raw:lo 0x90 0xde 0xb4 0xea -# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:hi +# CHECK: r17:16 += vrcmpys(r21:20,r31:30):<<1:sat:raw:hi 0x90 0xde 0xf4 0xea -# CHECK: r17:16 += vrcmpys(r21:20, r31:30):<<1:sat:raw:lo +# CHECK: r17:16 += vrcmpys(r21:20,r31:30):<<1:sat:raw:lo # Vector reduce complex multiply by scalar with round and pack 0xd1 0xde 0xb4 0xe9 -# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:hi +# CHECK: r17 = vrcmpys(r21:20,r31:30):<<1:rnd:sat:raw:hi 0xf1 0xde 0xb4 0xe9 -# CHECK: r17 = vrcmpys(r21:20, r31:30):<<1:rnd:sat:raw:lo +# CHECK: r17 = vrcmpys(r21:20,r31:30):<<1:rnd:sat:raw:lo # Vector reduce complex rotate 0xf0 0xff 0xd4 0xc3 -# CHECK: r17:16 = vrcrotate(r21:20, r31, #3) +# CHECK: r17:16 = vrcrotate(r21:20,r31,#3) 0x30 0xff 0xb4 0xcb -# CHECK: r17:16 += vrcrotate(r21:20, r31, #3) +# CHECK: r17:16 += vrcrotate(r21:20,r31,#3) diff --git a/test/MC/Disassembler/Hexagon/xtype_fp.txt b/test/MC/Disassembler/Hexagon/xtype_fp.txt index 70074208eda..31f2a5330f2 100644 --- a/test/MC/Disassembler/Hexagon/xtype_fp.txt +++ b/test/MC/Disassembler/Hexagon/xtype_fp.txt @@ -3,31 +3,31 @@ # Floating point addition 0x11 0xdf 0x15 0xeb -# CHECK: r17 = sfadd(r21, r31) +# CHECK: r17 = sfadd(r21,r31) # Classify floating-point value 0x03 0xd5 0xf1 0x85 -# CHECK: p3 = sfclass(r17, #21) +# CHECK: p3 = sfclass(r17,#21) 0xb3 0xc2 0x90 0xdc -# CHECK: p3 = dfclass(r17:16, #21) +# CHECK: p3 = dfclass(r17:16,#21) # Compare floating-point value 0x03 0xd5 0xf1 0xc7 -# CHECK: p3 = sfcmp.ge(r17, r21) +# CHECK: p3 = sfcmp.ge(r17,r21) 0x23 0xd5 0xf1 0xc7 -# CHECK: p3 = sfcmp.uo(r17, r21) +# CHECK: p3 = sfcmp.uo(r17,r21) 0x63 0xd5 0xf1 0xc7 -# CHECK: p3 = sfcmp.eq(r17, r21) +# CHECK: p3 = sfcmp.eq(r17,r21) 0x83 0xd5 0xf1 0xc7 -# CHECK: p3 = sfcmp.gt(r17, r21) +# CHECK: p3 = sfcmp.gt(r17,r21) 0x03 0xd4 0xf0 0xd2 -# CHECK: p3 = dfcmp.eq(r17:16, r21:20) +# CHECK: p3 = dfcmp.eq(r17:16,r21:20) 0x23 0xd4 0xf0 0xd2 -# CHECK: p3 = dfcmp.gt(r17:16, r21:20) +# CHECK: p3 = dfcmp.gt(r17:16,r21:20) 0x43 0xd4 0xf0 0xd2 -# CHECK: p3 = dfcmp.ge(r17:16, r21:20) +# CHECK: p3 = dfcmp.ge(r17:16,r21:20) 0x63 0xd4 0xf0 0xd2 -# CHECK: p3 = dfcmp.uo(r17:16, r21:20) +# CHECK: p3 = dfcmp.uo(r17:16,r21:20) # Convert floating-point value to other format 0x10 0xc0 0x95 0x84 @@ -91,29 +91,29 @@ 0x11 0xc0 0xb5 0x8b # CHECK: r17 = sffixupr(r21) 0x11 0xdf 0xd5 0xeb -# CHECK: r17 = sffixupn(r21, r31) +# CHECK: r17 = sffixupn(r21,r31) 0x31 0xdf 0xd5 0xeb -# CHECK: r17 = sffixupd(r21, r31) +# CHECK: r17 = sffixupd(r21,r31) # Floating point fused multiply-add 0x91 0xdf 0x15 0xef -# CHECK: r17 += sfmpy(r21, r31) +# CHECK: r17 += sfmpy(r21,r31) 0xb1 0xdf 0x15 0xef -# CHECK: r17 -= sfmpy(r21, r31) +# CHECK: r17 -= sfmpy(r21,r31) # Floating point fused multiply-add with scaling 0xf1 0xdf 0x75 0xef -# CHECK: r17 += sfmpy(r21, r31, p3):scale +# CHECK: r17 += sfmpy(r21,r31,p3):scale # Floating point reciprocal square root approximation 0x71 0xc0 0xf5 0x8b -# CHECK: r17, p3 = sfinvsqrta(r21) +# CHECK: r17,p3 = sfinvsqrta(r21) # Floating point fused multiply-add for library routines 0xd1 0xdf 0x15 0xef -# CHECK: r17 += sfmpy(r21, r31):lib +# CHECK: r17 += sfmpy(r21,r31):lib 0xf1 0xdf 0x15 0xef -# CHECK: r17 -= sfmpy(r21, r31):lib +# CHECK: r17 -= sfmpy(r21,r31):lib # Create floating-point constant 0xb1 0xc2 0x00 0xd6 @@ -127,20 +127,20 @@ # Floating point maximum 0x11 0xdf 0x95 0xeb -# CHECK: r17 = sfmax(r21, r31) +# CHECK: r17 = sfmax(r21,r31) # Floating point minimum 0x31 0xdf 0x95 0xeb -# CHECK: r17 = sfmin(r21, r31) +# CHECK: r17 = sfmin(r21,r31) # Floating point multiply 0x11 0xdf 0x55 0xeb -# CHECK: r17 = sfmpy(r21, r31) +# CHECK: r17 = sfmpy(r21,r31) # Floating point reciprocal approximation 0xf1 0xdf 0xf5 0xeb -# CHECK: r17, p3 = sfrecipa(r21, r31) +# CHECK: r17,p3 = sfrecipa(r21,r31) # Floating point subtraction 0x31 0xdf 0x15 0xeb -# CHECK: r17 = sfsub(r21, r31) +# CHECK: r17 = sfsub(r21,r31) diff --git a/test/MC/Disassembler/Hexagon/xtype_mpy.txt b/test/MC/Disassembler/Hexagon/xtype_mpy.txt index ada32162a81..dde6e76b266 100644 --- a/test/MC/Disassembler/Hexagon/xtype_mpy.txt +++ b/test/MC/Disassembler/Hexagon/xtype_mpy.txt @@ -3,398 +3,398 @@ # Multiply and use lower result 0xb1 0xdf 0x35 0xd7 -# CHECK: r17 = add(#21, mpyi(r21, r31)) +# CHECK: r17 = add(#21,mpyi(r21,r31)) 0xbf 0xd1 0x35 0xd8 -# CHECK: r17 = add(#21, mpyi(r21, #31)) +# CHECK: r17 = add(#21,mpyi(r21,#31)) 0xb5 0xd1 0x3f 0xdf -# CHECK: r17 = add(r21, mpyi(#84, r31)) +# CHECK: r17 = add(r21,mpyi(#84,r31)) 0xf5 0xf1 0xb5 0xdf -# CHECK: r17 = add(r21, mpyi(r21, #31)) +# CHECK: r17 = add(r21,mpyi(r21,#31)) 0x15 0xd1 0x1f 0xe3 -# CHECK: r17 = add(r21, mpyi(r17, r31)) +# CHECK: r17 = add(r21,mpyi(r17,r31)) 0xf1 0xc3 0x15 0xe0 -# CHECK: r17 =+ mpyi(r21, #31) +# CHECK: r17 = +mpyi(r21,#31) 0xf1 0xc3 0x95 0xe0 -# CHECK: r17 =- mpyi(r21, #31) +# CHECK: r17 = -mpyi(r21,#31) 0xf1 0xc3 0x15 0xe1 -# CHECK: r17 += mpyi(r21, #31) +# CHECK: r17 += mpyi(r21,#31) 0xf1 0xc3 0x95 0xe1 -# CHECK: r17 -= mpyi(r21, #31) +# CHECK: r17 -= mpyi(r21,#31) 0x11 0xdf 0x15 0xed -# CHECK: r17 = mpyi(r21, r31) +# CHECK: r17 = mpyi(r21,r31) 0x11 0xdf 0x15 0xef -# CHECK: r17 += mpyi(r21, r31) +# CHECK: r17 += mpyi(r21,r31) # Vector multiply word by signed half (32x16) 0xb0 0xde 0x14 0xe8 -# CHECK: r17:16 = vmpyweh(r21:20, r31:30):sat +# CHECK: r17:16 = vmpyweh(r21:20,r31:30):sat 0xb0 0xde 0x94 0xe8 -# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vmpyweh(r21:20,r31:30):<<1:sat 0xf0 0xde 0x14 0xe8 -# CHECK: r17:16 = vmpywoh(r21:20, r31:30):sat +# CHECK: r17:16 = vmpywoh(r21:20,r31:30):sat 0xf0 0xde 0x94 0xe8 -# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vmpywoh(r21:20,r31:30):<<1:sat 0xb0 0xde 0x34 0xe8 -# CHECK: r17:16 = vmpyweh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vmpyweh(r21:20,r31:30):rnd:sat 0xb0 0xde 0xb4 0xe8 -# CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 = vmpyweh(r21:20,r31:30):<<1:rnd:sat 0xf0 0xde 0x34 0xe8 -# CHECK: r17:16 = vmpywoh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vmpywoh(r21:20,r31:30):rnd:sat 0xf0 0xde 0xb4 0xe8 -# CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 = vmpywoh(r21:20,r31:30):<<1:rnd:sat 0xb0 0xde 0x14 0xea -# CHECK: r17:16 += vmpyweh(r21:20, r31:30):sat +# CHECK: r17:16 += vmpyweh(r21:20,r31:30):sat 0xb0 0xde 0x94 0xea -# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vmpyweh(r21:20,r31:30):<<1:sat 0xf0 0xde 0x14 0xea -# CHECK: r17:16 += vmpywoh(r21:20, r31:30):sat +# CHECK: r17:16 += vmpywoh(r21:20,r31:30):sat 0xf0 0xde 0x94 0xea -# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vmpywoh(r21:20,r31:30):<<1:sat 0xb0 0xde 0x34 0xea -# CHECK: r17:16 += vmpyweh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 += vmpyweh(r21:20,r31:30):rnd:sat 0xb0 0xde 0xb4 0xea -# CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 += vmpyweh(r21:20,r31:30):<<1:rnd:sat 0xf0 0xde 0x34 0xea -# CHECK: r17:16 += vmpywoh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 += vmpywoh(r21:20,r31:30):rnd:sat 0xf0 0xde 0xb4 0xea -# CHECK: r17:16 += vmpywoh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 += vmpywoh(r21:20,r31:30):<<1:rnd:sat # Vector multiply word by unsigned half (32x16) 0xb0 0xde 0x54 0xe8 -# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):sat +# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):sat 0xb0 0xde 0xd4 0xe8 -# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):<<1:sat 0xf0 0xde 0x54 0xe8 -# CHECK: r17:16 = vmpywouh(r21:20, r31:30):sat +# CHECK: r17:16 = vmpywouh(r21:20,r31:30):sat 0xf0 0xde 0xd4 0xe8 -# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vmpywouh(r21:20,r31:30):<<1:sat 0xb0 0xde 0x74 0xe8 -# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):rnd:sat 0xb0 0xde 0xf4 0xe8 -# CHECK: r17:16 = vmpyweuh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 = vmpyweuh(r21:20,r31:30):<<1:rnd:sat 0xf0 0xde 0x74 0xe8 -# CHECK: r17:16 = vmpywouh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 = vmpywouh(r21:20,r31:30):rnd:sat 0xf0 0xde 0xf4 0xe8 -# CHECK: r17:16 = vmpywouh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 = vmpywouh(r21:20,r31:30):<<1:rnd:sat 0xb0 0xde 0x54 0xea -# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):sat +# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):sat 0xb0 0xde 0xd4 0xea -# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):<<1:sat 0xf0 0xde 0x54 0xea -# CHECK: r17:16 += vmpywouh(r21:20, r31:30):sat +# CHECK: r17:16 += vmpywouh(r21:20,r31:30):sat 0xf0 0xde 0xd4 0xea -# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vmpywouh(r21:20,r31:30):<<1:sat 0xb0 0xde 0x74 0xea -# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):rnd:sat 0xb0 0xde 0xf4 0xea -# CHECK: r17:16 += vmpyweuh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 += vmpyweuh(r21:20,r31:30):<<1:rnd:sat 0xf0 0xde 0x74 0xea -# CHECK: r17:16 += vmpywouh(r21:20, r31:30):rnd:sat +# CHECK: r17:16 += vmpywouh(r21:20,r31:30):rnd:sat 0xf0 0xde 0xf4 0xea -# CHECK: r17:16 += vmpywouh(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17:16 += vmpywouh(r21:20,r31:30):<<1:rnd:sat # Multiply signed halfwords 0x10 0xdf 0x95 0xe4 -# CHECK: r17:16 = mpy(r21.l, r31.l):<<1 +# CHECK: r17:16 = mpy(r21.l,r31.l):<<1 0x30 0xdf 0x95 0xe4 -# CHECK: r17:16 = mpy(r21.l, r31.h):<<1 +# CHECK: r17:16 = mpy(r21.l,r31.h):<<1 0x50 0xdf 0x95 0xe4 -# CHECK: r17:16 = mpy(r21.h, r31.l):<<1 +# CHECK: r17:16 = mpy(r21.h,r31.l):<<1 0x70 0xdf 0x95 0xe4 -# CHECK: r17:16 = mpy(r21.h, r31.h):<<1 +# CHECK: r17:16 = mpy(r21.h,r31.h):<<1 0x10 0xdf 0xb5 0xe4 -# CHECK: r17:16 = mpy(r21.l, r31.l):<<1:rnd +# CHECK: r17:16 = mpy(r21.l,r31.l):<<1:rnd 0x30 0xdf 0xb5 0xe4 -# CHECK: r17:16 = mpy(r21.l, r31.h):<<1:rnd +# CHECK: r17:16 = mpy(r21.l,r31.h):<<1:rnd 0x50 0xdf 0xb5 0xe4 -# CHECK: r17:16 = mpy(r21.h, r31.l):<<1:rnd +# CHECK: r17:16 = mpy(r21.h,r31.l):<<1:rnd 0x70 0xdf 0xb5 0xe4 -# CHECK: r17:16 = mpy(r21.h, r31.h):<<1:rnd +# CHECK: r17:16 = mpy(r21.h,r31.h):<<1:rnd 0x10 0xdf 0x95 0xe6 -# CHECK: r17:16 += mpy(r21.l, r31.l):<<1 +# CHECK: r17:16 += mpy(r21.l,r31.l):<<1 0x30 0xdf 0x95 0xe6 -# CHECK: r17:16 += mpy(r21.l, r31.h):<<1 +# CHECK: r17:16 += mpy(r21.l,r31.h):<<1 0x50 0xdf 0x95 0xe6 -# CHECK: r17:16 += mpy(r21.h, r31.l):<<1 +# CHECK: r17:16 += mpy(r21.h,r31.l):<<1 0x70 0xdf 0x95 0xe6 -# CHECK: r17:16 += mpy(r21.h, r31.h):<<1 +# CHECK: r17:16 += mpy(r21.h,r31.h):<<1 0x10 0xdf 0xb5 0xe6 -# CHECK: r17:16 -= mpy(r21.l, r31.l):<<1 +# CHECK: r17:16 -= mpy(r21.l,r31.l):<<1 0x30 0xdf 0xb5 0xe6 -# CHECK: r17:16 -= mpy(r21.l, r31.h):<<1 +# CHECK: r17:16 -= mpy(r21.l,r31.h):<<1 0x50 0xdf 0xb5 0xe6 -# CHECK: r17:16 -= mpy(r21.h, r31.l):<<1 +# CHECK: r17:16 -= mpy(r21.h,r31.l):<<1 0x70 0xdf 0xb5 0xe6 -# CHECK: r17:16 -= mpy(r21.h, r31.h):<<1 +# CHECK: r17:16 -= mpy(r21.h,r31.h):<<1 0x11 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.l, r31.l):<<1 +# CHECK: r17 = mpy(r21.l,r31.l):<<1 0x31 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.l, r31.h):<<1 +# CHECK: r17 = mpy(r21.l,r31.h):<<1 0x51 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.h, r31.l):<<1 +# CHECK: r17 = mpy(r21.h,r31.l):<<1 0x71 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.h, r31.h):<<1 +# CHECK: r17 = mpy(r21.h,r31.h):<<1 0x91 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.l, r31.l):<<1:sat +# CHECK: r17 = mpy(r21.l,r31.l):<<1:sat 0xb1 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.l, r31.h):<<1:sat +# CHECK: r17 = mpy(r21.l,r31.h):<<1:sat 0xd1 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.h, r31.l):<<1:sat +# CHECK: r17 = mpy(r21.h,r31.l):<<1:sat 0xf1 0xdf 0x95 0xec -# CHECK: r17 = mpy(r21.h, r31.h):<<1:sat +# CHECK: r17 = mpy(r21.h,r31.h):<<1:sat 0x11 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.l, r31.l):<<1:rnd +# CHECK: r17 = mpy(r21.l,r31.l):<<1:rnd 0x31 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.l, r31.h):<<1:rnd +# CHECK: r17 = mpy(r21.l,r31.h):<<1:rnd 0x51 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.h, r31.l):<<1:rnd +# CHECK: r17 = mpy(r21.h,r31.l):<<1:rnd 0x71 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.h, r31.h):<<1:rnd +# CHECK: r17 = mpy(r21.h,r31.h):<<1:rnd 0x91 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.l, r31.l):<<1:rnd:sat +# CHECK: r17 = mpy(r21.l,r31.l):<<1:rnd:sat 0xb1 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.l, r31.h):<<1:rnd:sat +# CHECK: r17 = mpy(r21.l,r31.h):<<1:rnd:sat 0xd1 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.h, r31.l):<<1:rnd:sat +# CHECK: r17 = mpy(r21.h,r31.l):<<1:rnd:sat 0xf1 0xdf 0xb5 0xec -# CHECK: r17 = mpy(r21.h, r31.h):<<1:rnd:sat +# CHECK: r17 = mpy(r21.h,r31.h):<<1:rnd:sat 0x11 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.l, r31.l):<<1 +# CHECK: r17 += mpy(r21.l,r31.l):<<1 0x31 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.l, r31.h):<<1 +# CHECK: r17 += mpy(r21.l,r31.h):<<1 0x51 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.h, r31.l):<<1 +# CHECK: r17 += mpy(r21.h,r31.l):<<1 0x71 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.h, r31.h):<<1 +# CHECK: r17 += mpy(r21.h,r31.h):<<1 0x91 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.l, r31.l):<<1:sat +# CHECK: r17 += mpy(r21.l,r31.l):<<1:sat 0xb1 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.l, r31.h):<<1:sat +# CHECK: r17 += mpy(r21.l,r31.h):<<1:sat 0xd1 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.h, r31.l):<<1:sat +# CHECK: r17 += mpy(r21.h,r31.l):<<1:sat 0xf1 0xdf 0x95 0xee -# CHECK: r17 += mpy(r21.h, r31.h):<<1:sat +# CHECK: r17 += mpy(r21.h,r31.h):<<1:sat 0x11 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.l, r31.l):<<1 +# CHECK: r17 -= mpy(r21.l,r31.l):<<1 0x31 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.l, r31.h):<<1 +# CHECK: r17 -= mpy(r21.l,r31.h):<<1 0x51 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.h, r31.l):<<1 +# CHECK: r17 -= mpy(r21.h,r31.l):<<1 0x71 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.h, r31.h):<<1 +# CHECK: r17 -= mpy(r21.h,r31.h):<<1 0x91 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.l, r31.l):<<1:sat +# CHECK: r17 -= mpy(r21.l,r31.l):<<1:sat 0xb1 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.l, r31.h):<<1:sat +# CHECK: r17 -= mpy(r21.l,r31.h):<<1:sat 0xd1 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.h, r31.l):<<1:sat +# CHECK: r17 -= mpy(r21.h,r31.l):<<1:sat 0xf1 0xdf 0xb5 0xee -# CHECK: r17 -= mpy(r21.h, r31.h):<<1:sat +# CHECK: r17 -= mpy(r21.h,r31.h):<<1:sat # Multiply unsigned halfwords 0x10 0xdf 0xd5 0xe4 -# CHECK: r17:16 = mpyu(r21.l, r31.l):<<1 +# CHECK: r17:16 = mpyu(r21.l,r31.l):<<1 0x30 0xdf 0xd5 0xe4 -# CHECK: r17:16 = mpyu(r21.l, r31.h):<<1 +# CHECK: r17:16 = mpyu(r21.l,r31.h):<<1 0x50 0xdf 0xd5 0xe4 -# CHECK: r17:16 = mpyu(r21.h, r31.l):<<1 +# CHECK: r17:16 = mpyu(r21.h,r31.l):<<1 0x70 0xdf 0xd5 0xe4 -# CHECK: r17:16 = mpyu(r21.h, r31.h):<<1 +# CHECK: r17:16 = mpyu(r21.h,r31.h):<<1 0x10 0xdf 0xd5 0xe6 -# CHECK: r17:16 += mpyu(r21.l, r31.l):<<1 +# CHECK: r17:16 += mpyu(r21.l,r31.l):<<1 0x30 0xdf 0xd5 0xe6 -# CHECK: r17:16 += mpyu(r21.l, r31.h):<<1 +# CHECK: r17:16 += mpyu(r21.l,r31.h):<<1 0x50 0xdf 0xd5 0xe6 -# CHECK: r17:16 += mpyu(r21.h, r31.l):<<1 +# CHECK: r17:16 += mpyu(r21.h,r31.l):<<1 0x70 0xdf 0xd5 0xe6 -# CHECK: r17:16 += mpyu(r21.h, r31.h):<<1 +# CHECK: r17:16 += mpyu(r21.h,r31.h):<<1 0x10 0xdf 0xf5 0xe6 -# CHECK: r17:16 -= mpyu(r21.l, r31.l):<<1 +# CHECK: r17:16 -= mpyu(r21.l,r31.l):<<1 0x30 0xdf 0xf5 0xe6 -# CHECK: r17:16 -= mpyu(r21.l, r31.h):<<1 +# CHECK: r17:16 -= mpyu(r21.l,r31.h):<<1 0x50 0xdf 0xf5 0xe6 -# CHECK: r17:16 -= mpyu(r21.h, r31.l):<<1 +# CHECK: r17:16 -= mpyu(r21.h,r31.l):<<1 0x70 0xdf 0xf5 0xe6 -# CHECK: r17:16 -= mpyu(r21.h, r31.h):<<1 +# CHECK: r17:16 -= mpyu(r21.h,r31.h):<<1 0x11 0xdf 0xd5 0xec -# CHECK: r17 = mpyu(r21.l, r31.l):<<1 +# CHECK: r17 = mpyu(r21.l,r31.l):<<1 0x31 0xdf 0xd5 0xec -# CHECK: r17 = mpyu(r21.l, r31.h):<<1 +# CHECK: r17 = mpyu(r21.l,r31.h):<<1 0x51 0xdf 0xd5 0xec -# CHECK: r17 = mpyu(r21.h, r31.l):<<1 +# CHECK: r17 = mpyu(r21.h,r31.l):<<1 0x71 0xdf 0xd5 0xec -# CHECK: r17 = mpyu(r21.h, r31.h):<<1 +# CHECK: r17 = mpyu(r21.h,r31.h):<<1 0x11 0xdf 0xd5 0xee -# CHECK: r17 += mpyu(r21.l, r31.l):<<1 +# CHECK: r17 += mpyu(r21.l,r31.l):<<1 0x31 0xdf 0xd5 0xee -# CHECK: r17 += mpyu(r21.l, r31.h):<<1 +# CHECK: r17 += mpyu(r21.l,r31.h):<<1 0x51 0xdf 0xd5 0xee -# CHECK: r17 += mpyu(r21.h, r31.l):<<1 +# CHECK: r17 += mpyu(r21.h,r31.l):<<1 0x71 0xdf 0xd5 0xee -# CHECK: r17 += mpyu(r21.h, r31.h):<<1 +# CHECK: r17 += mpyu(r21.h,r31.h):<<1 0x11 0xdf 0xf5 0xee -# CHECK: r17 -= mpyu(r21.l, r31.l):<<1 +# CHECK: r17 -= mpyu(r21.l,r31.l):<<1 0x31 0xdf 0xf5 0xee -# CHECK: r17 -= mpyu(r21.l, r31.h):<<1 +# CHECK: r17 -= mpyu(r21.l,r31.h):<<1 0x51 0xdf 0xf5 0xee -# CHECK: r17 -= mpyu(r21.h, r31.l):<<1 +# CHECK: r17 -= mpyu(r21.h,r31.l):<<1 0x71 0xdf 0xf5 0xee -# CHECK: r17 -= mpyu(r21.h, r31.h):<<1 +# CHECK: r17 -= mpyu(r21.h,r31.h):<<1 # Polynomial multiply words 0xf0 0xdf 0x55 0xe5 -# CHECK: r17:16 = pmpyw(r21, r31) +# CHECK: r17:16 = pmpyw(r21,r31) 0xf0 0xdf 0x35 0xe7 -# CHECK: r17:16 ^= pmpyw(r21, r31) +# CHECK: r17:16 ^= pmpyw(r21,r31) # Vector reduce multiply word by signed half (32x16) 0x50 0xde 0x34 0xe8 -# CHECK: r17:16 = vrmpywoh(r21:20, r31:30) +# CHECK: r17:16 = vrmpywoh(r21:20,r31:30) 0x50 0xde 0xb4 0xe8 -# CHECK: r17:16 = vrmpywoh(r21:20, r31:30):<<1 +# CHECK: r17:16 = vrmpywoh(r21:20,r31:30):<<1 0x90 0xde 0x54 0xe8 -# CHECK: r17:16 = vrmpyweh(r21:20, r31:30) +# CHECK: r17:16 = vrmpyweh(r21:20,r31:30) 0x90 0xde 0xd4 0xe8 -# CHECK: r17:16 = vrmpyweh(r21:20, r31:30):<<1 +# CHECK: r17:16 = vrmpyweh(r21:20,r31:30):<<1 0xd0 0xde 0x74 0xea -# CHECK: r17:16 += vrmpywoh(r21:20, r31:30) +# CHECK: r17:16 += vrmpywoh(r21:20,r31:30) 0xd0 0xde 0xf4 0xea -# CHECK: r17:16 += vrmpywoh(r21:20, r31:30):<<1 +# CHECK: r17:16 += vrmpywoh(r21:20,r31:30):<<1 0xd0 0xde 0x34 0xea -# CHECK: r17:16 += vrmpyweh(r21:20, r31:30) +# CHECK: r17:16 += vrmpyweh(r21:20,r31:30) 0xd0 0xde 0xb4 0xea -# CHECK: r17:16 += vrmpyweh(r21:20, r31:30):<<1 +# CHECK: r17:16 += vrmpyweh(r21:20,r31:30):<<1 # Multiply and use upper result 0x31 0xdf 0x15 0xed -# CHECK: r17 = mpy(r21, r31) +# CHECK: r17 = mpy(r21,r31) 0x31 0xdf 0x35 0xed -# CHECK: r17 = mpy(r21, r31):rnd +# CHECK: r17 = mpy(r21,r31):rnd 0x31 0xdf 0x55 0xed -# CHECK: r17 = mpyu(r21, r31) +# CHECK: r17 = mpyu(r21,r31) 0x31 0xdf 0x75 0xed -# CHECK: r17 = mpysu(r21, r31) +# CHECK: r17 = mpysu(r21,r31) 0x11 0xdf 0xb5 0xed -# CHECK: r17 = mpy(r21, r31.h):<<1:sat +# CHECK: r17 = mpy(r21,r31.h):<<1:sat 0x31 0xdf 0xb5 0xed -# CHECK: r17 = mpy(r21, r31.l):<<1:sat +# CHECK: r17 = mpy(r21,r31.l):<<1:sat 0x91 0xdf 0xb5 0xed -# CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat +# CHECK: r17 = mpy(r21,r31.h):<<1:rnd:sat 0x11 0xdf 0xf5 0xed -# CHECK: r17 = mpy(r21, r31):<<1:sat +# CHECK: r17 = mpy(r21,r31):<<1:sat 0x91 0xdf 0xf5 0xed -# CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat +# CHECK: r17 = mpy(r21,r31.l):<<1:rnd:sat 0x51 0xdf 0xb5 0xed -# CHECK: r17 = mpy(r21, r31):<<1 +# CHECK: r17 = mpy(r21,r31):<<1 0x11 0xdf 0x75 0xef -# CHECK: r17 += mpy(r21, r31):<<1:sat +# CHECK: r17 += mpy(r21,r31):<<1:sat 0x31 0xdf 0x75 0xef -# CHECK: r17 -= mpy(r21, r31):<<1:sat +# CHECK: r17 -= mpy(r21,r31):<<1:sat # Multiply and use full result 0x10 0xdf 0x15 0xe5 -# CHECK: r17:16 = mpy(r21, r31) +# CHECK: r17:16 = mpy(r21,r31) 0x10 0xdf 0x55 0xe5 -# CHECK: r17:16 = mpyu(r21, r31) +# CHECK: r17:16 = mpyu(r21,r31) 0x10 0xdf 0x15 0xe7 -# CHECK: r17:16 += mpy(r21, r31) +# CHECK: r17:16 += mpy(r21,r31) 0x10 0xdf 0x35 0xe7 -# CHECK: r17:16 -= mpy(r21, r31) +# CHECK: r17:16 -= mpy(r21,r31) 0x10 0xdf 0x55 0xe7 -# CHECK: r17:16 += mpyu(r21, r31) +# CHECK: r17:16 += mpyu(r21,r31) 0x10 0xdf 0x75 0xe7 -# CHECK: r17:16 -= mpyu(r21, r31) +# CHECK: r17:16 -= mpyu(r21,r31) # Vector dual multiply 0x90 0xde 0x14 0xe8 -# CHECK: r17:16 = vdmpy(r21:20, r31:30):sat +# CHECK: r17:16 = vdmpy(r21:20,r31:30):sat 0x90 0xde 0x94 0xe8 -# CHECK: r17:16 = vdmpy(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vdmpy(r21:20,r31:30):<<1:sat 0x90 0xde 0x14 0xea -# CHECK: r17:16 += vdmpy(r21:20, r31:30):sat +# CHECK: r17:16 += vdmpy(r21:20,r31:30):sat 0x90 0xde 0x94 0xea -# CHECK: r17:16 += vdmpy(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vdmpy(r21:20,r31:30):<<1:sat # Vector dual multiply with round and pack 0x11 0xde 0x14 0xe9 -# CHECK: r17 = vdmpy(r21:20, r31:30):rnd:sat +# CHECK: r17 = vdmpy(r21:20,r31:30):rnd:sat 0x11 0xde 0x94 0xe9 -# CHECK: r17 = vdmpy(r21:20, r31:30):<<1:rnd:sat +# CHECK: r17 = vdmpy(r21:20,r31:30):<<1:rnd:sat # Vector reduce multiply bytes 0x30 0xde 0x94 0xe8 -# CHECK: r17:16 = vrmpybu(r21:20, r31:30) +# CHECK: r17:16 = vrmpybu(r21:20,r31:30) 0x30 0xde 0xd4 0xe8 -# CHECK: r17:16 = vrmpybsu(r21:20, r31:30) +# CHECK: r17:16 = vrmpybsu(r21:20,r31:30) 0x30 0xde 0x94 0xea -# CHECK: r17:16 += vrmpybu(r21:20, r31:30) +# CHECK: r17:16 += vrmpybu(r21:20,r31:30) 0x30 0xde 0xd4 0xea -# CHECK: r17:16 += vrmpybsu(r21:20, r31:30) +# CHECK: r17:16 += vrmpybsu(r21:20,r31:30) # Vector dual multiply signed by unsigned bytes 0x30 0xde 0xb4 0xe8 -# CHECK: r17:16 = vdmpybsu(r21:20, r31:30):sat +# CHECK: r17:16 = vdmpybsu(r21:20,r31:30):sat 0x30 0xde 0x34 0xea -# CHECK: r17:16 += vdmpybsu(r21:20, r31:30):sat +# CHECK: r17:16 += vdmpybsu(r21:20,r31:30):sat # Vector multiply even haldwords 0xd0 0xde 0x14 0xe8 -# CHECK: r17:16 = vmpyeh(r21:20, r31:30):sat +# CHECK: r17:16 = vmpyeh(r21:20,r31:30):sat 0xd0 0xde 0x94 0xe8 -# CHECK: r17:16 = vmpyeh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 = vmpyeh(r21:20,r31:30):<<1:sat 0x50 0xde 0x34 0xea -# CHECK: r17:16 += vmpyeh(r21:20, r31:30) +# CHECK: r17:16 += vmpyeh(r21:20,r31:30) 0xd0 0xde 0x14 0xea -# CHECK: r17:16 += vmpyeh(r21:20, r31:30):sat +# CHECK: r17:16 += vmpyeh(r21:20,r31:30):sat 0xd0 0xde 0x94 0xea -# CHECK: r17:16 += vmpyeh(r21:20, r31:30):<<1:sat +# CHECK: r17:16 += vmpyeh(r21:20,r31:30):<<1:sat # Vector multiply halfwords 0xb0 0xdf 0x15 0xe5 -# CHECK: r17:16 = vmpyh(r21, r31):sat +# CHECK: r17:16 = vmpyh(r21,r31):sat 0xb0 0xdf 0x95 0xe5 -# CHECK: r17:16 = vmpyh(r21, r31):<<1:sat +# CHECK: r17:16 = vmpyh(r21,r31):<<1:sat 0x30 0xdf 0x35 0xe7 -# CHECK: r17:16 += vmpyh(r21, r31) +# CHECK: r17:16 += vmpyh(r21,r31) 0xb0 0xdf 0x15 0xe7 -# CHECK: r17:16 += vmpyh(r21, r31):sat +# CHECK: r17:16 += vmpyh(r21,r31):sat 0xb0 0xdf 0x95 0xe7 -# CHECK: r17:16 += vmpyh(r21, r31):<<1:sat +# CHECK: r17:16 += vmpyh(r21,r31):<<1:sat # Vector multiply halfwords with round and pack 0xf1 0xdf 0x35 0xed -# CHECK: r17 = vmpyh(r21, r31):rnd:sat +# CHECK: r17 = vmpyh(r21,r31):rnd:sat 0xf1 0xdf 0xb5 0xed -# CHECK: r17 = vmpyh(r21, r31):<<1:rnd:sat +# CHECK: r17 = vmpyh(r21,r31):<<1:rnd:sat # Vector multiply halfwords signed by unsigned 0xf0 0xdf 0x15 0xe5 -# CHECK: r17:16 = vmpyhsu(r21, r31):sat +# CHECK: r17:16 = vmpyhsu(r21,r31):sat 0xf0 0xdf 0x95 0xe5 -# CHECK: r17:16 = vmpyhsu(r21, r31):<<1:sat +# CHECK: r17:16 = vmpyhsu(r21,r31):<<1:sat 0xb0 0xdf 0x75 0xe7 -# CHECK: r17:16 += vmpyhsu(r21, r31):sat +# CHECK: r17:16 += vmpyhsu(r21,r31):sat 0xb0 0xdf 0xf5 0xe7 -# CHECK: r17:16 += vmpyhsu(r21, r31):<<1:sat +# CHECK: r17:16 += vmpyhsu(r21,r31):<<1:sat # Vector reduce multiply halfwords 0x50 0xde 0x14 0xe8 -# CHECK: r17:16 = vrmpyh(r21:20, r31:30) +# CHECK: r17:16 = vrmpyh(r21:20,r31:30) 0x50 0xde 0x14 0xea -# CHECK: r17:16 += vrmpyh(r21:20, r31:30) +# CHECK: r17:16 += vrmpyh(r21:20,r31:30) # Vector multiply bytes 0x30 0xdf 0x55 0xe5 -# CHECK: r17:16 = vmpybsu(r21, r31) +# CHECK: r17:16 = vmpybsu(r21,r31) 0x30 0xdf 0x95 0xe5 -# CHECK: r17:16 = vmpybu(r21, r31) +# CHECK: r17:16 = vmpybu(r21,r31) 0x30 0xdf 0x95 0xe7 -# CHECK: r17:16 += vmpybu(r21, r31) +# CHECK: r17:16 += vmpybu(r21,r31) 0x30 0xdf 0xd5 0xe7 -# CHECK: r17:16 += vmpybsu(r21, r31) +# CHECK: r17:16 += vmpybsu(r21,r31) # Vector polynomial multiply halfwords 0xf0 0xdf 0xd5 0xe5 -# CHECK: r17:16 = vpmpyh(r21, r31) +# CHECK: r17:16 = vpmpyh(r21,r31) 0xf0 0xdf 0xb5 0xe7 -# CHECK: r17:16 ^= vpmpyh(r21, r31) +# CHECK: r17:16 ^= vpmpyh(r21,r31) diff --git a/test/MC/Disassembler/Hexagon/xtype_perm.txt b/test/MC/Disassembler/Hexagon/xtype_perm.txt index 91d2fc5ae69..e8173fb049c 100644 --- a/test/MC/Disassembler/Hexagon/xtype_perm.txt +++ b/test/MC/Disassembler/Hexagon/xtype_perm.txt @@ -3,7 +3,7 @@ # CABAC decode bin 0xd0 0xde 0xd4 0xc1 -# CHECK: r17:16 = decbin(r21:20, r31:30) +# CHECK: r17:16 = decbin(r21:20,r31:30) # Saturate 0x11 0xc0 0xd4 0x88 @@ -23,9 +23,9 @@ # Vector align 0x70 0xd4 0x1e 0xc2 -# CHECK: r17:16 = valignb(r21:20, r31:30, p3) +# CHECK: r17:16 = valignb(r21:20,r31:30,p3) 0x70 0xde 0x94 0xc2 -# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3) +# CHECK: r17:16 = vspliceb(r21:20,r31:30,p3) # Vector round and pack 0x91 0xc0 0x94 0x88 @@ -59,13 +59,13 @@ # Vector shuffle 0x50 0xde 0x14 0xc1 -# CHECK: r17:16 = shuffeb(r21:20, r31:30) +# CHECK: r17:16 = shuffeb(r21:20,r31:30) 0x90 0xd4 0x1e 0xc1 -# CHECK: r17:16 = shuffob(r21:20, r31:30) +# CHECK: r17:16 = shuffob(r21:20,r31:30) 0xd0 0xde 0x14 0xc1 -# CHECK: r17:16 = shuffeh(r21:20, r31:30) +# CHECK: r17:16 = shuffeh(r21:20,r31:30) 0x10 0xd4 0x9e 0xc1 -# CHECK: r17:16 = shuffoh(r21:20, r31:30) +# CHECK: r17:16 = shuffoh(r21:20,r31:30) # Vector splat bytes 0xf1 0xc0 0x55 0x8c @@ -77,9 +77,9 @@ # Vector splice 0x70 0xde 0x94 0xc0 -# CHECK: r17:16 = vspliceb(r21:20, r31:30, #3) +# CHECK: r17:16 = vspliceb(r21:20,r31:30,#3) 0x70 0xde 0x94 0xc2 -# CHECK: r17:16 = vspliceb(r21:20, r31:30, p3) +# CHECK: r17:16 = vspliceb(r21:20,r31:30,p3) # Vector sign extend 0x10 0xc0 0x15 0x84 @@ -93,9 +93,9 @@ 0x51 0xc0 0x94 0x88 # CHECK: r17 = vtrunehb(r21:20) 0x50 0xde 0x94 0xc1 -# CHECK: r17:16 = vtrunewh(r21:20, r31:30) +# CHECK: r17:16 = vtrunewh(r21:20,r31:30) 0x90 0xde 0x94 0xc1 -# CHECK: r17:16 = vtrunowh(r21:20, r31:30) +# CHECK: r17:16 = vtrunowh(r21:20,r31:30) # Vector zero extend 0x50 0xc0 0x15 0x84 diff --git a/test/MC/Disassembler/Hexagon/xtype_pred.txt b/test/MC/Disassembler/Hexagon/xtype_pred.txt index cec6d1be0f1..816eef58a09 100644 --- a/test/MC/Disassembler/Hexagon/xtype_pred.txt +++ b/test/MC/Disassembler/Hexagon/xtype_pred.txt @@ -3,59 +3,59 @@ # Bounds check 0x83 0xf4 0x10 0xd2 -# CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo +# CHECK: p3 = boundscheck(r17:16,r21:20):raw:lo 0xa3 0xf4 0x10 0xd2 -# CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi +# CHECK: p3 = boundscheck(r17:16,r21:20):raw:hi # Compare byte 0x43 0xd5 0xd1 0xc7 -# CHECK: p3 = cmpb.gt(r17, r21) +# CHECK: p3 = cmpb.gt(r17,r21) 0xc3 0xd5 0xd1 0xc7 -# CHECK: p3 = cmpb.eq(r17, r21) +# CHECK: p3 = cmpb.eq(r17,r21) 0xe3 0xd5 0xd1 0xc7 -# CHECK: p3 = cmpb.gtu(r17, r21) +# CHECK: p3 = cmpb.gtu(r17,r21) 0xa3 0xc2 0x11 0xdd -# CHECK: p3 = cmpb.eq(r17, #21) +# CHECK: p3 = cmpb.eq(r17,#21) 0xa3 0xc2 0x31 0xdd -# CHECK: p3 = cmpb.gt(r17, #21) +# CHECK: p3 = cmpb.gt(r17,#21) 0xa3 0xc2 0x51 0xdd -# CHECK: p3 = cmpb.gtu(r17, #21) +# CHECK: p3 = cmpb.gtu(r17,#21) # Compare half 0x63 0xd5 0xd1 0xc7 -# CHECK: p3 = cmph.eq(r17, r21) +# CHECK: p3 = cmph.eq(r17,r21) 0x83 0xd5 0xd1 0xc7 -# CHECK: p3 = cmph.gt(r17, r21) +# CHECK: p3 = cmph.gt(r17,r21) 0xa3 0xd5 0xd1 0xc7 -# CHECK: p3 = cmph.gtu(r17, r21) +# CHECK: p3 = cmph.gtu(r17,r21) 0xab 0xc2 0x11 0xdd -# CHECK: p3 = cmph.eq(r17, #21) +# CHECK: p3 = cmph.eq(r17,#21) 0xab 0xc2 0x31 0xdd -# CHECK: p3 = cmph.gt(r17, #21) +# CHECK: p3 = cmph.gt(r17,#21) 0xab 0xc2 0x51 0xdd -# CHECK: p3 = cmph.gtu(r17, #21) +# CHECK: p3 = cmph.gtu(r17,#21) # Compare doublewords 0x03 0xde 0x94 0xd2 -# CHECK: p3 = cmp.eq(r21:20, r31:30) +# CHECK: p3 = cmp.eq(r21:20,r31:30) 0x43 0xde 0x94 0xd2 -# CHECK: p3 = cmp.gt(r21:20, r31:30) +# CHECK: p3 = cmp.gt(r21:20,r31:30) 0x83 0xde 0x94 0xd2 -# CHECK: p3 = cmp.gtu(r21:20, r31:30) +# CHECK: p3 = cmp.gtu(r21:20,r31:30) # Compare bitmask 0x03 0xd5 0x91 0x85 -# CHECK: p3 = bitsclr(r17, #21) +# CHECK: p3 = bitsclr(r17,#21) 0x03 0xd5 0xb1 0x85 -# CHECK: p3 = !bitsclr(r17, #21) +# CHECK: p3 = !bitsclr(r17,#21) 0x03 0xd5 0x51 0xc7 -# CHECK: p3 = bitsset(r17, r21) +# CHECK: p3 = bitsset(r17,r21) 0x03 0xd5 0x71 0xc7 -# CHECK: p3 = !bitsset(r17, r21) +# CHECK: p3 = !bitsset(r17,r21) 0x03 0xd5 0x91 0xc7 -# CHECK: p3 = bitsclr(r17, r21) +# CHECK: p3 = bitsclr(r17,r21) 0x03 0xd5 0xb1 0xc7 -# CHECK: p3 = !bitsclr(r17, r21) +# CHECK: p3 = !bitsclr(r17,r21) # mask generate from predicate 0x10 0xc3 0x00 0x86 @@ -63,7 +63,7 @@ # Check for TLB match 0x63 0xf5 0x10 0xd2 -# CHECK: p3 = tlbmatch(r17:16, r21) +# CHECK: p3 = tlbmatch(r17:16,r21) # Predicate Transfer 0x03 0xc0 0x45 0x85 @@ -73,64 +73,64 @@ # Test bit 0x03 0xd5 0x11 0x85 -# CHECK: p3 = tstbit(r17, #21) +# CHECK: p3 = tstbit(r17,#21) 0x03 0xd5 0x31 0x85 -# CHECK: p3 = !tstbit(r17, #21) +# CHECK: p3 = !tstbit(r17,#21) 0x03 0xd5 0x11 0xc7 -# CHECK: p3 = tstbit(r17, r21) +# CHECK: p3 = tstbit(r17,r21) 0x03 0xd5 0x31 0xc7 -# CHECK: p3 = !tstbit(r17, r21) +# CHECK: p3 = !tstbit(r17,r21) # Vector compare halfwords 0x63 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.eq(r21:20, r31:30) +# CHECK: p3 = vcmph.eq(r21:20,r31:30) 0x83 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.gt(r21:20, r31:30) +# CHECK: p3 = vcmph.gt(r21:20,r31:30) 0xa3 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.gtu(r21:20, r31:30) +# CHECK: p3 = vcmph.gtu(r21:20,r31:30) 0xeb 0xc3 0x14 0xdc -# CHECK: p3 = vcmph.eq(r21:20, #31) +# CHECK: p3 = vcmph.eq(r21:20,#31) 0xeb 0xc3 0x34 0xdc -# CHECK: p3 = vcmph.gt(r21:20, #31) +# CHECK: p3 = vcmph.gt(r21:20,#31) 0xeb 0xc3 0x54 0xdc -# CHECK: p3 = vcmph.gtu(r21:20, #31) +# CHECK: p3 = vcmph.gtu(r21:20,#31) # Vector compare bytes for any match 0x03 0xfe 0x14 0xd2 -# CHECK: p3 = any8(vcmpb.eq(r21:20, r31:30)) +# CHECK: p3 = any8(vcmpb.eq(r21:20,r31:30)) # Vector compare bytes 0x63 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.eq(r21:20, r31:30) +# CHECK: p3 = vcmph.eq(r21:20,r31:30) 0x83 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.gt(r21:20, r31:30) +# CHECK: p3 = vcmph.gt(r21:20,r31:30) 0xa3 0xde 0x14 0xd2 -# CHECK: p3 = vcmph.gtu(r21:20, r31:30) +# CHECK: p3 = vcmph.gtu(r21:20,r31:30) 0xeb 0xc3 0x14 0xdc -# CHECK: p3 = vcmph.eq(r21:20, #31) +# CHECK: p3 = vcmph.eq(r21:20,#31) 0xeb 0xc3 0x34 0xdc -# CHECK: p3 = vcmph.gt(r21:20, #31) +# CHECK: p3 = vcmph.gt(r21:20,#31) 0xeb 0xc3 0x54 0xdc -# CHECK: p3 = vcmph.gtu(r21:20, #31) +# CHECK: p3 = vcmph.gtu(r21:20,#31) # Vector compare words 0x03 0xde 0x14 0xd2 -# CHECK: p3 = vcmpw.eq(r21:20, r31:30) +# CHECK: p3 = vcmpw.eq(r21:20,r31:30) 0x23 0xde 0x14 0xd2 -# CHECK: p3 = vcmpw.gt(r21:20, r31:30) +# CHECK: p3 = vcmpw.gt(r21:20,r31:30) 0x43 0xde 0x14 0xd2 -# CHECK: p3 = vcmpw.gtu(r21:20, r31:30) +# CHECK: p3 = vcmpw.gtu(r21:20,r31:30) 0xf3 0xc3 0x14 0xdc -# CHECK: p3 = vcmpw.eq(r21:20, #31) +# CHECK: p3 = vcmpw.eq(r21:20,#31) 0xf3 0xc3 0x34 0xdc -# CHECK: p3 = vcmpw.gt(r21:20, #31) +# CHECK: p3 = vcmpw.gt(r21:20,#31) 0xf3 0xc3 0x54 0xdc -# CHECK: p3 = vcmpw.gtu(r21:20, #31) +# CHECK: p3 = vcmpw.gtu(r21:20,#31) # Viterbi pack even and odd predicate bits 0x11 0xc2 0x03 0x89 -# CHECK: r17 = vitpack(p3, p2) +# CHECK: r17 = vitpack(p3,p2) # Vector mux 0x70 0xde 0x14 0xd1 -# CHECK: r17:16 = vmux(p3, r21:20, r31:30) +# CHECK: r17:16 = vmux(p3,r21:20,r31:30) diff --git a/test/MC/Disassembler/Hexagon/xtype_shift.txt b/test/MC/Disassembler/Hexagon/xtype_shift.txt index e2d6816c1ca..d5688c962cf 100644 --- a/test/MC/Disassembler/Hexagon/xtype_shift.txt +++ b/test/MC/Disassembler/Hexagon/xtype_shift.txt @@ -3,258 +3,258 @@ # Shift by immediate 0x10 0xdf 0x14 0x80 -# CHECK: r17:16 = asr(r21:20, #31) +# CHECK: r17:16 = asr(r21:20,#31) 0x30 0xdf 0x14 0x80 -# CHECK: r17:16 = lsr(r21:20, #31) +# CHECK: r17:16 = lsr(r21:20,#31) 0x50 0xdf 0x14 0x80 -# CHECK: r17:16 = asl(r21:20, #31) +# CHECK: r17:16 = asl(r21:20,#31) 0x11 0xdf 0x15 0x8c -# CHECK: r17 = asr(r21, #31) +# CHECK: r17 = asr(r21,#31) 0x31 0xdf 0x15 0x8c -# CHECK: r17 = lsr(r21, #31) +# CHECK: r17 = lsr(r21,#31) 0x51 0xdf 0x15 0x8c -# CHECK: r17 = asl(r21, #31) +# CHECK: r17 = asl(r21,#31) # Shift by immediate and accumulate 0x10 0xdf 0x14 0x82 -# CHECK: r17:16 -= asr(r21:20, #31) +# CHECK: r17:16 -= asr(r21:20,#31) 0x30 0xdf 0x14 0x82 -# CHECK: r17:16 -= lsr(r21:20, #31) +# CHECK: r17:16 -= lsr(r21:20,#31) 0x50 0xdf 0x14 0x82 -# CHECK: r17:16 -= asl(r21:20, #31) +# CHECK: r17:16 -= asl(r21:20,#31) 0x90 0xdf 0x14 0x82 -# CHECK: r17:16 += asr(r21:20, #31) +# CHECK: r17:16 += asr(r21:20,#31) 0xb0 0xdf 0x14 0x82 -# CHECK: r17:16 += lsr(r21:20, #31) +# CHECK: r17:16 += lsr(r21:20,#31) 0xd0 0xdf 0x14 0x82 -# CHECK: r17:16 += asl(r21:20, #31) +# CHECK: r17:16 += asl(r21:20,#31) 0x11 0xdf 0x15 0x8e -# CHECK: r17 -= asr(r21, #31) +# CHECK: r17 -= asr(r21,#31) 0x31 0xdf 0x15 0x8e -# CHECK: r17 -= lsr(r21, #31) +# CHECK: r17 -= lsr(r21,#31) 0x51 0xdf 0x15 0x8e -# CHECK: r17 -= asl(r21, #31) +# CHECK: r17 -= asl(r21,#31) 0x91 0xdf 0x15 0x8e -# CHECK: r17 += asr(r21, #31) +# CHECK: r17 += asr(r21,#31) 0xb1 0xdf 0x15 0x8e -# CHECK: r17 += lsr(r21, #31) +# CHECK: r17 += lsr(r21,#31) 0xd1 0xdf 0x15 0x8e -# CHECK: r17 += asl(r21, #31) +# CHECK: r17 += asl(r21,#31) 0x4c 0xf7 0x11 0xde -# CHECK: r17 = add(#21, asl(r17, #23)) +# CHECK: r17 = add(#21,asl(r17,#23)) 0x4e 0xf7 0x11 0xde -# CHECK: r17 = sub(#21, asl(r17, #23)) +# CHECK: r17 = sub(#21,asl(r17,#23)) 0x5c 0xf7 0x11 0xde -# CHECK: r17 = add(#21, lsr(r17, #23)) +# CHECK: r17 = add(#21,lsr(r17,#23)) 0x5e 0xf7 0x11 0xde -# CHECK: r17 = sub(#21, lsr(r17, #23)) +# CHECK: r17 = sub(#21,lsr(r17,#23)) # Shift by immediate and add 0xf1 0xd5 0x1f 0xc4 -# CHECK: r17 = addasl(r21, r31, #7) +# CHECK: r17 = addasl(r21,r31,#7) # Shift by immediate and logical 0x10 0xdf 0x54 0x82 -# CHECK: r17:16 &= asr(r21:20, #31) +# CHECK: r17:16 &= asr(r21:20,#31) 0x30 0xdf 0x54 0x82 -# CHECK: r17:16 &= lsr(r21:20, #31) +# CHECK: r17:16 &= lsr(r21:20,#31) 0x50 0xdf 0x54 0x82 -# CHECK: r17:16 &= asl(r21:20, #31) +# CHECK: r17:16 &= asl(r21:20,#31) 0x90 0xdf 0x54 0x82 -# CHECK: r17:16 |= asr(r21:20, #31) +# CHECK: r17:16 |= asr(r21:20,#31) 0xb0 0xdf 0x54 0x82 -# CHECK: r17:16 |= lsr(r21:20, #31) +# CHECK: r17:16 |= lsr(r21:20,#31) 0xd0 0xdf 0x54 0x82 -# CHECK: r17:16 |= asl(r21:20, #31) +# CHECK: r17:16 |= asl(r21:20,#31) 0x30 0xdf 0x94 0x82 -# CHECK: r17:16 ^= lsr(r21:20, #31) +# CHECK: r17:16 ^= lsr(r21:20,#31) 0x50 0xdf 0x94 0x82 -# CHECK: r17:16 ^= asl(r21:20, #31) +# CHECK: r17:16 ^= asl(r21:20,#31) 0x11 0xdf 0x55 0x8e -# CHECK: r17 &= asr(r21, #31) +# CHECK: r17 &= asr(r21,#31) 0x31 0xdf 0x55 0x8e -# CHECK: r17 &= lsr(r21, #31) +# CHECK: r17 &= lsr(r21,#31) 0x51 0xdf 0x55 0x8e -# CHECK: r17 &= asl(r21, #31) +# CHECK: r17 &= asl(r21,#31) 0x91 0xdf 0x55 0x8e -# CHECK: r17 |= asr(r21, #31) +# CHECK: r17 |= asr(r21,#31) 0xb1 0xdf 0x55 0x8e -# CHECK: r17 |= lsr(r21, #31) +# CHECK: r17 |= lsr(r21,#31) 0xd1 0xdf 0x55 0x8e -# CHECK: r17 |= asl(r21, #31) +# CHECK: r17 |= asl(r21,#31) 0x31 0xdf 0x95 0x8e -# CHECK: r17 ^= lsr(r21, #31) +# CHECK: r17 ^= lsr(r21,#31) 0x51 0xdf 0x95 0x8e -# CHECK: r17 ^= asl(r21, #31) +# CHECK: r17 ^= asl(r21,#31) 0x48 0xff 0x11 0xde -# CHECK: r17 = and(#21, asl(r17, #31)) +# CHECK: r17 = and(#21,asl(r17,#31)) 0x4a 0xff 0x11 0xde -# CHECK: r17 = or(#21, asl(r17, #31)) +# CHECK: r17 = or(#21,asl(r17,#31)) 0x58 0xff 0x11 0xde -# CHECK: r17 = and(#21, lsr(r17, #31)) +# CHECK: r17 = and(#21,lsr(r17,#31)) 0x5a 0xff 0x11 0xde -# CHECK: r17 = or(#21, lsr(r17, #31)) +# CHECK: r17 = or(#21,lsr(r17,#31)) # Shift right by immediate with rounding 0xf0 0xdf 0xd4 0x80 -# CHECK: r17:16 = asr(r21:20, #31):rnd +# CHECK: r17:16 = asr(r21:20,#31):rnd 0x11 0xdf 0x55 0x8c -# CHECK: r17 = asr(r21, #31):rnd +# CHECK: r17 = asr(r21,#31):rnd # Shift left by immediate with saturation 0x51 0xdf 0x55 0x8c -# CHECK: r17 = asl(r21, #31):sat +# CHECK: r17 = asl(r21,#31):sat # Shift by register 0x10 0xdf 0x94 0xc3 -# CHECK: r17:16 = asr(r21:20, r31) +# CHECK: r17:16 = asr(r21:20,r31) 0x50 0xdf 0x94 0xc3 -# CHECK: r17:16 = lsr(r21:20, r31) +# CHECK: r17:16 = lsr(r21:20,r31) 0x90 0xdf 0x94 0xc3 -# CHECK: r17:16 = asl(r21:20, r31) +# CHECK: r17:16 = asl(r21:20,r31) 0xd0 0xdf 0x94 0xc3 -# CHECK: r17:16 = lsl(r21:20, r31) +# CHECK: r17:16 = lsl(r21:20,r31) 0x11 0xdf 0x55 0xc6 -# CHECK: r17 = asr(r21, r31) +# CHECK: r17 = asr(r21,r31) 0x51 0xdf 0x55 0xc6 -# CHECK: r17 = lsr(r21, r31) +# CHECK: r17 = lsr(r21,r31) 0x91 0xdf 0x55 0xc6 -# CHECK: r17 = asl(r21, r31) +# CHECK: r17 = asl(r21,r31) 0xd1 0xdf 0x55 0xc6 -# CHECK: r17 = lsl(r21, r31) +# CHECK: r17 = lsl(r21,r31) 0xf1 0xdf 0x8a 0xc6 -# CHECK: r17 = lsl(#21, r31) +# CHECK: r17 = lsl(#21,r31) # Shift by register and accumulate 0x10 0xdf 0x94 0xcb -# CHECK: r17:16 -= asr(r21:20, r31) +# CHECK: r17:16 -= asr(r21:20,r31) 0x50 0xdf 0x94 0xcb -# CHECK: r17:16 -= lsr(r21:20, r31) +# CHECK: r17:16 -= lsr(r21:20,r31) 0x90 0xdf 0x94 0xcb -# CHECK: r17:16 -= asl(r21:20, r31) +# CHECK: r17:16 -= asl(r21:20,r31) 0xd0 0xdf 0x94 0xcb -# CHECK: r17:16 -= lsl(r21:20, r31) +# CHECK: r17:16 -= lsl(r21:20,r31) 0x10 0xdf 0xd4 0xcb -# CHECK: r17:16 += asr(r21:20, r31) +# CHECK: r17:16 += asr(r21:20,r31) 0x50 0xdf 0xd4 0xcb -# CHECK: r17:16 += lsr(r21:20, r31) +# CHECK: r17:16 += lsr(r21:20,r31) 0x90 0xdf 0xd4 0xcb -# CHECK: r17:16 += asl(r21:20, r31) +# CHECK: r17:16 += asl(r21:20,r31) 0xd0 0xdf 0xd4 0xcb -# CHECK: r17:16 += lsl(r21:20, r31) +# CHECK: r17:16 += lsl(r21:20,r31) 0x11 0xdf 0x95 0xcc -# CHECK: r17 -= asr(r21, r31) +# CHECK: r17 -= asr(r21,r31) 0x51 0xdf 0x95 0xcc -# CHECK: r17 -= lsr(r21, r31) +# CHECK: r17 -= lsr(r21,r31) 0x91 0xdf 0x95 0xcc -# CHECK: r17 -= asl(r21, r31) +# CHECK: r17 -= asl(r21,r31) 0xd1 0xdf 0x95 0xcc -# CHECK: r17 -= lsl(r21, r31) +# CHECK: r17 -= lsl(r21,r31) 0x11 0xdf 0xd5 0xcc -# CHECK: r17 += asr(r21, r31) +# CHECK: r17 += asr(r21,r31) 0x51 0xdf 0xd5 0xcc -# CHECK: r17 += lsr(r21, r31) +# CHECK: r17 += lsr(r21,r31) 0x91 0xdf 0xd5 0xcc -# CHECK: r17 += asl(r21, r31) +# CHECK: r17 += asl(r21,r31) 0xd1 0xdf 0xd5 0xcc -# CHECK: r17 += lsl(r21, r31) +# CHECK: r17 += lsl(r21,r31) # Shift by register and logical 0x10 0xdf 0x14 0xcb -# CHECK: r17:16 |= asr(r21:20, r31) +# CHECK: r17:16 |= asr(r21:20,r31) 0x50 0xdf 0x14 0xcb -# CHECK: r17:16 |= lsr(r21:20, r31) +# CHECK: r17:16 |= lsr(r21:20,r31) 0x90 0xdf 0x14 0xcb -# CHECK: r17:16 |= asl(r21:20, r31) +# CHECK: r17:16 |= asl(r21:20,r31) 0xd0 0xdf 0x14 0xcb -# CHECK: r17:16 |= lsl(r21:20, r31) +# CHECK: r17:16 |= lsl(r21:20,r31) 0x10 0xdf 0x54 0xcb -# CHECK: r17:16 &= asr(r21:20, r31) +# CHECK: r17:16 &= asr(r21:20,r31) 0x50 0xdf 0x54 0xcb -# CHECK: r17:16 &= lsr(r21:20, r31) +# CHECK: r17:16 &= lsr(r21:20,r31) 0x90 0xdf 0x54 0xcb -# CHECK: r17:16 &= asl(r21:20, r31) +# CHECK: r17:16 &= asl(r21:20,r31) 0xd0 0xdf 0x54 0xcb -# CHECK: r17:16 &= lsl(r21:20, r31) +# CHECK: r17:16 &= lsl(r21:20,r31) 0x10 0xdf 0x74 0xcb -# CHECK: r17:16 ^= asr(r21:20, r31) +# CHECK: r17:16 ^= asr(r21:20,r31) 0x50 0xdf 0x74 0xcb -# CHECK: r17:16 ^= lsr(r21:20, r31) +# CHECK: r17:16 ^= lsr(r21:20,r31) 0x90 0xdf 0x74 0xcb -# CHECK: r17:16 ^= asl(r21:20, r31) +# CHECK: r17:16 ^= asl(r21:20,r31) 0xd0 0xdf 0x74 0xcb -# CHECK: r17:16 ^= lsl(r21:20, r31) +# CHECK: r17:16 ^= lsl(r21:20,r31) 0x11 0xdf 0x15 0xcc -# CHECK: r17 |= asr(r21, r31) +# CHECK: r17 |= asr(r21,r31) 0x51 0xdf 0x15 0xcc -# CHECK: r17 |= lsr(r21, r31) +# CHECK: r17 |= lsr(r21,r31) 0x91 0xdf 0x15 0xcc -# CHECK: r17 |= asl(r21, r31) +# CHECK: r17 |= asl(r21,r31) 0xd1 0xdf 0x15 0xcc -# CHECK: r17 |= lsl(r21, r31) +# CHECK: r17 |= lsl(r21,r31) 0x11 0xdf 0x55 0xcc -# CHECK: r17 &= asr(r21, r31) +# CHECK: r17 &= asr(r21,r31) 0x51 0xdf 0x55 0xcc -# CHECK: r17 &= lsr(r21, r31) +# CHECK: r17 &= lsr(r21,r31) 0x91 0xdf 0x55 0xcc -# CHECK: r17 &= asl(r21, r31) +# CHECK: r17 &= asl(r21,r31) 0xd1 0xdf 0x55 0xcc -# CHECK: r17 &= lsl(r21, r31) +# CHECK: r17 &= lsl(r21,r31) # Shift by register with saturation 0x11 0xdf 0x15 0xc6 -# CHECK: r17 = asr(r21, r31):sat +# CHECK: r17 = asr(r21,r31):sat 0x91 0xdf 0x15 0xc6 -# CHECK: r17 = asl(r21, r31):sat +# CHECK: r17 = asl(r21,r31):sat # Vector shift halfwords by immediate 0x10 0xc5 0x94 0x80 -# CHECK: r17:16 = vasrh(r21:20, #5) +# CHECK: r17:16 = vasrh(r21:20,#5) 0x30 0xc5 0x94 0x80 -# CHECK: r17:16 = vlsrh(r21:20, #5) +# CHECK: r17:16 = vlsrh(r21:20,#5) 0x50 0xc5 0x94 0x80 -# CHECK: r17:16 = vaslh(r21:20, #5) +# CHECK: r17:16 = vaslh(r21:20,#5) # Vector arithmetic shift halfwords with round 0x10 0xc5 0x34 0x80 -# CHECK: r17:16 = vasrh(r21:20, #5):raw +# CHECK: r17:16 = vasrh(r21:20,#5):raw # Vector arithmetic shift halfwords with saturate and pack 0x91 0xc5 0x74 0x88 -# CHECK: r17 = vasrhub(r21:20, #5):raw +# CHECK: r17 = vasrhub(r21:20,#5):raw 0xb1 0xc5 0x74 0x88 -# CHECK: r17 = vasrhub(r21:20, #5):sat +# CHECK: r17 = vasrhub(r21:20,#5):sat # Vector shift halfwords by register 0x10 0xdf 0x54 0xc3 -# CHECK: r17:16 = vasrh(r21:20, r31) +# CHECK: r17:16 = vasrh(r21:20,r31) 0x50 0xdf 0x54 0xc3 -# CHECK: r17:16 = vlsrh(r21:20, r31) +# CHECK: r17:16 = vlsrh(r21:20,r31) 0x90 0xdf 0x54 0xc3 -# CHECK: r17:16 = vaslh(r21:20, r31) +# CHECK: r17:16 = vaslh(r21:20,r31) 0xd0 0xdf 0x54 0xc3 -# CHECK: r17:16 = vlslh(r21:20, r31) +# CHECK: r17:16 = vlslh(r21:20,r31) # Vector shift words by immediate 0x10 0xdf 0x54 0x80 -# CHECK: r17:16 = vasrw(r21:20, #31) +# CHECK: r17:16 = vasrw(r21:20,#31) 0x30 0xdf 0x54 0x80 -# CHECK: r17:16 = vlsrw(r21:20, #31) +# CHECK: r17:16 = vlsrw(r21:20,#31) 0x50 0xdf 0x54 0x80 -# CHECK: r17:16 = vaslw(r21:20, #31) +# CHECK: r17:16 = vaslw(r21:20,#31) # Vector shift words by register 0x10 0xdf 0x14 0xc3 -# CHECK: r17:16 = vasrw(r21:20, r31) +# CHECK: r17:16 = vasrw(r21:20,r31) 0x50 0xdf 0x14 0xc3 -# CHECK: r17:16 = vlsrw(r21:20, r31) +# CHECK: r17:16 = vlsrw(r21:20,r31) 0x90 0xdf 0x14 0xc3 -# CHECK: r17:16 = vaslw(r21:20, r31) +# CHECK: r17:16 = vaslw(r21:20,r31) 0xd0 0xdf 0x14 0xc3 -# CHECK: r17:16 = vlslw(r21:20, r31) +# CHECK: r17:16 = vlslw(r21:20,r31) # Vector shift words with truncate and pack 0x51 0xdf 0xd4 0x88 -# CHECK: r17 = vasrw(r21:20, #31) +# CHECK: r17 = vasrw(r21:20,#31) 0x51 0xdf 0x14 0xc5 -# CHECK: r17 = vasrw(r21:20, r31) +# CHECK: r17 = vasrw(r21:20,r31) diff --git a/test/MC/Hexagon/align.s b/test/MC/Hexagon/align.s index 01a112392ed..80cebf125ce 100644 --- a/test/MC/Hexagon/align.s +++ b/test/MC/Hexagon/align.s @@ -3,7 +3,7 @@ # Verify that the .align directive emits the proper insn packets. { r1 = sub(#1, r1) } -# CHECK: 76414021 { r1 = sub(#1, r1) +# CHECK: 76414021 { r1 = sub(#1,r1) # CHECK-NEXT: 7f004000 nop # CHECK-NEXT: 7f004000 nop # CHECK-NEXT: 7f00c000 nop } @@ -11,8 +11,8 @@ .align 16 { r1 = sub(#1, r1) r2 = sub(#1, r2) } -# CHECK: 76414021 { r1 = sub(#1, r1) -# CHECK-NEXT: 76424022 r2 = sub(#1, r2) +# CHECK: 76414021 { r1 = sub(#1,r1) +# CHECK-NEXT: 76424022 r2 = sub(#1,r2) # CHECK-NEXT: 7f004000 nop # CHECK-NEXT: 7f00c000 nop } @@ -20,7 +20,7 @@ { r1 = sub(#1, r1) r2 = sub(#1, r2) r3 = sub(#1, r3) } -# CHECK: 76434023 r3 = sub(#1, r3) +# CHECK: 76434023 r3 = sub(#1,r3) # CHECK-NEXT: 7f00c000 nop } .align 16 @@ -33,13 +33,13 @@ # CHECK: 9200c020 { r0 = vextract(v0,r0) } r0 = vextract(v0, r0) .align 128 -# CHECK: 76414021 { r1 = sub(#1, r1) +# CHECK: 76414021 { r1 = sub(#1,r1) # CHECK-NEXT: 7f00c000 nop } { r1 = sub(#1, r1) } -#CHECK: { r1 = sub(#1, r1) -#CHECK: r2 = sub(#1, r2) -#CHECK: r3 = sub(#1, r3) } +#CHECK: { r1 = sub(#1,r1) +#CHECK: r2 = sub(#1,r2) +#CHECK: r3 = sub(#1,r3) } .falign .align 8 { r1 = sub(#1, r1) @@ -47,14 +47,14 @@ r0 = vextract(v0, r0) r3 = sub(#1, r3) } # CHECK: { immext(#0) -# CHECK: r0 = sub(##1, r0) +# CHECK: r0 = sub(##1,r0) # CHECK: immext(#0) -# CHECK: r1 = sub(##1, r1) } +# CHECK: r1 = sub(##1,r1) } # CHECK: { nop # CHECK: nop # CHECK: nop } -# CHECK: { r0 = sub(#1, r0) } +# CHECK: { r0 = sub(#1,r0) } { r0 = sub (##1, r0) r1 = sub (##1, r1) } .align 16 -{ r0 = sub (#1, r0) }
\ No newline at end of file +{ r0 = sub (#1, r0) } diff --git a/test/MC/Hexagon/asmMap.s b/test/MC/Hexagon/asmMap.s index f9dc0afc47c..4a2ca2499cc 100644 --- a/test/MC/Hexagon/asmMap.s +++ b/test/MC/Hexagon/asmMap.s @@ -2,607 +2,607 @@ # Make sure that the assembler mapped instructions are being handled correctly. -#CHECK: 3c56c000 { memw(r22{{ *}}+{{ *}}#0)=#0 +#CHECK: 3c56c000 { memw(r22+#0) = #0 memw(r22)=#0 -#CHECK: 3c23e05f { memh(r3{{ *}}+{{ *}}#0)=#-33 +#CHECK: 3c23e05f { memh(r3+#0) = #-33 memh(r3)=#-33 -#CHECK: 3c07c012 { memb(r7{{ *}}+{{ *}}#0)=#18 +#CHECK: 3c07c012 { memb(r7+#0) = #18 memb(r7)=#18 -#CHECK: 4101c008 { if (p0) r8 = memb(r1{{ *}}+{{ *}}#0) +#CHECK: 4101c008 { if (p0) r8 = memb(r1+#0) if (p0) r8=memb(r1) -#CHECK: 4519d817 { if (!p3) r23 = memb(r25{{ *}}+{{ *}}#0) +#CHECK: 4519d817 { if (!p3) r23 = memb(r25+#0) if (!p3) r23=memb(r25) -#CHECK: 412dc002 { if (p0) r2 = memub(r13{{ *}}+{{ *}}#0) +#CHECK: 412dc002 { if (p0) r2 = memub(r13+#0) if (p0) r2=memub(r13) -#CHECK: 453cc01a { if (!p0) r26 = memub(r28{{ *}}+{{ *}}#0) +#CHECK: 453cc01a { if (!p0) r26 = memub(r28+#0) if (!p0) r26=memub(r28) -#CHECK: 416bc818 { if (p1) r24 = memuh(r11{{ *}}+{{ *}}#0) +#CHECK: 416bc818 { if (p1) r24 = memuh(r11+#0) if (p1) r24=memuh(r11) -#CHECK: 457fc012 { if (!p0) r18 = memuh(r31{{ *}}+{{ *}}#0) +#CHECK: 457fc012 { if (!p0) r18 = memuh(r31+#0) if (!p0) r18=memuh(r31) -#CHECK: 455dc014 { if (!p0) r20 = memh(r29{{ *}}+{{ *}}#0) +#CHECK: 455dc014 { if (!p0) r20 = memh(r29+#0) if (!p0) r20=memh(r29) -#CHECK: 415dc01d { if (p0) r29 = memh(r29{{ *}}+{{ *}}#0) +#CHECK: 415dc01d { if (p0) r29 = memh(r29+#0) if (p0) r29=memh(r29) -#CHECK: 4583c01d { if (!p0) r29 = memw(r3{{ *}}+{{ *}}#0) +#CHECK: 4583c01d { if (!p0) r29 = memw(r3+#0) if (!p0) r29=memw(r3) -#CHECK: 419bd01e { if (p2) r30 = memw(r27{{ *}}+{{ *}}#0) +#CHECK: 419bd01e { if (p2) r30 = memw(r27+#0) if (p2) r30=memw(r27) -#CHECK: 90e2c018 { r25:24 = membh(r2{{ *}}+{{ *}}#0) +#CHECK: 90e2c018 { r25:24 = membh(r2+#0) r25:24=membh(r2) -#CHECK: 902bc006 { r6 = membh(r11{{ *}}+{{ *}}#0) +#CHECK: 902bc006 { r6 = membh(r11+#0) r6=membh(r11) -#CHECK: 90a2c01c { r29:28 = memubh(r2{{ *}}+{{ *}}#0) +#CHECK: 90a2c01c { r29:28 = memubh(r2+#0) r29:28=memubh(r2) -#CHECK: 906ec00d { r13 = memubh(r14{{ *}}+{{ *}}#0) +#CHECK: 906ec00d { r13 = memubh(r14+#0) r13=memubh(r14) -#CHECK: 91dac00c { r13:12 = memd(r26{{ *}}+{{ *}}#0) +#CHECK: 91dac00c { r13:12 = memd(r26+#0) r13:12=memd(r26) -#CHECK: 919bc004 { r4 = memw(r27{{ *}}+{{ *}}#0) +#CHECK: 919bc004 { r4 = memw(r27+#0) r4=memw(r27) -#CHECK: 914cc005 { r5 = memh(r12{{ *}}+{{ *}}#0) +#CHECK: 914cc005 { r5 = memh(r12+#0) r5=memh(r12) -#CHECK: 9176c010 { r16 = memuh(r22{{ *}}+{{ *}}#0) +#CHECK: 9176c010 { r16 = memuh(r22+#0) r16=memuh(r22) -#CHECK: 910bc017 { r23 = memb(r11{{ *}}+{{ *}}#0) +#CHECK: 910bc017 { r23 = memb(r11+#0) r23=memb(r11) -#CHECK: 912bc01b { r27 = memub(r11{{ *}}+{{ *}}#0) +#CHECK: 912bc01b { r27 = memub(r11+#0) r27=memub(r11) -#CHECK: 404ede01 { if (p1) memh(r14{{ *}}+{{ *}}#0) = r30 +#CHECK: 404ede01 { if (p1) memh(r14+#0) = r30 if (p1) memh(r14)=r30 -#CHECK: 4449d900 { if (!p0) memh(r9{{ *}}+{{ *}}#0) = r25 +#CHECK: 4449d900 { if (!p0) memh(r9+#0) = r25 if (!p0) memh(r9)=r25 -#CHECK: 400ecd00 { if (p0) memb(r14{{ *}}+{{ *}}#0) = r13 +#CHECK: 400ecd00 { if (p0) memb(r14+#0) = r13 if (p0) memb(r14)=r13 -#CHECK: 440bcc01 { if (!p1) memb(r11{{ *}}+{{ *}}#0) = r12 +#CHECK: 440bcc01 { if (!p1) memb(r11+#0) = r12 if (!p1) memb(r11)=r12 -#CHECK: 41d0d804 { if (p3) r5:4 = memd(r16{{ *}}+{{ *}}#0) +#CHECK: 41d0d804 { if (p3) r5:4 = memd(r16+#0) if (p3) r5:4=memd(r16) -#CHECK: 45d9c00c { if (!p0) r13:12 = memd(r25{{ *}}+{{ *}}#0) +#CHECK: 45d9c00c { if (!p0) r13:12 = memd(r25+#0) if (!p0) r13:12=memd(r25) -#CHECK: 385ee06d { if (p3) memw(r30{{ *}}+{{ *}}#0)=#-19 +#CHECK: 385ee06d { if (p3) memw(r30+#0) = #-19 if (p3) memw(r30)=#-19 -#CHECK: 38c6c053 { if (!p2) memw(r6{{ *}}+{{ *}}#0)=#19 +#CHECK: 38c6c053 { if (!p2) memw(r6+#0) = #19 if (!p2) memw(r6)=#19 -#CHECK: 381fc034 { if (p1) memb(r31{{ *}}+{{ *}}#0)=#20 +#CHECK: 381fc034 { if (p1) memb(r31+#0) = #20 if (p1) memb(r31)=#20 -#CHECK: 389dc010 { if (!p0) memb(r29{{ *}}+{{ *}}#0)=#16 +#CHECK: 389dc010 { if (!p0) memb(r29+#0) = #16 if (!p0) memb(r29)=#16 -#CHECK: 3833e019 { if (p0) memh(r19{{ *}}+{{ *}}#0)=#-7 +#CHECK: 3833e019 { if (p0) memh(r19+#0) = #-7 if (p0) memh(r19)=#-7 -#CHECK: 38b7c013 { if (!p0) memh(r23{{ *}}+{{ *}}#0)=#19 +#CHECK: 38b7c013 { if (!p0) memh(r23+#0) = #19 if (!p0) memh(r23)=#19 -#CHECK: 4488d401 { if (!p1) memw(r8{{ *}}+{{ *}}#0) = r20 +#CHECK: 4488d401 { if (!p1) memw(r8+#0) = r20 if (!p1) memw(r8)=r20 -#CHECK: 409ddc02 { if (p2) memw(r29{{ *}}+{{ *}}#0) = r28 +#CHECK: 409ddc02 { if (p2) memw(r29+#0) = r28 if (p2) memw(r29)=r28 -#CHECK: 446fc301 { if (!p1) memh(r15{{ *}}+{{ *}}#0) = r3.h +#CHECK: 446fc301 { if (!p1) memh(r15+#0) = r3.h if (!p1) memh(r15)=r3.h -#CHECK: 406dc201 { if (p1) memh(r13{{ *}}+{{ *}}#0) = r2.h +#CHECK: 406dc201 { if (p1) memh(r13+#0) = r2.h if (p1) memh(r13)=r2.h -#CHECK: 40d9c601 { if (p1) memd(r25{{ *}}+{{ *}}#0) = r7:6 +#CHECK: 40d9c601 { if (p1) memd(r25+#0) = r7:6 if (p1) memd(r25)=r7:6 -#CHECK: 44dad803 { if (!p3) memd(r26{{ *}}+{{ *}}#0) = r25:24 +#CHECK: 44dad803 { if (!p3) memd(r26+#0) = r25:24 if (!p3) memd(r26)=r25:24 -#CHECK: 3e21c011 { memh(r1{{ *}}+{{ *}}#0) {{ *}}+={{ *}} r17 +#CHECK: 3e21c011 { memh(r1+#0) += r17 memh(r1)+=r17 -#CHECK: 3e4fc019 { memw(r15{{ *}}+{{ *}}#0) {{ *}}+={{ *}} r25 +#CHECK: 3e4fc019 { memw(r15+#0) += r25 memw(r15)+=r25 -#CHECK: 3e5dc022 { memw(r29{{ *}}+{{ *}}#0) {{ *}}-={{ *}} r2 +#CHECK: 3e5dc022 { memw(r29+#0) -= r2 memw(r29)-=r2 -#CHECK: 3e04c004 { memb(r4{{ *}}+{{ *}}#0) {{ *}}+={{ *}} r4 +#CHECK: 3e04c004 { memb(r4+#0) += r4 memb(r4)+=r4 -#CHECK: 3f53c016 { memw(r19{{ *}}+{{ *}}#0){{ *}}{{ *}}+={{ *}}{{ *}}#22 +#CHECK: 3f53c016 { memw(r19+#0) += #22 memw(r19)+=#22 -#CHECK: 3f24c01e { memh(r4{{ *}}+{{ *}}#0){{ *}}{{ *}}+={{ *}}{{ *}}#30 +#CHECK: 3f24c01e { memh(r4+#0) += #30 memh(r4)+=#30 -#CHECK: 3e27c02d { memh(r7{{ *}}+{{ *}}#0) {{ *}}-={{ *}} r13 +#CHECK: 3e27c02d { memh(r7+#0) -= r13 memh(r7)-=r13 -#CHECK: 3e1ec032 { memb(r30{{ *}}+{{ *}}#0) {{ *}}-={{ *}} r18 +#CHECK: 3e1ec032 { memb(r30+#0) -= r18 memb(r30)-=r18 -#CHECK: 3e49c05b { memw(r9{{ *}}+{{ *}}#0) &= r27 +#CHECK: 3e49c05b { memw(r9+#0) &= r27 memw(r9)&=r27 -#CHECK: 3e2dc040 { memh(r13{{ *}}+{{ *}}#0) &= r0 +#CHECK: 3e2dc040 { memh(r13+#0) &= r0 memh(r13)&=r0 -#CHECK: 3e05c046 { memb(r5{{ *}}+{{ *}}#0) &= r6 +#CHECK: 3e05c046 { memb(r5+#0) &= r6 memb(r5)&=r6 -#CHECK: 3e45c06a { memw(r5{{ *}}+{{ *}}#0) |= r10 +#CHECK: 3e45c06a { memw(r5+#0) |= r10 memw(r5)|=r10 -#CHECK: 3e21c07e { memh(r1{{ *}}+{{ *}}#0) |= r30 +#CHECK: 3e21c07e { memh(r1+#0) |= r30 memh(r1)|=r30 -#CHECK: 3e09c06f { memb(r9{{ *}}+{{ *}}#0) |= r15 +#CHECK: 3e09c06f { memb(r9+#0) |= r15 memb(r9)|=r15 -#CHECK: a157d100 { memh(r23{{ *}}+{{ *}}#0) = r17 +#CHECK: a157d100 { memh(r23+#0) = r17 memh(r23)=r17 -#CHECK: a10fd400 { memb(r15{{ *}}+{{ *}}#0) = r20 +#CHECK: a10fd400 { memb(r15+#0) = r20 memb(r15)=r20 -#CHECK: 9082c014 { r21:20 = memb_fifo(r2{{ *}}+{{ *}}#0) +#CHECK: 9082c014 { r21:20 = memb_fifo(r2+#0) r21:20=memb_fifo(r2) -#CHECK: 9056c01c { r29:28 = memh_fifo(r22{{ *}}+{{ *}}#0) +#CHECK: 9056c01c { r29:28 = memh_fifo(r22+#0) r29:28=memh_fifo(r22) -#CHECK: a1d8ca00 { memd(r24{{ *}}+{{ *}}#0) = r11:10 +#CHECK: a1d8ca00 { memd(r24+#0) = r11:10 memd(r24)=r11:10 -#CHECK: a19ed900 { memw(r30{{ *}}+{{ *}}#0) = r25 +#CHECK: a19ed900 { memw(r30+#0) = r25 memw(r30)=r25 -#CHECK: a169ce00 { memh(r9{{ *}}+{{ *}}#0) = r14.h +#CHECK: a169ce00 { memh(r9+#0) = r14.h memh(r9)=r14.h -#CHECK: 3f07c06b { memb(r7{{ *}}+{{ *}}#0) = setbit(#11) +#CHECK: 3f07c06b { memb(r7+#0) = setbit(#11) memb(r7)=setbit(#11) -#CHECK: 3f34c07b { memh(r20{{ *}}+{{ *}}#0) = setbit(#27) +#CHECK: 3f34c07b { memh(r20+#0) = setbit(#27) memh(r20)=setbit(#27) -#CHECK: 3f1cc032 { memb(r28{{ *}}+{{ *}}#0){{ *}}-={{ *}}#18 +#CHECK: 3f1cc032 { memb(r28+#0) -= #18 memb(r28)-=#18 -#CHECK: 3f29c02a { memh(r9{{ *}}+{{ *}}#0){{ *}}-={{ *}}#10 +#CHECK: 3f29c02a { memh(r9+#0) -= #10 memh(r9)-=#10 -#CHECK: 3f4cc026 { memw(r12{{ *}}+{{ *}}#0){{ *}}-={{ *}}#6 +#CHECK: 3f4cc026 { memw(r12+#0) -= #6 memw(r12)-=#6 -#CHECK: 3f00c00c { memb(r0{{ *}}+{{ *}}#0){{ *}}+={{ *}}#12 +#CHECK: 3f00c00c { memb(r0+#0) += #12 memb(r0)+=#12 -#CHECK: 3f50c07a { memw(r16{{ *}}+{{ *}}#0) = setbit(#26) +#CHECK: 3f50c07a { memw(r16+#0) = setbit(#26) memw(r16)=setbit(#26) -#CHECK: 3f1fc05d { memb(r31{{ *}}+{{ *}}#0) = clrbit(#29) +#CHECK: 3f1fc05d { memb(r31+#0) = clrbit(#29) memb(r31)=clrbit(#29) -#CHECK: 3f20c05e { memh(r0{{ *}}+{{ *}}#0) = clrbit(#30) +#CHECK: 3f20c05e { memh(r0+#0) = clrbit(#30) memh(r0)=clrbit(#30) -#CHECK: 3f42c059 { memw(r2{{ *}}+{{ *}}#0) = clrbit(#25) +#CHECK: 3f42c059 { memw(r2+#0) = clrbit(#25) memw(r2)=clrbit(#25) -#CHECK: 39cfe072 if (!p3.new) memw(r15{{ *}}+{{ *}}#0)=#-14 +#CHECK: 39cfe072 if (!p3.new) memw(r15+#0) = #-14 { p3=cmp.eq(r5,##-1997506977) if (!p3.new) memw(r15)=#-14 } -#CHECK: 3959e06b if (p3.new) memw(r25{{ *}}+{{ *}}#0)=#-21 +#CHECK: 3959e06b if (p3.new) memw(r25+#0) = #-21 { p3=cmp.eq(r0,##1863618461) if (p3.new) memw(r25)=#-21 } -#CHECK: 4312c801 if (p1.new) r1 = memb(r18{{ *}}+{{ *}}#0) +#CHECK: 4312c801 if (p1.new) r1 = memb(r18+#0) { if (p1.new) r1=memb(r18) p1=cmp.eq(r23,##-1105571618) } -#CHECK: 4718d803 if (!p3.new) r3 = memb(r24{{ *}}+{{ *}}#0) +#CHECK: 4718d803 if (!p3.new) r3 = memb(r24+#0) { if (!p3.new) r3=memb(r24) p3=cmp.eq(r3,##-210870878) } -#CHECK: 4326c81b if (p1.new) r27 = memub(r6{{ *}}+{{ *}}#0) +#CHECK: 4326c81b if (p1.new) r27 = memub(r6+#0) { if (p1.new) r27=memub(r6) p1=cmp.eq(r29,##-188410493) } -#CHECK: 473ad00d if (!p2.new) r13 = memub(r26{{ *}}+{{ *}}#0) +#CHECK: 473ad00d if (!p2.new) r13 = memub(r26+#0) { p2=cmp.eq(r30,##-1823852150) if (!p2.new) r13=memub(r26) } -#CHECK: 4785d80e if (!p3.new) r14 = memw(r5{{ *}}+{{ *}}#0) +#CHECK: 4785d80e if (!p3.new) r14 = memw(r5+#0) { if (!p3.new) r14=memw(r5) p3=cmp.eq(r31,##-228524711) } -#CHECK: 438cc81a if (p1.new) r26 = memw(r12{{ *}}+{{ *}}#0) +#CHECK: 438cc81a if (p1.new) r26 = memw(r12+#0) { if (p1.new) r26=memw(r12) p1=cmp.eq(r11,##-485232313) } -#CHECK: 477dc019 if (!p0.new) r25 = memuh(r29{{ *}}+{{ *}}#0) +#CHECK: 477dc019 if (!p0.new) r25 = memuh(r29+#0) { p0=cmp.eq(r23,##127565957) if (!p0.new) r25=memuh(r29) } -#CHECK: 4377c807 if (p1.new) r7 = memuh(r23{{ *}}+{{ *}}#0) +#CHECK: 4377c807 if (p1.new) r7 = memuh(r23+#0) { p1=cmp.eq(r30,##-222020054) if (p1.new) r7=memuh(r23) } -#CHECK: 4754c81c if (!p1.new) r28 = memh(r20{{ *}}+{{ *}}#0) +#CHECK: 4754c81c if (!p1.new) r28 = memh(r20+#0) { p1=cmp.eq(r18,##1159699785) if (!p1.new) r28=memh(r20) } -#CHECK: 435ec01b if (p0.new) r27 = memh(r30{{ *}}+{{ *}}#0) +#CHECK: 435ec01b if (p0.new) r27 = memh(r30+#0) { p0=cmp.eq(r7,##-1114567705) if (p0.new) r27=memh(r30) } -#CHECK: 420dd100 if (p0.new) memb(r13{{ *}}+{{ *}}#0) = r17 +#CHECK: 420dd100 if (p0.new) memb(r13+#0) = r17 { p0=cmp.eq(r21,##-1458796638) if (p0.new) memb(r13)=r17 } -#CHECK: 4601d602 if (!p2.new) memb(r1{{ *}}+{{ *}}#0) = r22 +#CHECK: 4601d602 if (!p2.new) memb(r1+#0) = r22 { p2=cmp.eq(r20,##-824022439) if (!p2.new) memb(r1)=r22 } -#CHECK: 43dcd808 if (p3.new) r9:8 = memd(r28{{ *}}+{{ *}}#0) +#CHECK: 43dcd808 if (p3.new) r9:8 = memd(r28+#0) { p3=cmp.eq(r13,##56660744) if (p3.new) r9:8=memd(r28) } -#CHECK: 47d8c80e if (!p1.new) r15:14 = memd(r24{{ *}}+{{ *}}#0) +#CHECK: 47d8c80e if (!p1.new) r15:14 = memd(r24+#0) { if (!p1.new) r15:14=memd(r24) p1=cmp.eq(r15,##1536716489) } -#CHECK: 3918e045 if (p2.new) memb(r24{{ *}}+{{ *}}#0)=#-27 +#CHECK: 3918e045 if (p2.new) memb(r24+#0) = #-27 { if (p2.new) memb(r24)=#-27 p2=cmp.eq(r21,##1741091811) } -#CHECK: 398fe04d if (!p2.new) memb(r15{{ *}}+{{ *}}#0)=#-19 +#CHECK: 398fe04d if (!p2.new) memb(r15+#0) = #-19 { if (!p2.new) memb(r15)=#-19 p2=cmp.eq(r15,##779870261) } -#CHECK: 3931c04b if (p2.new) memh(r17{{ *}}+{{ *}}#0)=#11 +#CHECK: 3931c04b if (p2.new) memh(r17+#0) = #11 { if (p2.new) memh(r17)=#11 p2=cmp.eq(r13,##-1171145798) } -#CHECK: 39aee056 if (!p2.new) memh(r14{{ *}}+{{ *}}#0)=#-10 +#CHECK: 39aee056 if (!p2.new) memh(r14+#0) = #-10 { p2=cmp.eq(r23,##-633976762) if (!p2.new) memh(r14)=#-10 } -#CHECK: 4692df01 if (!p1.new) memw(r18{{ *}}+{{ *}}#0) = r31 +#CHECK: 4692df01 if (!p1.new) memw(r18+#0) = r31 { if (!p1.new) memw(r18)=r31 p1=cmp.eq(r11,##-319375732) } -#CHECK: 428dc402 if (p2.new) memw(r13{{ *}}+{{ *}}#0) = r4 +#CHECK: 428dc402 if (p2.new) memw(r13+#0) = r4 { if (p2.new) memw(r13)=r4 p2=cmp.eq(r18,##1895120239) } -#CHECK: 4670c300 if (!p0.new) memh(r16{{ *}}+{{ *}}#0) = r3.h +#CHECK: 4670c300 if (!p0.new) memh(r16+#0) = r3.h { p0=cmp.eq(r25,##1348715015) if (!p0.new) memh(r16)=r3.h } -#CHECK: 426ddf02 if (p2.new) memh(r13{{ *}}+{{ *}}#0) = r31.h +#CHECK: 426ddf02 if (p2.new) memh(r13+#0) = r31.h { p2=cmp.eq(r25,##1085560657) if (p2.new) memh(r13)=r31.h } -#CHECK: 464bcb01 if (!p1.new) memh(r11{{ *}}+{{ *}}#0) = r11 +#CHECK: 464bcb01 if (!p1.new) memh(r11+#0) = r11 { p1=cmp.eq(r10,##1491455911) if (!p1.new) memh(r11)=r11 } -#CHECK: 4248d200 if (p0.new) memh(r8{{ *}}+{{ *}}#0) = r18 +#CHECK: 4248d200 if (p0.new) memh(r8+#0) = r18 { p0=cmp.eq(r3,##687581160) if (p0.new) memh(r8)=r18 } -#CHECK: 42deca00 if (p0.new) memd(r30{{ *}}+{{ *}}#0) = r11:10 +#CHECK: 42deca00 if (p0.new) memd(r30+#0) = r11:10 { if (p0.new) memd(r30)=r11:10 p0=cmp.eq(r28,##562796189) } -#CHECK: 46d5cc03 if (!p3.new) memd(r21{{ *}}+{{ *}}#0) = r13:12 +#CHECK: 46d5cc03 if (!p3.new) memd(r21+#0) = r13:12 { if (!p3.new) memd(r21)=r13:12 p3=cmp.eq(r6,##-969273288) } -#CHECK: 42bad201 if (p1.new) memw(r26{{ *}}+{{ *}}#0) = r22.new +#CHECK: 42bad201 if (p1.new) memw(r26+#0) = r22.new { if (p1.new) memw(r26)=r22.new p1=cmp.eq(r0,##-1110065473) r22=add(r28,r9) } -#CHECK: 46b9d201 if (!p1.new) memw(r25{{ *}}+{{ *}}#0) = r26.new +#CHECK: 46b9d201 if (!p1.new) memw(r25+#0) = r26.new { p1=cmp.eq(r11,##-753121346) r26=add(r19,r7) if (!p1.new) memw(r25)=r26.new } -#CHECK: 40aad200 if (p0) memw(r10{{ *}}+{{ *}}#0) = r6.new +#CHECK: 40aad200 if (p0) memw(r10+#0) = r6.new { r6=add(r30,r0) if (p0) memw(r10)=r6.new } -#CHECK: 44a6d202 if (!p2) memw(r6{{ *}}+{{ *}}#0) = r4.new +#CHECK: 44a6d202 if (!p2) memw(r6+#0) = r4.new { if (!p2) memw(r6)=r4.new r4=add(r0,r3) } -#CHECK: 40b9c200 if (p0) memb(r25{{ *}}+{{ *}}#0) = r29.new +#CHECK: 40b9c200 if (p0) memb(r25+#0) = r29.new { if (p0) memb(r25)=r29.new r29=add(r27,r30) } -#CHECK: 44bec203 if (!p3) memb(r30{{ *}}+{{ *}}#0) = r8.new +#CHECK: 44bec203 if (!p3) memb(r30+#0) = r8.new { if (!p3) memb(r30)=r8.new r8=add(r24,r4) } -#CHECK: 46aecc01 if (!p1.new) memh(r14{{ *}}+{{ *}}#0) = r13.new +#CHECK: 46aecc01 if (!p1.new) memh(r14+#0) = r13.new { if (!p1.new) memh(r14)=r13.new r13=add(r21,r2) p1=cmp.eq(r3,##-1529345886) } -#CHECK: 42bcca02 if (p2.new) memh(r28{{ *}}+{{ *}}#0) = r18.new +#CHECK: 42bcca02 if (p2.new) memh(r28+#0) = r18.new { p2=cmp.eq(r15,##2048545649) if (p2.new) memh(r28)=r18.new r18=add(r9,r3) } -#CHECK: 46aac200 if (!p0.new) memb(r10{{ *}}+{{ *}}#0) = r30.new +#CHECK: 46aac200 if (!p0.new) memb(r10+#0) = r30.new { p0=cmp.eq(r21,##-1160401822) r30=add(r9,r22) if (!p0.new) memb(r10)=r30.new } -#CHECK: 42b8c202 if (p2.new) memb(r24{{ *}}+{{ *}}#0) = r11.new +#CHECK: 42b8c202 if (p2.new) memb(r24+#0) = r11.new { if (p2.new) memb(r24)=r11.new p2=cmp.eq(r30,##1267977346) r11=add(r8,r18) } -#CHECK: 44a3ca00 if (!p0) memh(r3{{ *}}+{{ *}}#0) = r28.new +#CHECK: 44a3ca00 if (!p0) memh(r3+#0) = r28.new { r28=add(r16,r11) if (!p0) memh(r3)=r28.new } -#CHECK: 40abca03 if (p3) memh(r11{{ *}}+{{ *}}#0) = r24.new +#CHECK: 40abca03 if (p3) memh(r11+#0) = r24.new { if (p3) memh(r11)=r24.new r24=add(r18,r19) } -#CHECK: a1abd200 memw(r11{{ *}}+{{ *}}#0) = r5.new +#CHECK: a1abd200 memw(r11+#0) = r5.new { memw(r11)=r5.new r5=add(r0,r10) } -#CHECK: a1a2ca00 memh(r2{{ *}}+{{ *}}#0) = r18.new +#CHECK: a1a2ca00 memh(r2+#0) = r18.new { r18=add(r27,r18) memh(r2)=r18.new } -#CHECK: a1bac200 memb(r26{{ *}}+{{ *}}#0) = r15.new +#CHECK: a1bac200 memb(r26+#0) = r15.new { r15=add(r22,r17) memb(r26)=r15.new } -#CHECK: d328ce1c { r29:28{{ *}}={{ *}}vsubub(r15:14, r9:8) +#CHECK: d328ce1c { r29:28 = vsubub(r15:14,r9:8) r29:28=vsubb(r15:14,r9:8) -#CHECK: 8c5ed60c { r12{{ *}}={{ *}}asr(r30, #22):rnd +#CHECK: 8c5ed60c { r12 = asr(r30,#22):rnd r12=asrrnd(r30,#23) -#CHECK: ed1ec109 { r9{{ *}}={{ *}}mpyi(r30, r1) +#CHECK: ed1ec109 { r9 = mpyi(r30,r1) r9=mpyui(r30,r1) -#CHECK: e010d787 { r7{{ *}}={{ *}}+{{ *}}mpyi(r16, #188) +#CHECK: e010d787 { r7 = +mpyi(r16,#188) r7=mpyi(r16,#188) -#CHECK: d206eea2 { p2{{ *}}={{ *}}boundscheck(r7:6, r15:14):raw:hi +#CHECK: d206eea2 { p2 = boundscheck(r7:6,r15:14):raw:hi p2=boundscheck(r7,r15:14) -#CHECK: f27ac102 { p2{{ *}}={{ *}}cmp.gtu(r26, r1) +#CHECK: f27ac102 { p2 = cmp.gtu(r26,r1) p2=cmp.ltu(r1,r26) -#CHECK: f240df00 { p0{{ *}}={{ *}}cmp.gt(r0, r31) +#CHECK: f240df00 { p0 = cmp.gt(r0,r31) p0=cmp.lt(r31,r0) -#CHECK: 7586cc01 { p1{{ *}}={{ *}}cmp.gtu(r6, #96) +#CHECK: 7586cc01 { p1 = cmp.gtu(r6,#96) p1=cmp.geu(r6,#97) -#CHECK: 755dc9a2 { p2{{ *}}={{ *}}cmp.gt(r29, #77) +#CHECK: 755dc9a2 { p2 = cmp.gt(r29,#77) p2=cmp.ge(r29,#78) -#CHECK: d310d60a { r11:10{{ *}}={{ *}}vaddub(r17:16, r23:22) +#CHECK: d310d60a { r11:10 = vaddub(r17:16,r23:22) r11:10=vaddb(r17:16,r23:22) -#CHECK: 8753d1e6 { r6{{ *}}={{ *}}tableidxh(r19, #7, #17):raw +#CHECK: 8753d1e6 { r6 = tableidxh(r19,#7,#17):raw r6=tableidxh(r19,#7,#18) -#CHECK: 8786d277 { r23{{ *}}={{ *}}tableidxw(r6, #3, #18):raw +#CHECK: 8786d277 { r23 = tableidxw(r6,#3,#18):raw r23=tableidxw(r6,#3,#20) -#CHECK: 7c4dfff8 { r25:24{{ *}}={{ *}}combine(#-1, #-101) +#CHECK: 7c4dfff8 { r25:24 = combine(#-1,#-101) r25:24=#-101 -#CHECK: 8866c09a { r26{{ *}}={{ *}}vasrhub(r7:6, #0):raw +#CHECK: 8866c09a { r26 = vasrhub(r7:6,#0):raw r26=vasrhub(r7:6,#1):rnd:sat -#CHECK: 7654c016 { r22{{ *}}={{ *}}sub(#0, r20) +#CHECK: 7654c016 { r22 = sub(#0,r20) r22=neg(r20) -#CHECK: 802cc808 { r9:8{{ *}}={{ *}}vasrh(r13:12, #8):raw +#CHECK: 802cc808 { r9:8 = vasrh(r13:12,#8):raw r9:8=vasrh(r13:12,#9):rnd -#CHECK: 7614dfe5 { r5{{ *}}={{ *}}{{zxtb\(r20\)|and\(r20, *#255\)}} +#CHECK: 7614dfe5 { r5 = {{zxtb\(r20\)|and\(r20,#255\)}} r5=zxtb(r20) #CHECK: 00ab68e2 immext(#179976320) -#CHECK: 7500c500 p0{{ *}}={{ *}}cmp.eq(r0, ##179976360) +#CHECK: 7500c500 p0 = cmp.eq(r0,##179976360) { if (p0.new) r11=r26 p0=cmp.eq(r0,##179976360) } -#CHECK: 74f9c00f { if (!p3) r15{{ *}} ={{ *}}add(r25, #0) +#CHECK: 74f9c00f { if (!p3) r15 = add(r25,#0) if (!p3) r15=r25 -#CHECK: 7425c005 { if (p1) r5{{ *}}={{ *}}add(r5, #0) +#CHECK: 7425c005 { if (p1) r5 = add(r5,#0) if (p1) r5=r5 -#CHECK: e9badae2 { r2{{ *}}={{ *}}vrcmpys(r27:26, r27:26):<<1:rnd:sat:raw:lo +#CHECK: e9badae2 { r2 = vrcmpys(r27:26,r27:26):<<1:rnd:sat:raw:lo r2=vrcmpys(r27:26,r26):<<1:rnd:sat -#CHECK: fd13f20e if (p0.new) r15:14{{ *}}={{ *}}{{r19:18|combine\(r19, *r18\)}} +#CHECK: fd13f20e if (p0.new) r15:14 = {{r19:18|combine\(r19,r18\)}} { p0=cmp.eq(r26,##1766934387) if (p0.new) r15:14=r19:18 } -#CHECK: fd07c6c2 { if (!p2) r3:2{{ *}}={{ *}}{{r7:6|combine\(r7, *r6\)}} +#CHECK: fd07c6c2 { if (!p2) r3:2 = {{r7:6|combine\(r7,r6\)}} if (!p2) r3:2=r7:6 -#CHECK: fd0dcc7e { if (p3) r31:30{{ *}}={{ *}}{{r13:12|combine\(r13, *r12\)}} +#CHECK: fd0dcc7e { if (p3) r31:30 = {{r13:12|combine\(r13,r12\)}} if (p3) r31:30=r13:12 -#CHECK: 748ae015 if (!p0.new) r21{{ *}}={{ *}}add(r10, #0) +#CHECK: 748ae015 if (!p0.new) r21 = add(r10,#0) { p0=cmp.eq(r23,##805633208) if (!p0.new) r21=r10 } -#CHECK: d36ec6c8 { r9:8{{ *}}={{ *}}add(r15:14, r7:6):raw:lo +#CHECK: d36ec6c8 { r9:8 = add(r15:14,r7:6):raw:lo r9:8=add(r14,r7:6) #CHECK: 01e65477 immext(#509943232) -#CHECK: 7516c3a3 p3{{ *}}={{ *}}cmp.eq(r22, ##509943261) +#CHECK: 7516c3a3 p3 = cmp.eq(r22,##509943261) { - if (!p3.new) r9:8=r25:24 + if (!p3.new) r9:8 = r25:24 p3=cmp.eq(r22,##509943261) } -#CHECK: 87e0d5e5 { r5{{ *}}={{ *}}tableidxd(r0, #15, #21):raw +#CHECK: 87e0d5e5 { r5 = tableidxd(r0,#15,#21):raw r5=tableidxd(r0,#15,#24) -#CHECK: 8701db65 { r5{{ *}}={{ *}}tableidxb(r1, #3, #27):raw +#CHECK: 8701db65 { r5 = tableidxb(r1,#3,#27):raw r5=tableidxb(r1,#3,#27) -#CHECK: 767affe3 { r3{{ *}}={{ *}}sub(#-1, r26) +#CHECK: 767affe3 { r3 = sub(#-1,r26) r3=not(r26) -#CHECK: f51ddc06 { r7:6{{ *}}={{ *}}{{r29:28|combine\(r29, *r28\)}} +#CHECK: f51ddc06 { r7:6 = {{r29:28|combine\(r29,r28\)}} r7:6=r29:28 -#CHECK: 9406c000 { dcfetch(r6 + #0) +#CHECK: 9406c000 { dcfetch(r6+#0) dcfetch(r6) -#CHECK: 6b20c001 { p1{{ *}}={{ *}}or(p0, p0) +#CHECK: 6b20c001 { p1 = or(p0,p0) p1=p0 -#CHECK: eafcdc82 { r3:2 += vrcmpys(r29:28, r29:28):<<1:sat:raw:lo +#CHECK: eafcdc82 { r3:2 += vrcmpys(r29:28,r29:28):<<1:sat:raw:lo r3:2+=vrcmpys(r29:28,r28):<<1:sat -#CHECK: e8ead092 { r19:18{{ *}}={{ *}}vrcmpys(r11:10, r17:16):<<1:sat:raw:lo +#CHECK: e8ead092 { r19:18 = vrcmpys(r11:10,r17:16):<<1:sat:raw:lo r19:18=vrcmpys(r11:10,r16):<<1:sat -#CHECK: 9082c014 { r21:20{{ *}}={{ *}}memb_fifo(r2{{ *}}+{{ *}}#0) +#CHECK: 9082c014 { r21:20 = memb_fifo(r2+#0) r21:20=memb_fifo(r2) -#CHECK: 9056c01c { r29:28{{ *}}={{ *}}memh_fifo(r22{{ *}}+{{ *}}#0) +#CHECK: 9056c01c { r29:28 = memh_fifo(r22+#0) r29:28=memh_fifo(r22) diff --git a/test/MC/Hexagon/capitalizedEndloop.s b/test/MC/Hexagon/capitalizedEndloop.s index d20ff34de6f..c7a25d9fb27 100644 --- a/test/MC/Hexagon/capitalizedEndloop.s +++ b/test/MC/Hexagon/capitalizedEndloop.s @@ -15,7 +15,7 @@ { R0 = mpyi(R0,R0) } : ENDLOOP0 : ENDLOOP1 { R0 = mpyi(R0,R0) }:endloop0:endloop1 -# CHECK: r0 = mpyi(r0, r0) +# CHECK: r0 = mpyi(r0,r0) # CHECK: :endloop0 # CHECK: :endloop0 # CHECK: :endloop0 diff --git a/test/MC/Hexagon/duplex-registers.s b/test/MC/Hexagon/duplex-registers.s index f0cde7f9628..2a02b4534f2 100644 --- a/test/MC/Hexagon/duplex-registers.s +++ b/test/MC/Hexagon/duplex-registers.s @@ -7,4 +7,4 @@ } # CHECK: 289808ba -# CHECK: r16 = memuh(r17 + #0);{{ *}}r18 = memuh(r19 + #0) +# CHECK: r16 = memuh(r17+#0);{{ *}}r18 = memuh(r19+#0) diff --git a/test/MC/Hexagon/fixups.s b/test/MC/Hexagon/fixups.s index 059a18fa882..33913362df7 100644 --- a/test/MC/Hexagon/fixups.s +++ b/test/MC/Hexagon/fixups.s @@ -3,7 +3,7 @@ .text # CHECK-LABEL: 0: # CHECK: 2442e106 -# CHECK: if (!cmp.eq(r1.new, #1)) jump:t 0xc +# CHECK: if (!cmp.eq(r1.new,#1)) jump:t 0xc { r1 = zxth(r2) if (!cmp.eq(r1.new, #1)) jump:t .L1 @@ -15,7 +15,7 @@ # CHECK: 00004020 # CHECK: immext(#2048) # CHECK: 2442e118 -# CHECK: if (!cmp.eq(r1.new, #1)) jump:t 0x81c +# CHECK: if (!cmp.eq(r1.new,#1)) jump:t 0x81c { r1 = zxth(r2) if (!cmp.eq(r1.new, #1)) jump:t .L2 diff --git a/test/MC/Hexagon/iconst.s b/test/MC/Hexagon/iconst.s index 277c4de8692..917cc64ba95 100644 --- a/test/MC/Hexagon/iconst.s +++ b/test/MC/Hexagon/iconst.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d -r - | FileCheck %s a: -# CHECK: r0 = add(r0, #0) +# CHECK: r0 = add(r0,#0) # CHECK: R_HEX_23_REG -r0 = iconst(#a)
\ No newline at end of file +r0 = iconst(#a) diff --git a/test/MC/Hexagon/inst_cmp_eq.ll b/test/MC/Hexagon/inst_cmp_eq.ll index 98202368aff..5c483451d71 100644 --- a/test/MC/Hexagon/inst_cmp_eq.ll +++ b/test/MC/Hexagon/inst_cmp_eq.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: p0 = cmp.eq(r0, r1) +; CHECK: p0 = cmp.eq(r0,r1) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_eqi.ll b/test/MC/Hexagon/inst_cmp_eqi.ll index 612dfdc8f23..5d8132b70bb 100644 --- a/test/MC/Hexagon/inst_cmp_eqi.ll +++ b/test/MC/Hexagon/inst_cmp_eqi.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: p0 = cmp.eq(r0, #42) +; CHECK: p0 = cmp.eq(r0,#42) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_gt.ll b/test/MC/Hexagon/inst_cmp_gt.ll index 3ce1c0addad..45a4e33e940 100644 --- a/test/MC/Hexagon/inst_cmp_gt.ll +++ b/test/MC/Hexagon/inst_cmp_gt.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: p0 = cmp.gt(r0, r1) +; CHECK: p0 = cmp.gt(r0,r1) ; CHECK: r0 = p0 -; CHECK: jumpr r31 }
\ No newline at end of file +; CHECK: jumpr r31 } diff --git a/test/MC/Hexagon/inst_cmp_gti.ll b/test/MC/Hexagon/inst_cmp_gti.ll index f3c13a2fb96..67cdc4c909b 100644 --- a/test/MC/Hexagon/inst_cmp_gti.ll +++ b/test/MC/Hexagon/inst_cmp_gti.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: p0 = cmp.gt(r0, #42) +; CHECK: p0 = cmp.gt(r0,#42) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_lt.ll b/test/MC/Hexagon/inst_cmp_lt.ll index 80ba16f4141..b19a4a676aa 100644 --- a/test/MC/Hexagon/inst_cmp_lt.ll +++ b/test/MC/Hexagon/inst_cmp_lt.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: p0 = cmp.gt(r1, r0) +; CHECK: p0 = cmp.gt(r1,r0) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_ugt.ll b/test/MC/Hexagon/inst_cmp_ugt.ll index 07fa784dc64..7af40c6ed03 100644 --- a/test/MC/Hexagon/inst_cmp_ugt.ll +++ b/test/MC/Hexagon/inst_cmp_ugt.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: p0 = cmp.gtu(r0, r1) +; CHECK: p0 = cmp.gtu(r0,r1) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_ugti.ll b/test/MC/Hexagon/inst_cmp_ugti.ll index 59db552b39f..63d94e4ff87 100644 --- a/test/MC/Hexagon/inst_cmp_ugti.ll +++ b/test/MC/Hexagon/inst_cmp_ugti.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a) ret i1 %1 } -; CHECK: p0 = cmp.gtu(r0, #42) +; CHECK: p0 = cmp.gtu(r0,#42) ; CHECK: r0 = p0 ; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/inst_cmp_ult.ll b/test/MC/Hexagon/inst_cmp_ult.ll index c880ac8a229..ecda120a459 100644 --- a/test/MC/Hexagon/inst_cmp_ult.ll +++ b/test/MC/Hexagon/inst_cmp_ult.ll @@ -7,6 +7,6 @@ define i1 @foo (i32 %a, i32 %b) ret i1 %1 } -; CHECK: p0 = cmp.gtu(r1, r0) +; CHECK: p0 = cmp.gtu(r1,r0) ; CHECK: r0 = p0 -; CHECK: jumpr r31
\ No newline at end of file +; CHECK: jumpr r31 diff --git a/test/MC/Hexagon/instructions/system_user.s b/test/MC/Hexagon/instructions/system_user.s index f0ead9645dd..02c81fa0992 100644 --- a/test/MC/Hexagon/instructions/system_user.s +++ b/test/MC/Hexagon/instructions/system_user.s @@ -57,6 +57,3 @@ syncht # CHECK: 18 df 00 54 trap0(#254) - -# CHECK: 14 df 80 54 -trap1(#253) diff --git a/test/MC/Hexagon/jumpdoublepound.s b/test/MC/Hexagon/jumpdoublepound.s index 6b829360a90..8d0eef7fb60 100644 --- a/test/MC/Hexagon/jumpdoublepound.s +++ b/test/MC/Hexagon/jumpdoublepound.s @@ -7,7 +7,7 @@ mylabel: # CHECK: if (p0) jump if (p0) jump ##mylabel -# CHECK: if (cmp.gtu(r5.new, r4)) jump:t +# CHECK: if (cmp.gtu(r5.new,r4)) jump:t { r5 = r4 if (cmp.gtu(r5.new, r4)) jump:t ##mylabel } diff --git a/test/MC/Hexagon/labels.s b/test/MC/Hexagon/labels.s index d52ae004b07..f2b62d1412b 100644 --- a/test/MC/Hexagon/labels.s +++ b/test/MC/Hexagon/labels.s @@ -10,17 +10,17 @@ r1: # CHECK: nop r3:nop -# CHECK: r5:4 = combine(r5, r4) +# CHECK: r5:4 = combine(r5,r4) r5:4 = r5:4 # CHECK: r0 = r1 -# CHECK: p0 = tstbit(r0, #10) +# CHECK: p0 = tstbit(r0,#10) # CHECK: if (!p0) jump 1:r0=r1; p0=tstbit(r0, #10); if !p0 jump 1b; # CHECK: nop -# CHECK: r1 = add(r1, #4) -# CHECK: r5 = memw(r1 + #0) +# CHECK: r1 = add(r1,#4) +# CHECK: r5 = memw(r1+#0) # CHECK: endloop0 b: { r5 = memw(r1) - r1 = add(r1, #4) } : endloop0
\ No newline at end of file + r1 = add(r1, #4) } : endloop0 diff --git a/test/MC/Hexagon/register-alt-names.s b/test/MC/Hexagon/register-alt-names.s index 97bfd32c51d..3e514661887 100644 --- a/test/MC/Hexagon/register-alt-names.s +++ b/test/MC/Hexagon/register-alt-names.s @@ -9,6 +9,6 @@ r1 = fp # CHECK: r2 = r29 r2 = sp -# CHECK: r1:0 = combine(r31, r30) +# CHECK: r1:0 = combine(r31,r30) r1:0 = lr:fp diff --git a/test/MC/Hexagon/relaxed_newvalue.s b/test/MC/Hexagon/relaxed_newvalue.s index 65fbd312e0a..4e8c6cc2cbc 100644 --- a/test/MC/Hexagon/relaxed_newvalue.s +++ b/test/MC/Hexagon/relaxed_newvalue.s @@ -1,9 +1,9 @@ # RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s # Make sure relaxation doesn't hinder newvalue calculation -#CHECK: r18 = add(r2, #-6) +#CHECK: r18 = add(r2,#-6) #CHECK-NEXT: immext(#0) -#CHECK-NEXT: if (!cmp.gt(r18.new, #1)) jump:t +#CHECK-NEXT: if (!cmp.gt(r18.new,#1)) jump:t { r18 = add(r2, #-6) if (!cmp.gt(r18.new, #1)) jump:t .unknown diff --git a/test/MC/Hexagon/two-extenders.s b/test/MC/Hexagon/two-extenders.s index 49016639de1..31457927013 100644 --- a/test/MC/Hexagon/two-extenders.s +++ b/test/MC/Hexagon/two-extenders.s @@ -19,7 +19,7 @@ if (p3.new) r23 = memb(##2164335510) p3 = or(p2,or(p3, p0)) } -# CHECK: { p3 = or(p2, or(p3, p0)) +# CHECK: { p3 = or(p2,or(p3,p0)) # CHECK: immext(#2164335488) # CHECK: if (p3.new) r23 = memb(##2164335510) } diff --git a/test/MC/Hexagon/v60-misc.s b/test/MC/Hexagon/v60-misc.s index e16034948dc..b278447ab10 100644 --- a/test/MC/Hexagon/v60-misc.s +++ b/test/MC/Hexagon/v60-misc.s @@ -14,10 +14,10 @@ if (p2) jumpr r0 # CHECK: 5361c300 { if (!p3) jumpr:nt if (!p3) jumpr r1 -# CHECK: 1c2eceee { v14 = vxor(v14,{{ *}}v14) } +# CHECK: 1c2eceee { v14 = vxor(v14,v14) } v14 = #0 -# CHECK: 1c80c0a0 { v1:0.w = vsub(v1:0.w,v1:0.w) } +# CHECK: 1c9edea0 { v1:0.w = vsub(v31:30.w,v31:30.w) } v1:0 = #0 # CHECK: 1f42c3e0 { v1:0 = vcombine(v3,v2) } @@ -53,7 +53,7 @@ q0 = vcmp.eq(v8.uw, v9.uw) # CHECK: 1c8aea09 { q1 &= vcmp.eq(v10.w,v10.w) } q1 &= vcmp.eq(v10.uw, v10.uw) -# CHECK: 1c8ceb46 { q2 |= vcmp.eq(v11.h,v12.h) } +# CHECK: 1c8ceb4a { q2 |= vcmp.eq(v11.w,v12.w) } q2 |= vcmp.eq(v11.uw, v12.uw) # CHECK: 1c8eed8b { q3 ^= vcmp.eq(v13.w,v14.w) } diff --git a/test/MC/Hexagon/v60-vmem.s b/test/MC/Hexagon/v60-vmem.s index fe202251ec4..0580a1e6244 100644 --- a/test/MC/Hexagon/v60-vmem.s +++ b/test/MC/Hexagon/v60-vmem.s @@ -327,25 +327,25 @@ vmem(r6+#-6):nt=v16.new } -#CHECK: 28b1cd42 if(p1) vmem(r17+#5) = v17.new } +#CHECK: 28b1cd42 if (p1) vmem(r17+#5) = v17.new } { v17 = v25 if(p1)vmem(r17+#5)=v17.new } -#CHECK: 28bbeb6a if(!p1) vmem(r27+#-5) = v17.new } +#CHECK: 28bbeb6a if (!p1) vmem(r27+#-5) = v17.new } { v17 = v15 if(!p1)vmem(r27+#-5)=v17.new } -#CHECK: 28e4d252 if(p2) vmem(r4+#2):nt = v24.new } +#CHECK: 28e4d252 if (p2) vmem(r4+#2):nt = v24.new } { v24 = v10 if(p2)vmem(r4+#2):nt=v24.new } -#CHECK: 28f8d17a if(!p2) vmem(r24+#1):nt = v4.new } +#CHECK: 28f8d17a if (!p2) vmem(r24+#1):nt = v4.new } { v4 = v8 if(!p2)vmem(r24+#1):nt=v4.new @@ -363,25 +363,25 @@ vmem(r1++#1):nt=v7.new } -#CHECK: 29a6d042 if(p2) vmem(r6++#0) = v11.new } +#CHECK: 29a6d042 if (p2) vmem(r6++#0) = v11.new } { v11 = v13 if(p2)vmem(r6++#0)=v11.new } -#CHECK: 29a2cb6a if(!p1) vmem(r2++#3) = v25.new } +#CHECK: 29a2cb6a if (!p1) vmem(r2++#3) = v25.new } { v25 = v17 if(!p1)vmem(r2++#3)=v25.new } -#CHECK: 29f5c952 if(p1) vmem(r21++#1):nt = v14.new } +#CHECK: 29f5c952 if (p1) vmem(r21++#1):nt = v14.new } { v14 = v13 if(p1)vmem(r21++#1):nt=v14.new } -#CHECK: 29f7cd7a if(!p1) vmem(r23++#-3):nt = v1.new } +#CHECK: 29f7cd7a if (!p1) vmem(r23++#-3):nt = v1.new } { v1 = v0 if(!p1)vmem(r23++#-3):nt=v1.new @@ -399,25 +399,25 @@ vmem(r15++m0):nt=v19.new } -#CHECK: 2bb7f042 if(p2) vmem(r23++m1) = v6.new } +#CHECK: 2bb7f042 if (p2) vmem(r23++m1) = v6.new } { v6 = v30 if(p2)vmem(r23++m1)=v6.new } -#CHECK: 2ba2f06a if(!p2) vmem(r2++m1) = v12.new } +#CHECK: 2ba2f06a if (!p2) vmem(r2++m1) = v12.new } { v12 = v9 if(!p2)vmem(r2++m1)=v12.new } -#CHECK: 2be7e852 if(p1) vmem(r7++m1):nt = v3.new } +#CHECK: 2be7e852 if (p1) vmem(r7++m1):nt = v3.new } { v3 = v13 if(p1)vmem(r7++m1):nt=v3.new } -#CHECK: 2bfdd07a if(!p2) vmem(r29++m0):nt = v29.new } +#CHECK: 2bfdd07a if (!p2) vmem(r29++m0):nt = v29.new } { v29 = v9 if(!p2)vmem(r29++m0):nt=v29.new |