diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 9 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/rlwimi-dyn-and.ll | 48 |
2 files changed, 56 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 3bbc8397c92..de77ef94af5 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -458,8 +458,15 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; } if (Op1Opc == ISD::AND) { + // The AND mask might not be a constant, and we need to make sure that + // if we're going to fold the masking with the insert, all bits not + // know to be zero in the mask are known to be one. + APInt MKZ, MKO; + CurDAG->ComputeMaskedBits(Op1.getOperand(1), MKZ, MKO); + bool CanFoldMask = InsertMask == MKO.getZExtValue(); + unsigned SHOpc = Op1.getOperand(0).getOpcode(); - if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && + if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask && isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { // Note that Value must be in range here (less than 32) because // otherwise there would not be any bits set in InsertMask. diff --git a/test/CodeGen/PowerPC/rlwimi-dyn-and.ll b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll new file mode 100644 index 00000000000..e02801fafbf --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll @@ -0,0 +1,48 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @test1() #0 { +entry: + %conv67.reload = load i32* undef + %const = bitcast i32 65535 to i32 + br label %next + +next: + %shl161 = shl nuw nsw i32 %conv67.reload, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %const_mat = add i32 %const, -32767 + %shl161.masked = and i32 %shl161, %const_mat + %conv174 = or i32 %shl170, %shl161.masked + ret i32 %conv174 + +; CHECK-LABEL: @test1 +; CHECK-NOT: rlwimi 3, {{[0-9]+}}, 15, 0, 16 +; CHECK: blr +} + +define i32 @test2() #0 { +entry: + %conv67.reload = load i32* undef + %const = bitcast i32 65535 to i32 + br label %next + +next: + %shl161 = shl nuw nsw i32 %conv67.reload, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %shl161.masked = and i32 %shl161, 32768 + %conv174 = or i32 %shl170, %shl161.masked + ret i32 %conv174 + +; CHECK-LABEL: @test2 +; CHECK: slwi 3, {{[0-9]+}}, 7 +; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16 +; CHECK: blr +} + +attributes #0 = { nounwind } + |