diff options
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll | 23 |
2 files changed, 24 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index de2ac42ad51..c397ddcd3bc 100644 --- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -280,7 +280,7 @@ HexagonTargetLowering::LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); MVT SubVecTy = tyVector(ty(Ext), ElemTy); SDValue Ins = insertVector(DAG.getBitcast(SubVecTy, Ext), - ValV, SubIdx, dl, SubVecTy, DAG); + ValV, SubIdx, dl, ElemTy, DAG); // 3. Insert the 32-bit word back into the original vector. return InsertWord(VecV, Ins, ByteIdx); diff --git a/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll b/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll new file mode 100644 index 00000000000..22afa4a3c1f --- /dev/null +++ b/test/CodeGen/Hexagon/autohvx/lower-insert-elt.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; REQUIRES: asserts + +; Check that this testcase compiles successfully. +; CHECK: vextract + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon-unknown--elf" + +define void @fred() local_unnamed_addr #0 { +b0: + %v1 = load <64 x i8>, <64 x i8>* undef, align 64 + %v2 = insertelement <64 x i8> %v1, i8 0, i32 0 + br label %b3 + +b3: ; preds = %b3, %b0 + %v4 = phi <64 x i8> [ %v2, %b0 ], [ %v6, %b3 ] + %v5 = extractelement <64 x i8> %v4, i32 0 + %v6 = insertelement <64 x i8> %v4, i8 undef, i32 0 + br label %b3 +} + +attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } |