summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp96
-rw-r--r--test/CodeGen/PowerPC/testComparesigesll.ll128
-rw-r--r--test/CodeGen/PowerPC/testComparesilesll.ll130
-rw-r--r--test/CodeGen/PowerPC/testComparesllgesll.ll128
-rw-r--r--test/CodeGen/PowerPC/testCompareslllesll.ll138
5 files changed, 620 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1547646f1ff..c64aceceb65 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3216,6 +3216,8 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
+ bool IsRHSOne = RHSValue == 1;
+ bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: return SDValue();
case ISD::SETEQ: {
@@ -3242,6 +3244,51 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
Xor, AC.getValue(1)), 0);
}
+ case ISD::SETGE: {
+ // {subc.reg, subc.CA} = (subcarry %a, %b)
+ // (zext (setcc %a, %b, setge)) ->
+ // (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
+ // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
+ if (IsRHSZero)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
+ std::swap(LHS, RHS);
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+ IsRHSZero = RHSConst && RHSConst->isNullValue();
+ LLVM_FALLTHROUGH;
+ }
+ case ISD::SETLE: {
+ // {subc.reg, subc.CA} = (subcarry %b, %a)
+ // (zext (setcc %a, %b, setge)) ->
+ // (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
+ // (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
+ if (IsRHSZero)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
+ SDValue ShiftL =
+ SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
+ getI64Imm(1, dl), getI64Imm(63, dl)), 0);
+ SDValue ShiftR =
+ SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
+ getI64Imm(63, dl)), 0);
+ SDValue SubtractCarry =
+ SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
+ LHS, RHS), 1);
+ return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
+ ShiftR, ShiftL, SubtractCarry), 0);
+ }
+ case ISD::SETGT: {
+ if (IsRHSNegOne)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
+ std::swap(LHS, RHS);
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+ IsRHSZero = RHSConst && RHSConst->isNullValue();
+ IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
+ LLVM_FALLTHROUGH;
+ }
+ case ISD::SETLT: {
+ if (IsRHSOne)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
+ return SDValue();
+ }
}
}
@@ -3251,6 +3298,8 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
int64_t RHSValue, SDLoc dl) {
bool IsRHSZero = RHSValue == 0;
+ bool IsRHSOne = RHSValue == 1;
+ bool IsRHSNegOne = RHSValue == -1LL;
switch (CC) {
default: return SDValue();
case ISD::SETEQ: {
@@ -3279,6 +3328,53 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
SC, SC.getValue(1)), 0);
}
+ case ISD::SETGE: {
+ // {subc.reg, subc.CA} = (subcarry %a, %b)
+ // (zext (setcc %a, %b, setge)) ->
+ // (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
+ // (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
+ if (IsRHSZero)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
+ std::swap(LHS, RHS);
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+ IsRHSZero = RHSConst && RHSConst->isNullValue();
+ LLVM_FALLTHROUGH;
+ }
+ case ISD::SETLE: {
+ // {subc.reg, subc.CA} = (subcarry %b, %a)
+ // (zext (setcc %a, %b, setge)) ->
+ // (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
+ // (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
+ if (IsRHSZero)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
+ SDValue ShiftR =
+ SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
+ getI64Imm(63, dl)), 0);
+ SDValue ShiftL =
+ SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
+ getI64Imm(1, dl), getI64Imm(63, dl)), 0);
+ SDValue SubtractCarry =
+ SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
+ LHS, RHS), 1);
+ SDValue Adde =
+ SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
+ ShiftR, ShiftL, SubtractCarry), 0);
+ return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
+ }
+ case ISD::SETGT: {
+ if (IsRHSNegOne)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
+ std::swap(LHS, RHS);
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
+ IsRHSZero = RHSConst && RHSConst->isNullValue();
+ IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
+ LLVM_FALLTHROUGH;
+ }
+ case ISD::SETLT: {
+ if (IsRHSOne)
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
+ return SDValue();
+ }
}
}
diff --git a/test/CodeGen/PowerPC/testComparesigesll.ll b/test/CodeGen/PowerPC/testComparesigesll.ll
new file mode 100644
index 00000000000..95be923b88a
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_igesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define signext i32 @test_igesll_z(i64 %a) {
+; CHECK-LABEL: test_igesll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_igesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define void @test_igesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r3, 63
+; CHECK: subfc r3, r4, r3
+; CHECK: rldicl r3, r4, 1, 63
+; CHECK: adde r3, r6, r3
+; CHECK: std r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_igesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igesll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r6, r3, 63
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: rldicl r3, r4, 1, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_igesll_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_igesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_igesll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesilesll.ll b/test/CodeGen/PowerPC/testComparesilesll.ll
new file mode 100644
index 00000000000..04381c5ed28
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -0,0 +1,130 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define signext i32 @test_ilesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define signext i32 @test_ilesll_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+define signext i32 @test_ilesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %sub = sext i1 %cmp to i32
+ ret i32 %sub
+}
+
+define void @test_ilesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK: subfc r4, r3, r4
+; CHECK: rldicl r3, r3, 1, 63
+; CHECK: adde r3, r6, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ilesll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK-DAG: rldicl r3, r3, 1, 63
+; CHECK-DAG: subfc r4, r3, r4
+; CHECK: adde r3, r6, r3
+; CHECK: neg r3, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_ilesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_ilesll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testComparesllgesll.ll b/test/CodeGen/PowerPC/testComparesllgesll.ll
new file mode 100644
index 00000000000..e75c0fad513
--- /dev/null
+++ b/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -0,0 +1,128 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+define i64 @test_llgesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i64 @test_llgesll_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i64 @test_llgesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define void @test_llgesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r3, 63
+; CHECK: subfc r3, r4, r3
+; CHECK: rldicl r3, r4, 1, 63
+; CHECK: adde r3, r6, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_llgesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgesll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r6, r3, 63
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: rldicl r3, r4, 1, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
+; CHECK-NEXT: adde r3, r6, r3
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sge i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_llgesll_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+define void @test_llgesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_llgesll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sgt i64 %a, -1
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
diff --git a/test/CodeGen/PowerPC/testCompareslllesll.ll b/test/CodeGen/PowerPC/testCompareslllesll.ll
new file mode 100644
index 00000000000..1b6c204443b
--- /dev/null
+++ b/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -0,0 +1,138 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+@glob = common local_unnamed_addr global i64 0, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_sext:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r12, r3, r4
+; CHECK-NEXT: adde r3, r5, r6
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_z(i64 %a) {
+; CHECK-LABEL: test_lllesll_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i64 @test_lllesll_sext_z(i64 %a) {
+; CHECK-LABEL: test_lllesll_sext_z:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: or r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = sext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK: subfc r4, r3, r4
+; CHECK: rldicl r3, r3, 1, 63
+; CHECK: adde r3, r6, r3
+; CHECK: std r3,
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_store(i64 %a, i64 %b) {
+; CHECK-LABEL: test_lllesll_sext_store:
+; CHECK: # BB#0: # %entry
+; CHECK: sradi r6, r4, 63
+; CHECK-DAG: rldicl r3, r3, 1, 63
+; CHECK-DAG: subfc r4, r3, r4
+; CHECK: adde r3, r6, r3
+; CHECK: neg r3, r3
+; CHECK: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp sle i64 %a, %b
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = zext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @test_lllesll_sext_z_store(i64 %a) {
+; CHECK-LABEL: test_lllesll_sext_z_store:
+; CHECK: # BB#0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
+; CHECK-NEXT: or r3, r5, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
+entry:
+ %cmp = icmp slt i64 %a, 1
+ %conv1 = sext i1 %cmp to i64
+ store i64 %conv1, i64* @glob, align 8
+ ret void
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 19:13:57 +0000