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authorCraig Topper <craig.topper@gmail.com>2017-03-13 00:36:49 +0000
committerCraig Topper <craig.topper@gmail.com>2017-03-13 00:36:49 +0000
commitc68171ad8f91cd6097152768d9ea0ceabac078ac (patch)
tree4ea7d8ac1a0e101b99e97931993bf4d2b031c03d /utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
parent026472f7e817c2817fcdebc50b6efc93d5646dfb (diff)
[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/X86EVEX2VEXTablesEmitter.cpp')
-rw-r--r--utils/TableGen/X86EVEX2VEXTablesEmitter.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
index 24f84aec6ca..142a969d340 100644
--- a/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
+++ b/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
@@ -72,7 +72,8 @@ private:
"VPSRAQ",
"VDBPSADBW",
"VRNDSCALE",
- "VSCALEFPS"
+ "VSCALEFPS",
+ "VSCALEFSS",
};
bool inExceptionList(const CodeGenInstruction *Inst) {
@@ -242,7 +243,7 @@ public:
if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
return false;
} else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
- return false;
+ continue;
} else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
return false;