diff options
author | Matthias Braun <matze@braunis.de> | 2016-04-28 03:07:07 +0000 |
---|---|---|
committer | Matthias Braun <matze@braunis.de> | 2016-04-28 03:07:07 +0000 |
commit | 89abe6466acd48cbae831cf1eb54a7237139d554 (patch) | |
tree | e899bf9383af0ebebad5477d7864e32fcb66eac9 /utils/TableGen/RegisterInfoEmitter.cpp | |
parent | 3b74a145c873826c9aadedf27c774c8fe293eb35 (diff) |
TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()
This function performs the reverse computation of
composeSubRegIndexLaneMask().
It will be used in the upcoming "DetectDeadLanes" pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267849 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/RegisterInfoEmitter.cpp')
-rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index b727df75626..4ec3e7de0f7 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -728,15 +728,11 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, SubReg2SequenceIndexMap.push_back(Found); } - OS << "unsigned " << ClName - << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, unsigned LaneMask)" - " const {\n"; - OS << " struct MaskRolOp {\n" " unsigned Mask;\n" " uint8_t RotateLeft;\n" " };\n" - " static const MaskRolOp Seqs[] = {\n"; + " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; unsigned Idx = 0; for (size_t s = 0, se = Sequences.size(); s != se; ++s) { OS << " "; @@ -756,24 +752,43 @@ RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { OS << " "; unsigned Idx = SubReg2SequenceIndexMap[i]; - OS << format("&Seqs[%u]", Idx); + OS << format("&LaneMaskComposeSequences[%u]", Idx); if (i+1 != e) OS << ","; OS << " // to " << SubRegIndices[i].getName() << "\n"; } OS << " };\n\n"; - OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() + OS << "LaneBitmask " << ClName + << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" + " const {\n" + " --IdxA; assert(IdxA < " << SubRegIndices.size() << " && \"Subregister index out of bounds\");\n" - " unsigned Result = 0;\n" + " LaneBitmask Result = 0;\n" " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)" " {\n" - " unsigned Masked = LaneMask & Ops->Mask;\n" + " LaneBitmask Masked = LaneMask & Ops->Mask;\n" " Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n" " Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n" " }\n" " return Result;\n" - "}\n"; + "}\n\n"; + + OS << "LaneBitmask " << ClName + << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " + " LaneBitmask LaneMask) const {\n" + " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" + " --IdxA; assert(IdxA < " << SubRegIndices.size() + << " && \"Subregister index out of bounds\");\n" + " LaneBitmask Result = 0;\n" + " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)" + " {\n" + " LaneBitmask Rotated = (LaneMask >> Ops->RotateLeft) |\n" + " ((LaneMask << ((32 - Ops->RotateLeft) & 0x1F)) & 0xFFFFFFFF);\n" + " Result |= Rotated & Ops->Mask;\n" + " }\n" + " return Result;\n" + "}\n\n"; } // @@ -1078,8 +1093,10 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, if (!RegBank.getSubRegIndices().empty()) { OS << " unsigned composeSubRegIndicesImpl" << "(unsigned, unsigned) const override;\n" - << " unsigned composeSubRegIndexLaneMaskImpl" - << "(unsigned, unsigned) const override;\n" + << " LaneBitmask composeSubRegIndexLaneMaskImpl" + << "(unsigned, LaneBitmask) const override;\n" + << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" + << "(unsigned, LaneBitmask) const override;\n" << " const TargetRegisterClass *getSubClassWithSubReg" << "(const TargetRegisterClass*, unsigned) const override;\n"; } |