diff options
| author | Matthias Braun <matze@braunis.de> | 2015-03-19 00:21:58 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2015-03-19 00:21:58 +0000 |
| commit | 5101c89f134092c7827ee6adc3689c9326134ad4 (patch) | |
| tree | 57abb66dcb90e62f0fd4d6da23d99732869319d5 /utils/TableGen/RegisterInfoEmitter.cpp | |
| parent | cc690d62e3813d1bf6eb23cc350a52d23991f633 (diff) | |
Do not track subregister liveness when it brings no benefits
Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multiple
disjunct parts. Avoid tracking subregister liveness in these cases as it
is not beneficial.
Differential Revision: http://reviews.llvm.org/D8429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232695 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'utils/TableGen/RegisterInfoEmitter.cpp')
| -rw-r--r-- | utils/TableGen/RegisterInfoEmitter.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index f1c25ce00fd..17bee6e7666 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -1286,7 +1286,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n " - << format("0x%08x,\n ", RC.LaneMask); + << format("0x%08x,\n ", RC.LaneMask) + << (RC.HasDisjunctSubRegs?"true":"false") + << ", /* HasDisjunctSubRegs */\n "; if (RC.getSuperClasses().empty()) OS << "NullRegClasses,\n "; else |