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author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 07:27:53 +0000 |
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committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 07:27:53 +0000 |
commit | 01cfc43fe473b6cac0e01795556324dbef4388fc (patch) | |
tree | 5ef7373e9074aa134ba680262ac678093d353c16 /tools | |
parent | d077c9767cdcf039217726503664e5103c358df5 (diff) |
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
This patch adds the necessary infrastructure to convert instructions that
take two register operands to those that take a register and immediate if
the necessary operand is produced by a load-immediate. Furthermore, it uses
this infrastructure to perform such conversions twice - first at MachineSSA
and then pre-emit.
There are a number of reasons we may end up with opportunities for this
transformation, including but not limited to:
- X-Form instructions chosen since the exact offset isn't available at ISEL time
- Atomic instructions with constant operands (we will add patterns for this
in the future)
- Tail duplication may duplicate code where one block contains this redundancy
- When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant
comparands specially
Furthermore, this patch moves the initialization of PPCMIPeepholePass so that
it can be used for MIR tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320791 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions