diff options
| author | Tom Stellard <tstellar@redhat.com> | 2018-04-17 20:17:43 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-04-17 20:17:43 +0000 |
| commit | f1b37feef3d5f09dadf6a46fdb11fa7e4218cf6c (patch) | |
| tree | c2b0c14a32f942189536989c8099ad91fdbb300a /test | |
| parent | 0b57b47378e5b31693c6b2ef899ffb10c6b09e09 (diff) | |
Merging r329761:
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r329761 | gberry | 2018-04-10 14:43:03 -0700 (Tue, 10 Apr 2018) | 13 lines
[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.
Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.
Reviewers: mcrosier
Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45502
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330209 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AArch64/falkor-hwpf-fix.mir | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/falkor-hwpf-fix.mir b/test/CodeGen/AArch64/falkor-hwpf-fix.mir index 38622ae0e49..28b19f87768 100644 --- a/test/CodeGen/AArch64/falkor-hwpf-fix.mir +++ b/test/CodeGen/AArch64/falkor-hwpf-fix.mir @@ -353,3 +353,28 @@ body: | bb.1: RET_ReallyLR ... +--- +# Check that non-base registers are considered live when finding a +# scratch register by making sure we don't use %x2 for the scratch +# register for the inserted ORRXrs. +# CHECK-LABEL: name: hwpf_offreg +# CHECK: %x3 = ORRXrs %xzr, %x1, 0 +# CHECK: %w10 = LDRWroX %x3, %x2, 0, 0 +name: hwpf_offreg +tracksRegLiveness: true +body: | + bb.0: + liveins: %w0, %x1, %x2, %x17, %x18 + + %w10 = LDRWroX %x1, %x2, 0, 0 :: ("aarch64-strided-access" load 4) + + %x2 = ORRXrs %xzr, %x10, 0 + %w26 = LDRWroX %x1, %x2, 0, 0 + + %w0 = SUBWri %w0, 1, 0 + %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv + Bcc 9, %bb.0, implicit %nzcv + + bb.1: + RET_ReallyLR +... |