Revert "r225808 - [PowerPC] Add StackMap/PatchPoint support"

Reverting this while I investiage buildbot failures (segfaulting in
GetCostForDef at ScheduleDAGRRList.cpp:314).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225811 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 0 insertions, 792 deletions

diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
deleted file mode 100644
index 479c7a7af25..00000000000
--- a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s
-;
-; Check that misuse of anyregcc results in a compile time error.
-
-; CHECK: LLVM ERROR: ran out of registers during register allocation
-define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
-                        i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
-                        i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
-                        i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) {
-entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32,
-                i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8,
-                i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16,
-                i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24,
-                i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32)
-  ret i64 %result
-}
-
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll
deleted file mode 100644
index 7cd3c4b3820..00000000000
--- a/test/CodeGen/PowerPC/ppc64-anyregcc.ll
+++ /dev/null
@@ -1,367 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-; Stackmap Header: no constants - 6 callsites
-; CHECK-LABEL: .section	.llvm_stackmaps
-; CHECK-NEXT:  __LLVM_StackMaps:
-; Header
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 0
-; CHECK-NEXT:   .short 0
-; Num Functions
-; CHECK-NEXT:   .long 8
-; Num LargeConstants
-; CHECK-NEXT:   .long 0
-; Num Callsites
-; CHECK-NEXT:   .long 8
-
-; Functions and stack size
-; CHECK-NEXT:   .quad test
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad property_access1
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad property_access2
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad property_access3
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad anyreg_test1
-; CHECK-NEXT:   .quad 160
-; CHECK-NEXT:   .quad anyreg_test2
-; CHECK-NEXT:   .quad 160
-; CHECK-NEXT:   .quad patchpoint_spilldef
-; CHECK-NEXT:   .quad 256
-; CHECK-NEXT:   .quad patchpoint_spillargs
-; CHECK-NEXT:   .quad 288
-
-
-; test
-; CHECK-LABEL:  .long   .L{{.*}}-.L.test
-; CHECK-NEXT:   .short  0
-; 3 locations
-; CHECK-NEXT:   .short  3
-; Loc 0: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 2: Constant 3
-; CHECK-NEXT:   .byte 4
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long 3
-define i64 @test() nounwind ssp uwtable {
-entry:
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3)
-  ret i64 0
-}
-
-; property access 1 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access1
-; CHECK-NEXT:   .short  0
-; 2 locations
-; CHECK-NEXT:   .short  2
-; Loc 0: Register <-- this is the return register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
-entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj)
-  ret i64 %ret
-}
-
-; property access 2 - %obj is an anyreg call argument and should therefore be in a register
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access2
-; CHECK-NEXT:   .short  0
-; 2 locations
-; CHECK-NEXT:   .short  2
-; Loc 0: Register <-- this is the return register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-define i64 @property_access2() nounwind ssp uwtable {
-entry:
-  %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj)
-  ret i64 %ret
-}
-
-; property access 3 - %obj is a frame index
-; CHECK-LABEL:  .long   .L{{.*}}-.L.property_access3
-; CHECK-NEXT:   .short  0
-; 2 locations
-; CHECK-NEXT:   .short  2
-; Loc 0: Register <-- this is the return register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Direct FP - 8
-; CHECK-NEXT:   .byte 2
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short 31
-; CHECK-NEXT:   .long 112
-define i64 @property_access3() nounwind ssp uwtable {
-entry:
-  %obj = alloca i64, align 8
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj)
-  ret i64 %ret
-}
-
-; anyreg_test1
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test1
-; CHECK-NEXT:   .short  0
-; 14 locations
-; CHECK-NEXT:   .short  14
-; Loc 0: Register <-- this is the return register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 2: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 3: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 4: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 5: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 6: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 7: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 8: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 9: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 10: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 11: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 12: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 13: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
-entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
-  ret i64 %ret
-}
-
-; anyreg_test2
-; CHECK-LABEL:  .long   .L{{.*}}-.L.anyreg_test2
-; CHECK-NEXT:   .short  0
-; 14 locations
-; CHECK-NEXT:   .short  14
-; Loc 0: Register <-- this is the return register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 1: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 2: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 3: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 4: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 5: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 6: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 7: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 8: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 9: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 10: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 11: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 12: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-; Loc 13: Register
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short {{[0-9]+}}
-; CHECK-NEXT:   .long 0
-define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
-entry:
-  %f = inttoptr i64 281474417671919 to i8*
-  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
-  ret i64 %ret
-}
-
-; Test spilling the return value of an anyregcc call.
-;
-; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
-;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 3
-; Loc 0: Register (some register that will be spilled to the stack)
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-; Loc 1: Register
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-; Loc 1: Register
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
-  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
-},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  ret i64 %result
-}
-
-; Test spilling the arguments of an anyregcc call.
-;
-; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
-;
-; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 5
-; Loc 0: Return a register
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-; Loc 1: Arg0 in a Register
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-; Loc 2: Arg1 in a Register
-; CHECK-NEXT: .byte  1
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long  0
-; Loc 3: Arg2 spilled to FP -96
-; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short 31
-; CHECK-NEXT: .long 128
-; Loc 4: Arg3 spilled to FP - 88
-; CHECK-NEXT: .byte  3
-; CHECK-NEXT: .byte  8
-; CHECK-NEXT: .short 31
-; CHECK-NEXT: .long 136
-define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
-},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
-  ret i64 %result
-}
-
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
diff --git a/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/test/CodeGen/PowerPC/ppc64-patchpoint.ll
deleted file mode 100644
index 5e58fdab216..00000000000
--- a/test/CodeGen/PowerPC/ppc64-patchpoint.ll
+++ /dev/null
@@ -1,93 +0,0 @@
-; RUN: llc                             < %s | FileCheck %s
-; RUN: llc -fast-isel -fast-isel-abort < %s | FileCheck %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-; Trivial patchpoint codegen
-;
-define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-; CHECK-LABEL: trivial_patchpoint_codegen:
-
-; CHECK: li 11, -8531
-; CHECK-NEXT: rldic 11, 11, 32, 16
-; CHECK-NEXT: oris 11, 11, 48879
-; CHECK-NEXT: ori 11, 11, 51966
-; CHECK-NEXT: mtctr 11
-; CHECK-NEXT: bctrl
-
-; CHECK: li 11, -8531
-; CHECK-NEXT: rldic 11, 11, 32, 16
-; CHECK-NEXT: oris 11, 11, 48879
-; CHECK-NEXT: ori 11, 11, 51967
-; CHECK-NEXT: mtctr 11
-; CHECK-NEXT: bctrl
-
-; CHECK: blr
-
-  %resolveCall2 = inttoptr i64 244837814094590 to i8*
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
-  %resolveCall3 = inttoptr i64 244837814094591 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
-  ret i64 %result
-}
-
-; Caller frame metadata with stackmaps. This should not be optimized
-; as a leaf function.
-;
-; CHECK-LABEL: caller_meta_leaf
-; CHECK: stdu 1, -80(1)
-; CHECK: Ltmp
-; CHECK: addi 1, 1, 80
-; CHECK: blr
-
-define void @caller_meta_leaf() {
-entry:
-  %metadata = alloca i64, i32 3, align 8
-  store i64 11, i64* %metadata
-  store i64 12, i64* %metadata
-  store i64 13, i64* %metadata
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
-  ret void
-}
-
-; Test patchpoints reusing the same TargetConstant.
-; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
-; There is no way to verify this, since it depends on memory allocation.
-; But I think it's useful to include as a working example.
-define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
-entry:
-  %tmp80 = add i64 %tmp79, -16
-  %tmp81 = inttoptr i64 %tmp80 to i64*
-  %tmp82 = load i64* %tmp81, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
-  %tmp83 = load i64* %tmp33, align 8
-  %tmp84 = add i64 %tmp83, -24
-  %tmp85 = inttoptr i64 %tmp84 to i64*
-  %tmp86 = load i64* %tmp85, align 8
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
-  ret i64 10
-}
-
-; Test small patchpoints that don't emit calls.
-define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-; CHECK-LABEL: small_patchpoint_codegen:
-; CHECK:      Ltmp
-; CHECK:      nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NOT:  nop
-; CHECK: blr
-  %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
-  ret void
-}
-
-declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
-
diff --git a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
deleted file mode 100644
index 368ddc5c833..00000000000
--- a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-gnu-linux | FileCheck %s
-
-define void @test_shadow_optimization() {
-entry:
-; Expect 12 bytes worth of nops here rather than 32: With the shadow optimization
-; in place, 20 bytes will be consumed by the frame teardown and return instr.
-; CHECK-LABEL: test_shadow_optimization:
-
-; CHECK:      nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NOT:  nop
-; CHECK: addi 1, 1, 64
-; CHECK: ld [[REG1:[0-9]+]], 16(1)
-; CHECK: ld 31, -8(1)
-; CHECK: mtlr [[REG1]]
-; CHECK: blr
-
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64  0, i32  32)
-  ret void
-}
-
-declare void @llvm.experimental.stackmap(i64, i32, ...)
-
diff --git a/test/CodeGen/PowerPC/ppc64-stackmap.ll b/test/CodeGen/PowerPC/ppc64-stackmap.ll
deleted file mode 100644
index 9be8d0c8ad4..00000000000
--- a/test/CodeGen/PowerPC/ppc64-stackmap.ll
+++ /dev/null
@@ -1,289 +0,0 @@
-; RUN: llc                             < %s | FileCheck %s
-;
-; Note: Print verbose stackmaps using -debug-only=stackmaps.
-
-; We are not getting the correct stack alignment when cross compiling for arm64.
-; So specify a datalayout here.
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-; CHECK-LABEL:  .section  .llvm_stackmaps
-; CHECK-NEXT:  __LLVM_StackMaps:
-; Header
-; CHECK-NEXT:   .byte 1
-; CHECK-NEXT:   .byte 0
-; CHECK-NEXT:   .short 0
-; Num Functions
-; CHECK-NEXT:   .long 11
-; Num LargeConstants
-; CHECK-NEXT:   .long 2
-; Num Callsites
-; CHECK-NEXT:   .long 11
-
-; Functions and stack size
-; CHECK-NEXT:   .quad constantargs
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad osrinline
-; CHECK-NEXT:   .quad 144
-; CHECK-NEXT:   .quad osrcold
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad propertyRead
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad propertyWrite
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad jsVoidCall
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad jsIntCall
-; CHECK-NEXT:   .quad 128
-; CHECK-NEXT:   .quad spilledValue
-; CHECK-NEXT:   .quad 320
-; CHECK-NEXT:   .quad spilledStackMapValue
-; CHECK-NEXT:   .quad 224
-; CHECK-NEXT:   .quad liveConstant
-; CHECK-NEXT:   .quad 64
-; CHECK-NEXT:   .quad clobberLR
-; CHECK-NEXT:   .quad 208
-
-; Num LargeConstants
-; CHECK-NEXT:   .quad   4294967295
-; CHECK-NEXT:   .quad   4294967296
-
-; Constant arguments
-;
-; CHECK-NEXT:   .quad   1
-; CHECK-NEXT:   .long   .L{{.*}}-.L.constantargs
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  4
-; SmallConstant
-; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long   65535
-; SmallConstant
-; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long   65536
-; SmallConstant
-; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long   0
-; LargeConstant at index 0
-; CHECK-NEXT:   .byte   5
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long   1
-
-define void @constantargs() {
-entry:
-  %0 = inttoptr i64 244837814094590 to i8*
-  tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
-  ret void
-}
-
-; Inline OSR Exit
-;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.osrinline
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  2
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long  0
-define void @osrinline(i64 %a, i64 %b) {
-entry:
-  ; Runtime void->void call.
-  call void inttoptr (i64 244837814094590 to void ()*)()
-  ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
-  ret void
-}
-
-; Cold OSR Exit
-;
-; 2 live variables in register.
-;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.osrcold
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  2
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long  0
-define void @osrcold(i64 %a, i64 %b) {
-entry:
-  %test = icmp slt i64 %a, %b
-  br i1 %test, label %ret, label %cold
-cold:
-  ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
-  %thunk = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b)
-  unreachable
-ret:
-  ret void
-}
-
-; Property Read
-; CHECK-LABEL:  .long   .L{{.*}}-.L.propertyRead
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  0
-;
-; FIXME: There are currently no stackmap entries. After moving to
-; AnyRegCC, we will have entries for the object and return value.
-define i64 @propertyRead(i64* %obj) {
-entry:
-  %resolveRead = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj)
-  %add = add i64 %result, 3
-  ret i64 %add
-}
-
-; Property Write
-; CHECK-LABEL:  .long   .L{{.*}}-.L.propertyWrite
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  2
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
-entry:
-  %resolveWrite = inttoptr i64 244837814094590 to i8*
-  call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
-  ret void
-}
-
-; Void JS Call
-;
-; 2 live variables in registers.
-;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.jsVoidCall
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  2
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
-entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
-  ret void
-}
-
-; i64 JS Call
-;
-; 2 live variables in registers.
-;
-; CHECK-LABEL:  .long   .L{{.*}}-.L.jsIntCall
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .short  2
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-; CHECK-NEXT:   .byte   1
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  {{[0-9]+}}
-; CHECK-NEXT:   .long   0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
-entry:
-  %resolveCall = inttoptr i64 244837814094590 to i8*
-  %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
-  %add = add i64 %result, 3
-  ret i64 %add
-}
-
-; Spilled stack map values.
-;
-; Verify 28 stack map entries.
-;
-; CHECK-LABEL:  .long .L{{.*}}-.L.spilledValue
-; CHECK-NEXT:   .short 0
-; CHECK-NEXT:   .short 28
-;
-; Check that at least one is a spilled entry from r31.
-; Location: Indirect FP + ...
-; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short 31
-define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
-entry:
-  call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
-  ret void
-}
-
-; Spilled stack map values.
-;
-; Verify 30 stack map entries.
-;
-; CHECK-LABEL:  .long .L{{.*}}-.L.spilledStackMapValue
-; CHECK-NEXT:   .short 0
-; CHECK-NEXT:   .short 30
-;
-; Check that at least one is a spilled entry from r31.
-; Location: Indirect FP + ...
-; CHECK:        .byte 3
-; CHECK-NEXT:   .byte 8
-; CHECK-NEXT:   .short 31
-define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
-entry:
-  call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
-  ret void
-}
-
-
-; Map a constant value.
-;
-; CHECK-LABEL:  .long .L{{.*}}-.L.liveConstant
-; CHECK-NEXT:   .short 0
-; 1 location
-; CHECK-NEXT:   .short 1
-; Loc 0: SmallConstant
-; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .byte   8
-; CHECK-NEXT:   .short  0
-; CHECK-NEXT:   .long   33
-
-define void @liveConstant() {
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
-  ret void
-}
-
-; Map a value when LR is the only free register.
-;
-; CHECK-LABEL:  .long .L{{.*}}-.L.clobberLR
-; CHECK-NEXT:   .short 0
-; 1 location
-; CHECK-NEXT:   .short 1
-; Loc 0: Indirect FP (r31) - offset
-; CHECK-NEXT:   .byte   3
-; CHECK-NEXT:   .byte   4
-; CHECK-NEXT:   .short  31
-; CHECK-NEXT:   .long   {{[0-9]+}}
-define void @clobberLR(i32 %a) {
-  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
-  tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
-  ret void
-}
-
-declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)