diff options
author | Nirav Dave <niravd@google.com> | 2017-12-02 04:01:26 +0000 |
---|---|---|
committer | Nirav Dave <niravd@google.com> | 2017-12-02 04:01:26 +0000 |
commit | deae672db68d0aeee0480a9dfa39b79b6cf3b605 (patch) | |
tree | 958dca05ac2759945fa62496e378cb9d1b487fec /test | |
parent | 527f9bdad5e47434aec78bb0ffa3dc299d44b211 (diff) |
[DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319607 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/AArch64/arm64-complex-ret.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/AArch64/arm64-narrow-st-merge.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/AArch64/arm64-variadic-aapcs.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/AArch64/tailcall-explicit-sret.ll | 14 | ||||
-rw-r--r-- | test/CodeGen/AArch64/tailcall-implicit-sret.ll | 12 |
5 files changed, 26 insertions, 23 deletions
diff --git a/test/CodeGen/AArch64/arm64-complex-ret.ll b/test/CodeGen/AArch64/arm64-complex-ret.ll index b4a38544ca1..250edac553c 100644 --- a/test/CodeGen/AArch64/arm64-complex-ret.ll +++ b/test/CodeGen/AArch64/arm64-complex-ret.ll @@ -2,7 +2,6 @@ define { i192, i192, i21, i192 } @foo(i192) { ; CHECK-LABEL: foo: -; CHECK-DAG: str xzr, [x8, #16] -; CHECK-DAG: str q0, [x8] +; CHECK: stp xzr, xzr, [x8] ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3} } diff --git a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll index b48f3b46cb4..ec7c227e169 100644 --- a/test/CodeGen/AArch64/arm64-narrow-st-merge.ll +++ b/test/CodeGen/AArch64/arm64-narrow-st-merge.ll @@ -19,7 +19,7 @@ entry: } ; CHECK-LABEL: Strh_zero_4 -; CHECK: str xzr +; CHECK: stp wzr, wzr ; CHECK-STRICT-LABEL: Strh_zero_4 ; CHECK-STRICT: strh wzr ; CHECK-STRICT: strh wzr @@ -137,7 +137,7 @@ entry: } ; CHECK-LABEL: Sturh_zero_4 -; CHECK: stur xzr +; CHECK: stp wzr, wzr ; CHECK-STRICT-LABEL: Sturh_zero_4 ; CHECK-STRICT: sturh wzr ; CHECK-STRICT: sturh wzr diff --git a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll index a09853a0b40..375877c5179 100644 --- a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll +++ b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll @@ -32,9 +32,11 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: mov [[GRVR:x[0-9]+]], #-545460846720 -; CHECK: movk [[GRVR]], #65480 -; CHECK: str [[GRVR]], [x[[VA_LIST]], #24] +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-56 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] + +; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) @@ -68,9 +70,11 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: mov [[GRVR_OFFS:x[0-9]+]], #-40 -; CHECK: movk [[GRVR_OFFS]], #65424, lsl #32 -; CHECK: str [[GRVR_OFFS]], [x[[VA_LIST]], #24] +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-40 +; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] + +; CHECK: mov [[VR_OFFS:w[0-9]+]], #-11 +; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) diff --git a/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/test/CodeGen/AArch64/tailcall-explicit-sret.ll index b60958b5a25..c1579336189 100644 --- a/test/CodeGen/AArch64/tailcall-explicit-sret.ll +++ b/test/CodeGen/AArch64/tailcall-explicit-sret.ll @@ -35,7 +35,7 @@ define void @test_tailcall_explicit_sret_alloca_unused() #0 { } ; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_dummyusers: -; CHECK: ldr [[PTRLOAD1:q[0-9]+]], [x0] +; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0] ; CHECK: str [[PTRLOAD1]], [sp] ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret @@ -64,8 +64,8 @@ define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret -; CHECK-NEXT: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { %l = alloca i1024, align 8 @@ -79,8 +79,8 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { ; CHECK-DAG: mov [[FPTR:x[0-9]+]], x0 ; CHECK: mov x0, sp ; CHECK-NEXT: blr [[FPTR]] -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 { %l = alloca i1024, align 8 @@ -94,8 +94,8 @@ define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, v ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 { %ret = tail call i1024 %f() diff --git a/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/test/CodeGen/AArch64/tailcall-implicit-sret.ll index f449a7e0658..10c4ba4c31d 100644 --- a/test/CodeGen/AArch64/tailcall-implicit-sret.ll +++ b/test/CodeGen/AArch64/tailcall-implicit-sret.ll @@ -11,8 +11,8 @@ declare i1024 @test_sret() #0 ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_call_sret() #0 { %a = call i1024 @test_sret() @@ -23,8 +23,8 @@ define i1024 @test_call_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_sret() #0 { %a = tail call i1024 @test_sret() @@ -35,8 +35,8 @@ define i1024 @test_tailcall_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 { %a = tail call i1024 %f() |