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| author | Sanjay Patel <spatel@rotateright.com> | 2017-10-16 15:20:00 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2017-10-16 15:20:00 +0000 |
| commit | cd102716d7fd4b8ed292fe0068a3787a0270060a (patch) | |
| tree | 58cbd19ce07c0c34db5969c598edea2fda4d6e24 /test | |
| parent | 09c266d1240a390a66782ac62bb75df78898d72a (diff) | |
[x86] add minmax tests with more predicate coverage; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315913 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/vec_minmax_match.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/X86/vec_minmax_match.ll b/test/CodeGen/X86/vec_minmax_match.ll index 98f77912779..b377bbee3d7 100644 --- a/test/CodeGen/X86/vec_minmax_match.ll +++ b/test/CodeGen/X86/vec_minmax_match.ll @@ -219,3 +219,33 @@ define <4 x i32> @clamp_unsigned2(<4 x i32> %x) { ret <4 x i32> %r } +define <4 x i32> @wrong_pred_for_smin_with_not(<4 x i32> %x) { +; CHECK-LABEL: wrong_pred_for_smin_with_not: +; CHECK: # BB#0: +; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm1 +; CHECK-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 +; CHECK-NEXT: vpcmpgtd {{.*}}(%rip), %xmm0, %xmm0 +; CHECK-NEXT: vmovaps {{.*#+}} xmm2 = [4294967291,4294967291,4294967291,4294967291] +; CHECK-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0 +; CHECK-NEXT: retq + %not_x = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + %cmp = icmp ugt <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4> + %sel = select <4 x i1> %cmp, <4 x i32> %not_x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5> + ret <4 x i32> %sel +} + +define <4 x i32> @wrong_pred_for_smin_with_subnsw(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: wrong_pred_for_smin_with_subnsw: +; CHECK: # BB#0: +; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm2 +; CHECK-NEXT: vpminud %xmm1, %xmm0, %xmm1 +; CHECK-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 +; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0 +; CHECK-NEXT: retq + %sub = sub nsw <4 x i32> %x, %y + %cmp = icmp ugt <4 x i32> %x, %y + %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %sub + ret <4 x i32> %sel +} + |