diff options
author | Lei Huang <lei@ca.ibm.com> | 2017-07-10 16:44:45 +0000 |
---|---|---|
committer | Lei Huang <lei@ca.ibm.com> | 2017-07-10 16:44:45 +0000 |
commit | b6988767a83875c8d0a64a1c0ff9cdf962d556ab (patch) | |
tree | 2fea04e610771f032783ccbc08c60076c2937507 /test | |
parent | 0fd6ce773dc03bd9901ad277bf045244a39ffc3a (diff) |
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
For this example:
float test (int *arr) {
return arr[2];
}
We currently generate the following code:
li r4, 8
lxsiwax f0, r3, r4
xscvsxdsp f1, f0
With this patch, we will now generate:
addi r3, r3, 8
lxsiwax f0, 0, r3
xscvsxdsp f1, f0
Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204
Differential Revision: https://reviews.llvm.org/D35027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307553 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/PowerPC/build-vector-tests.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/ppc64le-smallarg.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/select-addrRegRegOnly.ll | 37 | ||||
-rw-r--r-- | test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll | 16 |
4 files changed, 49 insertions, 12 deletions
diff --git a/test/CodeGen/PowerPC/build-vector-tests.ll b/test/CodeGen/PowerPC/build-vector-tests.ll index c42f677d17a..60bec4d18f1 100644 --- a/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/test/CodeGen/PowerPC/build-vector-tests.ll @@ -1028,7 +1028,7 @@ entry: ; P9LE: vperm ; P9LE: blr ; P8BE: sldi {{r[0-9]+}}, r4, 2 -; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3, +; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 ; P8BE-DAG: lxvw4x ; P8BE: vperm ; P8BE: blr @@ -2187,7 +2187,7 @@ entry: ; P9LE: vperm ; P9LE: blr ; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 -; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3 +; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 ; P8BE-DAG: lxvw4x ; P8BE: vperm ; P8BE: blr diff --git a/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/test/CodeGen/PowerPC/ppc64le-smallarg.ll index 0e871c35886..3a425406d04 100644 --- a/test/CodeGen/PowerPC/ppc64le-smallarg.ll +++ b/test/CodeGen/PowerPC/ppc64le-smallarg.ll @@ -53,8 +53,8 @@ entry: ret void } ; CHECK: @caller2 -; CHECK: li [[TOCOFF:[0-9]+]], 136 -; CHECK: stxsspx {{[0-9]+}}, 1, [[TOCOFF]] +; CHECK: addi [[TOCOFF:[0-9]+]], {{[0-9]+}}, 136 +; CHECK: stxsspx {{[0-9]+}}, 0, [[TOCOFF]] ; CHECK: bl test2 declare float @test2(float, float, float, float, float, float, float, float, float, float, float, float, float, float) diff --git a/test/CodeGen/PowerPC/select-addrRegRegOnly.ll b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll new file mode 100644 index 00000000000..f880d1faf9d --- /dev/null +++ b/test/CodeGen/PowerPC/select-addrRegRegOnly.ll @@ -0,0 +1,37 @@ +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s + +; Function Attrs: norecurse nounwind readonly +define float @testSingleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { +; CHECK-LABEL: testSingleAccess: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addi 3, 3, 8 +; CHECK-NEXT: lxsiwax 0, 0, 3 +; CHECK-NEXT: xscvsxdsp 1, 0 +; CHECK-NEXT: blr +entry: + %arrayidx = getelementptr inbounds i32, i32* %arr, i64 2 + %0 = load i32, i32* %arrayidx, align 4 + %conv = sitofp i32 %0 to float + ret float %conv +} + +; Function Attrs: norecurse nounwind readonly +define float @testMultipleAccess(i32* nocapture readonly %arr) local_unnamed_addr #0 { +; CHECK-LABEL: testMultipleAccess: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: lwz 4, 8(3) +; CHECK-NEXT: lwz 12, 12(3) +; CHECK-NEXT: add 3, 12, 4 +; CHECK-NEXT: mtvsrwa 0, 3 +; CHECK-NEXT: xscvsxdsp 1, 0 +; CHECK-NEXT: blr +entry: + %arrayidx = getelementptr inbounds i32, i32* %arr, i64 2 + %0 = load i32, i32* %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 3 + %1 = load i32, i32* %arrayidx1, align 4 + %add = add nsw i32 %1, %0 + %conv = sitofp i32 %add to float + ret float %conv +} diff --git a/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll b/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll index 67146e40db0..5346d8a429f 100644 --- a/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll +++ b/test/CodeGen/PowerPC/vsx-partword-int-loads-and-stores.ll @@ -321,8 +321,8 @@ entry: ; CHECK: lxsibzx 34, 0, 3 ; CHECK-NEXT: vspltb 2, 2, 7 ; CHECK-BE-LABEL: vecucus -; CHECK-BE: li [[OFFSET:[0-9]+]], 1 -; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]] +; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1 +; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]] ; CHECK-BE-NEXT: vspltb 2, 2, 7 } @@ -385,8 +385,8 @@ entry: ; CHECK: lxsibzx 34, 0, 3 ; CHECK-NEXT: vspltb 2, 2, 7 ; CHECK-BE-LABEL: vecscus -; CHECK-BE: li [[OFFSET:[0-9]+]], 1 -; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]] +; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1 +; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]] ; CHECK-BE-NEXT: vspltb 2, 2, 7 } @@ -487,8 +487,8 @@ entry: ; CHECK: lxsibzx 34, 0, 3 ; CHECK-NEXT: vspltb 2, 2, 7 ; CHECK-BE-LABEL: vecucss -; CHECK-BE: li [[OFFSET:[0-9]+]], 1 -; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]] +; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1 +; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]] ; CHECK-BE-NEXT: vspltb 2, 2, 7 } @@ -540,8 +540,8 @@ entry: ; CHECK: lxsibzx 34, 0, 3 ; CHECK-NEXT: vspltb 2, 2, 7 ; CHECK-BE-LABEL: vecscss -; CHECK-BE: li [[OFFSET:[0-9]+]], 1 -; CHECK-BE-NEXT: lxsibzx 34, 3, [[OFFSET]] +; CHECK-BE: addi [[OFFSET:[0-9]+]], [[OFFSET]], 1 +; CHECK-BE-NEXT: lxsibzx 34, 0, [[OFFSET]] ; CHECK-BE-NEXT: vspltb 2, 2, 7 } |