diff options
| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-02-03 21:58:23 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2015-02-03 21:58:23 +0000 |
| commit | 8c775a4e7b39674f0450b63d176fc090d4f8d379 (patch) | |
| tree | 0eba00422cc5565c5bf165a7eec006d3ff21ebf0 /test | |
| parent | 04e540582bed6352741d9a0d013a9888df5996a6 (diff) | |
[PowerPC] Implement the vpopcnt instructions for POWER8
Patch by Kit Barton.
Add the vector population count instructions for byte, halfword, word,
and doubleword sizes. There are two major changes here:
PPCISelLowering.cpp: Make CTPOP legal for vector types.
PPCRegisterInfo.td: Added v2i64 to the VRRC register
definition. This is needed for the doubleword variations of the
integer ops that were added in P8.
Test Plan
Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s
Test the generation of the vpopcnt instructions for various vector
data types. When adding the v2i64 type to the Vector Register set, I
also needed to add the appropriate bit conversion patterns between
v2i64 and the existing vector types. Testing for these conversions
were also added in the test case by passing a different vector type as
a parameter into the test functions. There is also a run step that
will ensure the vpopcnt instructions are generated when the vsx
feature is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228046 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt | 12 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding-vmx.s | 17 |
2 files changed, 29 insertions, 0 deletions
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt index 3896bf75543..72c5e64ab48 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -501,6 +501,18 @@ # CHECK: vrsqrtefp 2, 3 0x10 0x40 0x19 0x4a +# CHECK: vpopcntb 2, 3 +0x10 0x40 0x1f 0x03 + +# CHECK: vpopcnth 2, 3 +0x10 0x40 0x1f 0x43 + +# CHECK: vpopcntw 2, 3 +0x10 0x40 0x1f 0x83 + +# CHECK: vpopcntd 2, 3 +0x10 0x40 0x1f 0xc3 + # CHECK: mtvscr 2 0x10 0x00 0x16 0x44 diff --git a/test/MC/PowerPC/ppc64-encoding-vmx.s b/test/MC/PowerPC/ppc64-encoding-vmx.s index 3d2df841415..3247d407f5e 100644 --- a/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -543,6 +543,23 @@ # CHECK-LE: vrsqrtefp 2, 3 # encoding: [0x4a,0x19,0x40,0x10] vrsqrtefp 2, 3 +# Vector population count instructions +# CHECK-BE: vpopcntb 2, 3 # encoding: [0x10,0x40,0x1f,0x03] +# CHECK-LE: vpopcntb 2, 3 # encoding: [0x03,0x1f,0x40,0x10] + vpopcntb 2, 3 + +# CHECK-BE: vpopcnth 2, 3 # encoding: [0x10,0x40,0x1f,0x43] +# CHECK-LE: vpopcnth 2, 3 # encoding: [0x43,0x1f,0x40,0x10] + vpopcnth 2, 3 + +# CHECK-BE: vpopcntw 2, 3 # encoding: [0x10,0x40,0x1f,0x83] +# CHECK-LE: vpopcntw 2, 3 # encoding: [0x83,0x1f,0x40,0x10] + vpopcntw 2, 3 + +# BCHECK-BE: vpopcntd 2, 3 # encoding: [0x10,0x40,0x1f,0xC3] +# BCHECK-LE: vpopcntd 2, 3 # encoding: [0xC3,0x1f,0x40,0x10] +# vpopcntd 2, 3 + # Vector status and control register instructions # CHECK-BE: mtvscr 2 # encoding: [0x10,0x00,0x16,0x44] |