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authorSanjay Patel <spatel@rotateright.com>2017-06-23 14:58:21 +0000
committerSanjay Patel <spatel@rotateright.com>2017-06-23 14:58:21 +0000
commit65b48742f40e1af147cb615f28924815454317f6 (patch)
treee5723ba6fb6e6989bac21f2c6d8b3e523910a203 /test
parent47b190de86f90f07af1fedf525ffba0154f122ec (diff)
[x86] rename test file and auto-generate complete checks; NFC
The command-line params override the target setting in the file itself, so delete that. Also, remove the cpu and arch because those don't matter and neither does the OS specification in the triple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306109 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/X86/2012-12-06-python27-miscompile.ll23
-rw-r--r--test/CodeGen/X86/merge-consecutive-stores.ll35
2 files changed, 35 insertions, 23 deletions
diff --git a/test/CodeGen/X86/2012-12-06-python27-miscompile.ll b/test/CodeGen/X86/2012-12-06-python27-miscompile.ll
deleted file mode 100644
index b80ae3ae2b7..00000000000
--- a/test/CodeGen/X86/2012-12-06-python27-miscompile.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32 | FileCheck %s
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-macosx10.8.0"
-
-; Make sure that we are zeroing one memory location at a time using xorl and
-; not both using XMM registers.
-
-;CHECK: @foo
-;CHECK: xorl
-;CHECK-NOT: xmm
-;CHECK: ret
-define i32 @foo (i64* %so) nounwind uwtable ssp {
-entry:
- %used = getelementptr inbounds i64, i64* %so, i32 3
- store i64 0, i64* %used, align 8
- %fill = getelementptr inbounds i64, i64* %so, i32 2
- %L = load i64, i64* %fill, align 8
- store i64 0, i64* %fill, align 8
- %cmp28 = icmp sgt i64 %L, 0
- %R = sext i1 %cmp28 to i32
- ret i32 %R
-}
diff --git a/test/CodeGen/X86/merge-consecutive-stores.ll b/test/CodeGen/X86/merge-consecutive-stores.ll
new file mode 100644
index 00000000000..80a5a6c3963
--- /dev/null
+++ b/test/CodeGen/X86/merge-consecutive-stores.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
+
+; Make sure that we are zeroing one memory location at a time using xorl and
+; not both using XMM registers.
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+define i32 @foo (i64* %so) nounwind uwtable ssp {
+; CHECK-LABEL: foo:
+; CHECK: # BB#0:
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: movl $0, 28(%eax)
+; CHECK-NEXT: movl $0, 24(%eax)
+; CHECK-NEXT: movl 20(%eax), %ecx
+; CHECK-NEXT: movl $0, 20(%eax)
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: cmpl 16(%eax), %edx
+; CHECK-NEXT: movl $0, 16(%eax)
+; CHECK-NEXT: sbbl %ecx, %edx
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: jl .LBB0_2
+; CHECK-NEXT: # BB#1:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: .LBB0_2:
+; CHECK-NEXT: retl
+ %used = getelementptr inbounds i64, i64* %so, i32 3
+ store i64 0, i64* %used, align 8
+ %fill = getelementptr inbounds i64, i64* %so, i32 2
+ %L = load i64, i64* %fill, align 8
+ store i64 0, i64* %fill, align 8
+ %cmp28 = icmp sgt i64 %L, 0
+ %R = sext i1 %cmp28 to i32
+ ret i32 %R
+}