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authorHans Wennborg <hans@hanshq.net>2018-02-07 10:01:03 +0000
committerHans Wennborg <hans@hanshq.net>2018-02-07 10:01:03 +0000
commit5d4f6a8d9baa3cb5bb57e94317aad4a692abab62 (patch)
tree9c22dadfaaa22f2cd630585f03afbb9b58140076 /test
parentc00e97dc8ce0be0627432e653dd691722a6f7108 (diff)
Merging r324422:
------------------------------------------------------------------------ r324422 | efriedma | 2018-02-07 00:00:17 +0100 (Wed, 07 Feb 2018) | 16 lines [LivePhysRegs] Fix handling of return instructions. See D42509 for the original version of this. Basically, there are two significant changes to behavior here: - addLiveOuts always adds all pristine registers (even if a block has no successors). - addLiveOuts and addLiveOutsNoPristines always add all callee-saved registers for return blocks (including conditional return blocks). I cleaned up the functions a bit to make it clear these properties hold. Differential Revision: https://reviews.llvm.org/D42655 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@324466 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/pr25838.ll2
-rw-r--r--test/CodeGen/Thumb/stm-scavenging.ll46
2 files changed, 47 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/pr25838.ll b/test/CodeGen/ARM/pr25838.ll
index 0aa95fd2d72..f3bb98f4260 100644
--- a/test/CodeGen/ARM/pr25838.ll
+++ b/test/CodeGen/ARM/pr25838.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -verify-machineinstrs < %s
; PR25838
target triple = "armv7--linux-android"
diff --git a/test/CodeGen/Thumb/stm-scavenging.ll b/test/CodeGen/Thumb/stm-scavenging.ll
new file mode 100644
index 00000000000..3ed5763f295
--- /dev/null
+++ b/test/CodeGen/Thumb/stm-scavenging.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s | FileCheck %s
+target triple = "thumbv6---gnueabi"
+
+; Use STM to save the three registers
+; CHECK-LABEL: use_stm:
+; CHECK: .save {r7, lr}
+; CHECK: .setfp r7, sp
+; CHECK: stm r3!, {r0, r1, r2}
+; CHECK: bl throws_1
+define void @use_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
+entry:
+ %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
+ store i32 %a, i32* %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
+ store i32 %b, i32* %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
+ store i32 %c, i32* %arrayidx2, align 4
+ tail call void @throws_1(i32 %a, i32 %b, i32 %c) noreturn
+ unreachable
+}
+
+; Don't use STM: there is no available register to store
+; the address. We could transform this with some extra math, but
+; that currently isn't implemented.
+; CHECK-LABEL: no_stm:
+; CHECK: .save {r7, lr}
+; CHECK: .setfp r7, sp
+; CHECK: str r0,
+; CHECK: str r1,
+; CHECK: str r2,
+; CHECK: bl throws_2
+define void @no_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
+entry:
+ %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
+ store i32 %a, i32* %arrayidx, align 4
+ %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
+ store i32 %b, i32* %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
+ store i32 %c, i32* %arrayidx2, align 4
+ tail call void @throws_2(i32 %a, i32 %b, i32 %c, i32* %d) noreturn
+ unreachable
+}
+
+
+declare void @throws_1(i32, i32, i32) noreturn
+declare void @throws_2(i32, i32, i32, i32*) noreturn