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| author | Sam Parker <sam.parker@arm.com> | 2017-12-04 15:14:59 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2017-12-04 15:14:59 +0000 |
| commit | 4effab6b152682552a55a2f0997348cdc4f4c793 (patch) | |
| tree | c77b04a549810c842a2cc1b4100e39ef6d859895 /test | |
| parent | 7c3eddc7d6cbdde997da70dee1997751f8e48dfc (diff) | |
[ARM] CodeGen test
Add another and + load DAG combine test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/ARM/and-load-combine.ll | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/and-load-combine.ll b/test/CodeGen/ARM/and-load-combine.ll index 93c116561b7..f4ea7ebcf62 100644 --- a/test/CodeGen/ARM/and-load-combine.ll +++ b/test/CodeGen/ARM/and-load-combine.ll @@ -913,3 +913,54 @@ entry: %and = and i32 %or, 65535 ret i32 %and } + +define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) { +; ARM-LABEL: test5: +; ARM: @ BB#0: @ %entry +; ARM-NEXT: ldr r1, [r1] +; ARM-NEXT: ldr r0, [r0] +; ARM-NEXT: mul r1, r2, r1 +; ARM-NEXT: eor r0, r0, r3 +; ARM-NEXT: orr r0, r0, r1 +; ARM-NEXT: uxth r0, r0 +; ARM-NEXT: bx lr +; +; ARMEB-LABEL: test5: +; ARMEB: @ BB#0: @ %entry +; ARMEB-NEXT: ldr r1, [r1] +; ARMEB-NEXT: ldr r0, [r0] +; ARMEB-NEXT: mul r1, r2, r1 +; ARMEB-NEXT: eor r0, r0, r3 +; ARMEB-NEXT: orr r0, r0, r1 +; ARMEB-NEXT: uxth r0, r0 +; ARMEB-NEXT: bx lr +; +; THUMB1-LABEL: test5: +; THUMB1: @ BB#0: @ %entry +; THUMB1-NEXT: ldr r1, [r1] +; THUMB1-NEXT: muls r1, r2, r1 +; THUMB1-NEXT: ldr r0, [r0] +; THUMB1-NEXT: eors r0, r3 +; THUMB1-NEXT: orrs r0, r1 +; THUMB1-NEXT: uxth r0, r0 +; THUMB1-NEXT: bx lr +; +; THUMB2-LABEL: test5: +; THUMB2: @ BB#0: @ %entry +; THUMB2-NEXT: ldr r1, [r1] +; THUMB2-NEXT: ldr r0, [r0] +; THUMB2-NEXT: muls r1, r2, r1 +; THUMB2-NEXT: eors r0, r3 +; THUMB2-NEXT: orrs r0, r1 +; THUMB2-NEXT: uxth r0, r0 +; THUMB2-NEXT: bx lr +entry: + %0 = load i32, i32* %a, align 4 + %1 = load i32, i32* %b, align 4 + %mul = mul i32 %x, %1 + %ext = zext i16 %y to i32 + %xor = xor i32 %0, %ext + %or = or i32 %xor, %mul + %and = and i32 %or, 65535 + ret i32 %and +} |