Merging r323781:

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r323781 | sdardis | 2018-01-30 17:24:10 +0100 (Tue, 30 Jan 2018) | 15 lines

[mips] Fix incorrect sign extension for fpowi libcall

PR36061 showed that during the expansion of ISD::FPOWI, that there
was an incorrect zero extension of the integer argument which for
MIPS64 would then give incorrect results. Address this with the
existing mechanism for correcting sign extensions.

This resolves PR36061.

Thanks to James Cowgill for reporting the issue!

Reviewers: atanasyan, hfinkel

Differential Revision: https://reviews.llvm.org/D42537

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@324085 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 65 insertions, 0 deletions

diff --git a/test/CodeGen/Mips/pr36061.ll b/test/CodeGen/Mips/pr36061.ll
new file mode 100644
index 00000000000..6a9aa72aae0
--- /dev/null
+++ b/test/CodeGen/Mips/pr36061.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n64 | FileCheck %s --check-prefix=MIPSN64
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n32 | FileCheck %s --check-prefix=MIPSN32
+
+; Test that powi has its integer argument sign extended on mips64.
+
+declare double @llvm.powi.f64(double, i32)
+
+define double @powi(double %value, i32 %power) {
+; MIPSN64-LABEL: powi:
+; MIPSN64:       # %bb.0:
+; MIPSN64-NEXT:    daddiu $sp, $sp, -16
+; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN64-NEXT:    .cfi_offset 31, -8
+; MIPSN64-NEXT:    jal __powidf2
+; MIPSN64-NEXT:    sll $5, $5, 0
+; MIPSN64-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN64-NEXT:    jr $ra
+; MIPSN64-NEXT:    daddiu $sp, $sp, 16
+;
+; MIPSN32-LABEL: powi:
+; MIPSN32:       # %bb.0:
+; MIPSN32-NEXT:    addiu $sp, $sp, -16
+; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN32-NEXT:    .cfi_offset 31, -8
+; MIPSN32-NEXT:    jal __powidf2
+; MIPSN32-NEXT:    sll $5, $5, 0
+; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN32-NEXT:    jr $ra
+; MIPSN32-NEXT:    addiu $sp, $sp, 16
+        %1 = tail call double @llvm.powi.f64(double %value, i32 %power)
+        ret double %1
+}
+
+declare float @llvm.powi.f32(float, i32)
+
+define float @powfi(float %value, i32 %power) {
+; MIPSN64-LABEL: powfi:
+; MIPSN64:       # %bb.0:
+; MIPSN64-NEXT:    daddiu $sp, $sp, -16
+; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN64-NEXT:    .cfi_offset 31, -8
+; MIPSN64-NEXT:    jal __powisf2
+; MIPSN64-NEXT:    sll $5, $5, 0
+; MIPSN64-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN64-NEXT:    jr $ra
+; MIPSN64-NEXT:    daddiu $sp, $sp, 16
+;
+; MIPSN32-LABEL: powfi:
+; MIPSN32:       # %bb.0:
+; MIPSN32-NEXT:    addiu $sp, $sp, -16
+; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
+; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
+; MIPSN32-NEXT:    .cfi_offset 31, -8
+; MIPSN32-NEXT:    jal __powisf2
+; MIPSN32-NEXT:    sll $5, $5, 0
+; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
+; MIPSN32-NEXT:    jr $ra
+; MIPSN32-NEXT:    addiu $sp, $sp, 16
+        %1 = tail call float @llvm.powi.f32(float %value, i32 %power)
+        ret float %1
+}