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| author | Hans Wennborg <hans@hanshq.net> | 2018-08-14 09:30:11 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2018-08-14 09:30:11 +0000 |
| commit | 9360946c87148bfd76c4cf5e39bbd98ef1d18bb7 (patch) | |
| tree | 2b006d0aa033e448f023143e3911f671feccc72a /test | |
| parent | 1415ff0e98586ce902d8f135f7518e6f8f377772 (diff) | |
Merging r339600:
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r339600 | scott.linder | 2018-08-13 20:44:21 +0200 (Mon, 13 Aug 2018) | 8 lines
[CodeGen] Fix assert in SelectionDAG::computeKnownBits
Fix SelectionDAG::computeKnownBits asserting when handling EXTRACT_SUBVECTOR
when zero extending the demanded elements mask if it is already as long as the
source vector.
Differential Revision: https://reviews.llvm.org/D49574
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@339664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/AMDGPU/extract-subvector-equal-length.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll b/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll new file mode 100644 index 00000000000..6f7fb53f76c --- /dev/null +++ b/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll @@ -0,0 +1,30 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck %s + +; Test for ICE in SelectionDAG::computeKnownBits when visiting EXTRACT_SUBVECTOR +; with DemandedElts already as wide as the source vector. + +define <3 x i32> @quux() #0 { +; CHECK-LABEL: quux: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 1 +; CHECK-NEXT: v_mov_b32_e32 v2, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] +bb: + %tmp = shufflevector <4 x i8> <i8 1, i8 2, i8 3, i8 4>, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> + %tmp1 = extractelement <3 x i8> %tmp, i64 0 + %tmp2 = zext i8 %tmp1 to i32 + %tmp3 = insertelement <3 x i32> undef, i32 %tmp2, i32 0 + %tmp4 = extractelement <3 x i8> %tmp, i64 1 + %tmp5 = zext i8 %tmp4 to i32 + %tmp6 = insertelement <3 x i32> %tmp3, i32 %tmp5, i32 1 + %tmp7 = extractelement <3 x i8> %tmp, i64 2 + %tmp8 = zext i8 %tmp7 to i32 + %tmp9 = insertelement <3 x i32> %tmp6, i32 %tmp8, i32 2 + %tmp10 = lshr <3 x i32> %tmp9, <i32 1, i32 1, i32 1> + ret <3 x i32> %tmp10 +} + +attributes #0 = { noinline optnone } |