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| author | Hans Wennborg <hans@hanshq.net> | 2018-01-17 16:20:48 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2018-01-17 16:20:48 +0000 |
| commit | 7f0f287f2bc93e589bca62f124771055f8a4c4a7 (patch) | |
| tree | e63bed3db0939edf27b5b5e51b26dec02b33d994 /test/Transforms | |
| parent | 56c600d7e6837a18e20f9c3daa43379a1d449062 (diff) | |
Merging r322106:
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r322106 | abataev | 2018-01-09 11:08:22 -0800 (Tue, 09 Jan 2018) | 11 lines
[COST]Fix PR35865: Fix cost model evaluation for shuffle on X86.
Summary:
If the vector type is transformed to non-vector single type, the compile
may crash trying to get vector information about non-vector type.
Reviewers: RKSimon, spatel, mkuper, hfinkel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41862
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322680 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms')
| -rw-r--r-- | test/Transforms/SLPVectorizer/X86/PR35865.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/Transforms/SLPVectorizer/X86/PR35865.ll b/test/Transforms/SLPVectorizer/X86/PR35865.ll new file mode 100644 index 00000000000..b022dd7d915 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/PR35865.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s + +define void @_Z10fooConvertPDv4_xS0_S0_PKS_() { +; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4 +; CHECK-NEXT: [[CONV_I_4_I:%.*]] = fpext half [[TMP0]] to float +; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[CONV_I_4_I]] to i32 +; CHECK-NEXT: [[VECINS_I_4_I:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 4 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x half> undef, i32 5 +; CHECK-NEXT: [[CONV_I_5_I:%.*]] = fpext half [[TMP2]] to float +; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[CONV_I_5_I]] to i32 +; CHECK-NEXT: [[VECINS_I_5_I:%.*]] = insertelement <8 x i32> [[VECINS_I_4_I]], i32 [[TMP3]], i32 5 +; CHECK-NEXT: ret void +; +entry: + %0 = extractelement <16 x half> undef, i32 4 + %conv.i.4.i = fpext half %0 to float + %1 = bitcast float %conv.i.4.i to i32 + %vecins.i.4.i = insertelement <8 x i32> undef, i32 %1, i32 4 + %2 = extractelement <16 x half> undef, i32 5 + %conv.i.5.i = fpext half %2 to float + %3 = bitcast float %conv.i.5.i to i32 + %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5 + ret void +} |