[AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified

Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified.

Reviewers: rengolin, fhahn, olista01, echristo, efriedma

Reviewed By: fhahn

Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40363

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320992 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 69 insertions, 69 deletions

diff --git a/test/MC/AArch64/SVE/add.s b/test/MC/AArch64/SVE/add.s
index 30cb6ffc305..fa073ce1107 100644
--- a/test/MC/AArch64/SVE/add.s
+++ b/test/MC/AArch64/SVE/add.s
@@ -10,95 +10,95 @@
 add     z31.s, z31.s, z31.s
 // CHECK-INST: add     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 03 bf 04 <unknown>
 
 add     z23.d, z13.d, z8.d
 // CHECK-INST: add     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 01 e8 04 <unknown>
 
 add     z0.s, z0.s, z0.s
 // CHECK-INST: add     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 a0 04 <unknown>
 
 add     z31.d, z31.d, z31.d
 // CHECK-INST: add     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x03,0xff,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 03 ff 04 <unknown>
 
 add     z21.b, z10.b, z21.b
 // CHECK-INST: add     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x01,0x35,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 01 35 04 <unknown>
 
 add     z31.b, z31.b, z31.b
 // CHECK-INST: add     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 03 3f 04 <unknown>
 
 add     z0.h, z0.h, z0.h
 // CHECK-INST: add     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x60,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 60 04 <unknown>
 
 add     z23.b, z13.b, z8.b
 // CHECK-INST: add     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 01 28 04 <unknown>
 
 add     z0.d, z0.d, z0.d
 // CHECK-INST: add     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 e0 04 <unknown>
 
 add     z31.h, z31.h, z31.h
 // CHECK-INST: add     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 03 7f 04 <unknown>
 
 add     z0.b, z0.b, z0.b
 // CHECK-INST: add     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x20,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 20 04 <unknown>
 
 add     z21.d, z10.d, z21.d
 // CHECK-INST: add     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 01 f5 04 <unknown>
 
 add     z21.h, z10.h, z21.h
 // CHECK-INST: add     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x01,0x75,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 01 75 04 <unknown>
 
 add     z21.s, z10.s, z21.s
 // CHECK-INST: add     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 01 b5 04 <unknown>
 
 add     z23.h, z13.h, z8.h
 // CHECK-INST: add     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 01 68 04 <unknown>
 
 add     z23.s, z13.s, z8.s
 // CHECK-INST: add     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 01 a8 04 <unknown>
diff --git a/test/MC/AArch64/SVE/sub.s b/test/MC/AArch64/SVE/sub.s
index 73a75ab859e..0dd83c1bc40 100644
--- a/test/MC/AArch64/SVE/sub.s
+++ b/test/MC/AArch64/SVE/sub.s
@@ -10,95 +10,95 @@
 sub     z0.h, z0.h, z0.h
 // CHECK-INST: sub     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x04,0x60,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 04 60 04 <unknown>
 
 sub     z21.b, z10.b, z21.b
 // CHECK-INST: sub     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x05,0x35,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 05 35 04 <unknown>
 
 sub     z31.h, z31.h, z31.h
 // CHECK-INST: sub     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x07,0x7f,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 07 7f 04 <unknown>
 
 sub     z21.h, z10.h, z21.h
 // CHECK-INST: sub     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x05,0x75,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 05 75 04 <unknown>
 
 sub     z31.b, z31.b, z31.b
 // CHECK-INST: sub     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x07,0x3f,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 07 3f 04 <unknown>
 
 sub     z0.s, z0.s, z0.s
 // CHECK-INST: sub     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x04,0xa0,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 04 a0 04 <unknown>
 
 sub     z23.b, z13.b, z8.b
 // CHECK-INST: sub     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x05,0x28,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 05 28 04 <unknown>
 
 sub     z21.d, z10.d, z21.d
 // CHECK-INST: sub     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x05,0xf5,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 05 f5 04 <unknown>
 
 sub     z21.s, z10.s, z21.s
 // CHECK-INST: sub     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x05,0xb5,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 05 b5 04 <unknown>
 
 sub     z0.b, z0.b, z0.b
 // CHECK-INST: sub     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x04,0x20,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 04 20 04 <unknown>
 
 sub     z23.d, z13.d, z8.d
 // CHECK-INST: sub     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x05,0xe8,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 05 e8 04 <unknown>
 
 sub     z23.s, z13.s, z8.s
 // CHECK-INST: sub     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x05,0xa8,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 05 a8 04 <unknown>
 
 sub     z31.d, z31.d, z31.d
 // CHECK-INST: sub     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x07,0xff,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 07 ff 04 <unknown>
 
 sub     z23.h, z13.h, z8.h
 // CHECK-INST: sub     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x05,0x68,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: b7 05 68 04 <unknown>
 
 sub     z0.d, z0.d, z0.d
 // CHECK-INST: sub     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x04,0xe0,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 04 e0 04 <unknown>
 
 sub     z31.s, z31.s, z31.s
 // CHECK-INST: sub     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x07,0xbf,0x04]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 07 bf 04 <unknown>
diff --git a/test/MC/AArch64/SVE/zip1.s b/test/MC/AArch64/SVE/zip1.s
index 5dfdc596e19..47d08328fd9 100644
--- a/test/MC/AArch64/SVE/zip1.s
+++ b/test/MC/AArch64/SVE/zip1.s
@@ -10,95 +10,95 @@
 zip1    z0.b, z0.b, z0.b
 // CHECK-INST: zip1    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x60,0x20,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 20 05 <unknown>
 
 zip1    z0.h, z0.h, z0.h
 // CHECK-INST: zip1    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x60,0x60,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 05 <unknown>
 
 zip1    z0.s, z0.s, z0.s
 // CHECK-INST: zip1    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 a0 05 <unknown>
 
 zip1    z0.d, z0.d, z0.d
 // CHECK-INST: zip1    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 05 <unknown>
 
 zip1    z31.b, z31.b, z31.b
 // CHECK-INST: zip1    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 63 3f 05 <unknown>
 
 zip1    z31.h, z31.h, z31.h
 // CHECK-INST: zip1    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 63 7f 05 <unknown>
 
 zip1    z31.s, z31.s, z31.s
 // CHECK-INST: zip1    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 63 bf 05 <unknown>
 
 zip1    z31.d, z31.d, z31.d
 // CHECK-INST: zip1    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x63,0xff,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 63 ff 05 <unknown>
 
 zip1    p0.b, p0.b, p0.b
 // CHECK-INST: zip1    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x20,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 20 05 <unknown>
 
 zip1    p0.h, p0.h, p0.h
 // CHECK-INST: zip1    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x40,0x60,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 60 05 <unknown>
 
 zip1    p0.s, p0.s, p0.s
 // CHECK-INST: zip1    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 a0 05 <unknown>
 
 zip1    p0.d, p0.d, p0.d
 // CHECK-INST: zip1    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 e0 05 <unknown>
 
 zip1    p15.b, p15.b, p15.b
 // CHECK-INST: zip1    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 41 2f 05 <unknown>
 
 zip1    p15.s, p15.s, p15.s
 // CHECK-INST: zip1    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 41 af 05 <unknown>
 
 zip1    p15.h, p15.h, p15.h
 // CHECK-INST: zip1    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 41 6f 05 <unknown>
 
 zip1    p15.d, p15.d, p15.d
 // CHECK-INST: zip1    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x41,0xef,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 41 ef 05 <unknown>
diff --git a/test/MC/AArch64/SVE/zip2.s b/test/MC/AArch64/SVE/zip2.s
index d3e6126e2d7..3158e989ce7 100644
--- a/test/MC/AArch64/SVE/zip2.s
+++ b/test/MC/AArch64/SVE/zip2.s
@@ -10,95 +10,95 @@
 zip2    z0.b, z0.b, z0.b
 // CHECK-INST: zip2    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x64,0x20,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 64 20 05 <unknown>
 
 zip2    z0.h, z0.h, z0.h
 // CHECK-INST: zip2    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x64,0x60,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 64 60 05 <unknown>
 
 zip2    z0.s, z0.s, z0.s
 // CHECK-INST: zip2    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 64 a0 05 <unknown>
 
 zip2    z0.d, z0.d, z0.d
 // CHECK-INST: zip2    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 64 e0 05 <unknown>
 
 zip2    z31.b, z31.b, z31.b
 // CHECK-INST: zip2    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 67 3f 05 <unknown>
 
 zip2    z31.h, z31.h, z31.h
 // CHECK-INST: zip2    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 67 7f 05 <unknown>
 
 zip2    z31.s, z31.s, z31.s
 // CHECK-INST: zip2    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 67 bf 05 <unknown>
 
 zip2    z31.d, z31.d, z31.d
 // CHECK-INST: zip2    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x67,0xff,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ff 67 ff 05 <unknown>
 
 zip2    p0.b, p0.b, p0.b
 // CHECK-INST: zip2    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x44,0x20,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 44 20 05 <unknown>
 
 zip2    p0.h, p0.h, p0.h
 // CHECK-INST: zip2    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x44,0x60,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 44 60 05 <unknown>
 
 zip2    p0.s, p0.s, p0.s
 // CHECK-INST: zip2    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 44 a0 05 <unknown>
 
 zip2    p0.d, p0.d, p0.d
 // CHECK-INST: zip2    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 44 e0 05 <unknown>
 
 zip2    p15.b, p15.b, p15.b
 // CHECK-INST: zip2    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 45 2f 05 <unknown>
 
 zip2    p15.h, p15.h, p15.h
 // CHECK-INST: zip2    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 45 6f 05 <unknown>
 
 zip2    p15.s, p15.s, p15.s
 // CHECK-INST: zip2    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 45 af 05 <unknown>
 
 zip2    p15.d, p15.d, p15.d
 // CHECK-INST: zip2    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x45,0xef,0x05]
-// CHECK-ERROR: invalid operand for instruction
+// CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: ef 45 ef 05 <unknown>
diff --git a/test/MC/AArch64/armv8.2a-statistical-profiling.s b/test/MC/AArch64/armv8.2a-statistical-profiling.s
index 5cb10931878..a11a4b227ac 100644
--- a/test/MC/AArch64/armv8.2a-statistical-profiling.s
+++ b/test/MC/AArch64/armv8.2a-statistical-profiling.s
@@ -3,7 +3,7 @@
 
   psb csync
 // CHECK: psb csync              // encoding: [0x3f,0x22,0x03,0xd5]
-// NO_SPE:  invalid operand for instruction
+// NO_SPE:  instruction requires: spe
 
   msr pmblimitr_el1, x0
   msr pmbptr_el1, x0
diff --git a/test/MC/AArch64/armv8.3a-rcpc.s b/test/MC/AArch64/armv8.3a-rcpc.s
index 0d2da8e2d03..cd254acdf96 100644
--- a/test/MC/AArch64/armv8.3a-rcpc.s
+++ b/test/MC/AArch64/armv8.3a-rcpc.s
@@ -18,9 +18,9 @@
 // CHECK: ldapr x0, [x0]     // encoding: [0x00,0xc0,0xbf,0xf8]
 // CHECK: ldapr w18, [x0]    // encoding: [0x12,0xc0,0xbf,0xb8]
 // CHECK: ldapr x15, [x0]    // encoding: [0x0f,0xc0,0xbf,0xf8]
-// CHECK-REQ: error: invalid operand for instruction
-// CHECK-REQ: error: invalid operand for instruction
-// CHECK-REQ: error: invalid operand for instruction
-// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: instruction requires: rcpc
+// CHECK-REQ: error: instruction requires: rcpc
+// CHECK-REQ: error: instruction requires: rcpc
+// CHECK-REQ: error: instruction requires: rcpc
 // CHECK-REQ: error: instruction requires: rcpc
 // CHECK-REQ: error: instruction requires: rcpc