diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:56:07 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:56:07 +0000 |
| commit | 94253b305095f523da61fbec7e9d7b8a84d5cce0 (patch) | |
| tree | 06519a00d8b53bf903f5a5896f5116f468f57ee9 /test/MC | |
| parent | b9b4df7d228873b4ed71c585af6de41232a8a3d2 (diff) | |
[RISCV] MC layer support for the standard RV64M instruction set extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320026 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
| -rw-r--r-- | test/MC/RISCV/rv32m-invalid.s | 9 | ||||
| -rw-r--r-- | test/MC/RISCV/rv64m-valid.s | 20 |
2 files changed, 29 insertions, 0 deletions
diff --git a/test/MC/RISCV/rv32m-invalid.s b/test/MC/RISCV/rv32m-invalid.s new file mode 100644 index 00000000000..5e268e8b916 --- /dev/null +++ b/test/MC/RISCV/rv32m-invalid.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+m < %s 2>&1 | FileCheck %s + +# RV64M instructions can't be used for RV32 +mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled +remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled + diff --git a/test/MC/RISCV/rv64m-valid.s b/test/MC/RISCV/rv64m-valid.s new file mode 100644 index 00000000000..3de540dac21 --- /dev/null +++ b/test/MC/RISCV/rv64m-valid.s @@ -0,0 +1,20 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+m -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \ +# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: mulw ra, sp, gp +# CHECK: encoding: [0xbb,0x00,0x31,0x02] +mulw ra, sp, gp +# CHECK-INST: divw tp, t0, t1 +# CHECK: encoding: [0x3b,0xc2,0x62,0x02] +divw tp, t0, t1 +# CHECK-INST: divuw t2, s0, s2 +# CHECK: encoding: [0xbb,0x53,0x24,0x03] +divuw t2, s0, s2 +# CHECK-INST: remw a0, a1, a2 +# CHECK: encoding: [0x3b,0xe5,0xc5,0x02] +remw a0, a1, a2 +# CHECK-INST: remuw a3, a4, a5 +# CHECK: encoding: [0xbb,0x76,0xf7,0x02] +remuw a3, a4, a5 |