MIR: Print the register class or bank in vreg defs

This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8
author: Justin Bogner <mail@justinbogner.com> 2017-10-24 18:04:54 +0000
committer: Justin Bogner <mail@justinbogner.com> 2017-10-24 18:04:54 +0000
commit: edab7579664b13faad3680c676c6b8a49d2ea00b (patch)
tree: dee3b97d46f3325ed2ceb0ddedb5e54e151a3676 /test/CodeGen
parent: 7c330fabaedaba3d02c58bc3cc1198896c895f34 (diff)
245 files changed, 5380 insertions, 6937 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index a70cee0efcb..40f65b3774e 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -4,14 +4,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-apple-ios9.0"
 
 ; CHECK-LABEL: name: test_varargs
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
-; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
-; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
+; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
 
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %d0 = COPY [[D_ONE]]
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 0e77adc16fe..3888628fd1e 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -4,14 +4,14 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-linux-gnu"
 
 ; CHECK-LABEL: name: args_i32
-; CHECK: %[[ARG0:[0-9]+]](s32) = COPY %w0
-; CHECK: %{{[0-9]+}}(s32) = COPY %w1
-; CHECK: %{{[0-9]+}}(s32) = COPY %w2
-; CHECK: %{{[0-9]+}}(s32) = COPY %w3
-; CHECK: %{{[0-9]+}}(s32) = COPY %w4
-; CHECK: %{{[0-9]+}}(s32) = COPY %w5
-; CHECK: %{{[0-9]+}}(s32) = COPY %w6
-; CHECK: %{{[0-9]+}}(s32) = COPY %w7
+; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
+; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
 ; CHECK: %w0 = COPY %[[ARG0]]
 
 define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
@@ -20,14 +20,14 @@ define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
 }
 
 ; CHECK-LABEL: name: args_i64
-; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %x0
-; CHECK: %{{[0-9]+}}(s64) = COPY %x1
-; CHECK: %{{[0-9]+}}(s64) = COPY %x2
-; CHECK: %{{[0-9]+}}(s64) = COPY %x3
-; CHECK: %{{[0-9]+}}(s64) = COPY %x4
-; CHECK: %{{[0-9]+}}(s64) = COPY %x5
-; CHECK: %{{[0-9]+}}(s64) = COPY %x6
-; CHECK: %{{[0-9]+}}(s64) = COPY %x7
+; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
+; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
 ; CHECK: %x0 = COPY %[[ARG0]]
 define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
                      i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
@@ -36,14 +36,14 @@ define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
 
 
 ; CHECK-LABEL: name: args_ptrs
-; CHECK: %[[ARG0:[0-9]+]](p0) = COPY %x0
-; CHECK: %{{[0-9]+}}(p0) = COPY %x1
-; CHECK: %{{[0-9]+}}(p0) = COPY %x2
-; CHECK: %{{[0-9]+}}(p0) = COPY %x3
-; CHECK: %{{[0-9]+}}(p0) = COPY %x4
-; CHECK: %{{[0-9]+}}(p0) = COPY %x5
-; CHECK: %{{[0-9]+}}(p0) = COPY %x6
-; CHECK: %{{[0-9]+}}(p0) = COPY %x7
+; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
+; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
 ; CHECK: %x0 = COPY %[[ARG0]]
 define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
                       [3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
@@ -51,28 +51,28 @@ define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
 }
 
 ; CHECK-LABEL: name: args_arr
-; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %d0
+; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
 ; CHECK: %d0 = COPY %[[ARG0]]
 define [1 x double] @args_arr([1 x double] %d0) {
   ret [1 x double] %d0
 }
 
 ; CHECK-LABEL: name: test_varargs
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3
-; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1
-; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[D_ONE:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[TWELVE:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[THREE:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
+; CHECK: [[ONE:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+; CHECK: [[FOUR:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
 
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %d0 = COPY [[D_ONE]]
 ; CHECK: %x1 = COPY [[TWELVE]]
-; CHECK: [[THREE_TMP:%[0-9]+]](s32) = G_ANYEXT [[THREE]]
+; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
 ; CHECK: %w2 = COPY [[THREE_TMP]](s32)
-; CHECK: [[ONE_TMP:%[0-9]+]](s32) = G_ANYEXT [[ONE]]
+; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
 ; CHECK: %w3 = COPY [[ONE_TMP]](s32)
 ; CHECK: %w4 = COPY [[FOUR]](s32)
 ; CHECK: %s1 = COPY [[F_ONE]](s32)
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
index cd3ea9715e0..62abf3d81d5 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
@@ -7,8 +7,8 @@
 ; CHECK:  - { id: 0, name: StackGuardSlot,  type: default, offset: 0, size: 8, alignment: 8,
 ; CHECK-NOT: id: 1
 
-; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
-; CHECK: [[GUARD:%[0-9]+]](p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
+; CHECK: [[GUARD_SLOT:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
+; CHECK: [[GUARD:%[0-9]+]]:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard)
 ; CHECK: G_STORE [[GUARD]](p0), [[GUARD_SLOT]](p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
 declare void @llvm.stackprotector(i8*, i8**)
 define void @test_stack_guard_remat2() {
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 6a35af55f6c..7c67a22e23c 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -7,9 +7,9 @@ target triple = "aarch64--"
 
 ; Tests for add.
 ; CHECK-LABEL: name: addi64
-; CHECK:      [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]]
+; CHECK:      [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @addi64(i64 %arg1, i64 %arg2) {
@@ -18,9 +18,9 @@ define i64 @addi64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: muli64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @muli64(i64 %arg1, i64 %arg2) {
@@ -41,10 +41,10 @@ define i64 @muli64(i64 %arg1, i64 %arg2) {
 ; CHECK-NEXT:       stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
 ; CHECK-NEXT:       di-variable: '', di-expression: '', di-location: '' }
 ; CHECK-NEXT:   - { id: 3, name: ptr4, type: default, offset: 0, size: 1, alignment: 8,
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3
-; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.3.ptr4
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.ptr1
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.1.ptr2
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.2.ptr3
+; CHECK: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.3.ptr4
 define void @allocai64() {
   %ptr1 = alloca i64
   %ptr2 = alloca i64, align 1
@@ -107,10 +107,10 @@ end:
 ; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
 ; CHECK:                  %[[FALSE:bb.[0-9]+.false]](0x40000000)
 ;
-; CHECK: [[ADDR:%.*]](p0) = COPY %x0
+; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
 ;
 ; Check that we emit the correct branch.
-; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0)
+; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
 ; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]]
 ; CHECK: G_BR %[[FALSE]]
 ;
@@ -135,19 +135,19 @@ false:
 ;
 ; CHECK: {{bb.[0-9]+.entry}}:
 ; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
-; CHECK: %0(s32) = COPY %w0
-; CHECK: %[[reg100:[0-9]+]](s32) = G_CONSTANT i32 100
-; CHECK: %[[reg200:[0-9]+]](s32) = G_CONSTANT i32 200
-; CHECK: %[[reg0:[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: %[[reg1:[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: %[[reg2:[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: %[[regicmp100:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
+; CHECK: %0:_(s32) = COPY %w0
+; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
+; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
+; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: %[[reg1:[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: %[[reg2:[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: %[[regicmp100:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0
 ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
 ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
 ;
 ; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
 ; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
-; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
+; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
 ; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
 ; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
 ;
@@ -157,20 +157,20 @@ false:
 ;
 ; CHECK: [[BB_DEFAULT]]:
 ; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
-; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]]
+; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]]
 ; CHECK: G_BR %[[BB_RET]]
 ;
 ; CHECK: [[BB_CASE100]]:
 ; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
-; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]]
+; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]]
 ; CHECK: G_BR %[[BB_RET]]
 ;
 ; CHECK: [[BB_CASE200]]:
 ; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
-; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]]
+; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]]
 ;
 ; CHECK: [[BB_RET]]:
-; CHECK-NEXT: %[[regret:[0-9]+]](s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
+; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
 ; CHECK:  %w0 = COPY %[[regret]](s32)
 ; CHECK:  RET_ReallyLR implicit %w0
 ;
@@ -289,9 +289,9 @@ L2:                                               ; preds = %L1
 
 ; Tests for or.
 ; CHECK-LABEL: name: ori64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @ori64(i64 %arg1, i64 %arg2) {
@@ -300,9 +300,9 @@ define i64 @ori64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: ori32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @ori32(i32 %arg1, i32 %arg2) {
@@ -312,9 +312,9 @@ define i32 @ori32(i32 %arg1, i32 %arg2) {
 
 ; Tests for xor.
 ; CHECK-LABEL: name: xori64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @xori64(i64 %arg1, i64 %arg2) {
@@ -323,9 +323,9 @@ define i64 @xori64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: xori32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @xori32(i32 %arg1, i32 %arg2) {
@@ -335,9 +335,9 @@ define i32 @xori32(i32 %arg1, i32 %arg2) {
 
 ; Tests for and.
 ; CHECK-LABEL: name: andi64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @andi64(i64 %arg1, i64 %arg2) {
@@ -346,9 +346,9 @@ define i64 @andi64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: andi32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @andi32(i32 %arg1, i32 %arg2) {
@@ -358,9 +358,9 @@ define i32 @andi32(i32 %arg1, i32 %arg2) {
 
 ; Tests for sub.
 ; CHECK-LABEL: name: subi64
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @subi64(i64 %arg1, i64 %arg2) {
@@ -369,9 +369,9 @@ define i64 @subi64(i64 %arg1, i64 %arg2) {
 }
 
 ; CHECK-LABEL: name: subi32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @subi32(i32 %arg1, i32 %arg2) {
@@ -380,8 +380,8 @@ define i32 @subi32(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: ptrtoint
-; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[ARG1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @ptrtoint(i64* %a) {
@@ -390,8 +390,8 @@ define i64 @ptrtoint(i64* %a) {
 }
 
 ; CHECK-LABEL: name: inttoptr
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[RES:%[0-9]+]](p0) = G_INTTOPTR [[ARG1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64* @inttoptr(i64 %a) {
@@ -400,7 +400,7 @@ define i64* @inttoptr(i64 %a) {
 }
 
 ; CHECK-LABEL: name: trivial_bitcast
-; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK: %x0 = COPY [[ARG1]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64* @trivial_bitcast(i8* %a) {
@@ -409,13 +409,13 @@ define i64* @trivial_bitcast(i8* %a) {
 }
 
 ; CHECK-LABEL: name: trivial_bitcast_with_copy
-; CHECK:     [[A:%[0-9]+]](p0) = COPY %x0
+; CHECK:     [[A:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK:     G_BR %[[CAST:bb\.[0-9]+.cast]]
 
 ; CHECK: [[END:bb\.[0-9]+.end]]:
 
 ; CHECK: [[CAST]]:
-; CHECK:     {{%[0-9]+}}(p0) = COPY [[A]]
+; CHECK:     {{%[0-9]+}}:_(p0) = COPY [[A]]
 ; CHECK:     G_BR %[[END]]
 define i64* @trivial_bitcast_with_copy(i8* %a) {
   br label %cast
@@ -429,9 +429,9 @@ cast:
 }
 
 ; CHECK-LABEL: name: bitcast
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[RES1:%[0-9]+]](<2 x s32>) = G_BITCAST [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]](s64) = G_BITCAST [[RES1]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
 ; CHECK: %x0 = COPY [[RES2]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @bitcast(i64 %a) {
@@ -441,10 +441,10 @@ define i64 @bitcast(i64 %a) {
 }
 
 ; CHECK-LABEL: name: trunc
-; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_LOAD
-; CHECK: [[RES1:%[0-9]+]](s8) = G_TRUNC [[ARG1]]
-; CHECK: [[RES2:%[0-9]+]](<4 x s16>) = G_TRUNC [[VEC]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
+; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
+; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
 define void @trunc(i64 %a) {
   %vecptr = alloca <4 x i32>
   %vec = load <4 x i32>, <4 x i32>* %vecptr
@@ -454,13 +454,13 @@ define void @trunc(i64 %a) {
 }
 
 ; CHECK-LABEL: name: load
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
-; CHECK: [[VAL1:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
-; CHECK: [[VAL2:%[0-9]+]](s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
-; CHECK: [[SUM2:%.*]](s64) = G_ADD [[VAL1]], [[VAL2]]
-; CHECK: [[VAL3:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
-; CHECK: [[SUM3:%[0-9]+]](s64) = G_ADD [[SUM2]], [[VAL3]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
+; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
+; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42)
+; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
+; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
+; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
 ; CHECK: %x0 = COPY [[SUM3]]
 ; CHECK: RET_ReallyLR implicit %x0
 define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
@@ -475,10 +475,10 @@ define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
 }
 
 ; CHECK-LABEL: name: store
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1
-; CHECK: [[VAL1:%[0-9]+]](s64) = COPY %x2
-; CHECK: [[VAL2:%[0-9]+]](s64) = COPY %x3
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
+; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY %x2
+; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY %x3
 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16)
 ; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42)
 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr)
@@ -492,12 +492,12 @@ define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2)
 }
 
 ; CHECK-LABEL: name: intrinsics
-; CHECK: [[CUR:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[BITS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[CREG:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
-; CHECK: [[PTR_VEC:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr.vec
-; CHECK: [[VEC:%[0-9]+]](<8 x s8>) = G_LOAD [[PTR_VEC]]
+; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[CREG:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
+; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
+; CHECK: [[VEC:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[PTR_VEC]]
 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0)
 ; CHECK: RET_ReallyLR
 declare i8* @llvm.returnaddress(i32)
@@ -516,12 +516,12 @@ define void @intrinsics(i32 %cur, i32 %bits) {
 ; CHECK:     G_BR %[[FALSE:bb\.[0-9]+.false]]
 
 ; CHECK: [[TRUE]]:
-; CHECK:     [[RES1:%[0-9]+]](s32) = G_LOAD
+; CHECK:     [[RES1:%[0-9]+]]:_(s32) = G_LOAD
 
 ; CHECK: [[FALSE]]:
-; CHECK:     [[RES2:%[0-9]+]](s32) = G_LOAD
+; CHECK:     [[RES2:%[0-9]+]]:_(s32) = G_LOAD
 
-; CHECK:     [[RES:%[0-9]+]](s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
+; CHECK:     [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
 ; CHECK:     %w0 = COPY [[RES]]
 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
   br i1 %tst, label %true, label %false
@@ -551,13 +551,13 @@ define void @unreachable(i32 %a) {
   ; It's important that constants are after argument passing, but before the
   ; rest of the entry block.
 ; CHECK-LABEL: name: constant_int
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[ONE:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
 
 ; CHECK: {{bb.[0-9]+}}.next:
-; CHECK: [[SUM1:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[SUM2:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]]
-; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[SUM1]], [[SUM2]]
+; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
 ; CHECK: %w0 = COPY [[RES]]
 
 define i32 @constant_int(i32 %in) {
@@ -571,24 +571,24 @@ next:
 }
 
 ; CHECK-LABEL: name: constant_int_start
-; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]]
+; CHECK: [[TWO:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[TWO]], [[ANSWER]]
 define i32 @constant_int_start() {
   %res = add i32 2, 42
   ret i32 %res
 }
 
 ; CHECK-LABEL: name: test_undef
-; CHECK: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
+; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
 ; CHECK: %w0 = COPY [[UNDEF]]
 define i32 @test_undef() {
   ret i32 undef
 }
 
 ; CHECK-LABEL: name: test_constant_inttoptr
-; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
-; CHECK: [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[ONE]]
+; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
 ; CHECK: %x0 = COPY [[PTR]]
 define i8* @test_constant_inttoptr() {
   ret i8* inttoptr(i64 1 to i8*)
@@ -597,15 +597,15 @@ define i8* @test_constant_inttoptr() {
   ; This failed purely because the Constant -> VReg map was kept across
   ; functions, so reuse the "i64 1" from above.
 ; CHECK-LABEL: name: test_reused_constant
-; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1
+; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
 ; CHECK: %x0 = COPY [[ONE]]
 define i64 @test_reused_constant() {
   ret i64 1
 }
 
 ; CHECK-LABEL: name: test_sext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s64) = G_SEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_sext(i32 %in) {
   %res = sext i32 %in to i64
@@ -613,8 +613,8 @@ define i64 @test_sext(i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_zext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s64) = G_ZEXT [[IN]]
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_zext(i32 %in) {
   %res = zext i32 %in to i64
@@ -622,9 +622,9 @@ define i64 @test_zext(i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_shl
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_shl(i32 %arg1, i32 %arg2) {
@@ -634,9 +634,9 @@ define i32 @test_shl(i32 %arg1, i32 %arg2) {
 
 
 ; CHECK-LABEL: name: test_lshr
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_lshr(i32 %arg1, i32 %arg2) {
@@ -645,9 +645,9 @@ define i32 @test_lshr(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_ashr
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_ashr(i32 %arg1, i32 %arg2) {
@@ -656,9 +656,9 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_sdiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
@@ -667,9 +667,9 @@ define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_udiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_udiv(i32 %arg1, i32 %arg2) {
@@ -678,9 +678,9 @@ define i32 @test_udiv(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_srem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_srem(i32 %arg1, i32 %arg2) {
@@ -689,9 +689,9 @@ define i32 @test_srem(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_urem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @test_urem(i32 %arg1, i32 %arg2) {
@@ -700,15 +700,15 @@ define i32 @test_urem(i32 %arg1, i32 %arg2) {
 }
 
 ; CHECK-LABEL: name: test_constant_null
-; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: %x0 = COPY [[NULL]]
 define i8* @test_constant_null() {
   ret i8* null
 }
 
 ; CHECK-LABEL: name: test_struct_memops
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from  %ir.addr, align 4)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from  %ir.addr, align 4)
 ; CHECK: G_STORE [[VAL]](s64), [[ADDR]](p0) :: (store 8 into  %ir.addr, align 4)
 define void @test_struct_memops({ i8, i32 }* %addr) {
   %val = load { i8, i32 }, { i8, i32 }* %addr
@@ -717,8 +717,8 @@ define void @test_struct_memops({ i8, i32 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_i1_memops
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s1) = G_LOAD [[ADDR]](p0) :: (load 1 from  %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load 1 from  %ir.addr)
 ; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store 1 into  %ir.addr)
 define void @test_i1_memops(i1* %addr) {
   %val = load i1, i1* %addr
@@ -727,10 +727,10 @@ define void @test_i1_memops(i1* %addr) {
 }
 
 ; CHECK-LABEL: name: int_comparison
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
 define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
   %res = icmp ne i32 %a, %b
@@ -739,10 +739,10 @@ define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
 }
 
 ; CHECK-LABEL: name: ptr_comparison
-; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
 define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
   %res = icmp eq i8* %a, %b
@@ -751,9 +751,9 @@ define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
 }
 
 ; CHECK-LABEL: name: test_fadd
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fadd(float %arg1, float %arg2) {
@@ -762,9 +762,9 @@ define float @test_fadd(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fsub
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fsub(float %arg1, float %arg2) {
@@ -773,9 +773,9 @@ define float @test_fsub(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fmul
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fmul(float %arg1, float %arg2) {
@@ -784,9 +784,9 @@ define float @test_fmul(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_fdiv
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_fdiv(float %arg1, float %arg2) {
@@ -795,9 +795,9 @@ define float @test_fdiv(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_frem
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0
-; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1
-; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]]
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %s0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %s0
 define float @test_frem(float %arg1, float %arg2) {
@@ -806,13 +806,13 @@ define float @test_frem(float %arg1, float %arg2) {
 }
 
 ; CHECK-LABEL: name: test_sadd_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SADDO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
 define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -822,14 +822,14 @@ define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_uadd_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
 define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -839,13 +839,13 @@ define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_ssub_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SSUBO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32)
 define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
@@ -855,14 +855,14 @@ define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
 }
 
 ; CHECK-LABEL: name: test_usub_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
 define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
@@ -872,13 +872,13 @@ define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) {
 }
 
 ; CHECK-LABEL: name: test_smul_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SMULO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
 define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -888,13 +888,13 @@ define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_umul_overflow
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UMULO [[LHS]], [[RHS]]
-; CHECK: [[TMP:%[0-9]+]](s64) = G_IMPLICIT_DEF
-; CHECK: [[TMP1:%[0-9]+]](s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
-; CHECK: [[RES:%[0-9]+]](s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
+; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_INSERT [[TMP1]], [[OVERFLOW]](s1), 32
 ; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0)
 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
 define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
@@ -904,8 +904,8 @@ define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) {
 }
 
 ; CHECK-LABEL: name: test_extractvalue
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT [[STRUCT]](s128), 64
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT]](s128), 64
 ; CHECK: %w0 = COPY [[RES]]
 %struct.nested = type {i8, { i8, i32 }, i32}
 define i32 @test_extractvalue(%struct.nested* %addr) {
@@ -915,8 +915,8 @@ define i32 @test_extractvalue(%struct.nested* %addr) {
 }
 
 ; CHECK-LABEL: name: test_extractvalue_agg
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 32
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 32
 ; CHECK: G_STORE [[RES]]
 define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
   %struct = load %struct.nested, %struct.nested* %addr
@@ -926,9 +926,9 @@ define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
 }
 
 ; CHECK-LABEL: name: test_insertvalue
-; CHECK: [[VAL:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[NEWSTRUCT:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
+; CHECK: [[VAL:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[NEWSTRUCT:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
 ; CHECK: G_STORE [[NEWSTRUCT]](s128),
 define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
   %struct = load %struct.nested, %struct.nested* %addr
@@ -939,9 +939,9 @@ define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
 
 define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
 ; CHECK-LABEL: name: test_trivial_insert
-; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[RES:%[0-9]+]](s64) = COPY [[VAL]](s64)
+; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY [[VAL]](s64)
 ; CHECK: %x0 = COPY [[RES]]
   %res = insertvalue [1 x i64] %s, i64 %val, 0
   ret [1 x i64] %res
@@ -949,18 +949,18 @@ define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
 
 define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
 ; CHECK-LABEL: name: test_trivial_insert_ptr
-; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[VAL]](p0)
+; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[VAL]](p0)
 ; CHECK: %x0 = COPY [[RES]]
   %res = insertvalue [1 x i8*] %s, i8* %val, 0
   ret [1 x i8*] %res
 }
 
 ; CHECK-LABEL: name: test_insertvalue_agg
-; CHECK: [[SMALLSTRUCT:%[0-9]+]](s64) = G_LOAD
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
+; CHECK: [[SMALLSTRUCT:%[0-9]+]]:_(s64) = G_LOAD
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
+; CHECK: [[RES:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32
 ; CHECK: G_STORE [[RES]](s128)
 define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
   %smallstruct = load {i8, i32}, {i8, i32}* %addr2
@@ -971,11 +971,11 @@ define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
 }
 
 ; CHECK-LABEL: name: test_select
-; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w2
-; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w2
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %w0 = COPY [[RES]]
 define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
   %res = select i1 %tst, i32 %lhs, i32 %rhs
@@ -983,11 +983,11 @@ define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
 }
 
 ; CHECK-LABEL: name: test_select_ptr
-; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[RES:%[0-9]+]](p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %x0 = COPY [[RES]]
 define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
   %res = select i1 %tst, i8* %lhs, i8* %rhs
@@ -995,11 +995,11 @@ define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
 }
 
 ; CHECK-LABEL: name: test_select_vec
-; CHECK: [[TST_C:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TST:%[0-9]+]](s1) = G_TRUNC [[TST_C]]
-; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q1
-; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
+; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
+; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
 ; CHECK: %q0 = COPY [[RES]]
 define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
   %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
@@ -1007,11 +1007,11 @@ define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
 }
 
 ; CHECK-LABEL: name: test_vselect_vec
-; CHECK: [[TST32:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q1
-; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q2
-; CHECK: [[TST:%[0-9]+]](<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
-; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
+; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
+; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q2
+; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
+; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
 ; CHECK: %q0 = COPY [[RES]]
 define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
   %tst = trunc <4 x i32> %tst32 to <4 x i1>
@@ -1020,9 +1020,9 @@ define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %
 }
 
 ; CHECK-LABEL: name: test_fptosi
-; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOSI [[FP]](s32)
+; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_fptosi(float* %fp.addr) {
   %fp = load float, float* %fp.addr
@@ -1031,9 +1031,9 @@ define i64 @test_fptosi(float* %fp.addr) {
 }
 
 ; CHECK-LABEL: name: test_fptoui
-; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0)
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOUI [[FP]](s32)
+; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
 ; CHECK: %x0 = COPY [[RES]]
 define i64 @test_fptoui(float* %fp.addr) {
   %fp = load float, float* %fp.addr
@@ -1042,9 +1042,9 @@ define i64 @test_fptoui(float* %fp.addr) {
 }
 
 ; CHECK-LABEL: name: test_sitofp
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[FP:%[0-9]+]](s64) = G_SITOFP [[IN]](s32)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
 define void @test_sitofp(double* %addr, i32 %in) {
   %fp = sitofp i32 %in to double
@@ -1053,9 +1053,9 @@ define void @test_sitofp(double* %addr, i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_uitofp
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[FP:%[0-9]+]](s64) = G_UITOFP [[IN]](s32)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
 define void @test_uitofp(double* %addr, i32 %in) {
   %fp = uitofp i32 %in to double
@@ -1064,8 +1064,8 @@ define void @test_uitofp(double* %addr, i32 %in) {
 }
 
 ; CHECK-LABEL: name: test_fpext
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s64) = G_FPEXT [[IN]](s32)
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
 ; CHECK: %d0 = COPY [[RES]]
 define double @test_fpext(float %in) {
   %res = fpext float %in to double
@@ -1073,8 +1073,8 @@ define double @test_fpext(float %in) {
 }
 
 ; CHECK-LABEL: name: test_fptrunc
-; CHECK: [[IN:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FPTRUNC [[IN]](s64)
+; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
 ; CHECK: %s0 = COPY [[RES]]
 define float @test_fptrunc(double %in) {
   %res = fptrunc double %in to float
@@ -1082,8 +1082,8 @@ define float @test_fptrunc(double %in) {
 }
 
 ; CHECK-LABEL: name: test_constant_float
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT float 1.500000e+00
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
 ; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
 define void @test_constant_float(float* %addr) {
   store float 1.5, float* %addr
@@ -1091,12 +1091,12 @@ define void @test_constant_float(float* %addr) {
 }
 
 ; CHECK-LABEL: name: float_comparison
-; CHECK: [[LHSADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[RHSADDR:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[BOOLADDR:%[0-9]+]](p0) = COPY %x2
-; CHECK: [[LHS:%[0-9]+]](s32) = G_LOAD [[LHSADDR]](p0)
-; CHECK: [[RHS:%[0-9]+]](s32) = G_LOAD [[RHSADDR]](p0)
-; CHECK: [[TST:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
+; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY %x2
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
+; CHECK: [[TST:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
 ; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0)
 define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
   %a = load float, float* %a.addr
@@ -1107,10 +1107,10 @@ define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) {
 }
 
 ; CHECK-LABEL: name: trivial_float_comparison
-; CHECK: [[ENTRY_R1:%[0-9]+]](s1) = G_CONSTANT i1 false
-; CHECK: [[ENTRY_R2:%[0-9]+]](s1) = G_CONSTANT i1 true
-; CHECK: [[R1:%[0-9]+]](s1) = COPY [[ENTRY_R1]](s1)
-; CHECK: [[R2:%[0-9]+]](s1) = COPY [[ENTRY_R2]](s1)
+; CHECK: [[ENTRY_R1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+; CHECK: [[ENTRY_R2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
+; CHECK: [[R1:%[0-9]+]]:_(s1) = COPY [[ENTRY_R1]](s1)
+; CHECK: [[R2:%[0-9]+]]:_(s1) = COPY [[ENTRY_R2]](s1)
 ; CHECK: G_ADD [[R1]], [[R2]]
 define i1 @trivial_float_comparison(double %a, double %b) {
   %r1 = fcmp false double %a, %b
@@ -1123,7 +1123,7 @@ define i1 @trivial_float_comparison(double %a, double %b) {
 
 define i32* @test_global() {
 ; CHECK-LABEL: name: test_global
-; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @var{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p0)
 
   ret i32* @var
@@ -1132,7 +1132,7 @@ define i32* @test_global() {
 @var1 = addrspace(42) global i32 0
 define i32 addrspace(42)* @test_global_addrspace() {
 ; CHECK-LABEL: name: test_global
-; CHECK: [[TMP:%[0-9]+]](p42) = G_GLOBAL_VALUE @var1{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p42) = G_GLOBAL_VALUE @var1{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p42)
 
   ret i32 addrspace(42)* @var1
@@ -1141,7 +1141,7 @@ define i32 addrspace(42)* @test_global_addrspace() {
 
 define void()* @test_global_func() {
 ; CHECK-LABEL: name: test_global_func
-; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @allocai64{{$}}
+; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @allocai64{{$}}
 ; CHECK: %x0 = COPY [[TMP]](p0)
 
   ret void()* @allocai64
@@ -1150,9 +1150,9 @@ define void()* @test_global_func() {
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
 define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
 ; CHECK-LABEL: name: test_memcpy
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
 ; CHECK: %x1 = COPY [[SRC]]
 ; CHECK: %x2 = COPY [[SIZE]]
@@ -1164,9 +1164,9 @@ define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
 declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile)
 define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
 ; CHECK-LABEL: name: test_memmove
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
 ; CHECK: %x1 = COPY [[SRC]]
 ; CHECK: %x2 = COPY [[SIZE]]
@@ -1178,12 +1178,12 @@ define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
 declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i32 %align, i1 %volatile)
 define void @test_memset(i8* %dst, i8 %val, i64 %size) {
 ; CHECK-LABEL: name: test_memset
-; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[SRC_C:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[SRC:%[0-9]+]](s8) = G_TRUNC [[SRC_C]]
-; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2
+; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
 ; CHECK: %x0 = COPY [[DST]]
-; CHECK: [[SRC_TMP:%[0-9]+]](s32) = G_ANYEXT [[SRC]]
+; CHECK: [[SRC_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[SRC]]
 ; CHECK: %w1 = COPY [[SRC_TMP]]
 ; CHECK: %x2 = COPY [[SIZE]]
 ; CHECK: BL $memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2
@@ -1195,12 +1195,12 @@ declare i64 @llvm.objectsize.i64(i8*, i1)
 declare i32 @llvm.objectsize.i32(i8*, i1)
 define void @test_objectsize(i8* %addr0, i8* %addr1) {
 ; CHECK-LABEL: name: test_objectsize
-; CHECK: [[ADDR0:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[ADDR1:%[0-9]+]](p0) = COPY %x1
-; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 -1
-; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 0
-; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 -1
-; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 0
+; CHECK: [[ADDR0:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 -1
+; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 0
+; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 -1
+; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 0
   %size64.0 = call i64 @llvm.objectsize.i64(i8* %addr0, i1 0)
   %size64.intmin = call i64 @llvm.objectsize.i64(i8* %addr0, i1 1)
   %size32.0 = call i32 @llvm.objectsize.i32(i8* %addr0, i1 0)
@@ -1210,8 +1210,8 @@ define void @test_objectsize(i8* %addr0, i8* %addr1) {
 
 define void @test_large_const(i128* %addr) {
 ; CHECK-LABEL: name: test_large_const
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s128) = G_CONSTANT i128 42
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
 ; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
   store i128 42, i128* %addr
   ret void
@@ -1224,8 +1224,8 @@ define void @test_large_const(i128* %addr) {
 define i8* @test_const_placement() {
 ; CHECK-LABEL: name: test_const_placement
 ; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
-; CHECK:   [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK:   [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32)
+; CHECK:   [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK:   [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
 ; CHECK: {{bb.[0-9]+}}.next:
   br label %next
 
@@ -1245,7 +1245,7 @@ define void @test_va_end(i8* %list) {
 
 define void @test_va_arg(i8* %list) {
 ; CHECK-LABEL: test_va_arg
-; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK: G_VAARG [[LIST]](p0), 8
 ; CHECK: G_VAARG [[LIST]](p0), 1
 ; CHECK: G_VAARG [[LIST]](p0), 16
@@ -1259,9 +1259,9 @@ define void @test_va_arg(i8* %list) {
 declare float @llvm.pow.f32(float, float)
 define float @test_pow_intrin(float %l, float %r) {
 ; CHECK-LABEL: name: test_pow_intrin
-; CHECK: [[LHS:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RHS:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[RES:%[0-9]+]](s32) = G_FPOW [[LHS]], [[RHS]]
+; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPOW [[LHS]], [[RHS]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.pow.f32(float %l, float %r)
   ret float %res
@@ -1270,10 +1270,10 @@ define float @test_pow_intrin(float %l, float %r) {
 declare float @llvm.fma.f32(float, float, float)
 define float @test_fma_intrin(float %a, float %b, float %c) {
 ; CHECK-LABEL: name: test_fma_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[B:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[C:%[0-9]+]](s32) = COPY %s2
-; CHECK: [[RES:%[0-9]+]](s32) = G_FMA [[A]], [[B]], [[C]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[B:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[C:%[0-9]+]]:_(s32) = COPY %s2
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FMA [[A]], [[B]], [[C]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %res
@@ -1282,8 +1282,8 @@ define float @test_fma_intrin(float %a, float %b, float %c) {
 declare float @llvm.exp.f32(float)
 define float @test_exp_intrin(float %a) {
 ; CHECK-LABEL: name: test_exp_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.exp.f32(float %a)
   ret float %res
@@ -1292,8 +1292,8 @@ define float @test_exp_intrin(float %a) {
 declare float @llvm.exp2.f32(float)
 define float @test_exp2_intrin(float %a) {
 ; CHECK-LABEL: name: test_exp2_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FEXP2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP2 [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.exp2.f32(float %a)
   ret float %res
@@ -1302,8 +1302,8 @@ define float @test_exp2_intrin(float %a) {
 declare float @llvm.log.f32(float)
 define float @test_log_intrin(float %a) {
 ; CHECK-LABEL: name: test_log_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.log.f32(float %a)
   ret float %res
@@ -1312,8 +1312,8 @@ define float @test_log_intrin(float %a) {
 declare float @llvm.log2.f32(float)
 define float @test_log2_intrin(float %a) {
 ; CHECK-LABEL: name: test_log2_intrin
-; CHECK: [[A:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FLOG2 [[A]]
+; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
 ; CHECK: %s0 = COPY [[RES]]
   %res = call float @llvm.log2.f32(float %a)
   ret float %res
@@ -1331,12 +1331,12 @@ define void @test_lifetime_intrin() {
 
 define void @test_load_store_atomics(i8* %addr) {
 ; CHECK-LABEL: name: test_load_store_atomics
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[V0:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
 ; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr)
-; CHECK: [[V1:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
+; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
 ; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr)
-; CHECK: [[V2:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
+; CHECK: [[V2:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load syncscope("singlethread") seq_cst 1 from %ir.addr)
 ; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store syncscope("singlethread") monotonic 1 into %ir.addr)
   %v0 = load atomic i8, i8* %addr unordered, align 1
   store atomic i8 %v0, i8* %addr monotonic, align 1
@@ -1352,8 +1352,8 @@ define void @test_load_store_atomics(i8* %addr) {
 
 define float @test_fneg_f32(float %x) {
 ; CHECK-LABEL: name: test_fneg_f32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[RES:%[0-9]+]](s32) = G_FNEG [[ARG]]
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
 ; CHECK: %s0 = COPY [[RES]](s32)
   %neg = fsub float -0.000000e+00, %x
   ret float %neg
@@ -1361,8 +1361,8 @@ define float @test_fneg_f32(float %x) {
 
 define double @test_fneg_f64(double %x) {
 ; CHECK-LABEL: name: test_fneg_f64
-; CHECK: [[ARG:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[RES:%[0-9]+]](s64) = G_FNEG [[ARG]]
+; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
 ; CHECK: %d0 = COPY [[RES]](s64)
   %neg = fsub double -0.000000e+00, %x
   ret double %neg
@@ -1379,10 +1379,10 @@ define void @test_trivial_inlineasm() {
 
 define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
 ; CHECK-LABEL: name: test_insertelement
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[RES:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
 ; CHECK: %d0 = COPY [[RES]](<2 x s32>)
   %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
   ret <2 x i32> %res
@@ -1390,9 +1390,9 @@ define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
 
 define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
 ; CHECK-LABEL: name: test_extractelement
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
 ; CHECK: %w0 = COPY [[RES]](s32)
   %res = extractelement <2 x i32> %vec, i32 %idx
   ret i32 %res
@@ -1400,7 +1400,7 @@ define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
 
 define i32 @test_singleelementvector(i32 %elt){
 ; CHECK-LABEL: name: test_singleelementvector
-; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0
+; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
 ; CHECK-NOT: G_INSERT_VECTOR_ELT
 ; CHECK-NOT: G_EXTRACT_VECTOR_ELT
 ; CHECK: %w0 = COPY [[ELT]](s32)
@@ -1411,24 +1411,24 @@ define i32 @test_singleelementvector(i32 %elt){
 
 define <2 x i32> @test_constantaggzerovector_v2i32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v2i32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x i32> zeroinitializer
 }
 
 define <2 x float> @test_constantaggzerovector_v2f32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v2f32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float 0.000000e+00
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x float> zeroinitializer
 }
 
 define i32 @test_constantaggzerovector_v3i32() {
 ; CHECK-LABEL: name: test_constantaggzerovector_v3i32
-; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
+; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %elt = extractelement <3 x i32> zeroinitializer, i32 1
   ret i32 %elt
@@ -1436,19 +1436,19 @@ define i32 @test_constantaggzerovector_v3i32() {
 
 define <2 x i32> @test_constantdatavector_v2i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v2i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   ret <2 x i32> <i32 1, i32 2>
 }
 
 define i32 @test_constantdatavector_v3i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v3i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 1
   ret i32 %elt
@@ -1456,28 +1456,28 @@ define i32 @test_constantdatavector_v3i32() {
 
 define <4 x i32> @test_constantdatavector_v4i32() {
 ; CHECK-LABEL: name: test_constantdatavector_v4i32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
   ret <4 x i32> <i32 1, i32 2, i32 3, i32 4>
 }
 
 define <2 x double> @test_constantdatavector_v2f64() {
 ; CHECK-LABEL: name: test_constantdatavector_v2f64
-; CHECK: [[FC1:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00
-; CHECK: [[FC2:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
-; CHECK: [[VEC:%[0-9]+]](<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
+; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
 ; CHECK: %q0 = COPY [[VEC]](<2 x s64>)
   ret <2 x double> <double 1.0, double 2.0>
 }
 
 define i32 @test_constantaggzerovector_v1s32(i32 %arg){
 ; CHECK-LABEL: name: test_constantaggzerovector_v1s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
 ; CHECK-NOT: G_MERGE_VALUES
 ; CHECK: G_ADD [[ARG]], [[C0]]
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1488,8 +1488,8 @@ define i32 @test_constantaggzerovector_v1s32(i32 %arg){
 
 define i32 @test_constantdatavector_v1s32(i32 %arg){
 ; CHECK-LABEL: name: test_constantdatavector_v1s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
 ; CHECK-NOT: G_MERGE_VALUES
 ; CHECK: G_ADD [[ARG]], [[C1]]
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
@@ -1501,7 +1501,7 @@ define i32 @test_constantdatavector_v1s32(i32 %arg){
 declare ghccc float @different_call_conv_target(float %x)
 define float @test_different_call_conv_target(float %x) {
 ; CHECK-LABEL: name: test_different_call_conv
-; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
+; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
 ; CHECK: %s8 = COPY [[X]]
 ; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s8, implicit-def %s0
   %res = call ghccc float @different_call_conv_target(float %x)
@@ -1510,11 +1510,11 @@ define float @test_different_call_conv_target(float %x) {
 
 define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
   %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
@@ -1523,10 +1523,10 @@ define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
 
 define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
 ; CHECK: %w0 = COPY [[RES]](s32)
   %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
   %res = extractelement <1 x i32> %vec, i32 0
@@ -1535,12 +1535,12 @@ define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
 
 define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
   ret <2 x i32> %res
@@ -1548,12 +1548,12 @@ define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
 
 define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
   %res = extractelement <3 x i32> %vec, i32 0
@@ -1562,14 +1562,14 @@ define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
 
 define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0
-; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY %d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY %d1
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
   %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %res
@@ -1577,12 +1577,12 @@ define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg
 
 define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
 ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY %q0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
   %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
   ret <2 x i32> %res
@@ -1591,35 +1591,35 @@ define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
 
 define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
-; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0
-; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1
-; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11
-; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12
-; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5
-; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13
-; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6
-; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14
-; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
-; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
-; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
-; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY %d0
+; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY %d1
+; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
+; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
+; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+; CHECK: [[MASK:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
 ; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
   %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: test_constant_vector
-; CHECK: [[UNDEF:%[0-9]+]](s16) = G_IMPLICIT_DEF
-; CHECK: [[F:%[0-9]+]](s16) = G_FCONSTANT half 0xH3C00
-; CHECK: [[M:%[0-9]+]](<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
+; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
 ; CHECK: %d0 = COPY [[M]](<4 x s16>)
 define <4 x half> @test_constant_vector() {
   ret <4 x half> <half undef, half undef, half undef, half 0xH3C00>
@@ -1627,8 +1627,8 @@ define <4 x half> @test_constant_vector() {
 
 define i32 @test_target_mem_intrinsic(i32* %addr) {
 ; CHECK-LABEL: name: test_target_mem_intrinsic
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
 ; CHECK: G_TRUNC [[VAL]](s64)
   %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
   %trunc = trunc i64 %val to i32
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index 03861b19a77..4042047dfc2 100644
--- a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -99,17 +99,14 @@
 # Based on the type i32, this should be gpr.
 name:            defaultMapping
 legalized:       true
-# CHECK-LABEL: name: defaultMapping
-# CHECK:      registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0
-    ; CHECK:      %1(s32) = G_ADD %0
+    ; CHECK-LABEL: name: defaultMapping
+    ; CHECK:      %1:gpr(s32) = G_ADD %0
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
@@ -120,18 +117,15 @@ body: |
 # FPR is used for both floating point and vector registers.
 name:            defaultMappingVector
 legalized:       true
-# CHECK-LABEL: name: defaultMappingVector
-# CHECK:      registers:
-# CHECK:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %d0
-    ; CHECK:      %0(<2 x s32>) = COPY %d0
-    ; CHECK:      %1(<2 x s32>) = G_ADD %0
+    ; CHECK-LABEL: name: defaultMappingVector
+    ; CHECK:      %0:fpr(<2 x s32>) = COPY %d0
+    ; CHECK:      %1:fpr(<2 x s32>) = G_ADD %0
     %0(<2 x s32>) = COPY %d0
     %1(<2 x s32>) = G_ADD %0, %0
 ...
@@ -142,12 +136,6 @@ body: |
 # in FPR, but at the use, it should be GPR.
 name:            defaultMapping1Repair
 legalized:       true
-# CHECK-LABEL: name: defaultMapping1Repair
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -155,10 +143,11 @@ registers:
 body: |
   bb.0.entry:
     liveins: %s0, %x0
-    ; CHECK:           %0(s32) = COPY %s0
-    ; CHECK-NEXT:      %1(s32) = COPY %w0
-    ; CHECK-NEXT:      %3(s32) = COPY %0
-    ; CHECK-NEXT:      %2(s32) = G_ADD %3, %1
+    ; CHECK-LABEL: name: defaultMapping1Repair
+    ; CHECK:           %0:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %1:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %3, %1
     %0(s32) = COPY %s0
     %1(s32) = COPY %w0
     %2(s32) = G_ADD %0, %1
@@ -167,22 +156,17 @@ body: |
 # Check that we repair the assignment for %0 differently for both uses.
 name:            defaultMapping2Repairs
 legalized:       true
-# CHECK-LABEL: name: defaultMapping2Repairs
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
-    ; CHECK:           %0(s32) = COPY %s0
-    ; CHECK-NEXT:      %2(s32) = COPY %0
-    ; CHECK-NEXT:      %3(s32) = COPY %0
-    ; CHECK-NEXT:      %1(s32) = G_ADD %2, %3
+    ; CHECK-LABEL: name: defaultMapping2Repairs
+    ; CHECK:           %0:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %2:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %0
+    ; CHECK-NEXT:      %1:gpr(s32) = G_ADD %2, %3
     %0(s32) = COPY %s0
     %1(s32) = G_ADD %0, %0
 ...
@@ -194,20 +178,16 @@ body: |
 # fixes that.
 name:            defaultMappingDefRepair
 legalized:       true
-# CHECK-LABEL: name: defaultMappingDefRepair
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: fpr }
 body: |
   bb.0.entry:
     liveins: %w0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %2(s32) = G_ADD %0, %0
-    ; CHECK-NEXT:      %1(s32) = COPY %2
+    ; CHECK-LABEL: name: defaultMappingDefRepair
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %0, %0
+    ; CHECK-NEXT:      %1:fpr(s32) = COPY %2
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
@@ -255,12 +235,6 @@ body: |
 # Make sure we can repair physical register uses as well.
 name:            defaultMappingUseRepairPhysReg
 legalized:       true
-# CHECK-LABEL: name: defaultMappingUseRepairPhysReg
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -268,10 +242,11 @@ registers:
 body: |
   bb.0.entry:
     liveins: %w0, %s0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %1(s32) = COPY %s0
-    ; CHECK-NEXT:      %3(s32) = COPY %1
-    ; CHECK-NEXT:      %2(s32) = G_ADD %0, %3
+    ; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %1:fpr(s32) = COPY %s0
+    ; CHECK-NEXT:      %3:gpr(s32) = COPY %1
+    ; CHECK-NEXT:      %2:gpr(s32) = G_ADD %0, %3
     %0(s32) = COPY %w0
     %1(s32) = COPY %s0
     %2(s32) = G_ADD %0, %1
@@ -281,18 +256,15 @@ body: |
 # Make sure we can repair physical register defs.
 name:            defaultMappingDefRepairPhysReg
 legalized:       true
-# CHECK-LABEL: name: defaultMappingDefRepairPhysReg
-# CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0
-    ; CHECK:           %0(s32) = COPY %w0
-    ; CHECK-NEXT:      %1(s32) = G_ADD %0, %0
+    ; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
+    ; CHECK:           %0:gpr(s32) = COPY %w0
+    ; CHECK-NEXT:      %1:gpr(s32) = G_ADD %0, %0
     ; CHECK-NEXT:      %s0 = COPY %1
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
@@ -304,21 +276,6 @@ body: |
 # G_OR instruction from fpr to gpr.
 name:            greedyMappingOr
 legalized:       true
-# CHECK-LABEL: name: greedyMappingOr
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-
-# Fast mode maps vector instruction on FPR.
-# FAST-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-# Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
-
-# Greedy mode coalesce the computation on the GPR register
-# because it is the cheapest.
-# GREEDY-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -326,20 +283,19 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1
-    ; CHECK: %0(<2 x s32>) = COPY %x0
-    ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
-
+    ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
+    ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
-    ; FAST-NEXT: %3(<2 x s32>) = COPY %0
-    ; FAST-NEXT: %4(<2 x s32>) = COPY %1
+    ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
+    ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
+    ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %2(<2 x s32>) = G_OR %0, %1
+    ; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
     %0(<2 x s32>) = COPY %x0
     %1(<2 x s32>) = COPY %x1
     %2(<2 x s32>) = G_OR %0, %1
@@ -351,21 +307,6 @@ body: |
 # %2 constraint.
 name:            greedyMappingOrWithConstraints
 legalized:       true
-# CHECK-LABEL: name: greedyMappingOrWithConstraints
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: fpr, preferred-register: '' }
-
-# Fast mode maps vector instruction on FPR.
-# Fast mode needs two extra copies.
-# FAST-NEXT:  - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 4, class: fpr, preferred-register: '' }
-
-# Greedy mode coalesce the computation on the GPR register because it
-# is the cheapest, but will need one extra copy to materialize %2 into a FPR.
-# GREEDY-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -373,22 +314,23 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1
-    ; CHECK: %0(<2 x s32>) = COPY %x0
-    ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1
+    ; CHECK-LABEL: name: greedyMappingOrWithConstraints
 
+    ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
+    ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
-    ; FAST-NEXT: %3(<2 x s32>) = COPY %0
-    ; FAST-NEXT: %4(<2 x s32>) = COPY %1
+    ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
+    ; FAST-NEXT: %4:fpr(<2 x s32>) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4
+    ; FAST-NEXT: %2:fpr(<2 x s32>) = G_OR %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %3(<2 x s32>) = G_OR %0, %1
+    ; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
     ; We need to keep %2 into FPR because we do not know anything about it.
-    ; GREEDY-NEXT: %2(<2 x s32>) = COPY %3
+    ; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
     %0(<2 x s32>) = COPY %x0
     %1(<2 x s32>) = COPY %x1
     %2(<2 x s32>) = G_OR %0, %1
@@ -408,8 +350,8 @@ body: |
   bb.0:
     liveins: %x0
 
-    ; CHECK: %0 = COPY %x0
-    ; CHECK-NEXT: %1 = ADDXrr %0, %0
+    ; CHECK: %0:gpr64 = COPY %x0
+    ; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
     ; CHECK-NEXT: %x0 = COPY %1
     ; CHECK-NEXT: RET_ReallyLR implicit %x0
 
@@ -444,8 +386,8 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(s32) = COPY %w0
-# CHECK:    %1(s32) = G_BITCAST %0
+# CHECK:    %0:gpr(s32) = COPY %w0
+# CHECK:    %1:gpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
@@ -467,8 +409,8 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(<2 x s16>) = COPY %s0
-# CHECK:    %1(<2 x s16>) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s16>) = COPY %s0
+# CHECK:    %1:fpr(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
@@ -491,8 +433,9 @@ registers:
   - { id: 1, class: _ }
 
 # CHECK:  body:
-# CHECK:    %0(s32) = COPY %w0
-# CHECK:    %1(<2 x s16>) = G_BITCAST %0
+# CHECK:    %0:gpr(s32) = COPY %w0
+# FAST:     %1:fpr(<2 x s16>) = G_BITCAST %0
+# GREEDY:   %1:gpr(<2 x s16>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %w0
@@ -505,18 +448,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s32_fpr_gpr
 name:            bitcast_s32_fpr_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s16>) = COPY %s0
-# CHECK:    %1(s32) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s16>) = COPY %s0
+# FAST:     %1:gpr(s32) = G_BITCAST %0
+# GREEDY:   %1:fpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %s0
@@ -529,17 +467,12 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_gpr
 name:            bitcast_s64_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(s64) = COPY %x0
-# CHECK:    %1(s64) = G_BITCAST %0
+# CHECK:    %0:gpr(s64) = COPY %x0
+# CHECK:    %1:gpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
@@ -552,17 +485,12 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_fpr
 name:            bitcast_s64_fpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s32>) = COPY %d0
-# CHECK:    %1(<2 x s32>) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s32>) = COPY %d0
+# CHECK:    %1:fpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
@@ -575,17 +503,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_gpr_fpr
 name:            bitcast_s64_gpr_fpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 # CHECK:  body:
-# CHECK:    %0(s64) = COPY %x0
-# CHECK:    %1(<2 x s32>) = G_BITCAST %0
+# CHECK:    %0:gpr(s64) = COPY %x0
+# FAST:     %1:fpr(<2 x s32>) = G_BITCAST %0
+# GREEDY:   %1:gpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %x0
@@ -598,18 +522,13 @@ body:             |
 # CHECK-LABEL: name: bitcast_s64_fpr_gpr
 name:            bitcast_s64_fpr_gpr
 legalized:       true
-
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# FAST-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# GREEDY-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-
 # CHECK:  body:
-# CHECK:    %0(<2 x s32>) = COPY %d0
-# CHECK:    %1(s64) = G_BITCAST %0
+# CHECK:    %0:fpr(<2 x s32>) = COPY %d0
+# FAST:     %1:gpr(s64) = G_BITCAST %0
+# GREEDY:   %1:fpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: %d0
@@ -628,10 +547,8 @@ registers:
   - { id: 1, class: _}
   - { id: 2, class: _}
   - { id: 3, class: _}
-# CHECK: registers:
-# CHECK:  - { id: 2, class: fpr, preferred-register: '' }
-# CHECK:  - { id: 3, class: fpr, preferred-register: '' }
-# CHECK: %2(<2 x s64>) = G_BITCAST %3(s128)
+# CHECK: %3:fpr(s128) = G_MERGE_VALUES
+# CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
 body:             |
   bb.1:
     liveins: %x0, %x1
@@ -658,12 +575,9 @@ registers:
   - { id: 2, class: _}
   - { id: 3, class: _}
   - { id: 4, class: _}
-# CHECK: registers:
-# CHECK:  - { id: 2, class: fpr, preferred-register: '' }
-# CHECK:  - { id: 3, class: fpr, preferred-register: '' }
-# CHECK:  - { id: 4, class: fpr, preferred-register: '' }
-# CHECK: %4(s128) = COPY %3(s128)
-# CHECK-NEXT: %2(<2 x s64>) = G_BITCAST %4(s128)
+# CHECK: %3:fpr(s128) = G_MERGE_VALUES
+# CHECK: %4:fpr(s128) = COPY %3(s128)
+# CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
 body:             |
   bb.1:
     liveins: %x0, %x1
@@ -695,7 +609,7 @@ registers:
 # CHECK: registers:
 # CHECK:  - { id: 0, class: fpr128, preferred-register: '' }
 # CHECK:  - { id: 1, class: fpr, preferred-register: '' }
-# CHECK: %1(s128) = COPY %0
+# CHECK: %1:fpr(s128) = COPY %0
 body:             |
   bb.1:
     liveins: %x0
@@ -714,17 +628,6 @@ body:             |
 # CHECK-LABEL: name: greedyWithChainOfComputation
 name:            greedyWithChainOfComputation
 legalized:       true
-
-# CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 2, class: fpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 3, class: fpr, preferred-register: '' }
-# FAST-NEXT:   - { id: 4, class: fpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 2, class: gpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 3, class: gpr, preferred-register: '' }
-# GREEDY-NEXT: - { id: 4, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 5, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
@@ -732,17 +635,18 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
-
 # No repairing should be necessary for both modes.
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
-# CHECK-NEXT:    %2(<2 x s32>) = G_BITCAST %0(s64)
-# CHECK-NEXT:    %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
-# CHECK-NEXT:    %4(<2 x s32>) = G_OR %2, %3
-# CHECK-NEXT:    %5(s64) = G_BITCAST %4(<2 x s32>)
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
+# FAST-NEXT:     %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
+# FAST-NEXT:     %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# FAST-NEXT:     %4:fpr(<2 x s32>) = G_OR %2, %3
+# GREEDY-NEXT:   %2:gpr(<2 x s32>) = G_BITCAST %0(s64)
+# GREEDY-NEXT:   %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# GREEDY-NEXT:   %4:gpr(<2 x s32>) = G_OR %2, %3
+# CHECK-NEXT:    %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
 # CHECK-NEXT:    %x0 = COPY %5(s64)
 # CHECK-NEXT:    RET_ReallyLR implicit %x0
-
 body:             |
   bb.0:
     liveins: %x0, %x1
@@ -778,12 +682,12 @@ registers:
   - { id: 3, class: _ }
 
 # No repairing should be necessary for both modes.
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
-# CHECK-NEXT:    %2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
+# CHECK-NEXT:    %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
 # %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT:    %4(s64) = COPY %0
-# CHECK-NEXT:    %3(s64) = G_FADD %4, %2
+# CHECK-NEXT:    %4:fpr(s64) = COPY %0
+# CHECK-NEXT:    %3:fpr(s64) = G_FADD %4, %2
 # CHECK-NEXT:    %x0 = COPY %3(s64)
 # CHECK-NEXT:    RET_ReallyLR implicit %x0
 
@@ -818,12 +722,12 @@ registers:
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 
-# CHECK:         %0(s64) = COPY %x0
-# CHECK-NEXT:    %1(p0) = COPY %x1
+# CHECK:         %0:gpr(s64) = COPY %x0
+# CHECK-NEXT:    %1:gpr(p0) = COPY %x1
 # %0 has been mapped to GPR, we need to repair to match FPR.
-# CHECK-NEXT:    %3(s64) = COPY %0
-# CHECK-NEXT:    %4(s64) = COPY %0
-# CHECK-NEXT:    %2(s64) = G_FADD %3, %4
+# CHECK-NEXT:    %3:fpr(s64) = COPY %0
+# CHECK-NEXT:    %4:fpr(s64) = COPY %0
+# CHECK-NEXT:    %2:fpr(s64) = G_FADD %3, %4
 # CHECK-NEXT:    G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
 # CHECK-NEXT:    RET_ReallyLR
 
diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
index cdcdb964462..4b6fab704da 100644
--- a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
+++ b/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
@@ -5,12 +5,12 @@
 ; CHECK: fixedStack:
 ; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
 ; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
-; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
-; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]](s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
-; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[LHS]], [[RHS]]
-; CHECK: [[SUM32:%[0-9]+]](s32) = G_SEXT [[SUM]](s8)
+; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
+; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
+; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
+; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
 ; CHECK: %w0 = COPY [[SUM32]](s32)
 define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
   %sum = add i8 %lhs, %rhs
@@ -18,15 +18,15 @@ define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs)
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42
-; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
+; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
+; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
 ; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 1
-; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0)
 ; CHECK: BL @test_stack_slots
 define void @test_call_stack() {
@@ -46,27 +46,27 @@ define void @test_128bit_struct([2 x i64]* %ptr) {
 }
 
 ; CHECK-LABEL: name: take_128bit_struct
-; CHECK: {{%.*}}(p0) = COPY %x0
-; CHECK: {{%.*}}(s64) = COPY %x1
-; CHECK: {{%.*}}(s64) = COPY %x2
+; CHECK: {{%.*}}:_(p0) = COPY %x0
+; CHECK: {{%.*}}:_(s64) = COPY %x1
+; CHECK: {{%.*}}:_(s64) = COPY %x2
 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
   store [2 x i64] %in, [2 x i64]* %ptr
   ret void
 }
 
 ; CHECK-LABEL: name: test_split_struct
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD {{.*}}(p0)
-; CHECK: [[LO:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 0
-; CHECK: [[HI:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 64
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
 define void @test_split_struct([2 x i64]* %ptr) {
   %struct = load [2 x i64], [2 x i64]* %ptr
@@ -81,11 +81,11 @@ define void @test_split_struct([2 x i64]* %ptr) {
 ; CHECK-DAG:   - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
 ; CHECK-DAG:   - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
 
-; CHECK: [[LOPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
+; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
 
-; CHECK: [[HIPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
+; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
 define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
                                i64, i64, i64,
                                [2 x i64] %in) {
diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index 16856931b25..23a39a336fa 100644
--- a/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -12,7 +12,7 @@ define void @test_trivial_call() {
 
 ; CHECK-LABEL: name: test_simple_return
 ; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0
-; CHECK: [[RES:%[0-9]+]](s64) = COPY %x0
+; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY %x0
 ; CHECK: %x0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit %x0
 declare i64 @simple_return_callee()
@@ -22,7 +22,7 @@ define i64 @test_simple_return() {
 }
 
 ; CHECK-LABEL: name: test_simple_arg
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
 ; CHECK: %w0 = COPY [[IN]]
 ; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
 ; CHECK: RET_ReallyLR
@@ -36,7 +36,7 @@ define void @test_simple_arg(i32 %in) {
 ; CHECK: registers:
 ; Make sure the register feeding the indirect call is properly constrained.
 ; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
-; CHECK: %[[FUNC]](p0) = COPY %x0
+; CHECK: %[[FUNC]]:gpr64(p0) = COPY %x0
 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: RET_ReallyLR
 define void @test_indirect_call(void()* %func) {
@@ -45,8 +45,8 @@ define void @test_indirect_call(void()* %func) {
 }
 
 ; CHECK-LABEL: name: test_multiple_args
-; CHECK: [[IN:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
+; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
 ; CHECK: %w0 = COPY [[ANSWER]]
 ; CHECK: %x1 = COPY [[IN]]
 ; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1
@@ -59,17 +59,17 @@ define void @test_multiple_args(i64 %in) {
 
 
 ; CHECK-LABEL: name: test_struct_formal
-; CHECK: [[DBL:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[I64:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[I8_C:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[I8:%[0-9]+]](s8) = G_TRUNC [[I8_C]]
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2
+; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
 
-; CHECK: [[UNDEF:%[0-9]+]](s192) = G_IMPLICIT_DEF
-; CHECK: [[ARG0:%[0-9]+]](s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
-; CHECK: [[ARG1:%[0-9]+]](s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
-; CHECK: [[ARG2:%[0-9]+]](s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
-; CHECK: [[ARG:%[0-9]+]](s192) = COPY [[ARG2]]
+; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
+; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
+; CHECK: [[ARG1:%[0-9]+]]:_(s192) = G_INSERT [[ARG0]], [[I64]](s64), 64
+; CHECK: [[ARG2:%[0-9]+]]:_(s192) = G_INSERT [[ARG1]], [[I8]](s8), 128
+; CHECK: [[ARG:%[0-9]+]]:_(s192) = COPY [[ARG2]]
 
 ; CHECK: G_STORE [[ARG]](s192), [[ADDR]](p0)
 ; CHECK: RET_ReallyLR
@@ -80,12 +80,12 @@ define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr)
 
 
 ; CHECK-LABEL: name: test_struct_return
-; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[VAL:%[0-9]+]](s192) = G_LOAD [[ADDR]](p0)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_LOAD [[ADDR]](p0)
 
-; CHECK: [[DBL:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 0
-; CHECK: [[I64:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 64
-; CHECK: [[I32:%[0-9]+]](s32) = G_EXTRACT [[VAL]](s192), 128
+; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
+; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
+; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
 
 ; CHECK: %d0 = COPY [[DBL]](s64)
 ; CHECK: %x0 = COPY [[I64]](s64)
@@ -98,23 +98,23 @@ define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
 
 ; CHECK-LABEL: name: test_arr_call
 ; CHECK: hasCalls: true
-; CHECK: [[ARG:%[0-9]+]](s256) = G_LOAD
+; CHECK: [[ARG:%[0-9]+]]:_(s256) = G_LOAD
 
-; CHECK: [[E0:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 0
-; CHECK: [[E1:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 64
-; CHECK: [[E2:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 128
-; CHECK: [[E3:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 192
+; CHECK: [[E0:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 0
+; CHECK: [[E1:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 64
+; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
+; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
 
 ; CHECK: %x0 = COPY [[E0]](s64)
 ; CHECK: %x1 = COPY [[E1]](s64)
 ; CHECK: %x2 = COPY [[E2]](s64)
 ; CHECK: %x3 = COPY [[E3]](s64)
 ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3
-; CHECK: [[E0:%[0-9]+]](s64) = COPY %x0
-; CHECK: [[E1:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[E2:%[0-9]+]](s64) = COPY %x2
-; CHECK: [[E3:%[0-9]+]](s64) = COPY %x3
-; CHECK: [[RES:%[0-9]+]](s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
+; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY %x0
+; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY %x2
+; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY %x3
+; CHECK: [[RES:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
 ; CHECK: G_EXTRACT [[RES]](s256), 64
 declare [4 x i64] @arr_callee([4 x i64])
 define i64 @test_arr_call([4 x i64]* %addr) {
@@ -126,14 +126,14 @@ define i64 @test_arr_call([4 x i64]* %addr) {
 
 
 ; CHECK-LABEL: name: test_abi_exts_call
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: [[VAL_TMP:%[0-9]+]](s32) = G_ANYEXT [[VAL]]
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
 ; CHECK: %w0 = COPY [[VAL_TMP]]
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
-; CHECK: [[ZVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
+; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[ZVAL]](s32)
 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
 declare void @take_char(i8)
@@ -146,8 +146,8 @@ define void @test_abi_exts_call(i8* %addr) {
 }
 
 ; CHECK-LABEL: name: test_abi_sext_ret
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8)
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: RET_ReallyLR implicit %w0
 define signext i8 @test_abi_sext_ret(i8* %addr) {
@@ -156,8 +156,8 @@ define signext i8 @test_abi_sext_ret(i8* %addr) {
 }
 
 ; CHECK-LABEL: name: test_abi_zext_ret
-; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD
-; CHECK: [[SVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8)
+; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
+; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
 ; CHECK: %w0 = COPY [[SVAL]](s32)
 ; CHECK: RET_ReallyLR implicit %w0
 define zeroext i8 @test_abi_zext_ret(i8* %addr) {
@@ -170,13 +170,13 @@ define zeroext i8 @test_abi_zext_ret(i8* %addr) {
 ; CHECK-DAG:  - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8,
 ; CHECK-DAG:  - { id: [[STACK8:[0-9]+]], type: default, offset: 8, size: 8,
 ; CHECK-DAG:  - { id: [[STACK16:[0-9]+]], type: default, offset: 16, size: 8,
-; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
-; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; CHECK: [[RHS:%[0-9]+]](s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
-; CHECK: [[ADDR_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
-; CHECK: [[SUM:%[0-9]+]](s64) = G_ADD [[LHS]], [[RHS]]
+; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; CHECK: [[LHS:%[0-9]+]]:_(s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
+; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
+; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0)
+; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
 ; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
 define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
   %sum = add i64 %lhs, %rhs
@@ -185,21 +185,21 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
 }
 
 ; CHECK-LABEL: name: test_call_stack
-; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
-; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
-; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
+; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
+; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
 ; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[PTR_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 16
-; CHECK: [[PTR_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
+; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
 ; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0)
 ; CHECK: BL @test_stack_slots
 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
@@ -212,8 +212,8 @@ define void @test_call_stack() {
 ; CHECK: fixedStack:
 ; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
 ; CHECK-NEXT: isImmutable: true,
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
-; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]]
+; CHECK: {{%[0-9]+}}:_(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0)
 define void @test_mem_i1([8 x i64], i1 %in) {
   ret void
 }
@@ -230,27 +230,27 @@ define void @test_128bit_struct([2 x i64]* %ptr) {
 }
 
 ; CHECK-LABEL: name: take_128bit_struct
-; CHECK: {{%.*}}(p0) = COPY %x0
-; CHECK: {{%.*}}(s64) = COPY %x1
-; CHECK: {{%.*}}(s64) = COPY %x2
+; CHECK: {{%.*}}:_(p0) = COPY %x0
+; CHECK: {{%.*}}:_(s64) = COPY %x1
+; CHECK: {{%.*}}:_(s64) = COPY %x2
 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
   store [2 x i64] %in, [2 x i64]* %ptr
   ret void
 }
 
 ; CHECK-LABEL: name: test_split_struct
-; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD {{.*}}(p0)
-; CHECK: [[LO:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 0
-; CHECK: [[HI:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 64
+; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD {{.*}}(p0)
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF]]
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
 define void @test_split_struct([2 x i64]* %ptr) {
   %struct = load [2 x i64], [2 x i64]* %ptr
@@ -265,11 +265,11 @@ define void @test_split_struct([2 x i64]* %ptr) {
 ; CHECK-DAG:   - { id: [[LO_FRAME:[0-9]+]], type: default, offset: 0, size: 8
 ; CHECK-DAG:   - { id: [[HI_FRAME:[0-9]+]], type: default, offset: 8, size: 8
 
-; CHECK: [[LOPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
-; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
+; CHECK: [[LOPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LO_FRAME]]
+; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD [[LOPTR]](p0) :: (invariant load 8 from %fixed-stack.[[LO_FRAME]], align 0)
 
-; CHECK: [[HIPTR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
-; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
+; CHECK: [[HIPTR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[HI_FRAME]]
+; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD [[HIPTR]](p0) :: (invariant load 8 from %fixed-stack.[[HI_FRAME]], align 0)
 define void @take_split_struct([2 x i64]* %ptr, i64, i64, i64,
                                i64, i64, i64,
                                [2 x i64] %in) {
diff --git a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
index 8959ce25c73..eb2d2ec4307 100644
--- a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
+++ b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll
@@ -3,7 +3,7 @@
 
 ; CHECK-LABEL: name: debug_declare
 ; CHECK: stack:
-; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}}, 
+; CHECK:    - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
 ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12
@@ -26,7 +26,7 @@ entry:
 }
 
 ; CHECK-LABEL: name: debug_value
-; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0
+; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
 define void @debug_value(i32 %in) #0 !dbg !16 {
   %addr = alloca i32
 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18
diff --git a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
index 196910e96ce..62aceaa8130 100644
--- a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
+++ b/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll
@@ -1,15 +1,15 @@
 ; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
 
 ; CHECK-LABEL: name: test_simple_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
-; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 4
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 4
 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
-; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC]]
 define i8* @test_simple_alloca(i32 %numelts) {
   %addr = alloca i8, i32 %numelts
@@ -17,15 +17,15 @@ define i8* @test_simple_alloca(i32 %numelts) {
 }
 
 ; CHECK-LABEL: name: test_aligned_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
-; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 5
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 5
 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
-; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]]
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC]]
 define i8* @test_aligned_alloca(i32 %numelts) {
   %addr = alloca i8, i32 %numelts, align 32
@@ -33,14 +33,14 @@ define i8* @test_aligned_alloca(i32 %numelts) {
 }
 
 ; CHECK-LABEL: name: test_natural_alloca
-; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0
-; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -16
-; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32)
-; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
-; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
+; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
+; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
+; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
+; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
+; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
 ; CHECK: %sp = COPY [[ALLOC]]
-; CHECK: [[ALLOC_TMP:%[0-9]+]](p0) = COPY [[ALLOC]]
+; CHECK: [[ALLOC_TMP:%[0-9]+]]:_(p0) = COPY [[ALLOC]]
 ; CHECK: %x0 = COPY [[ALLOC_TMP]]
 define i128* @test_natural_alloca(i32 %numelts) {
   %addr = alloca i128, i32 %numelts
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
index 8d1b02216ea..70dddeb4585 100644
--- a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll
@@ -23,7 +23,7 @@ define i32 @test_bitcast_invalid_vreg() {
   %tmp15 = add i32 30, 30
 
 ; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
-; CHECK:  %46(s32) = G_CONSTANT i32 100
+; CHECK:  %46:_(s32) = G_CONSTANT i32 100
 ; CHECK:  %w0 = COPY %46(s32)
   %res = bitcast i32 100 to i32
   ret i32 %res
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index d9fec0ec7d4..0e7fbd32c6f 100644
--- a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -13,26 +13,26 @@ declare i32 @llvm.eh.typeid.for(i8*)
 ; CHECK:     EH_LABEL
 ; CHECK:     %w0 = COPY
 ; CHECK:     BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
-; CHECK:     {{%[0-9]+}}(s32) = COPY %w0
+; CHECK:     {{%[0-9]+}}:_(s32) = COPY %w0
 ; CHECK:     EH_LABEL
 ; CHECK:     G_BR %[[GOOD]]
 
 ; CHECK:   [[BAD]] (landing-pad):
 ; CHECK:     EH_LABEL
-; CHECK:     [[UNDEF:%[0-9]+]](s128) = G_IMPLICIT_DEF
-; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[VAL_WITH_PTR:%[0-9]+]](s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
-; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
-; CHECK:     [[PTR_SEL:%[0-9]+]](s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
-; CHECK:     [[PTR_RET:%[0-9]+]](s64) = G_EXTRACT [[PTR_SEL]](s128), 0
-; CHECK:     [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 64
+; CHECK:     [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK:     [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
+; CHECK:     [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
+; CHECK:     [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
+; CHECK:     [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
+; CHECK:     [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
 ; CHECK:     %x0 = COPY [[PTR_RET]]
 ; CHECK:     %w1 = COPY [[SEL_RET]]
 
 ; CHECK:   [[GOOD]]:
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK:     {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK:     {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
 
 define { i8*, i32 } @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
   %res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken
@@ -49,7 +49,7 @@ continue:
 }
 
 ; CHECK-LABEL: name: test_invoke_indirect
-; CHECK: [[CALLEE:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY %x0
 ; CHECK: BLR [[CALLEE]]
 define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
   invoke void %callee() to label %continue unwind label %broken
@@ -64,20 +64,20 @@ continue:
 
 ; CHECK-LABEL: name: test_invoke_varargs
 
-; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0
-; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42
-; CHECK: [[ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.0
+; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
+; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
 
 ; CHECK: %x0 = COPY [[NULL]]
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 0
-; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
 ; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]]
 
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 8
-; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
 ; CHECK: G_STORE [[ONE]](s32), [[SLOT]]
 
 ; CHECK: BL @printf
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
index 8cfc19fdddb..fa6727da1bb 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
@@ -35,14 +35,14 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_add_big
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY %x2
-    ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY %x3
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
-    ; CHECK: [[UADDE:%[0-9]+]](s64), [[UADDE1:%[0-9]+]](s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
-    ; CHECK: [[UADDE2:%[0-9]+]](s64), [[UADDE3:%[0-9]+]](s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
+    ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
+    ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
     ; CHECK: %x0 = COPY [[UADDE]](s64)
     ; CHECK: %x1 = COPY [[UADDE2]](s64)
     %0(s64) = COPY %x0
@@ -71,13 +71,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_add_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[ADD]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -105,12 +105,12 @@ body: |
     liveins: %q0, %q1, %q2, %q3
 
     ; CHECK-LABEL: name: test_vector_add
-    ; CHECK: [[COPY:%[0-9]+]](<2 x s64>) = COPY %q0
-    ; CHECK: [[COPY1:%[0-9]+]](<2 x s64>) = COPY %q1
-    ; CHECK: [[COPY2:%[0-9]+]](<2 x s64>) = COPY %q2
-    ; CHECK: [[COPY3:%[0-9]+]](<2 x s64>) = COPY %q3
-    ; CHECK: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
-    ; CHECK: [[ADD1:%[0-9]+]](<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
+    ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
     ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
     ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
     %0(<2 x s64>) = COPY %q0
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 15b0cbfd057..9646480e425 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -24,14 +24,14 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_and_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC2:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[TRUNC1]], [[TRUNC2]]
-    ; CHECK: [[TRUNC3:%[0-9]+]](s8) = G_TRUNC [[AND]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[TRUNC2]]
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index 51b1c3890ab..706ad118be8 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -32,18 +32,18 @@ body: |
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: [[CMP1:%[0-9]+]](s32) = G_ICMP intpred(sge), %0(s64), %1
-    ; CHECK: [[CMP_T1:%[0-9]+]](s1) = G_TRUNC [[CMP1]]
+    ; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %0(s64), %1
+    ; CHECK: [[CMP_T1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
     %4(s1) = G_ICMP intpred(sge), %0, %1
 
-    ; CHECK: [[CSTMASK1:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[T1:%[0-9]+]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[AND1:%[0-9]+]](s32) = G_AND [[T1]], [[CSTMASK1]]
-    ; CHECK: [[CSTMASK2:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[T2:%[0-9]+]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[AND2:%[0-9]+]](s32) = G_AND [[T2]], [[CSTMASK2]]
-    ; CHECK: [[CMP2:%[0-9]+]](s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND2]]
-    ; CHECK: [[CMP_T2:%[0-9]+]](s1) = G_TRUNC [[CMP2]]
+    ; CHECK: [[CSTMASK1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[T1]], [[CSTMASK1]]
+    ; CHECK: [[CSTMASK2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[T2]], [[CSTMASK2]]
+    ; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND2]]
+    ; CHECK: [[CMP_T2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
     %8(s1) = G_ICMP intpred(ult), %2, %3
 
     %9(p0) = G_INTTOPTR %0(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
index 71fb5bb74d9..eee1a44e547 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
@@ -19,11 +19,11 @@ body: |
 
     ; Here the types don't match.
     ; CHECK-LABEL: name: test_combines_2
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
-    ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
-    ; CHECK: [[EXTRACT:%[0-9]+]](s1) = G_EXTRACT [[MV]](s64), 0
-    ; CHECK: [[EXTRACT1:%[0-9]+]](s64) = G_EXTRACT [[MV]](s64), 0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s1) = G_EXTRACT [[MV]](s64), 0
+    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[MV]](s64), 0
     %0:_(s32) = COPY %w0
 
     %1:_(s32) = G_ADD %0, %0
@@ -39,9 +39,9 @@ body: |
     liveins: %w0
 
     ; CHECK-LABEL: name: test_combines_3
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
-    ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
     %0:_(s32) = COPY %w0
 
     %1:_(s32) = G_ADD %0, %0
@@ -57,9 +57,9 @@ body: |
     liveins: %x0
 
     ; CHECK-LABEL: name: test_combines_4
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY [[COPY]](s64)
-    ; CHECK: [[ADD:%[0-9]+]](s64) = G_ADD [[COPY1]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
     %0:_(s64) = COPY %x0
 
     %1:_(s128) = G_MERGE_VALUES %0, %0
@@ -74,9 +74,9 @@ body: |
     liveins: %w0
 
     ; CHECK-LABEL: name: test_combines_5
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
-    ; CHECK: [[ADD1:%[0-9]+]](s32) = G_ADD [[COPY]], [[ADD]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
     %0:_(s32) = COPY %w0
 
     %1:_(s32) = G_ADD %0, %0
@@ -93,9 +93,9 @@ body: |
 
     ; Check that we replace all the uses of a G_EXTRACT.
     ; CHECK-LABEL: name: test_combines_6
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]]
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[MUL]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY]]
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[MUL]]
     %0:_(s32) = COPY %w0
 
     %1:_(s32) = G_MERGE_VALUES %0
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
index 3c982008004..adeee11bfbf 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
@@ -29,15 +29,15 @@ body: |
   bb.0.entry:
 
     ; CHECK-LABEL: name: test_constant
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[C]](s32)
-    ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 42
-    ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[C1]](s32)
-    ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; CHECK: [[TRUNC2:%[0-9]+]](s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; CHECK: [[C4:%[0-9]+]](s64) = G_CONSTANT i64 1
-    ; CHECK: [[C5:%[0-9]+]](s64) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+    ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
     %0(s1) = G_CONSTANT i1 0
     %1(s8) = G_CONSTANT i8 42
     %2(s16) = G_CONSTANT i16 65535
@@ -56,10 +56,10 @@ body: |
   bb.0.entry:
 
     ; CHECK-LABEL: name: test_fconstant
-    ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-    ; CHECK: [[C1:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00
-    ; CHECK: [[C2:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
-    ; CHECK: [[FPTRUNC:%[0-9]+]](s16) = G_FPTRUNC [[C2]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
+    ; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
     %0(s32) = G_FCONSTANT float 1.0
     %1(s64) = G_FCONSTANT double 2.0
     %2(s16) = G_FCONSTANT half 0.0
@@ -73,6 +73,6 @@ body: |
   bb.0:
 
     ; CHECK-LABEL: name: test_global
-    ; CHECK: [[GV:%[0-9]+]](p0) = G_GLOBAL_VALUE @var
+    ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
     %0(p0) = G_GLOBAL_VALUE @var
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
index b869232590b..55e3e801023 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
@@ -26,30 +26,30 @@ body: |
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: [[A:%.*]](s64) = COPY %x0
-    ; CHECK: [[B:%.*]](s64) = COPY %x1
-    ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[S1:%.*]](s32) = G_TRUNC [[A]]
-    ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[S1]], [[C1]]
-    ; CHECK: [[SEXT1:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
-    ; CHECK: [[C2:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[S2:%.*]](s32) = G_TRUNC [[B]]
-    ; CHECK: [[SHL2:%.*]](s32) = G_SHL [[S2]], [[C2]]
-    ; CHECK: [[SEXT2:%.*]](s32) = G_ASHR [[SHL2]], [[C2]]
-    ; CHECK: [[DIV:%.*]](s32) = G_SDIV [[SEXT1]], [[SEXT2]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[DIV]]
+    ; CHECK: [[A:%.*]]:_(s64) = COPY %x0
+    ; CHECK: [[B:%.*]]:_(s64) = COPY %x1
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[S1:%.*]]:_(s32) = G_TRUNC [[A]]
+    ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[S1]], [[C1]]
+    ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[S2:%.*]]:_(s32) = G_TRUNC [[B]]
+    ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[S2]], [[C2]]
+    ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+    ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[SEXT1]], [[SEXT2]]
+    ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[DIV]]
 
     %4(s8) = G_SDIV %2, %3
 
 
-    ; CHECK: [[CMASK1:%.*]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[T1:%.*]](s32) = G_TRUNC [[A]]
-    ; CHECK: [[LHS32:%.*]](s32) = G_AND [[T1]], [[CMASK1]]
-    ; CHECK: [[CMASK2:%.*]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[T2:%.*]](s32) = G_TRUNC [[B]]
-    ; CHECK: [[RHS32:%.*]](s32) = G_AND [[T2]], [[CMASK2]]
-    ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_UDIV [[LHS32]], [[RHS32]]
-    ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
+    ; CHECK: [[CMASK1:%.*]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC [[A]]
+    ; CHECK: [[LHS32:%.*]]:_(s32) = G_AND [[T1]], [[CMASK1]]
+    ; CHECK: [[CMASK2:%.*]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC [[B]]
+    ; CHECK: [[RHS32:%.*]]:_(s32) = G_AND [[T2]], [[CMASK2]]
+    ; CHECK: [[QUOT32:%[0-9]+]]:_(s32) = G_UDIV [[LHS32]], [[RHS32]]
+    ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_TRUNC [[QUOT32]]
     %5(s8) = G_UDIV %2, %3
 
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index 42ca367e122..da40b274aa6 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -15,18 +15,18 @@ declare void @_Unwind_Resume(i8*)
 ; CHECK:   [[LP]] (landing-pad):
 ; CHECK:     EH_LABEL
 
-; CHECK:     [[PTR:%[0-9]+]](p0) = COPY %x0
-; CHECK:     [[STRUCT_PTR:%[0-9]+]](s64) = G_PTRTOINT [[PTR]](p0)
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK:     [[STRUCT_PTR:%[0-9]+]]:_(s64) = G_PTRTOINT [[PTR]](p0)
 
-; CHECK:     [[SEL_PTR:%[0-9]+]](p0) = COPY %x1
-; CHECK:     [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]]
-; CHECK:     [[STRUCT_SEL:%[0-9]+]](s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
+; CHECK:     [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
+; CHECK:     [[STRUCT_SEL:%[0-9]+]]:_(s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0
 
-; CHECK:     [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
+; CHECK:     [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[STRUCT_PTR]](s64)
 ; CHECK:     G_STORE [[PTR]](p0), {{%[0-9]+}}(p0)
 
-; CHECK:     [[SEL_TMP:%[0-9]+]](s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
-; CHECK:     [[SEL:%[0-9]+]](s32) = COPY [[SEL_TMP]]
+; CHECK:     [[SEL_TMP:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT_SEL]](s64), 0
+; CHECK:     [[SEL:%[0-9]+]]:_(s32) = COPY [[SEL_TMP]]
 ; CHECK:     G_STORE [[SEL]](s32), {{%[0-9]+}}(p0)
 
 define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index 70b55e4ebc6..d352630c16b 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -36,44 +36,44 @@ body: |
     liveins: %x0, %x1, %x2, %x3
     %0(s64) = COPY %x0
 
-    ; CHECK: %1(s1) = G_TRUNC %0
-    ; CHECK: %2(s8) = G_TRUNC %0
-    ; CHECK: %3(s16) = G_TRUNC %0
-    ; CHECK: %4(s32) = G_TRUNC %0
+    ; CHECK: %1:_(s1) = G_TRUNC %0
+    ; CHECK: %2:_(s8) = G_TRUNC %0
+    ; CHECK: %3:_(s16) = G_TRUNC %0
+    ; CHECK: %4:_(s32) = G_TRUNC %0
     %1(s1) = G_TRUNC %0
     %2(s8) = G_TRUNC %0
     %3(s16) = G_TRUNC %0
     %4(s32) = G_TRUNC %0
 
-    ; CHECK: %5(s64) = G_ANYEXT %1
-    ; CHECK: %6(s64) = G_ZEXT %2
-    ; CHECK: %7(s64) = G_ANYEXT %3
-    ; CHECK: %8(s64) = G_SEXT %4
+    ; CHECK: %5:_(s64) = G_ANYEXT %1
+    ; CHECK: %6:_(s64) = G_ZEXT %2
+    ; CHECK: %7:_(s64) = G_ANYEXT %3
+    ; CHECK: %8:_(s64) = G_SEXT %4
     %5(s64) = G_ANYEXT %1
     %6(s64) = G_ZEXT %2
     %7(s64) = G_ANYEXT %3
     %8(s64) = G_SEXT %4
 
-    ; CHECK: %9(s32) = G_SEXT %1
-    ; CHECK: %10(s32) = G_ZEXT %2
-    ; CHECK: %11(s32) = G_ANYEXT %3
+    ; CHECK: %9:_(s32) = G_SEXT %1
+    ; CHECK: %10:_(s32) = G_ZEXT %2
+    ; CHECK: %11:_(s32) = G_ANYEXT %3
     %9(s32) = G_SEXT %1
     %10(s32) = G_ZEXT %2
     %11(s32) = G_ANYEXT %3
 
-    ; CHECK: %12(s32) = G_ZEXT %1
-    ; CHECK: %13(s32) = G_ANYEXT %2
-    ; CHECK: %14(s32) = G_SEXT %3
+    ; CHECK: %12:_(s32) = G_ZEXT %1
+    ; CHECK: %13:_(s32) = G_ANYEXT %2
+    ; CHECK: %14:_(s32) = G_SEXT %3
     %12(s32) = G_ZEXT %1
     %13(s32) = G_ANYEXT %2
     %14(s32) = G_SEXT %3
 
-    ; CHECK: %15(s8) = G_ZEXT %1
-    ; CHECK: %16(s16) = G_ANYEXT %2
+    ; CHECK: %15:_(s8) = G_ZEXT %1
+    ; CHECK: %16:_(s16) = G_ANYEXT %2
     %15(s8) = G_ZEXT %1
     %16(s16) = G_ANYEXT %2
 
-    ; CHECK: %18(s64) = G_FPEXT %17
+    ; CHECK: %18:_(s64) = G_FPEXT %17
     %17(s32) = G_TRUNC  %0
     %18(s64) = G_FPEXT %17
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir b/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
index 567bb9020fd..3f6c00e20a2 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
@@ -11,14 +11,14 @@ body: |
     ; value stored is forwarded directly from first load.
 
     ; CHECK-LABEL: name: test_extracts_1
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
-    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
-    ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
-    ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
-    ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY %x2
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
     ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
     ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
@@ -38,16 +38,16 @@ body: |
 
       ; Low extraction wipes takes whole low register. High extraction is real.
     ; CHECK-LABEL: name: test_extracts_2
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]](p0) = COPY %x2
-    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY2]](p0) :: (load 16)
-    ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY2]], [[C]](s64)
-    ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP]](p0) :: (load 16)
-    ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY [[LOAD]](s64)
-    ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[LOAD1]](s64), 0
-    ; CHECK: [[COPY4:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY %x2
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD1]](s64), 0
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
     ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
     ; CHECK: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store 4)
     ; CHECK: RET_ReallyLR
@@ -70,11 +70,11 @@ body: |
 
 
     ; CHECK-LABEL: name: test_extracts_3
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
-    ; CHECK: [[EXTRACT1:%[0-9]+]](s32) = G_EXTRACT [[COPY1]](s64), 0
-    ; CHECK: [[MV:%[0-9]+]](s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
+    ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
     ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
@@ -91,10 +91,10 @@ body: |
 
 
     ; CHECK-LABEL: name: test_extracts_4
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[EXTRACT:%[0-9]+]](s32) = G_EXTRACT [[COPY]](s64), 32
-    ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY [[EXTRACT]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
     ; CHECK: RET_ReallyLR
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
index 64cbd93f46c..4f57ee55254 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
@@ -29,13 +29,13 @@ body: |
     %2(s32) = G_TRUNC %0
     %3(s32) = G_TRUNC %1
 
-    ; CHECK: [[CMP1:%[0-9]+]](s32) = G_FCMP floatpred(oge), %0(s64), %1
-    ; CHECK: [[TRUNC1:%[0-9]+]](s1) = G_TRUNC [[CMP1]]
+    ; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), %0(s64), %1
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
     %4(s32) = G_FCMP floatpred(oge), %0, %1
     %6(s1) = G_TRUNC %4(s32)
 
-    ; CHECK: [[CMP2:%[0-9]+]](s32) = G_FCMP floatpred(uno), %2(s32), %3
-    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[CMP2]]
+    ; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), %2(s32), %3
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
     %5(s32) = G_FCMP floatpred(uno), %2, %3
     %7(s1) = G_TRUNC %5(s32)
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
index 393165bb788..e7dc314f034 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir
@@ -22,9 +22,9 @@ body:             |
   bb.1:
     liveins: %s0
     ; CHECK-LABEL: name: test_fneg_f32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
-    ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[C]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %s0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -0.000000e+00
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
     ; CHECK: %s0 = COPY [[FSUB]](s32)
     %0(s32) = COPY %s0
     %1(s32) = G_FNEG %0
@@ -39,9 +39,9 @@ body:             |
   bb.1:
     liveins: %d0
     ; CHECK-LABEL: name: test_fneg_f64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0
-    ; CHECK: [[C:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
-    ; CHECK: [[FSUB:%[0-9]+]](s64) = G_FSUB [[C]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %d0
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -0.000000e+00
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
     ; CHECK: %d0 = COPY [[FSUB]](s64)
     %0(s64) = COPY %d0
     %1(s64) = G_FNEG %0
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
index 3a8f910303a..f82d13c71cb 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
@@ -31,8 +31,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptosi_s32_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s32) = G_FPTOSI %0
 ...
@@ -43,8 +43,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptoui_s32_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s32) = G_FPTOUI %0
 ...
@@ -55,8 +55,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptosi_s32_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s32) = G_FPTOSI %0
 ...
@@ -67,8 +67,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptoui_s32_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s32) = G_FPTOUI %0
 ...
@@ -79,8 +79,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptosi_s64_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s64) = G_FPTOSI %0
 ...
@@ -91,8 +91,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptoui_s64_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s64) = G_FPTOUI %0
 ...
@@ -103,8 +103,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptosi_s64_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = G_FPTOSI %0
 ...
@@ -115,8 +115,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptoui_s64_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s64) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = G_FPTOUI %0
 ...
@@ -129,9 +129,9 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptosi_s1_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOSI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_FPTOSI %0
 ...
@@ -142,9 +142,9 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptoui_s1_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FPTOUI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOUI]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_FPTOUI %0
 ...
@@ -155,9 +155,9 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptosi_s8_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOSI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOSI]](s32)
     %0:_(s64) = COPY %x0
     %1:_(s8) = G_FPTOSI %0
 ...
@@ -168,9 +168,9 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_fptoui_s8_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[FPTOUI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOUI]](s32)
     %0:_(s64) = COPY %x0
     %1:_(s8) = G_FPTOUI %0
 ...
@@ -181,9 +181,9 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptosi_s16_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s32) = G_FPTOSI [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOSI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOSI]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_FPTOSI %0
 ...
@@ -194,9 +194,9 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_fptoui_s16_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]](s16) = G_TRUNC [[FPTOUI]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOUI]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_FPTOUI %0
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir b/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
index 3faf71cd0f2..67310d10336 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
@@ -22,13 +22,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_gep_small
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 56
-    ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY [[COPY1]](s64)
-    ; CHECK: [[SHL:%[0-9]+]](s64) = G_SHL [[COPY2]], [[C]]
-    ; CHECK: [[ASHR:%[0-9]+]](s64) = G_ASHR [[SHL]], [[C]]
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[COPY]], [[ASHR]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[ASHR]](s64)
     ; CHECK: %x0 = COPY [[GEP]](p0)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
index 65fc6975b65..b0de3fc8092 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
@@ -17,7 +17,7 @@ body: |
     liveins: %x0
 
     ; CHECK-LABEL: name: test_copy
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
     ; CHECK: %x0 = COPY [[COPY]](s64)
     %0(s64) = COPY %x0
     %x0 = COPY %0
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index 16d9803c161..7432b6761b7 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -21,8 +21,8 @@ body: |
       ; forwarded to the G_STORE. Hi part is unchanged so (split) G_LOAD gets
       ; forwarded.
     ; CHECK-LABEL: name: test_inserts_1
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
     ; CHECK: G_STORE %0(s64)
     ; CHECK: G_STORE [[HI]]
     %0:_(s64) = COPY %x0
@@ -43,9 +43,9 @@ body: |
       ; Low insertion wipes out the old register entirely, so %0 gets forwarded
       ; to the G_STORE again. Second insertion is real.
     ; CHECK-LABEL: name: test_inserts_2
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[NEWHI:%[0-9]+]](s64) = G_INSERT [[HI]], %1(s32), 0
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[NEWHI:%[0-9]+]]:_(s64) = G_INSERT [[HI]], %1(s32), 0
     ; CHECK: G_STORE %0(s64)
     ; CHECK: G_STORE [[NEWHI]]
     %0:_(s64) = COPY %x0
@@ -68,9 +68,9 @@ body: |
       ; certainly better than the alternative of directly forwarding the value
       ; which would cause a nasty type mismatch.
     ; CHECK-LABEL: name: test_inserts_3
-    ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD
-    ; CHECK: [[NEWLO:%[0-9]+]](s64) = G_PTRTOINT %0(p0)
+    ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_LOAD
+    ; CHECK: [[NEWLO:%[0-9]+]]:_(s64) = G_PTRTOINT %0(p0)
     ; CHECK: G_STORE [[NEWLO]](s64)
     ; CHECK: G_STORE [[HI]]
     %0:_(p0) = COPY %x0
@@ -90,9 +90,9 @@ body: |
 
       ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair.
     ; CHECK-LABEL: name: test_inserts_4
-    ; CHECK: [[VALEXT:%[0-9]+]](s32) = COPY %2(s32)
-    ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %1(s1), 0
-    ; CHECK: %5(s8) = G_TRUNC [[VAL]](s32)
+    ; CHECK: [[VALEXT:%[0-9]+]]:_(s32) = COPY %2(s32)
+    ; CHECK: [[VAL:%[0-9]+]]:_(s32) = G_INSERT [[VALEXT]], %1(s1), 0
+    ; CHECK: %5:_(s8) = G_TRUNC [[VAL]](s32)
     %4:_(s32) = COPY %w0
     %0:_(s1) = G_TRUNC %4
     %5:_(s32) = COPY %w1
@@ -111,11 +111,11 @@ body: |
 
 
     ; CHECK-LABEL: name: test_inserts_5
-    ; CHECK: [[INS_LO:%[0-9]+]](s32) = G_EXTRACT %2(s64), 0
-    ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, [[INS_LO]](s32), 32
-    ; CHECK: [[INS_HI:%[0-9]+]](s32) = G_EXTRACT %2(s64), 32
-    ; CHECK: [[VAL_HI:%[0-9]+]](s64) = G_INSERT %1, [[INS_HI]](s32), 0
-    ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
+    ; CHECK: [[INS_LO:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 0
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, [[INS_LO]](s32), 32
+    ; CHECK: [[INS_HI:%[0-9]+]]:_(s32) = G_EXTRACT %2(s64), 32
+    ; CHECK: [[VAL_HI:%[0-9]+]]:_(s64) = G_INSERT %1, [[INS_HI]](s32), 0
+    ; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s64) = COPY %x2
@@ -132,8 +132,8 @@ body: |
 
 
     ; CHECK-LABEL: name: test_inserts_6
-    ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, %2(s32), 32
-    ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64)
+    ; CHECK: [[VAL_LO:%[0-9]+]]:_(s64) = G_INSERT %0, %2(s32), 32
+    ; CHECK: %4:_(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s32) = COPY %w2
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
index 1ada3b8a934..4ab9bf30914 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
@@ -31,8 +31,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s32_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s32) = G_SITOFP %0
 ...
@@ -43,8 +43,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_uitofp_s32_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s32) = G_UITOFP %0
 ...
@@ -55,8 +55,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_sitofp_s32_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s32) = G_SITOFP %0
 ...
@@ -67,8 +67,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_uitofp_s32_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s32) = G_UITOFP %0
 ...
@@ -79,8 +79,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s64_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s64) = G_SITOFP %0
 ...
@@ -91,8 +91,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_uitofp_s64_s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s64) = G_UITOFP %0
 ...
@@ -103,8 +103,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_sitofp_s64_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = G_SITOFP %0
 ...
@@ -115,8 +115,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_uitofp_s64_s64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64)
     %0:_(s64) = COPY %x0
     %1:_(s64) = G_UITOFP %0
 ...
@@ -128,12 +128,12 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s32_s1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 31
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
-    ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
-    ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_SITOFP %1
@@ -145,11 +145,11 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_uitofp_s32_s1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 1
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s1) = G_TRUNC %0
     %2:_(s32) = G_UITOFP %1
@@ -161,12 +161,12 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s64_s8
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
-    ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
-    ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[ASHR]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s8) = G_TRUNC %0
     %2:_(s64) = G_SITOFP %1
@@ -178,11 +178,11 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_uitofp_s64_s8
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]](s64) = G_UITOFP [[AND]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s8) = G_TRUNC %0
     %2:_(s64) = G_UITOFP %1
@@ -194,12 +194,12 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s32_s16
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 16
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY1]], [[C]]
-    ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[SHL]], [[C]]
-    ; CHECK: [[SITOFP:%[0-9]+]](s32) = G_SITOFP [[ASHR]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]]
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_TRUNC %0
     %2:_(s32) = G_SITOFP %1
@@ -211,11 +211,11 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_uitofp_s32_s16
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 65535
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[AND]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
     %0:_(s32) = COPY %w0
     %1:_(s16) = G_TRUNC %0
     %2:_(s32) = G_UITOFP %1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 0149043f9e5..cda82fb46e7 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -31,33 +31,33 @@ body: |
     ; CHECK-LABEL: name: test_load
     %0(p0) = COPY %x0
 
-    ; CHECK: [[BIT8:%[0-9]+]](s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
-    ; CHECK: %1(s1) = G_TRUNC [[BIT8]]
+    ; CHECK: [[BIT8:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
+    ; CHECK: %1:_(s1) = G_TRUNC [[BIT8]]
     %1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
 
-    ; CHECK: %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
+    ; CHECK: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
     %2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
 
-    ; CHECK: %3(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
+    ; CHECK: %3:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
     %3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
 
-    ; CHECK: %4(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
+    ; CHECK: %4:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
     %4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
 
-    ; CHECK: %5(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    ; CHECK: %5:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
 
-    ; CHECK: %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    ; CHECK: %6:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
 
-    ; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+    ; CHECK: %7:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
     %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
 
-    ; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
-    ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
-    ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
-    ; CHECK: %8(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
+    ; CHECK: [[LOAD0:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
+    ; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
+    ; CHECK: %8:_(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
     %8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
 ...
 
@@ -80,11 +80,11 @@ body: |
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
 
-    ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 1
-    ; CHECK: [[B:%.*]](s32) = COPY %1(s32)
-    ; CHECK: [[COPY_C1:%.*]](s32) = COPY [[C1]]
-    ; CHECK: [[AND:%.*]](s32) = G_AND [[B]], [[COPY_C1]]
-    ; CHECK: [[BIT8:%.*]](s8) = G_TRUNC [[AND]]
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[B:%.*]]:_(s32) = COPY %1(s32)
+    ; CHECK: [[COPY_C1:%.*]]:_(s32) = COPY [[C1]]
+    ; CHECK: [[AND:%.*]]:_(s32) = G_AND [[B]], [[COPY_C1]]
+    ; CHECK: [[BIT8:%.*]]:_(s8) = G_TRUNC [[AND]]
 
 
     ; CHECK: G_STORE [[BIT8]](s8), %0(p0) :: (store 1 into %ir.addr)
@@ -110,8 +110,8 @@ body: |
     G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
 
     ; CHECK: G_STORE %5(s64), %0(p0) :: (store 16 into %ir.addr)
-    ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
+    ; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP %0, [[OFFSET1]](s64)
     ; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr)
     %6(s64) = G_PTRTOINT %0(p0)
     %7(s128) = G_MERGE_VALUES %5, %6
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 42980edc16b..bbc559eb0e1 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -25,13 +25,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_mul_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[MUL]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[MUL]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -50,13 +50,13 @@ body: |
     liveins: %x0, %x1, %w2, %w3
 
     ; CHECK-LABEL: name: test_mul_overflow
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[MUL:%[0-9]+]](s64) = G_MUL [[COPY]], [[COPY1]]
-    ; CHECK: [[SMULH:%[0-9]+]](s64) = G_SMULH [[COPY]], [[COPY1]]
-    ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 0
-    ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+    ; CHECK: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
     %0:_(s64) = COPY %x0
     %1:_(s64) = COPY %x1
     %2:_(s64), %3:_(s1) = G_SMULO %0, %1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
index d657cf66964..b0c7d1324bf 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
@@ -19,10 +19,10 @@ body: |
   bb.0:
     liveins: %w0, %w1, %w2
     ; CHECK-LABEL: name: test_legalize_merge_v3s32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]](s32) = COPY %w2
-    ; CHECK: [[MV:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
+    ; CHECK: [[MV:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index 8570813ac0f..9536e8add2b 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -15,13 +15,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_or_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[OR]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -52,12 +52,12 @@ body: |
     ; copying the results of the G_OR ops.
 
     ; CHECK-LABEL: name: test_big_scalar_power_of_2
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[COPY2:%[0-9]+]](s64) = COPY %x2
-    ; CHECK: [[COPY3:%[0-9]+]](s64) = COPY %x3
-    ; CHECK: [[OR:%[0-9]+]](s64) = G_OR [[COPY]], [[COPY2]]
-    ; CHECK: [[OR1:%[0-9]+]](s64) = G_OR [[COPY1]], [[COPY3]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
+    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY2]]
+    ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[COPY3]]
     ; CHECK: %x0 = COPY [[OR]](s64)
     ; CHECK: %x1 = COPY [[OR1]](s64)
     ; CHECK: RET_ReallyLR implicit %x0, implicit %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 2345b4d4829..68a8e6d9537 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -4,7 +4,7 @@
   source_filename = "/tmp/test.ll"
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-unknown-unknown"
-  
+
   define i32 @legalize_phi(i32 %argc) {
   entry:
     ret i32 0
@@ -48,7 +48,7 @@ legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
@@ -60,26 +60,26 @@ registers:
   - { id: 8, class: _, preferred-register: '' }
   - { id: 9, class: _, preferred-register: '' }
   - { id: 10, class: _, preferred-register: '' }
-liveins:         
+liveins:
 body:             |
   bb.0:
    ; Test that we insert legalization artifacts(Truncs here) into the correct BBs
    ; while legalizing the G_PHI to s16.
    ; CHECK-LABEL: name: legalize_phi
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[ADD_BB1:%.*]](s32) = G_ADD
-   ; CHECK: [[RES_BB1:%.*]](s16) = G_TRUNC [[ADD_BB1]]
+   ; CHECK: [[ADD_BB1:%.*]]:_(s32) = G_ADD
+   ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[ADD_BB1]]
 
    ; CHECK-LABEL: bb.2:
-   ; CHECK: [[ADD_BB2:%.*]](s32) = G_ADD
-   ; CHECK: [[RES_BB2:%.*]](s16) = G_TRUNC [[ADD_BB2]]
+   ; CHECK: [[ADD_BB2:%.*]]:_(s32) = G_ADD
+   ; CHECK: [[RES_BB2:%.*]]:_(s16) = G_TRUNC [[ADD_BB2]]
 
    ; CHECK-LABEL: bb.3:
-   ; CHECK: [[RES_PHI:%.*]](s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
-   ; CHECK: [[RES:%.*]](s1) = G_TRUNC [[RES_PHI]]
+   ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
+   ; CHECK: [[RES:%.*]]:_(s1) = G_TRUNC [[RES_PHI]]
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: %w0
-  
+
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 0
     %3(s32) = G_CONSTANT i32 1
@@ -87,20 +87,20 @@ body:             |
     %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
     G_BRCOND %2(s1), %bb.1
     G_BR %bb.2
-  
+
   bb.1:
     successors: %bb.3(0x80000000)
-  
+
     %4(s32) = G_ADD %0, %3
     %5(s1) = G_TRUNC %4(s32)
     G_BR %bb.3
-  
+
   bb.2:
     successors: %bb.3(0x80000000)
-  
+
     %7(s32) = G_ADD %0, %6
     %8(s1) = G_TRUNC %7(s32)
-  
+
   bb.3:
     %9(s1) = G_PHI %5(s1), %bb.1, %8(s1), %bb.2
     %10(s32) = G_ZEXT %9(s1)
@@ -128,14 +128,14 @@ body:             |
   bb.1:
    ; CHECK-LABEL: name: legalize_phi_ptr
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[A:%[0-9]+]](p0) = COPY %x0
-   ; CHECK: [[B:%[0-9]+]](p0) = COPY %x1
-   ; CHECK: [[CE:%[0-9]+]](s32) = COPY %w2
-   ; CHECK: [[C:%[0-9]+]](s1) = G_TRUNC [[CE]]
+   ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
+   ; CHECK: [[B:%[0-9]+]]:_(p0) = COPY %x1
+   ; CHECK: [[CE:%[0-9]+]]:_(s32) = COPY %w2
+   ; CHECK: [[C:%[0-9]+]]:_(s1) = G_TRUNC [[CE]]
 
    ; CHECK-LABEL: bb.1:
    ; CHECK-LABEL: bb.2:
-   ; CHECK: %3(p0) = G_PHI [[A]](p0), %bb.0, [[B]](p0), %bb.1
+   ; CHECK: %3:_(p0) = G_PHI [[A]](p0), %bb.0, [[B]](p0), %bb.1
    ; CHECK: %x0 = COPY %3(p0)
     successors: %bb.2, %bb.3
     liveins: %w2, %x0, %x1
@@ -184,17 +184,17 @@ body:             |
    ; Test that we properly legalize a phi with a predecessor that's empty
    ; CHECK-LABEL: name: legalize_phi_empty
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[ENTRY_ADD:%.*]](s32) = G_ADD
+   ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
 
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[ADD_BB1:%.*]](s32) = G_ADD
-   ; CHECK: [[RES_BB1:%.*]](s16) = G_TRUNC [[ADD_BB1]]
+   ; CHECK: [[ADD_BB1:%.*]]:_(s32) = G_ADD
+   ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[ADD_BB1]]
 
    ; CHECK-LABEL: bb.2:
-   ; CHECK: [[RES_BB2:%.*]](s16) = G_TRUNC [[ENTRY_ADD]]
+   ; CHECK: [[RES_BB2:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
 
-   ; CHECK: [[RES_PHI:%.*]](s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
-   ; CHECK: [[RES:%.*]](s1) = G_TRUNC [[RES_PHI]]
+   ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
+   ; CHECK: [[RES:%.*]]:_(s1) = G_TRUNC [[RES_PHI]]
 
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 0
@@ -249,13 +249,13 @@ body:             |
    ; Test that we properly legalize a phi that uses a value from the same BB
    ; CHECK-LABEL: name: legalize_phi_loop
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[C0:%.*]](s32) = G_CONSTANT i32 0
-   ; CHECK: [[RES_BB1:%.*]](s16) = G_TRUNC [[C0]]
+   ; CHECK: [[C0:%.*]]:_(s32) = G_CONSTANT i32 0
+   ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[C0]]
 
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[RES_PHI:%.*]](s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
+   ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
    ; CHECK-NEXT: G_ANYEXT [[RES_PHI]]
-   ; CHECK: [[RES_BB2]](s16) = G_ANYEXT
+   ; CHECK: [[RES_BB2]]:_(s16) = G_ANYEXT
     %0(s32) = COPY %w0
     %2(s8) = G_CONSTANT i8 1
     %7(s8) = G_CONSTANT i8 0
@@ -297,13 +297,13 @@ body:             |
    ; Test that we properly legalize a phi that uses itself
    ; CHECK-LABEL: name: legalize_phi_cycle
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[C0:%.*]](s32) = G_CONSTANT i32 0
-   ; CHECK: [[RES_BB1:%.*]](s16) = G_TRUNC [[C0]]
+   ; CHECK: [[C0:%.*]]:_(s32) = G_CONSTANT i32 0
+   ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[C0]]
 
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[RES_PHI:%.*]](s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
+   ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
    ; CHECK-NEXT: G_TRUNC
-   ; CHECK: [[RES_BB2]](s16) = COPY
+   ; CHECK: [[RES_BB2]]:_(s16) = COPY
 
     %0(s32) = COPY %w0
     %4(s8) = G_CONSTANT i8 0
@@ -354,21 +354,21 @@ body:             |
    ; correct location (ie make sure G_PHIs are the first insts in the BB).
    ; CHECK-LABEL: name: legalize_phi_same_bb
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[C42:%.*]](s32) = G_CONSTANT i32 42
-   ; CHECK: [[ENTRY_ADD:%.*]](s32) = G_ADD
+   ; CHECK: [[C42:%.*]]:_(s32) = G_CONSTANT i32 42
+   ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
 
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[BB1_ADD:%.*]](s32) = G_ADD
-   ; CHECK: [[RES1_BB1:%.*]](s16) = G_TRUNC [[BB1_ADD]]
-   ; CHECK: [[RES2_BB1:%.*]](s16) = G_TRUNC [[BB1_ADD]]
+   ; CHECK: [[BB1_ADD:%.*]]:_(s32) = G_ADD
+   ; CHECK: [[RES1_BB1:%.*]]:_(s16) = G_TRUNC [[BB1_ADD]]
+   ; CHECK: [[RES2_BB1:%.*]]:_(s16) = G_TRUNC [[BB1_ADD]]
 
    ; CHECK-LABEL: bb.2:
-   ; CHECK: [[RES1_BB2:%.*]](s16) = G_TRUNC [[ENTRY_ADD]]
-   ; CHECK: [[RES2_BB2:%.*]](s16) = G_TRUNC [[C42]]
+   ; CHECK: [[RES1_BB2:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
+   ; CHECK: [[RES2_BB2:%.*]]:_(s16) = G_TRUNC [[C42]]
 
    ; CHECK-LABEL: bb.3:
-   ; CHECK: [[RES1_PHI:%.*]](s16) = G_PHI [[RES1_BB1]](s16), %bb.1, [[RES1_BB2]](s16), %bb.2
-   ; CHECK-NEXT: [[RES_PHI:%.*]](s16) = G_PHI [[RES2_BB1]](s16), %bb.1, [[RES2_BB2]](s16), %bb.2
+   ; CHECK: [[RES1_PHI:%.*]]:_(s16) = G_PHI [[RES1_BB1]](s16), %bb.1, [[RES1_BB2]](s16), %bb.2
+   ; CHECK-NEXT: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES2_BB1]](s16), %bb.1, [[RES2_BB2]](s16), %bb.2
    ; CHECK-NEXT: G_TRUNC
    ; CHECK-NEXT: G_TRUNC
 
@@ -438,19 +438,19 @@ body:             |
    ; in different BBs.
    ; CHECK-LABEL: name: legalize_phi_diff_bb
    ; CHECK-LABEL: bb.0:
-   ; CHECK: [[C44:%.*]](s32) = G_CONSTANT i32 44
-   ; CHECK: [[C43:%.*]](s32) = G_CONSTANT i32 43
-   ; CHECK: [[ENTRY_ADD:%.*]](s32) = G_ADD
-   ; CHECK: [[RES_ENTRY:%.*]](s16) = G_TRUNC [[ENTRY_ADD]]
-   ; CHECK: [[RES_ENTRY1:%.*]](s16) = G_TRUNC [[ENTRY_ADD]]
+   ; CHECK: [[C44:%.*]]:_(s32) = G_CONSTANT i32 44
+   ; CHECK: [[C43:%.*]]:_(s32) = G_CONSTANT i32 43
+   ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
+   ; CHECK: [[RES_ENTRY:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
+   ; CHECK: [[RES_ENTRY1:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
 
    ; CHECK-LABEL: bb.1:
-   ; CHECK: [[RES1_PHI:%.*]](s16) = G_PHI [[RES_ENTRY]](s16), %bb.0, [[RES_BB1:%.*]](s16), %bb.1
-   ; CHECK: [[RES_BB1:%.*]](s16) = G_TRUNC
-   ; CHECK: [[RES_FOR_BB2:%.*]](s16) = COPY [[RES1_PHI]]
+   ; CHECK: [[RES1_PHI:%.*]]:_(s16) = G_PHI [[RES_ENTRY]](s16), %bb.0, [[RES_BB1:%.*]](s16), %bb.1
+   ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC
+   ; CHECK: [[RES_FOR_BB2:%.*]]:_(s16) = COPY [[RES1_PHI]]
 
    ; CHECK-LABEL: bb.2:
-   ; CHECK: [[RES2_PHI:%.*]](s16) = G_PHI [[RES_FOR_BB2]](s16), %bb.1, [[RES_ENTRY1:%.*]](s16), %bb.0
+   ; CHECK: [[RES2_PHI:%.*]]:_(s16) = G_PHI [[RES_FOR_BB2]](s16), %bb.1, [[RES_ENTRY1:%.*]](s16), %bb.0
    ; CHECK-NEXT: G_TRUNC
 
     %0(s32) = COPY %w0
@@ -483,4 +483,3 @@ body:             |
     RET_ReallyLR implicit %w0
 
 ...
-
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
index 2becc2e134b..b3bfddccc56 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
@@ -26,13 +26,13 @@ body: |
     ; CHECK: %d0 = COPY %0
     ; CHECK: %d1 = COPY %1
     ; CHECK: BL $pow, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
-    ; CHECK: %4(s64) = COPY %d0
+    ; CHECK: %4:_(s64) = COPY %d0
     %4:_(s64) = G_FPOW %0, %1
 
     ; CHECK: %s0 = COPY %2
     ; CHECK: %s1 = COPY %3
     ; CHECK: BL $powf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
-    ; CHECK: %5(s32) = COPY %s0
+    ; CHECK: %5:_(s32) = COPY %s0
     %5:_(s32) = G_FPOW %2, %3
 
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
index ebc1cc270c5..a2bfa81d1b3 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
@@ -32,9 +32,9 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_urem_64
-    ; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1
-    ; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1
-    ; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]]
+    ; CHECK: [[QUOT:%[0-9]+]]:_(s64) = G_UDIV %0, %1
+    ; CHECK: [[PROD:%[0-9]+]]:_(s64) = G_MUL [[QUOT]], %1
+    ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SUB %0, [[PROD]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_UREM %0, %1
@@ -53,11 +53,11 @@ body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_srem_32
-    ; CHECK: [[T1:%.*]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[T2:%.*]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[DIV:%.*]](s32) = G_SDIV [[T1]], [[T2]]
-    ; CHECK: [[MUL:%.*]](s32) = G_MUL [[DIV]], [[T2]]
-    ; CHECK: [[RES:%.*]](s32) = G_SUB [[T1]], [[MUL]]
+    ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[T1]], [[T2]]
+    ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[DIV]], [[T2]]
+    ; CHECK: [[RES:%.*]]:_(s32) = G_SUB [[T1]], [[MUL]]
 
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -79,22 +79,22 @@ body: |
     liveins: %x0, %x1, %x2, %x3
     ; CHECK-LABEL: name: test_srem_8
 
-    ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[SRC1:%.*]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC1]], [[C1]]
-    ; CHECK: [[LHS_SEXT:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
-    ; CHECK: [[C2:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[SRC2:%.*]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[SHL2:%.*]](s32) = G_SHL [[SRC2]], [[C2]]
-    ; CHECK: [[RHS_SEXT:%.*]](s32) = G_ASHR [[SHL2]], [[C2]]
-    ; CHECK: [[SDIV:%.*]](s32) = G_SDIV [[LHS_SEXT]], [[RHS_SEXT]]
-    ; CHECK: [[A:%.*]](s32) = COPY [[SDIV]]
-    ; CHECK: [[SRC3:%.*]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[MUL:%.*]](s32) = G_MUL [[A]], [[SRC3]]
-    ; CHECK: [[SRC4:%.*]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[SRC5:%.*]](s32) = COPY [[MUL]]
-    ; CHECK: [[SUB:%.*]](s32) = G_SUB [[SRC4]], [[SRC5]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[SUB]]
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[SRC1:%.*]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC1]], [[C1]]
+    ; CHECK: [[LHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
+    ; CHECK: [[RHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+    ; CHECK: [[SDIV:%.*]]:_(s32) = G_SDIV [[LHS_SEXT]], [[RHS_SEXT]]
+    ; CHECK: [[A:%.*]]:_(s32) = COPY [[SDIV]]
+    ; CHECK: [[SRC3:%.*]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[A]], [[SRC3]]
+    ; CHECK: [[SRC4:%.*]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[SRC5:%.*]]:_(s32) = COPY [[MUL]]
+    ; CHECK: [[SUB:%.*]]:_(s32) = G_SUB [[SRC4]], [[SRC5]]
+    ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[SUB]]
 
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -119,7 +119,7 @@ body: |
     ; CHECK: %d0 = COPY %0
     ; CHECK: %d1 = COPY %1
     ; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
-    ; CHECK: [[RES:%.*]](s64) = COPY %d0
+    ; CHECK: [[RES:%.*]]:_(s64) = COPY %d0
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %2(s64) = G_FREM %0, %1
@@ -127,7 +127,7 @@ body: |
     ; CHECK: %s0 = COPY %3
     ; CHECK: %s1 = COPY %4
     ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
-    ; CHECK: [[RES:%.*]](s32) = COPY %s0
+    ; CHECK: [[RES:%.*]]:_(s32) = COPY %s0
     %3(s32) = G_TRUNC %0
     %4(s32) = G_TRUNC %1
     %5(s32) = G_FREM %3, %4
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index b15983471e6..7f8f10b2b27 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -27,32 +27,32 @@ body: |
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
 
-    ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[SRC:%.*]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[SHL1:%.*]](s32) = G_SHL [[SRC]], [[C1]]
-    ; CHECK: [[SEXT1:%.*]](s32) = G_ASHR [[SHL1]], [[C1]]
-    ; CHECK: [[C2:%.*]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[SRC2:%.*]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[SHL2:%.*]](s32) = G_SHL [[SRC2]], [[C2]]
-    ; CHECK: [[SEXT2:%.*]](s32) = G_ASHR [[SHL2]], [[C2]]
-    ; CHECK: [[RES32:%[0-9]+]](s32) = G_ASHR [[SEXT1]], [[SEXT2]]
-    ; CHECK: %4(s8) = G_TRUNC [[RES32]]
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC]], [[C1]]
+    ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
+    ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
+    ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[SEXT2]]
+    ; CHECK: %4:_(s8) = G_TRUNC [[RES32]]
     %4(s8) = G_ASHR %2, %3
 
 
-    ; CHECK: [[C1:%.*]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[SRC:%.*]](s32) = G_TRUNC %0(s64)
-    ; CHECK: [[ZEXT:%.*]](s32) = G_AND [[SRC]], [[C1]]
-    ; CHECK: [[C2:%.*]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[SRC2:%.*]](s32) = G_TRUNC %1(s64)
-    ; CHECK: [[ZEXT2:%.*]](s32) = G_AND [[SRC2]], [[C2]]
-    ; CHECK: [[RES32:%[0-9]+]](s32) = G_LSHR [[ZEXT]], [[ZEXT2]]
-    ; CHECK: %5(s8) = G_TRUNC [[RES32]]
+    ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
+    ; CHECK: [[ZEXT:%.*]]:_(s32) = G_AND [[SRC]], [[C1]]
+    ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
+    ; CHECK: [[ZEXT2:%.*]]:_(s32) = G_AND [[SRC2]], [[C2]]
+    ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT2]]
+    ; CHECK: %5:_(s8) = G_TRUNC [[RES32]]
     %5(s8) = G_LSHR %2, %3
 
-    ; CHECK: [[OP0:%.*]](s32) = G_TRUNC %0
-    ; CHECK: [[OP1:%.*]](s32) = G_TRUNC %1
-    ; CHECK: [[RES32:%.*]](s32) = G_SHL [[OP0]], [[OP1]]
-    ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32)
+    ; CHECK: [[OP0:%.*]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[OP1:%.*]]:_(s32) = G_TRUNC %1
+    ; CHECK: [[RES32:%.*]]:_(s32) = G_SHL [[OP0]], [[OP1]]
+    ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[RES32]](s32)
     %6(s8) = G_SHL %2, %3
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 495ea6c7504..0392dcd5cb2 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -45,8 +45,8 @@ body: |
     %4(s32) = G_TRUNC %0
 
     ; CHECK-LABEL: name: test_simple
-    ; CHECK: %5(p0) = G_INTTOPTR %0
-    ; CHECK: %6(s64) = G_PTRTOINT %5
+    ; CHECK: %5:_(p0) = G_INTTOPTR %0
+    ; CHECK: %6:_(s64) = G_PTRTOINT %5
     %5(p0) = G_INTTOPTR %0
     %6(s64) = G_PTRTOINT %5
 
@@ -55,32 +55,32 @@ body: |
 
   bb.1.next:
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %7(s1) = G_TRUNC [[RES]](s32)
+    ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
+    ; CHECK: %7:_(s1) = G_TRUNC [[RES]](s32)
     %7(s1) = G_SELECT %1, %1, %1
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %8(s8) = G_TRUNC [[RES]](s32)
+    ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
+    ; CHECK: %8:_(s8) = G_TRUNC [[RES]](s32)
     %8(s8) = G_SELECT %1, %2, %2
 
-    ; CHECK: [[LHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RHS:%[0-9]+]](s32) = G_TRUNC %0
-    ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
-    ; CHECK: %9(s16) = G_TRUNC [[RES]](s32)
+    ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
+    ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
+    ; CHECK: %9:_(s16) = G_TRUNC [[RES]](s32)
     %9(s16) = G_SELECT %1, %3, %3
 
     %10(s32) = G_SELECT %1, %4, %4
     %11(s64) = G_SELECT %1, %0, %0
 
-    ; CHECK: %12(<2 x s32>) = G_BITCAST %0
-    ; CHECK: %13(s64) = G_BITCAST %12
-    ; CHECK: %14(s32) = G_BITCAST %10
-    ; CHECK: %15(<4 x s8>) = G_BITCAST %0
-    ; CHECK: %16(<2 x s16>) = G_BITCAST %0
+    ; CHECK: %12:_(<2 x s32>) = G_BITCAST %0
+    ; CHECK: %13:_(s64) = G_BITCAST %12
+    ; CHECK: %14:_(s32) = G_BITCAST %10
+    ; CHECK: %15:_(<4 x s8>) = G_BITCAST %0
+    ; CHECK: %16:_(<2 x s16>) = G_BITCAST %0
     %12(<2 x s32>) = G_BITCAST %0
     %13(s64) = G_BITCAST %12
     %14(s32) = G_BITCAST %10
@@ -101,7 +101,7 @@ body:             |
     liveins: %x0, %x1
     ; CHECK-LABEL: bitcast128
     ; This is legal and shouldn't be changed.
-    ; CHECK: %2(<2 x s64>) = G_BITCAST %3(s128)
+    ; CHECK: %2:_(<2 x s64>) = G_BITCAST %3(s128)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
     %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
index 6b77419eef2..b1cf197e1e8 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
@@ -24,13 +24,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_sub_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[SUB:%[0-9]+]](s32) = G_SUB [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[SUB]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir b/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
index cb4f739b97e..9b59104eb36 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
@@ -7,10 +7,10 @@ registers:
 body: |
   bb.0.entry:
     liveins:
-    ; CHECK-LABEL: name: test_implicit_def
-    ; CHECK: [[DEF:%[0-9]+]](s64) = G_IMPLICIT_DEF
-    ; CHECK: [[DEF1:%[0-9]+]](s64) = G_IMPLICIT_DEF
-    ; CHECK: [[MV:%[0-9]+]](s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
 
+    ; CHECK-LABEL: name: test_implicit_def
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
     %0:_(s128) = G_IMPLICIT_DEF
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
index 8bda08d0a1d..30e81ad3228 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
@@ -13,27 +13,27 @@ body: |
     %0:_(p0) = COPY %x0
 
     ; CHECK-LABEL: name: test_vaarg
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %1(s8) = G_LOAD [[LIST]](p0) :: (load 1, align 8)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
+    ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
+    ; CHECK: %1:_(s8) = G_LOAD [[LIST]](p0) :: (load 1, align 8)
+    ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
     ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %1:_(s8) = G_VAARG %0(p0), 1
 
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %2(s64) = G_LOAD [[LIST]](p0) :: (load 8)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
+    ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
+    ; CHECK: %2:_(s64) = G_LOAD [[LIST]](p0) :: (load 8)
+    ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
     ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %2:_(s64) = G_VAARG %0(p0), 8
 
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: [[ALIGNM1:%[0-9]+]](s64) = G_CONSTANT i64 15
-    ; CHECK: [[ALIGNTMP:%[0-9]+]](p0) = G_GEP [[LIST]], [[ALIGNM1]](s64)
-    ; CHECK: [[LIST:%[0-9]+]](p0) = G_PTR_MASK [[ALIGNTMP]], 4
-    ; CHECK: %3(s64) = G_LOAD [[LIST]](p0) :: (load 8, align 16)
-    ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8
-    ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
+    ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
+    ; CHECK: [[ALIGNM1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+    ; CHECK: [[ALIGNTMP:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[ALIGNM1]](s64)
+    ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALIGNTMP]], 4
+    ; CHECK: %3:_(s64) = G_LOAD [[LIST]](p0) :: (load 8, align 16)
+    ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+    ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
     ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
     %3:_(s64) = G_VAARG %0(p0), 16
 ...
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 3c397527815..9f4a6c78806 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -24,13 +24,13 @@ body: |
     liveins: %x0, %x1, %x2, %x3
 
     ; CHECK-LABEL: name: test_scalar_xor_small
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %x1
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s32) = G_TRUNC [[COPY1]](s64)
-    ; CHECK: [[XOR:%[0-9]+]](s32) = G_XOR [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s8) = G_TRUNC [[XOR]](s32)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC2]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[XOR]](s32)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
     ; CHECK: %x0 = COPY [[ANYEXT]](s64)
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
diff --git a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
index 8e669320564..997205bc0ef 100644
--- a/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
+++ b/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
@@ -9,16 +9,16 @@
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-apple-ios"
-  
+
   define float @foo(float %arg, i1 %cond) {
     br i1 %cond, label %true, label %false
-  
+
   true:                                             ; preds = %0
     br label %end
-  
+
   false:                                            ; preds = %0
     br label %end
-  
+
   end:                                              ; preds = %false, %true
     %val = phi float [ 1.000000e+00, %true ], [ 2.000000e+00, %false ]
     %res = fadd float %arg, %val
@@ -55,23 +55,23 @@ registers:
 
 # First block remains untouched
 # CHECK: body
-# CHECK:   %4(s32) = G_FCONSTANT float 1.000000e+00
-# CHECK:   %5(s32) = G_FCONSTANT float 2.000000e+00
+# CHECK:   %4:fpr(s32) = G_FCONSTANT float 1.000000e+00
+# CHECK:   %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
 
 # Second block will get the constant 1.0 when the localizer is enabled.
 # CHECK: bb.1.true:
 # OPT-NOT: G_FCONSTANT
-# OPTNONE: [[FONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
 # CHECK: G_BR %bb.3.end
 
 # Thrid block will get the constant 2.0 when the localizer is enabled.
 # CHECK: bb.2.false:
 # OPT-NOT: G_FCONSTANT
-# OPTNONE: [[FTWO:%[0-9]+]](s32) = G_FCONSTANT float 2.000000e+00
+# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
 
 # CHECK: bb.3.end
-# OPTNONE: %2(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
-# OPT: %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
+# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
+# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
 # CHECK-NEXT: G_FADD %0, %2
 body:             |
   bb.0 (%ir-block.0):
@@ -84,12 +84,12 @@ body:             |
     %5(s32) = G_FCONSTANT float 2.000000e+00
     G_BRCOND %1(s1), %bb.1.true
     G_BR %bb.2.false
-  
+
   bb.1.true:
     G_BR %bb.3.end
-  
+
   bb.2.false:
-  
+
   bb.3.end:
     %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
     %3(s32) = G_FADD %0, %2
diff --git a/test/CodeGen/AArch64/GlobalISel/localizer.mir b/test/CodeGen/AArch64/GlobalISel/localizer.mir
index e900e8e5399..5de006a7d3f 100644
--- a/test/CodeGen/AArch64/GlobalISel/localizer.mir
+++ b/test/CodeGen/AArch64/GlobalISel/localizer.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=localizer -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK
 
 # Test the localizer.
@@ -23,11 +24,8 @@ regBankSelected: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: local_use
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT 1
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[C]], [[C]]
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+    ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
     %0:gpr(s32) = G_CONSTANT 1
     %1:gpr(s32) = G_ADD %0, %0
 ...
@@ -38,22 +36,17 @@ legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: non_local_1use
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[ADD]]
 
   ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
   ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 3, class: gpr
 
-  ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD:%[0-9]+]](s32) = G_ADD [[C]], [[C]]
-  ; CHECK: bb.1:
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD1:%[0-9]+]](s32) = G_ADD [[C1]], [[ADD]]
   bb.0:
     successors: %bb.1
 
@@ -70,22 +63,17 @@ legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: non_local_2uses
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
+  ; CHECK: bb.1:
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[C1]], [[C1]]
 
   ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
   ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 3, class: gpr
 
-  ; CHECK: bb.0:
-  ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD:%[0-9]+]](s32) = G_ADD [[C]], [[C]]
-  ; CHECK: bb.1:
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD1:%[0-9]+]](s32) = G_ADD [[C1]], [[C1]]
   bb.0:
     successors: %bb.1
 
@@ -103,26 +91,20 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi_use
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
-  ; CHECK-NEXT: id: 3, class: gpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 4, class: gpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD:%[0-9]+]](s32) = G_ADD [[C]], [[C]]
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
   ; CHECK: bb.2:
-  ; CHECK:   [[PHI:%[0-9]+]](s32) = PHI [[C1]](s32), %bb.1
-  ; CHECK:   [[ADD1:%[0-9]+]](s32) = G_ADD [[PHI]], [[PHI]]
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[PHI]]
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     successors: %bb.1
 
@@ -144,28 +126,21 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi_use_followed_by_use
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
-  ; CHECK-NEXT: id: 3, class: gpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 4, class: gpr
-  ; CHECK-NEXT: id: 5, class: gpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD:%[0-9]+]](s32) = G_ADD [[C]], [[C]]
+  ; CHECK:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_CONSTANT 1
+  ; CHECK:   [[C1:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
   ; CHECK: bb.2:
-  ; CHECK:   [[PHI:%[0-9]+]](s32) = PHI [[C1]](s32), %bb.1
-  ; CHECK:   [[C2:%[0-9]+]](s32) = G_CONSTANT 1
-  ; CHECK:   [[ADD1:%[0-9]+]](s32) = G_ADD [[PHI]], [[C2]]
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[C2]]
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     successors: %bb.1
 
@@ -187,28 +162,21 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi_use_followed_by_use_fi
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
-  ; CHECK-NEXT: id: 3, class: gpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 4, class: gpr
-  ; CHECK-NEXT: id: 5, class: gpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[FRAME_INDEX:%[0-9]+]](s32) = G_FRAME_INDEX 1
-  ; CHECK:   [[ADD:%[0-9]+]](s32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]
+  ; CHECK:   [[FRAME_INDEX:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+  ; CHECK:   [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[FRAME_INDEX]], [[FRAME_INDEX]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]](s32) = G_FRAME_INDEX 1
+  ; CHECK:   [[FRAME_INDEX1:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
   ; CHECK: bb.2:
-  ; CHECK:   [[PHI:%[0-9]+]](s32) = PHI [[FRAME_INDEX1]](s32), %bb.1
-  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]](s32) = G_FRAME_INDEX 1
-  ; CHECK:   [[ADD1:%[0-9]+]](s32) = G_ADD [[PHI]], [[FRAME_INDEX2]]
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(s32) = PHI [[FRAME_INDEX1]](s32), %bb.1
+  ; CHECK:   [[FRAME_INDEX2:%[0-9]+]]:gpr(s32) = G_FRAME_INDEX 1
+  ; CHECK:   [[ADD1:%[0-9]+]]:gpr(s32) = G_ADD [[PHI]], [[FRAME_INDEX2]]
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     successors: %bb.1
 
@@ -230,28 +198,21 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: float_non_local_phi_use_followed_by_use_fi
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: fpr
-  ; CHECK-NEXT: id: 1, class: fpr
-  ; CHECK-NEXT: id: 2, class: fpr
-  ; CHECK-NEXT: id: 3, class: fpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 4, class: fpr
-  ; CHECK-NEXT: id: 5, class: fpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-  ; CHECK:   [[FADD:%[0-9]+]](s32) = G_FADD [[C]], [[C]]
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
   ; CHECK: bb.2:
-  ; CHECK:   [[PHI:%[0-9]+]](s32) = PHI [[C1]](s32), %bb.1
-  ; CHECK:   [[C2:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-  ; CHECK:   [[FADD1:%[0-9]+]](s32) = G_FADD [[PHI]], [[C2]]
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr(s32) = PHI [[C1]](s32), %bb.1
+  ; CHECK:   [[C2:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[C2]]
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     successors: %bb.1
 
@@ -275,26 +236,20 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_phi
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: fpr
-  ; CHECK-NEXT: id: 1, class: fpr
-  ; CHECK-NEXT: id: 2, class: fpr
-  ; CHECK-NEXT: id: 3, class: fpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 4, class: fpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-  ; CHECK:   [[FADD:%[0-9]+]](s32) = G_FADD [[C]], [[C]]
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[PHI:%[0-9]+]](s32) = PHI [[FADD]](s32), %bb.0, %4(s32), %bb.1
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-  ; CHECK:   [[FADD1:%[0-9]+]](s32) = G_FADD [[PHI]], [[FADD]]
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr(s32) = PHI [[FADD]](s32), %bb.0, %4(s32), %bb.1
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[FADD]]
   ; CHECK:   G_BR %bb.1
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     successors: %bb.1
 
@@ -317,26 +272,21 @@ regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: non_local_label
-
-  ; Existing registers should be left untouched
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: fpr
-  ; CHECK-NEXT: id: 1, class: fpr
-  ; CHECK-NEXT: id: 2, class: fpr
-  ; The newly created reg should be on the same regbank/regclass as its origin.
-  ; CHECK-NEXT: id: 3, class: fpr
-
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   liveins: %s0
-  ; CHECK:   [[COPY:%[0-9]+]](s32) = COPY %s0
-  ; CHECK:   [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+  ; CHECK:   [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   EH_LABEL 1
-  ; CHECK:   [[C1:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-  ; CHECK:   [[FADD:%[0-9]+]](s32) = G_FADD [[COPY]], [[C1]]
+  ; CHECK:   [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
+  ; CHECK:   [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[C1]]
   ; CHECK:   G_BR %bb.1
+
+  ; Existing registers should be left untouched
+  ; The newly created reg should be on the same regbank/regclass as its origin.
+
   bb.0:
     liveins: %s0
     successors: %bb.1
diff --git a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
index b54a57daa3c..d4d23142ab9 100644
--- a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
+++ b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir
@@ -22,7 +22,7 @@ body:             |
     liveins: %w0
     ; CHECK-LABEL: name: unused_reg
     ; CHECK: liveins: %w0
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
     ; CHECK: %w0 = COPY [[COPY]]
     %0:gpr(s32) = COPY %w0
     %1:gpr(s32) = G_MERGE_VALUES %0(s32)
diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
index 62f04195580..df40a7f659a 100644
--- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -82,11 +82,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_add_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_ADD %0, %0
 ...
@@ -101,11 +98,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_add_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[ADD:%[0-9]+]](<4 x s32>) = G_ADD [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[ADD:%[0-9]+]]:fpr(<4 x s32>) = G_ADD [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_ADD %0, %0
 ...
@@ -120,11 +114,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sub_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SUB:%[0-9]+]](s32) = G_SUB [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SUB:%[0-9]+]]:gpr(s32) = G_SUB [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SUB %0, %0
 ...
@@ -139,11 +130,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_sub_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[SUB:%[0-9]+]](<4 x s32>) = G_SUB [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[SUB:%[0-9]+]]:fpr(<4 x s32>) = G_SUB [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SUB %0, %0
 ...
@@ -158,11 +146,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_mul_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[MUL:%[0-9]+]]:gpr(s32) = G_MUL [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_MUL %0, %0
 ...
@@ -177,11 +162,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_mul_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[MUL:%[0-9]+]](<4 x s32>) = G_MUL [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[MUL:%[0-9]+]]:fpr(<4 x s32>) = G_MUL [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_MUL %0, %0
 ...
@@ -196,11 +178,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_and_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_AND %0, %0
 ...
@@ -215,11 +194,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_and_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[AND:%[0-9]+]](<4 x s32>) = G_AND [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[AND:%[0-9]+]]:fpr(<4 x s32>) = G_AND [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_AND %0, %0
 ...
@@ -234,11 +210,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_or_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[OR:%[0-9]+]]:gpr(s32) = G_OR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_OR %0, %0
 ...
@@ -253,11 +226,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_or_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[OR:%[0-9]+]](<4 x s32>) = G_OR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[OR:%[0-9]+]]:fpr(<4 x s32>) = G_OR [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_OR %0, %0
 ...
@@ -272,11 +242,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_xor_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[XOR:%[0-9]+]](s32) = G_XOR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[XOR:%[0-9]+]]:gpr(s32) = G_XOR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_XOR %0, %0
 ...
@@ -291,11 +258,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_xor_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[XOR:%[0-9]+]](<4 x s32>) = G_XOR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[XOR:%[0-9]+]]:fpr(<4 x s32>) = G_XOR [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_XOR %0, %0
 ...
@@ -310,11 +274,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_shl_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SHL:%[0-9]+]]:gpr(s32) = G_SHL [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SHL %0, %0
 ...
@@ -329,11 +290,8 @@ body: |
   bb.0:
     liveins: %q0
     ; CHECK-LABEL: name: test_shl_v4s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0
-    ; CHECK: [[SHL:%[0-9]+]](<4 x s32>) = G_SHL [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY %q0
+    ; CHECK: [[SHL:%[0-9]+]]:fpr(<4 x s32>) = G_SHL [[COPY]], [[COPY]]
     %0(<4 x s32>) = COPY %q0
     %1(<4 x s32>) = G_SHL %0, %0
 ...
@@ -348,11 +306,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_lshr_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[LSHR:%[0-9]+]](s32) = G_LSHR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[LSHR:%[0-9]+]]:gpr(s32) = G_LSHR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_LSHR %0, %0
 ...
@@ -367,11 +322,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_ashr_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ASHR:%[0-9]+]]:gpr(s32) = G_ASHR [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_ASHR %0, %0
 ...
@@ -386,11 +338,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sdiv_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SDIV:%[0-9]+]](s32) = G_SDIV [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SDIV:%[0-9]+]]:gpr(s32) = G_SDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_SDIV %0, %0
 ...
@@ -405,11 +354,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_udiv_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[UDIV:%[0-9]+]](s32) = G_UDIV [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[UDIV:%[0-9]+]]:gpr(s32) = G_UDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_UDIV %0, %0
 ...
@@ -424,11 +370,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_anyext_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ANYEXT:%[0-9]+]]:gpr(s64) = G_ANYEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
 ...
@@ -443,11 +386,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sext_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SEXT:%[0-9]+]]:gpr(s64) = G_SEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
 ...
@@ -462,11 +402,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_zext_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ZEXT:%[0-9]+]]:gpr(s64) = G_ZEXT [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
 ...
@@ -481,11 +418,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_trunc_s32_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s32) = G_TRUNC [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
 ...
@@ -498,9 +432,7 @@ registers:
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_constant_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT 123
+    ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT 123
     %0(s32) = G_CONSTANT 123
 ...
 
@@ -512,9 +444,7 @@ registers:
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_constant_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK: [[C:%[0-9]+]](p0) = G_CONSTANT 0
+    ; CHECK: [[C:%[0-9]+]]:gpr(p0) = G_CONSTANT 0
     %0(p0) = G_CONSTANT 0
 ...
 
@@ -529,13 +459,9 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_icmp_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY]]
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
     %0(s32) = COPY %w0
     %1(s32) = G_ICMP intpred(ne), %0, %0
     %2(s1) = G_TRUNC %1(s32)
@@ -552,13 +478,9 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_icmp_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY]]
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[ICMP:%[0-9]+]]:gpr(s32) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s32)
     %0(p0) = COPY %x0
     %1(s32) = G_ICMP intpred(ne), %0, %0
     %2(s1) = G_TRUNC %1(s32)
@@ -574,9 +496,7 @@ stack:
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_frame_index_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK: [[FRAME_INDEX:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr0
+    ; CHECK: [[FRAME_INDEX:%[0-9]+]]:gpr(p0) = G_FRAME_INDEX %stack.0.ptr0
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
 ...
 
@@ -590,11 +510,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_ptrtoint_s64_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[PTRTOINT:%[0-9]+]](s64) = G_PTRTOINT [[COPY]](p0)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:gpr(s64) = G_PTRTOINT [[COPY]](p0)
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
 ...
@@ -609,11 +526,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_inttoptr_p0_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[INTTOPTR:%[0-9]+]](p0) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:gpr(p0) = G_INTTOPTR [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
 ...
@@ -628,11 +542,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_load_s32_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[LOAD:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: (load 4)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4)
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD %0 :: (load 4)
 ...
@@ -647,11 +558,8 @@ body: |
   bb.0:
     liveins: %x0, %w1
     ; CHECK-LABEL: name: test_store_s32_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s32) = COPY %w1
     ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store 4)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
@@ -668,11 +576,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fadd_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FADD:%[0-9]+]](s32) = G_FADD [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FADD %0, %0
 ...
@@ -687,11 +592,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fsub_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FSUB:%[0-9]+]]:fpr(s32) = G_FSUB [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FSUB %0, %0
 ...
@@ -706,11 +608,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fmul_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FMUL:%[0-9]+]]:fpr(s32) = G_FMUL [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FMUL %0, %0
 ...
@@ -725,11 +624,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fdiv_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FDIV:%[0-9]+]](s32) = G_FDIV [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FDIV:%[0-9]+]]:fpr(s32) = G_FDIV [[COPY]], [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_FDIV %0, %0
 ...
@@ -744,11 +640,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fpext_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FPEXT:%[0-9]+]](s64) = G_FPEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FPEXT:%[0-9]+]]:fpr(s64) = G_FPEXT [[COPY]](s32)
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
 ...
@@ -763,11 +656,8 @@ body: |
   bb.0:
     liveins: %d0
     ; CHECK-LABEL: name: test_fptrunc_s32_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0
-    ; CHECK: [[FPTRUNC:%[0-9]+]](s32) = G_FPTRUNC [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
+    ; CHECK: [[FPTRUNC:%[0-9]+]]:fpr(s32) = G_FPTRUNC [[COPY]](s64)
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
 ...
@@ -780,9 +670,7 @@ registers:
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_fconstant_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
     %0(s32) = G_FCONSTANT float 1.0
 ...
 
@@ -797,13 +685,9 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fcmp_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FCMP:%[0-9]+]](s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY]]
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FCMP]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[FCMP]](s32)
     %0(s32) = COPY %s0
     %1(s32) = G_FCMP floatpred(olt), %0, %0
     %2(s1) = G_TRUNC %1(s32)
@@ -819,11 +703,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_sitofp_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0
-    ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %w0
+    ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s64) = G_SITOFP [[COPY]](s32)
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
 ...
@@ -838,11 +719,8 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_uitofp_s32_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: fpr
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0
-    ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY %x0
+    ; CHECK: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[COPY]](s64)
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
 ...
@@ -857,11 +735,8 @@ body: |
   bb.0:
     liveins: %s0
     ; CHECK-LABEL: name: test_fptosi_s64_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0
-    ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %s0
+    ; CHECK: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[COPY]](s32)
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
 ...
@@ -876,11 +751,8 @@ body: |
   bb.0:
     liveins: %d0
     ; CHECK-LABEL: name: test_fptoui_s32_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0
-    ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64)
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %d0
+    ; CHECK: [[FPTOUI:%[0-9]+]]:gpr(s32) = G_FPTOUI [[COPY]](s64)
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
 ...
@@ -898,26 +770,19 @@ registers:
   - { id: 5, class: _, preferred-register: '' }
 body:             |
   ; CHECK-LABEL: name: test_gphi_ptr
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr
-  ; CHECK-NEXT: id: 3, class: gpr
-  ; CHECK-NEXT: id: 4, class: gpr
-  ; CHECK-NEXT: id: 5, class: _
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: %w2, %x0, %x1
-  ; CHECK:   [[COPY:%[0-9]+]](p0) = COPY %x0
-  ; CHECK:   [[COPY1:%[0-9]+]](p0) = COPY %x1
-  ; CHECK:   [[COPY2:%[0-9]+]](s32) = COPY %w2
-  ; CHECK:   [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY2]](s32)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr(p0) = COPY %x0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr(p0) = COPY %x1
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr(s32) = COPY %w2
+  ; CHECK:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY2]](s32)
   ; CHECK:   G_BRCOND [[TRUNC]](s1), %bb.1
   ; CHECK:   G_BR %bb.2
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK: bb.2:
-  ; CHECK:   [[PHI:%[0-9]+]](p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
   ; CHECK:   %x0 = COPY [[PHI]](p0)
   ; CHECK:   RET_ReallyLR implicit %x0
   bb.0:
diff --git a/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index 78d34bf5655..1badcf35492 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -73,13 +73,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: add_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[ADDWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -103,13 +99,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: add_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[ADDXrr:%[0-9]+]] = ADDXrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[ADDXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -132,12 +124,8 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: add_imm_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr32sp
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[ADDWri:%[0-9]+]] = ADDWri [[COPY]], 1, 0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
+    ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
     ; CHECK: %w0 = COPY [[ADDWri]]
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 1
@@ -160,12 +148,8 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: add_imm_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr64sp
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[ADDXri:%[0-9]+]] = ADDXri [[COPY]], 1, 0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0
     ; CHECK: %x0 = COPY [[ADDXri]]
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i32 1
@@ -185,16 +169,12 @@ registers:
 
 body:             |
   ; CHECK-LABEL: name: add_imm_s32_gpr_bb
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr32sp
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr32sp
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   [[COPY:%[0-9]+]] = COPY %w0
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY %w0
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
-  ; CHECK:   [[ADDWri:%[0-9]+]] = ADDWri [[COPY]], 1, 0
+  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0
   ; CHECK:   %w0 = COPY [[ADDWri]]
   bb.0:
     liveins: %w0, %w1
@@ -225,13 +205,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: sub_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[SUBSWrr:%[0-9]+]] = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv
     ; CHECK: %w0 = COPY [[SUBSWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -255,13 +231,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: sub_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[SUBSXrr:%[0-9]+]] = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv
     ; CHECK: %x0 = COPY [[SUBSXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -285,13 +257,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: or_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[ORRWrr:%[0-9]+]] = ORRWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[ORRWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -315,13 +283,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: or_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[ORRXrr:%[0-9]+]] = ORRXrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[ORRXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -347,13 +311,9 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: or_v2s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[ORRv8i8_:%[0-9]+]] = ORRv8i8 [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]]
     ; CHECK: %d0 = COPY [[ORRv8i8_]]
       %0(<2 x s32>) = COPY %d0
       %1(<2 x s32>) = COPY %d1
@@ -377,13 +337,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: and_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[ANDWrr:%[0-9]+]] = ANDWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[ANDWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -407,13 +363,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: and_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[ANDXrr:%[0-9]+]] = ANDXrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[ANDXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -437,13 +389,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: shl_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[LSLVWr:%[0-9]+]] = LSLVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[LSLVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -467,13 +415,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: shl_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[LSLVXr:%[0-9]+]] = LSLVXr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[LSLVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -497,13 +441,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: lshr_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[LSRVWr:%[0-9]+]] = LSRVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[LSRVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -527,13 +467,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: lshr_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[LSRVXr:%[0-9]+]] = LSRVXr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[LSRVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -557,13 +493,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: ashr_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[ASRVWr:%[0-9]+]] = ASRVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[ASRVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -587,13 +519,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: ashr_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[ASRVXr:%[0-9]+]] = ASRVXr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[ASRVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -618,13 +546,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: mul_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[MADDWrrr:%[0-9]+]] = MADDWrrr [[COPY]], [[COPY1]], %wzr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], %wzr
     ; CHECK: %w0 = COPY [[MADDWrrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -648,13 +572,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: mul_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[MADDXrrr:%[0-9]+]] = MADDXrrr [[COPY]], [[COPY1]], %xzr
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], %xzr
     ; CHECK: %x0 = COPY [[MADDXrrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -674,15 +594,10 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: mulh_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK-NEXT: id: 3, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[SMULHrr:%[0-9]+]] = SMULHrr [[COPY]], [[COPY1]]
-    ; CHECK: [[UMULHrr:%[0-9]+]] = UMULHrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]]
+    ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[SMULHrr]]
     ; CHECK: %x0 = COPY [[UMULHrr]]
     %0:gpr(s64) = COPY %x0
@@ -709,13 +624,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: sdiv_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[SDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -739,13 +650,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: sdiv_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[SDIVXr:%[0-9]+]] = SDIVXr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[SDIVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -769,13 +676,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: udiv_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[UDIVWr:%[0-9]+]] = UDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[UDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -799,13 +702,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: udiv_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[UDIVXr:%[0-9]+]] = UDIVXr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[UDIVXr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -829,13 +728,9 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: fadd_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[FADDSrr:%[0-9]+]] = FADDSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
     ; CHECK: %s0 = COPY [[FADDSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
@@ -858,13 +753,9 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: fadd_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[FADDDrr:%[0-9]+]] = FADDDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
     ; CHECK: %d0 = COPY [[FADDDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
@@ -887,13 +778,9 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: fsub_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[FSUBSrr:%[0-9]+]] = FSUBSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
     ; CHECK: %s0 = COPY [[FSUBSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
@@ -916,13 +803,9 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: fsub_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[FSUBDrr:%[0-9]+]] = FSUBDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
     ; CHECK: %d0 = COPY [[FSUBDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
@@ -945,13 +828,9 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: fmul_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[FMULSrr:%[0-9]+]] = FMULSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
     ; CHECK: %s0 = COPY [[FMULSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
@@ -974,13 +853,9 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: fmul_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[FMULDrr:%[0-9]+]] = FMULDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
     ; CHECK: %d0 = COPY [[FMULDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
@@ -1003,13 +878,9 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: fdiv_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[FDIVSrr:%[0-9]+]] = FDIVSrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
+    ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
     ; CHECK: %s0 = COPY [[FDIVSrr]]
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
@@ -1032,13 +903,9 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: fdiv_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[FDIVDrr:%[0-9]+]] = FDIVDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
     ; CHECK: %d0 = COPY [[FDIVDrr]]
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
index c19d0d4b187..e323aa310d5 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
@@ -29,11 +29,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32all
-    ; CHECK-NEXT: id: 1, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
@@ -54,11 +51,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: %s0 = COPY [[COPY1]]
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
@@ -79,11 +73,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32all
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: %s0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
@@ -104,11 +95,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
@@ -129,11 +117,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: bitcast_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64all
-    ; CHECK-NEXT: id: 1, class: gpr64all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
@@ -154,11 +139,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: %d0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
@@ -178,11 +160,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: bitcast_s64_gpr_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64all
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: %d0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
@@ -203,11 +182,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_fpr_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
@@ -228,11 +204,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_v2f32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(<2 x s32>) = G_BITCAST %0
@@ -253,11 +226,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_v8i8_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %d0
     %1(<8 x s8>) = G_BITCAST %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-br.mir b/test/CodeGen/AArch64/GlobalISel/select-br.mir
index cd4985505c7..0d6108fe322 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-br.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-br.mir
@@ -61,7 +61,7 @@ registers:
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    BR %0
 body:             |
   bb.0:
diff --git a/test/CodeGen/AArch64/GlobalISel/select-bswap.mir b/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
index d1118b64c52..17394fe86d2 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
@@ -22,11 +22,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: bswap_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[REVWr:%[0-9]+]] = REVWr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[REVWr:%[0-9]+]]:gpr32 = REVWr [[COPY]]
     ; CHECK: %w0 = COPY [[REVWr]]
     %0(s32) = COPY %w0
     %1(s32) = G_BSWAP %0
@@ -47,11 +44,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: bswap_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[REVXr:%[0-9]+]] = REVXr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[REVXr:%[0-9]+]]:gpr64 = REVXr [[COPY]]
     ; CHECK: %x0 = COPY [[REVXr]]
     %0(s64) = COPY %x0
     %1(s64) = G_BSWAP %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
index e13fa1e021d..f8f0126bdc3 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
@@ -15,7 +15,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %0:gpr32 = COPY %w0
 # CHECK:    CBZW %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -41,7 +41,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    CBZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -67,7 +67,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %0:gpr32 = COPY %w0
 # CHECK:    CBNZW %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
@@ -93,7 +93,7 @@ regBankSelected: true
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    %0 = COPY %x0
+# CHECK:    %0:gpr64 = COPY %x0
 # CHECK:    CBNZX %0, %bb.1
 # CHECK:    B %bb.0
 body:             |
diff --git a/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
index 37c1b89db65..fbe2ef1f2c8 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -23,7 +23,7 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: const_s32
-    ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 42
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
     ; CHECK: %w0 = COPY [[MOVi32imm]]
     %0(s32) = G_CONSTANT i32 42
     %w0 = COPY %0(s32)
@@ -39,7 +39,7 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: const_s64
-    ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234567890123
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234567890123
     ; CHECK: %x0 = COPY [[MOVi64imm]]
     %0(s64) = G_CONSTANT i64 1234567890123
     %x0 = COPY %0(s64)
@@ -55,8 +55,8 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fconst_s32
-    ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1080033280
-    ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi32imm]]
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1080033280
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
     ; CHECK: %s0 = COPY [[COPY]]
     %0(s32) = G_FCONSTANT float 3.5
     %s0 = COPY %0(s32)
@@ -72,8 +72,8 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fconst_s64
-    ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 4607182418800017408
-    ; CHECK: [[COPY:%[0-9]+]] = COPY [[MOVi64imm]]
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 4607182418800017408
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVi64imm]]
     ; CHECK: %d0 = COPY [[COPY]]
     %0(s64) = G_FCONSTANT double 1.0
     %d0 = COPY %0(s64)
@@ -89,7 +89,7 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fconst_s32_0
-    ; CHECK: [[FMOVS0_:%[0-9]+]] = FMOVS0
+    ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK: %s0 = COPY [[FMOVS0_]]
     %0(s32) = G_FCONSTANT float 0.0
     %s0 = COPY %0(s32)
@@ -105,7 +105,7 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: fconst_s64_0
-    ; CHECK: [[FMOVD0_:%[0-9]+]] = FMOVD0
+    ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
     ; CHECK: %x0 = COPY [[FMOVD0_]]
     %0(s64) = G_FCONSTANT double 0.0
     %x0 = COPY %0(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
index 8d8ecdd46b3..af83be5c075 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
@@ -43,8 +43,8 @@ body: |
   bb.0:
     liveins: %w0
     ; CHECK-LABEL: name: test_dbg_value
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[COPY]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
     ; CHECK: %w0 = COPY [[ADDWrr]]
     ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9
     %0:gpr(s32) = COPY %w0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/test/CodeGen/AArch64/GlobalISel/select-fma.mir
index 5013a7b3367..3e8743c3ce8 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-fma.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-fma.mir
@@ -23,15 +23,10 @@ body:             |
     liveins: %w0, %w1, %w2
 
     ; CHECK-LABEL: name: FMADDSrrr_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: fpr32
-    ; CHECK-NEXT: id: 3, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY %w2
-    ; CHECK: [[FMADDSrrr:%[0-9]+]] = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY %w2
+    ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
     ; CHECK: %w0 = COPY [[FMADDSrrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -39,4 +34,3 @@ body:             |
     %3(s32) = G_FMA %0, %1, %2
     %w0 = COPY %3
 ...
-
diff --git a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index f3c81e7d9c1..a163ba1db32 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -47,11 +47,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: fptrunc_s16_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTHSr:%[0-9]+]] = FCVTHSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
     ; CHECK: %h0 = COPY [[FCVTHSr]]
     %0(s32) = COPY %s0
     %1(s16) = G_FPTRUNC %0
@@ -72,11 +69,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptrunc_s16_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTHDr:%[0-9]+]] = FCVTHDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
     ; CHECK: %h0 = COPY [[FCVTHDr]]
     %0(s64) = COPY %d0
     %1(s16) = G_FPTRUNC %0
@@ -97,11 +91,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptrunc_s32_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTSDr:%[0-9]+]] = FCVTSDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
     ; CHECK: %s0 = COPY [[FCVTSDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTRUNC %0
@@ -122,11 +113,8 @@ body:             |
     liveins: %h0
 
     ; CHECK-LABEL: name: fpext_s32_s16_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr16
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %h0
-    ; CHECK: [[FCVTSHr:%[0-9]+]] = FCVTSHr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
     ; CHECK: %s0 = COPY [[FCVTSHr]]
     %0(s16) = COPY %h0
     %1(s32) = G_FPEXT %0
@@ -147,11 +135,8 @@ body:             |
     liveins: %h0
 
     ; CHECK-LABEL: name: fpext_s64_s16_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr16
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %h0
-    ; CHECK: [[FCVTDHr:%[0-9]+]] = FCVTDHr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY %h0
+    ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
     ; CHECK: %d0 = COPY [[FCVTDHr]]
     %0(s16) = COPY %h0
     %1(s64) = G_FPEXT %0
@@ -172,11 +157,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fpext_s64_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTDSr:%[0-9]+]] = FCVTDSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
     ; CHECK: %d0 = COPY [[FCVTDSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPEXT %0
@@ -197,11 +179,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sitofp_s32_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[SCVTFUWSri:%[0-9]+]] = SCVTFUWSri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
     ; CHECK: %s0 = COPY [[SCVTFUWSri]]
     %0(s32) = COPY %w0
     %1(s32) = G_SITOFP %0
@@ -222,11 +201,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: sitofp_s32_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[SCVTFUXSri:%[0-9]+]] = SCVTFUXSri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
     ; CHECK: %s0 = COPY [[SCVTFUXSri]]
     %0(s64) = COPY %x0
     %1(s32) = G_SITOFP %0
@@ -247,11 +223,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sitofp_s64_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[SCVTFUWDri:%[0-9]+]] = SCVTFUWDri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
     ; CHECK: %d0 = COPY [[SCVTFUWDri]]
     %0(s32) = COPY %w0
     %1(s64) = G_SITOFP %0
@@ -272,11 +245,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: sitofp_s64_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[SCVTFUXDri:%[0-9]+]] = SCVTFUXDri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
     ; CHECK: %d0 = COPY [[SCVTFUXDri]]
     %0(s64) = COPY %x0
     %1(s64) = G_SITOFP %0
@@ -297,11 +267,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: uitofp_s32_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[UCVTFUWSri:%[0-9]+]] = UCVTFUWSri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
     ; CHECK: %s0 = COPY [[UCVTFUWSri]]
     %0(s32) = COPY %w0
     %1(s32) = G_UITOFP %0
@@ -322,11 +289,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: uitofp_s32_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[UCVTFUXSri:%[0-9]+]] = UCVTFUXSri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
     ; CHECK: %s0 = COPY [[UCVTFUXSri]]
     %0(s64) = COPY %x0
     %1(s32) = G_UITOFP %0
@@ -347,11 +311,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: uitofp_s64_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[UCVTFUWDri:%[0-9]+]] = UCVTFUWDri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
     ; CHECK: %d0 = COPY [[UCVTFUWDri]]
     %0(s32) = COPY %w0
     %1(s64) = G_UITOFP %0
@@ -372,11 +333,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: uitofp_s64_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[UCVTFUXDri:%[0-9]+]] = UCVTFUXDri [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
     ; CHECK: %d0 = COPY [[UCVTFUXDri]]
     %0(s64) = COPY %x0
     %1(s64) = G_UITOFP %0
@@ -397,11 +355,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: fptosi_s32_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTZSUWSr:%[0-9]+]] = FCVTZSUWSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
     ; CHECK: %w0 = COPY [[FCVTZSUWSr]]
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOSI %0
@@ -422,11 +377,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptosi_s32_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTZSUWDr:%[0-9]+]] = FCVTZSUWDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
     ; CHECK: %w0 = COPY [[FCVTZSUWDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOSI %0
@@ -447,11 +399,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: fptosi_s64_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTZSUXSr:%[0-9]+]] = FCVTZSUXSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
     ; CHECK: %x0 = COPY [[FCVTZSUXSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOSI %0
@@ -472,11 +421,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptosi_s64_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTZSUXDr:%[0-9]+]] = FCVTZSUXDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
     ; CHECK: %x0 = COPY [[FCVTZSUXDr]]
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOSI %0
@@ -497,11 +443,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: fptoui_s32_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTZUUWSr:%[0-9]+]] = FCVTZUUWSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
     ; CHECK: %w0 = COPY [[FCVTZUUWSr]]
     %0(s32) = COPY %s0
     %1(s32) = G_FPTOUI %0
@@ -522,11 +465,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptoui_s32_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTZUUWDr:%[0-9]+]] = FCVTZUUWDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
     ; CHECK: %w0 = COPY [[FCVTZUUWDr]]
     %0(s64) = COPY %d0
     %1(s32) = G_FPTOUI %0
@@ -547,11 +487,8 @@ body:             |
     liveins: %s0
 
     ; CHECK-LABEL: name: fptoui_s64_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr32
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[FCVTZUUXSr:%[0-9]+]] = FCVTZUUXSr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
+    ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
     ; CHECK: %x0 = COPY [[FCVTZUUXSr]]
     %0(s32) = COPY %s0
     %1(s64) = G_FPTOUI %0
@@ -572,11 +509,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: fptoui_s64_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[FCVTZUUXDr:%[0-9]+]] = FCVTZUUXDr [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
     ; CHECK: %x0 = COPY [[FCVTZUUXDr]]
     %0(s64) = COPY %d0
     %1(s64) = G_FPTOUI %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/test/CodeGen/AArch64/GlobalISel/select-imm.mir
index 9dc969927fc..28fb4b39653 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -23,9 +23,7 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: imm_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm -1234
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1234
     ; CHECK: %w0 = COPY [[MOVi32imm]]
     %0(s32) = G_CONSTANT i32 -1234
     %w0 = COPY %0(s32)
@@ -45,9 +43,7 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: imm_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 1234
     ; CHECK: %x0 = COPY [[MOVi64imm]]
     %0(s64) = G_CONSTANT i64 1234
     %x0 = COPY %0(s64)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
index e2744e99d15..7b65fe3bf7d 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir
@@ -18,11 +18,8 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: implicit_def
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+    ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[DEF]], [[DEF]]
     ; CHECK: %w0 = COPY [[ADDWrr]]
     %0(s32) = G_IMPLICIT_DEF
     %1(s32) = G_ADD %0, %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
index e88e151bd24..c7b7ec9b6fe 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
@@ -15,12 +15,12 @@ body:             |
     %1:gpr(s64) = G_IMPLICIT_DEF
 
     ; CHECK:  body:
-    ; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
-    ; CHECK: %2 = BFMXri %1, [[TMP]], 0, 31
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15
+    ; CHECK: %2:gpr64 = BFMXri %1, [[TMP]], 0, 31
     %2:gpr(s64) = G_INSERT %1, %0, 0
 
-    ; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
-    ; CHECK: %3 = BFMXri %1, [[TMP]], 51, 31
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %0, 15
+    ; CHECK: %3:gpr64 = BFMXri %1, [[TMP]], 51, 31
     %3:gpr(s64) = G_INSERT %1, %0, 13
 
     %x0 = COPY %2
@@ -41,12 +41,12 @@ body:             |
     %0:gpr(s64) = COPY %x0
 
     ; CHECK:  body:
-    ; CHECK: [[TMP:%[0-9]+]] = UBFMXri %0, 0, 31
-    ; CHECK: %1 = COPY [[TMP]].sub_32
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 0, 31
+    ; CHECK: %1:gpr32 = COPY [[TMP]].sub_32
     %1:gpr(s32) = G_EXTRACT %0, 0
 
-    ; CHECK: [[TMP:%[0-9]+]] = UBFMXri %0, 13, 44
-    ; CHECK: %2 = COPY [[TMP]].sub_32
+    ; CHECK: [[TMP:%[0-9]+]]:gpr64 = UBFMXri %0, 13, 44
+    ; CHECK: %2:gpr32 = COPY [[TMP]].sub_32
     %2:gpr(s32) = G_EXTRACT %0, 13
 
     %w0 = COPY %1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
index 8b1da70e096..2c2e475a87a 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -32,13 +32,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: anyext_s64_from_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32all
-    ; CHECK-NEXT: id: 1, class: gpr64all
-    ; CHECK-NEXT: id: 2, class: gpr64all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[SUBREG_TO_REG]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], 15
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
@@ -59,13 +55,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: anyext_s32_from_s8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32all
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
@@ -87,13 +79,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s64_from_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
-    ; CHECK: [[UBFMXri:%[0-9]+]] = UBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15
+    ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
     ; CHECK: %x0 = COPY [[UBFMXri]]
     %0(s32) = COPY %w0
     %1(s64) = G_ZEXT %0
@@ -114,13 +102,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s32_from_s16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
     ; CHECK: %w0 = COPY [[UBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
@@ -142,13 +126,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s32_from_s8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
     ; CHECK: %w0 = COPY [[UBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
@@ -170,15 +150,10 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s16_from_s8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK-NEXT: id: 3, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY1]], 0, 7
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[UBFMWri]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
@@ -201,13 +176,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s64_from_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15
-    ; CHECK: [[SBFMXri:%[0-9]+]] = SBFMXri [[SUBREG_TO_REG]], 0, 31
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], 15
+    ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 31
     ; CHECK: %x0 = COPY [[SBFMXri]]
     %0(s32) = COPY %w0
     %1(s64) = G_SEXT %0
@@ -228,13 +199,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s32_from_s16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 15
     ; CHECK: %w0 = COPY [[SBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
@@ -256,13 +223,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s32_from_s8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
     ; CHECK: %w0 = COPY [[SBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
@@ -284,15 +247,10 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s16_from_s8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK-NEXT: id: 3, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY1]], 0, 7
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[SBFMWri]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
index 13c7b08771f..405634a00aa 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -24,11 +24,8 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: inttoptr_p0_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64all
-    ; CHECK-NEXT: id: 1, class: gpr64all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
@@ -47,11 +44,8 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s64_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
     ; CHECK: %x0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
@@ -70,11 +64,8 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s32_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s32) = G_PTRTOINT %0
@@ -93,13 +84,9 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s16_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s16) = G_PTRTOINT %0
@@ -119,13 +106,9 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s8_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s8) = G_PTRTOINT %0
@@ -145,13 +128,9 @@ body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s1_p0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(p0) = COPY %x0
     %1(s1) = G_PTRTOINT %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
index 7f0fc2cad6f..0387d7ab8ba 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir
@@ -24,13 +24,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: sdiv_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[SDIVWr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-load.mir b/test/CodeGen/AArch64/GlobalISel/select-load.mir
index 3c997e5d623..00f6c9418b7 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -46,11 +46,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr)
     ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
@@ -71,11 +68,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr)
     ; CHECK: %w0 = COPY [[LDRWui]]
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
@@ -96,13 +90,9 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s16_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRHHui]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
@@ -124,13 +114,9 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s8_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRBBui]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
@@ -155,10 +141,7 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_fi_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui %stack.0.ptr0, 0 :: (load 8)
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load 8)
     ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
     %1(s64) = G_LOAD %0 :: (load 8)
@@ -181,13 +164,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_128_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr)
     ; CHECK: %x0 = COPY [[LDRXui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 128
@@ -212,13 +190,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_512_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr)
     ; CHECK: %w0 = COPY [[LDRWui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 512
@@ -243,15 +216,9 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_64_s16_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr32
-    ; CHECK-NEXT: id: 4, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRHHui]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 64
@@ -277,15 +244,9 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_1_s8_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr32
-    ; CHECK-NEXT: id: 4, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[LDRBBui]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 1
@@ -309,11 +270,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
     ; CHECK: %d0 = COPY [[LDRDui]]
     %0(p0) = COPY %x0
     %1(s64) = G_LOAD  %0 :: (load 8 from %ir.addr)
@@ -334,11 +292,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr)
     ; CHECK: %s0 = COPY [[LDRSui]]
     %0(p0) = COPY %x0
     %1(s32) = G_LOAD  %0 :: (load 4 from %ir.addr)
@@ -359,11 +314,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s16_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr)
     ; CHECK: %h0 = COPY [[LDRHui]]
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
@@ -384,11 +336,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_s8_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr8
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr)
     ; CHECK: %b0 = COPY [[LDRBui]]
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
@@ -411,13 +360,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_8_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr)
     ; CHECK: %d0 = COPY [[LDRDui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 8
@@ -442,13 +386,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_16_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr)
     ; CHECK: %s0 = COPY [[LDRSui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 16
@@ -473,13 +412,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_64_s16_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: fpr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr)
     ; CHECK: %h0 = COPY [[LDRHui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 64
@@ -504,13 +438,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_gep_32_s8_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: fpr8
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr)
     ; CHECK: %b0 = COPY [[LDRBui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 32
@@ -532,11 +461,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: load_v2s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr)
     ; CHECK: %d0 = COPY [[LDRDui]]
     %0(p0) = COPY %x0
     %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir b/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
index 119812575c5..0771504032c 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-muladd.mir
@@ -26,18 +26,10 @@ body:             |
     liveins: %x0, %w1, %w2
 
     ; CHECK-LABEL: name: SMADDLrrr_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK-NEXT: id: 4, class: gpr
-    ; CHECK-NEXT: id: 5, class: gpr
-    ; CHECK-NEXT: id: 6, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY %w2
-    ; CHECK: [[SMADDLrrr:%[0-9]+]] = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY %w2
+    ; CHECK: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]]
     ; CHECK: %x0 = COPY [[SMADDLrrr]]
     %0(s64) = COPY %x0
     %1(s32) = COPY %w1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir b/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
index 4c3b069e88a..def06daae0b 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
@@ -23,12 +23,8 @@ body:             |
     liveins: %d0
 
     ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: fpr64
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[UCVTFd:%[0-9]+]] = UCVTFd [[COPY]], 12
+    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
+    ; CHECK: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
     ; CHECK: %d1 = COPY [[UCVTFd]]
     %0(s64) = COPY %d0
     %1(s32) = G_CONSTANT i32 12
diff --git a/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/test/CodeGen/AArch64/GlobalISel/select-phi.mir
index ccc4fcbe3aa..3454ffadcce 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-phi.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-phi.mir
@@ -4,20 +4,20 @@
   source_filename = "/tmp/test.ll"
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-unknown-unknown"
-  
+
   define i32 @test_phi(i32 %argc) {
   entry:
     %cmp = icmp ugt i32 %argc, 0
     br i1 %cmp, label %case1, label %case2
-  
+
   case1:                                            ; preds = %entry
     %tmp1 = add i32 %argc, 1
     br label %return
-  
+
   case2:                                            ; preds = %entry
     %tmp2 = add i32 %argc, 2
     br label %return
-  
+
   return:                                           ; preds = %case2, %case1
     %res = phi i32 [ %tmp1, %case1 ], [ %tmp2, %case2 ]
     ret i32 %res
@@ -37,7 +37,7 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
@@ -47,14 +47,14 @@ registers:
   - { id: 6, class: gpr, preferred-register: '' }
   - { id: 7, class: gpr, preferred-register: '' }
   - { id: 8, class: gpr, preferred-register: '' }
-liveins:         
+liveins:
 body:             |
   bb.1.entry:
     successors: %bb.2.case1(0x40000000), %bb.3.case2(0x40000000)
     liveins: %w0
     ; CHECK-LABEL: name: test_phi
-    ; CHECK: [[RES:%.*]] = PHI
-  
+    ; CHECK: [[RES:%.*]]:gpr32 = PHI
+
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 0
     %3(s32) = G_CONSTANT i32 1
@@ -63,18 +63,18 @@ body:             |
     %2(s1) = G_TRUNC %8(s32)
     G_BRCOND %2(s1), %bb.2.case1
     G_BR %bb.3.case2
-  
+
   bb.2.case1:
     successors: %bb.4.return(0x80000000)
-  
+
     %4(s32) = G_ADD %0, %3
     G_BR %bb.4.return
-  
+
   bb.3.case2:
     successors: %bb.4.return(0x80000000)
-  
+
     %6(s32) = G_ADD %0, %5
-  
+
   bb.4.return:
     %7(s32) = G_PHI %4(s32), %bb.2.case1, %6(s32), %bb.3.case2
     %w0 = COPY %7(s32)
@@ -116,7 +116,7 @@ body:             |
 
 
   bb.2:
-    ; CHECK: %{{[0-9]+}} = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
+    ; CHECK: %{{[0-9]+}}:gpr64 = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
     %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
     %x0 = COPY %3(p0)
     RET_ReallyLR implicit %x0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir b/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
index a35c8bffe5f..5e0ead2dbdb 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
@@ -53,9 +53,9 @@ body:             |
     liveins: %w0
     ; CHECK-LABEL: name: main
     ; CHECK: liveins: %w0
-    ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm 1
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[EONWrr:%[0-9]+]] = EONWrr [[COPY]], [[MOVi32imm]]
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[EONWrr:%[0-9]+]]:gpr32 = EONWrr [[COPY]], [[MOVi32imm]]
     ; CHECK: %w0 = COPY [[EONWrr]]
     %0(s32) = G_CONSTANT i32 -1
     %3(s32) = G_CONSTANT i32 1
diff --git a/test/CodeGen/AArch64/GlobalISel/select-store.mir b/test/CodeGen/AArch64/GlobalISel/select-store.mir
index 95f32c3a408..11710031e21 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -45,11 +45,8 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: store_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
     ; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
@@ -71,11 +68,8 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
     ; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
@@ -97,13 +91,9 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_s16_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
     ; CHECK: STRHHui [[COPY2]], [[COPY]], 0 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
     %2:gpr(s32) = COPY %w1
@@ -126,13 +116,9 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_s8_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
     ; CHECK: STRBBui [[COPY2]], [[COPY]], 0 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
     %2:gpr(s32) = COPY %w1
@@ -155,10 +141,7 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: store_zero_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 0
@@ -180,10 +163,7 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: store_zero_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = G_CONSTANT i32 0
@@ -208,10 +188,7 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: store_fi_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
     ; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8)
     %0(p0) = COPY %x0
     %1(p0) = G_FRAME_INDEX %stack.0.ptr0
@@ -234,13 +211,8 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: store_gep_128_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
     ; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %x1
@@ -265,13 +237,8 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_gep_512_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
     ; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %w1
@@ -296,15 +263,9 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_gep_64_s16_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK-NEXT: id: 4, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
     ; CHECK: STRHHui [[COPY2]], [[COPY]], 32 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
     %4:gpr(s32) = COPY %w1
@@ -330,15 +291,9 @@ body:             |
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_gep_1_s8_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK-NEXT: id: 4, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
     ; CHECK: STRBBui [[COPY2]], [[COPY]], 1 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
     %4:gpr(s32) = COPY %w1
@@ -362,11 +317,8 @@ body:             |
     liveins: %x0, %d1
 
     ; CHECK-LABEL: name: store_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
     ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %d1
@@ -388,11 +340,8 @@ body:             |
     liveins: %x0, %s1
 
     ; CHECK-LABEL: name: store_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
     ; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %s1
@@ -416,13 +365,8 @@ body:             |
     liveins: %x0, %d1
 
     ; CHECK-LABEL: name: store_gep_8_s64_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr64
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
     ; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s64) = COPY %d1
@@ -447,13 +391,8 @@ body:             |
     liveins: %x0, %s1
 
     ; CHECK-LABEL: name: store_gep_8_s32_fpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: fpr32
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gpr
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY %s1
     ; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr)
     %0(p0) = COPY %x0
     %1(s32) = COPY %s1
@@ -462,26 +401,22 @@ body:             |
     G_STORE %1, %3 :: (store 4 into %ir.addr)
 ...
 ---
-# CHECK-LABEL: name: store_v2s32
 name:            store_v2s32
 legalized:       true
 regBankSelected: true
 
-# CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr64sp, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
 
-# CHECK:  body:
-# CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %d1
-# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %d1
 
+    ; CHECK-LABEL: name: store_v2s32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY %d1
+    ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr)
     %0(p0) = COPY %x0
     %1(<2 x s32>) = COPY %d1
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
diff --git a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
index 1b51242230f..421a676f7a4 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -23,11 +23,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: trunc_s32_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64sp
-    ; CHECK-NEXT: id: 1, class: gpr32sp
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
     ; CHECK: %w0 = COPY [[COPY1]]
     %0(s64) = COPY %x0
     %1(s32) = G_TRUNC %0
@@ -48,13 +45,9 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: trunc_s8_s64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(s64) = COPY %x0
     %1(s8) = G_TRUNC %0
@@ -76,13 +69,9 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: trunc_s1_s32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32all
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; CHECK: [[COPY2:%[0-9]+]] = COPY [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
diff --git a/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
index ec6b1e4c8c9..8f0b0dccca6 100644
--- a/test/CodeGen/AArch64/GlobalISel/select-xor.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select-xor.mir
@@ -29,13 +29,9 @@ body:             |
     liveins: %w0, %w1
 
     ; CHECK-LABEL: name: xor_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr32
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1
-    ; CHECK: [[EORWrr:%[0-9]+]] = EORWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
+    ; CHECK: [[EORWrr:%[0-9]+]]:gpr32 = EORWrr [[COPY]], [[COPY1]]
     ; CHECK: %w0 = COPY [[EORWrr]]
     %0(s32) = COPY %w0
     %1(s32) = COPY %w1
@@ -59,13 +55,9 @@ body:             |
     liveins: %x0, %x1
 
     ; CHECK-LABEL: name: xor_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr64
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1
-    ; CHECK: [[EORXrr:%[0-9]+]] = EORXrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY %x1
+    ; CHECK: [[EORXrr:%[0-9]+]]:gpr64 = EORXrr [[COPY]], [[COPY1]]
     ; CHECK: %x0 = COPY [[EORXrr]]
     %0(s64) = COPY %x0
     %1(s64) = COPY %x1
@@ -90,12 +82,8 @@ body:             |
     liveins: %w0
 
     ; CHECK-LABEL: name: xor_constant_n1_s32_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr32
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %w0
-    ; CHECK: [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+    ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
     ; CHECK: %w0 = COPY [[ORNWrr]]
     %0(s32) = COPY %w0
     %1(s32) = G_CONSTANT i32 -1
@@ -119,12 +107,8 @@ body:             |
     liveins: %x0
 
     ; CHECK-LABEL: name: xor_constant_n1_s64_gpr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gpr64
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %x0
-    ; CHECK: [[ORNXrr:%[0-9]+]] = ORNXrr %xzr, [[COPY]]
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[ORNXrr:%[0-9]+]]:gpr64 = ORNXrr %xzr, [[COPY]]
     ; CHECK: %x0 = COPY [[ORNXrr]]
     %0(s64) = COPY %x0
     %1(s64) = G_CONSTANT i64 -1
@@ -146,16 +130,12 @@ registers:
 
 body:             |
   ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb
-  ; CHECK: registers:
-  ; CHECK-NEXT: id: 0, class: gpr32
-  ; CHECK-NEXT: id: 1, class: gpr
-  ; CHECK-NEXT: id: 2, class: gpr32
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
-  ; CHECK:   [[COPY:%[0-9]+]] = COPY %w0
-  ; CHECK:   [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]]
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY %w0
+  ; CHECK:   [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr %wzr, [[COPY]]
   ; CHECK:   %w0 = COPY [[ORNWrr]]
   bb.0:
     liveins: %w0, %w1
diff --git a/test/CodeGen/AArch64/GlobalISel/select.mir b/test/CodeGen/AArch64/GlobalISel/select.mir
index 1c72c3e0b07..c13b27adbb1 100644
--- a/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -43,7 +43,7 @@ stack:
   - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
 
 # CHECK:  body:
-# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
+# CHECK: %0:gpr64sp = ADDXri %stack.0.ptr0, 0, 0
 body:             |
   bb.0:
     %0(p0) = G_FRAME_INDEX %stack.0.ptr0
@@ -61,8 +61,8 @@ registers:
   - { id: 2, class: gpr }
 
 # CHECK:  body:
-# CHECK: %1 = MOVi64imm 42
-# CHECK: %2 = ADDXrr %0, %1
+# CHECK: %1:gpr64 = MOVi64imm 42
+# CHECK: %2:gpr64 = ADDXrr %0, %1
 body:             |
   bb.0:
       liveins: %x0
@@ -79,7 +79,7 @@ legalized:       true
 regBankSelected: true
 
 # CHECK:  body:
-# CHECK: %1 = ANDXri %0, 8060
+# CHECK: %1:gpr64sp = ANDXri %0, 8060
 body:             |
   bb.0:
       liveins: %x0
@@ -98,9 +98,9 @@ registers:
   - { id: 0, class: gpr }
 
 # CHECK:  body:
-# IOS: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_local
+# IOS: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-DEFAULT: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local
+# LINUX-PIC: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_local
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_local
@@ -116,9 +116,9 @@ registers:
   - { id: 0, class: gpr }
 
 # CHECK:  body:
-# IOS: %0 = LOADgot target-flags(aarch64-got) @var_got
-# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
-# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_got
+# IOS: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_got
+# LINUX-DEFAULT: %0:gpr64 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got
+# LINUX-PIC: %0:gpr64 = LOADgot target-flags(aarch64-got) @var_got
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @var_got
@@ -154,13 +154,13 @@ registers:
 
 # CHECK:  body:
 # CHECK:    %wzr = SUBSWrr %0, %0, implicit-def %nzcv
-# CHECK:    %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
+# CHECK:    %1:gpr32 = CSINCWr %wzr, %wzr, 1, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %2, %2, implicit-def %nzcv
-# CHECK:    %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
+# CHECK:    %3:gpr32 = CSINCWr %wzr, %wzr, 3, implicit %nzcv
 
 # CHECK:    %xzr = SUBSXrr %4, %4, implicit-def %nzcv
-# CHECK:    %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
+# CHECK:    %5:gpr32 = CSINCWr %wzr, %wzr, 0, implicit %nzcv
 
 body:             |
   bb.0:
@@ -210,12 +210,12 @@ registers:
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def %nzcv
-# CHECK:    [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv
-# CHECK:    [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv
-# CHECK:    %1 = ORRWrr [[TST_MI]], [[TST_GT]]
+# CHECK:    [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 5, implicit %nzcv
+# CHECK:    [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr %wzr, %wzr, 13, implicit %nzcv
+# CHECK:    %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
 
 # CHECK:    FCMPDrr %2, %2, implicit-def %nzcv
-# CHECK:    %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
+# CHECK:    %3:gpr32 = CSINCWr %wzr, %wzr, 4, implicit %nzcv
 
 body:             |
   bb.0:
@@ -253,7 +253,7 @@ registers:
 
 # CHECK:  body:
 # CHECK:    bb.1:
-# CHECK:      %2 = PHI %0, %bb.0, %2, %bb.1
+# CHECK:      %2:fpr32 = PHI %0, %bb.0, %2, %bb.1
 
 body:             |
   bb.0:
@@ -305,11 +305,11 @@ registers:
 
 # CHECK:  body:
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %3 = CSELWr %1, %2, 1, implicit %nzcv
+# CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %6 = CSELXr %4, %5, 1, implicit %nzcv
+# CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit %nzcv
 # CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
-# CHECK:      %9 = CSELXr %7, %8, 1, implicit %nzcv
+# CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
diff --git a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
index e4c18757418..865315bbe0a 100644
--- a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ b/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -4,9 +4,9 @@
 
 define %type* @first_offset_const(%type* %addr) {
 ; CHECK-LABEL: name: first_offset_const
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[RES:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[RES:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 1
@@ -15,8 +15,8 @@ define %type* @first_offset_const(%type* %addr) {
 
 define %type* @first_offset_trivial(%type* %addr) {
 ; CHECK-LABEL: name: first_offset_trivial
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[TRIVIAL:%[0-9]+]](p0) = COPY [[BASE]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[TRIVIAL:%[0-9]+]]:_(p0) = COPY [[BASE]](p0)
 ; CHECK: %x0 = COPY [[TRIVIAL]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 0
@@ -25,12 +25,12 @@ define %type* @first_offset_trivial(%type* %addr) {
 
 define %type* @first_offset_variable(%type* %addr, i64 %idx) {
 ; CHECK-LABEL: name: first_offset_variable
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[STEP0:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[STEP0]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i64 %idx
@@ -39,13 +39,13 @@ define %type* @first_offset_variable(%type* %addr, i64 %idx) {
 
 define %type* @first_offset_ext(%type* %addr, i32 %idx) {
 ; CHECK-LABEL: name: first_offset_ext
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX32:%[0-9]+]](s32) = COPY %w1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32
-; CHECK: [[IDX64:%[0-9]+]](s64) = G_SEXT [[IDX32]](s32)
-; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX64]]
-; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX32:%[0-9]+]]:_(s32) = COPY %w1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+; CHECK: [[IDX64:%[0-9]+]]:_(s64) = G_SEXT [[IDX32]](s32)
+; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX64]]
+; CHECK: [[STEP0:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[STEP0]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type, %type* %addr, i32 %idx
@@ -55,14 +55,14 @@ define %type* @first_offset_ext(%type* %addr, i32 %idx) {
 %type1 = type [4 x [4 x i32]]
 define i32* @const_then_var(%type1* %addr, i64 %idx) {
 ; CHECK-LABEL: name: const_then_var
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 272
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 4
-; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
-; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
-; CHECK: [[RES:%[0-9]+]](p0) = COPY [[BASE2]](p0)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+; CHECK: [[BASE1:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
+; CHECK: [[OFFSET2:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[BASE2:%[0-9]+]]:_(p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
+; CHECK: [[RES:%[0-9]+]]:_(p0) = COPY [[BASE2]](p0)
 ; CHECK: %x0 = COPY [[RES]](p0)
 
   %res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
@@ -71,13 +71,13 @@ define i32* @const_then_var(%type1* %addr, i64 %idx) {
 
 define i32* @var_then_const(%type1* %addr, i64 %idx) {
 ; CHECK-LABEL: name: var_then_const
-; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0
-; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1
-; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 64
-; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_CONSTANT i64 40
-; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]]
-; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
-; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
+; CHECK: [[BASE:%[0-9]+]]:_(p0) = COPY %x0
+; CHECK: [[IDX:%[0-9]+]]:_(s64) = COPY %x1
+; CHECK: [[SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+; CHECK: [[OFFSET2:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
+; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_MUL [[SIZE]], [[IDX]]
+; CHECK: [[BASE1:%[0-9]+]]:_(p0) = G_GEP [[BASE]], [[OFFSET1]](s64)
+; CHECK: [[BASE2:%[0-9]+]]:_(p0) = G_GEP [[BASE1]], [[OFFSET2]](s64)
 ; CHECK: %x0 = COPY [[BASE2]](p0)
 
   %res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
diff --git a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll b/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
index af0ab57b0b9..f92a5721a4e 100644
--- a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
+++ b/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
@@ -6,8 +6,8 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
 ; CHECK: fixedStack:
 ; CHECK:   - { id: [[VARARGS_SLOT:[0-9]+]], type: default, offset: 8
 ; CHECK: body:
-; CHECK:   [[LIST:%[0-9]+]] = COPY %x0
-; CHECK:   [[VARARGS_AREA:%[0-9]+]] = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
+; CHECK:   [[LIST:%[0-9]+]]:gpr64sp = COPY %x0
+; CHECK:   [[VARARGS_AREA:%[0-9]+]]:gpr64common = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
 ; CHECK:   STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0)
   call void @llvm.va_start(i8* %list)
   ret void
diff --git a/test/CodeGen/AArch64/GlobalISel/vastart.ll b/test/CodeGen/AArch64/GlobalISel/vastart.ll
index ae44e8fc5de..1fb3eb55e67 100644
--- a/test/CodeGen/AArch64/GlobalISel/vastart.ll
+++ b/test/CodeGen/AArch64/GlobalISel/vastart.ll
@@ -5,7 +5,7 @@
 declare void @llvm.va_start(i8*)
 define void @test_va_start(i8* %list) {
 ; CHECK-LABEL: name: test_va_start
-; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0
+; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
 ; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 0)
 ; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 0)
   call void @llvm.va_start(i8* %list)
diff --git a/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
index 9ad47c721c3..43d20394be4 100644
--- a/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
+++ b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
@@ -1,5 +1,5 @@
 # RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s | FileCheck %s
-# CHECK: %1 = ANDWri {{.*}}
+# CHECK: %1:gpr32common = ANDWri {{.*}}
 # CHECK-NEXT: %wzr = SUBSWri {{.*}}
 --- |
   define i32 @test01() nounwind {
diff --git a/test/CodeGen/AArch64/regcoal-physreg.mir b/test/CodeGen/AArch64/regcoal-physreg.mir
index f88b7482aca..095e8a4973c 100644
--- a/test/CodeGen/AArch64/regcoal-physreg.mir
+++ b/test/CodeGen/AArch64/regcoal-physreg.mir
@@ -13,7 +13,7 @@ name: func0
 body: |
   bb.0:
     ; We usually should not coalesce copies from allocatable physregs.
-    ; CHECK: %0 = COPY %w7
+    ; CHECK: %0:gpr32 = COPY %w7
     ; CHECK: STRWui %0, %x1, 0
     %0 : gpr32 = COPY %w7
     STRWui %0, %x1, 0
@@ -26,7 +26,7 @@ body: |
 
     ; It is not fine to coalesce copies from reserved physregs when they are
     ; clobbered.
-    ; CHECK: %2 = COPY %fp
+    ; CHECK: %2:gpr64 = COPY %fp
     ; CHECK: STRXui %2, %x1, 0
     %2 : gpr64 = COPY %fp
     %fp = SUBXri %fp, 4, 0
@@ -56,14 +56,14 @@ body: |
     ; Only coalesce when the source register is reserved as a whole (this is
     ; a limitation of the current code which cannot update liveness information
     ; of the non-reserved part).
-    ; CHECK: %6 = COPY %x28_fp
+    ; CHECK: %6:xseqpairsclass = COPY %x28_fp
     ; CHECK: HINT 0, implicit %6
     %6 : xseqpairsclass = COPY %x28_fp
     HINT 0, implicit %6
 
     ; It is not fine to coalesce copies from reserved physregs when they are
     ; clobbered by the regmask on a call.
-    ; CHECK: %7 = COPY %x18
+    ; CHECK: %7:gpr64 = COPY %x18
     ; CHECK: BL @f2, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
     ; CHECK: STRXui %7, %x1, 0
 
@@ -80,7 +80,7 @@ body: |
 
     ; Cannot coalesce when there are reads of the physreg.
     ; CHECK-NOT: %fp = SUBXri %fp, 8, 0
-    ; CHECK: %9 = SUBXri %fp, 8, 0
+    ; CHECK: %9:gpr64sp = SUBXri %fp, 8, 0
     ; CHECK: STRXui %fp, %fp, 0
     ; CHECK: %fp = COPY %9
     %9 : gpr64sp = SUBXri %fp, 8, 0
@@ -96,7 +96,7 @@ body: |
     ; Cannot coalesce physreg because we have reads on other CFG paths (we
     ; currently abort for any control flow)
     ; CHECK-NOT: %fp = SUBXri
-    ; CHECK: %0 = SUBXri %fp, 12, 0
+    ; CHECK: %0:gpr64sp = SUBXri %fp, 12, 0
     ; CHECK: CBZX undef %x0, %bb.1
     ; CHECK: B %bb.2
     %0 : gpr64sp = SUBXri %fp, 12, 0
diff --git a/test/CodeGen/AArch64/spill-undef.mir b/test/CodeGen/AArch64/spill-undef.mir
index 4294df286bd..c4f589b5cc4 100644
--- a/test/CodeGen/AArch64/spill-undef.mir
+++ b/test/CodeGen/AArch64/spill-undef.mir
@@ -5,19 +5,19 @@
 --- |
   ; ModuleID = 'stuff.ll'
   target triple = "aarch64--"
-  
+
   @g = external global i32
-  
+
   define void @foobar() {
     ret void
   }
-  
+
 ...
 ---
 name:            foobar
 alignment:       2
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr32 }
   - { id: 1, class: gpr32 }
   - { id: 2, class: gpr32all }
@@ -37,25 +37,25 @@ body:             |
     ; But on that path, we don't care about its value.
     ; Emit a simple KILL instruction instead of an
     ; actual spill.
-    ; CHECK: [[UNDEF:%[0-9]+]] = IMPLICIT_DEF
+    ; CHECK: [[UNDEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
     ; CHECK-NEXT: KILL [[UNDEF]]
     %8 = IMPLICIT_DEF
     ; %9 us going to be spilled.
     ; But it is only partially undef.
     ; Make sure we spill it properly
-    ; CHECK: [[NINE:%[0-9]+]] = COPY %x0
-    ; CHECK: [[NINE]].sub_32 = IMPLICIT_DEF
+    ; CHECK: [[NINE:%[0-9]+]]:gpr64 = COPY %x0
+    ; CHECK: [[NINE]].sub_32:gpr64 = IMPLICIT_DEF
     ; CHECK-NEXT: STRXui [[NINE]]
     %9 = COPY %x0
     %9.sub_32 = IMPLICIT_DEF
     CBNZW %wzr, %bb.2
     B %bb.1
-  
+
   bb.1:
     %4 = ADRP target-flags(aarch64-page) @g
     %8 = LDRWui %4, target-flags(aarch64-pageoff, aarch64-nc) @g :: (volatile dereferenceable load 4 from @g)
     INLINEASM $nop, 1, 12, implicit-def dead early-clobber %x0, 12, implicit-def dead early-clobber %x1, 12, implicit-def dead early-clobber %x2, 12, implicit-def dead early-clobber %x3, 12, implicit-def dead early-clobber %x4, 12, implicit-def dead early-clobber %x5, 12, implicit-def dead early-clobber %x6, 12, implicit-def dead early-clobber %x7, 12, implicit-def dead early-clobber %x8, 12, implicit-def dead early-clobber %x9, 12, implicit-def dead early-clobber %x10, 12, implicit-def dead early-clobber %x11, 12, implicit-def dead early-clobber %x12, 12, implicit-def dead early-clobber %x13, 12, implicit-def dead early-clobber %x14, 12, implicit-def dead early-clobber %x15, 12, implicit-def dead early-clobber %x16, 12, implicit-def dead early-clobber %x17, 12, implicit-def dead early-clobber %x18, 12, implicit-def dead early-clobber %x19, 12, implicit-def dead early-clobber %x20, 12, implicit-def dead early-clobber %x21, 12, implicit-def dead early-clobber %x22, 12, implicit-def dead early-clobber %x23, 12, implicit-def dead early-clobber %x24, 12, implicit-def dead early-clobber %x25, 12, implicit-def dead early-clobber %x26, 12, implicit-def dead early-clobber %x27, 12, implicit-def dead early-clobber %x28, 12, implicit-def dead early-clobber %fp, 12, implicit-def dead early-clobber %lr
-  
+
   bb.2:
     INLINEASM $nop, 1, 12, implicit-def dead early-clobber %x0, 12, implicit-def dead early-clobber %x1, 12, implicit-def dead early-clobber %x2, 12, implicit-def dead early-clobber %x3, 12, implicit-def dead early-clobber %x4, 12, implicit-def dead early-clobber %x5, 12, implicit-def dead early-clobber %x6, 12, implicit-def dead early-clobber %x7, 12, implicit-def dead early-clobber %x8, 12, implicit-def dead early-clobber %x9, 12, implicit-def dead early-clobber %x10, 12, implicit-def dead early-clobber %x11, 12, implicit-def dead early-clobber %x12, 12, implicit-def dead early-clobber %x13, 12, implicit-def dead early-clobber %x14, 12, implicit-def dead early-clobber %x15, 12, implicit-def dead early-clobber %x16, 12, implicit-def dead early-clobber %x17, 12, implicit-def dead early-clobber %x18, 12, implicit-def dead early-clobber %x19, 12, implicit-def dead early-clobber %x20, 12, implicit-def dead early-clobber %x21, 12, implicit-def dead early-clobber %x22, 12, implicit-def dead early-clobber %x23, 12, implicit-def dead early-clobber %x24, 12, implicit-def dead early-clobber %x25, 12, implicit-def dead early-clobber %x26, 12, implicit-def dead early-clobber %x27, 12, implicit-def dead early-clobber %x28, 12, implicit-def dead early-clobber %fp, 12, implicit-def dead early-clobber %lr
     %6 = ADRP target-flags(aarch64-page) @g
diff --git a/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
index cdfb667c26b..8f83feac51d 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
+++ b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
@@ -5,7 +5,7 @@
 
 ; Tests for add.
 ; CHECK: name: addi32
-; CHECK: {{%[0-9]+}}(s32) = G_ADD
+; CHECK: {{%[0-9]+}}:_(s32) = G_ADD
 define amdgpu_kernel void @addi32(i32 %arg1, i32 %arg2) {
   %res = add i32 %arg1, %arg2
   store i32 %res, i32 addrspace(1)* undef
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
index 56a9e7022db..9b53b029691 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
@@ -13,7 +13,7 @@ legalized:       true
 regBankSelected: true
 
 # GCN: global_addrspace
-# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
+# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1
 # GCN: FLAT_LOAD_DWORD  [[PTR]], 0, 0, 0
 
 body: |
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
index ea2ad2ba83a..4c05383615a 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
@@ -14,83 +14,83 @@ legalized:       true
 regBankSelected: true
 
 # GCN: body:
-# GCN: [[PTR:%[0-9]+]] = COPY %sgpr0_sgpr1
+# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY %sgpr0_sgpr1
 
 # Immediate offset:
 # SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0
-# VI:   S_LOAD_DWORD_IMM [[PTR]], 4, 0 
+# VI:   S_LOAD_DWORD_IMM [[PTR]], 4, 0
 
 # Max immediate offset for SI
 # SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0
 # VI:   S_LOAD_DWORD_IMM [[PTR]], 1020, 0
 
 # Immediate overflow for SI
-# SI: [[K1024:%[0-9]+]] = S_MOV_B32 1024
+# SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
 # SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
 # VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0
 
 # Max immediate offset for VI
-# SI: [[K1048572:%[0-9]+]] = S_MOV_B32 1048572
+# SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 1048572
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
 # VI: S_LOAD_DWORD_IMM [[PTR]], 1048572
 
 #
 # Immediate overflow for VI
-# SIVI: [[K1048576:%[0-9]+]] = S_MOV_B32 1048576
+# SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576
 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0
 
 # Max immediate for CI
-# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 4294967292
-# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 3
-# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
-# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
-# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
+# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
+# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 3
+# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
+# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
+# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
+# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
+# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
+# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
+# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
+# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0
 
 # Immediate overflow for CI
-# GCN: [[K_LO:%[0-9]+]] = S_MOV_B32 0
-# GCN: [[K_HI:%[0-9]+]] = S_MOV_B32 4
-# GCN: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# GCN-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# GCN-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
-# GCN: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# GCN-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# GCN-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
-# GCN: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# GCN: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
+# GCN: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+# GCN: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 4
+# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
+# GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
+# GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
+# GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
+# GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
+# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
+# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
+# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
 
 # Max 32-bit byte offset
-# SIVI: [[K4294967292:%[0-9]+]] = S_MOV_B32 4294967292
+# SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292
 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0
 
 # Overflow 32-bit byte offset
-# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 0
-# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 1
-# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
-# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
-# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
-# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
-# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
-# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
-# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
-# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
+# SIVI: [[K_LO:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+# SIVI: [[K_HI:%[0-9]+]]:sreg_32 = S_MOV_B32 1
+# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
+# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
+# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
+# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
+# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
+# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
+# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
+# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0
 
 body: |
   bb.0:
     liveins: %sgpr0_sgpr1
-   
+
     %0:sgpr(p2) = COPY %sgpr0_sgpr1
 
     %1:sgpr(s64) = G_CONSTANT i64 4
diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
index ea435725bf2..0b8092778bd 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
@@ -13,8 +13,8 @@ legalized:       true
 regBankSelected: true
 
 # GCN: global_addrspace
-# GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
-# GCN: [[VAL:%[0-9]+]] = COPY %vgpr2
+# GCN: [[PTR:%[0-9]+]]:vreg_64 = COPY %vgpr0_vgpr1
+# GCN: [[VAL:%[0-9]+]]:vgpr_32 = COPY %vgpr2
 # GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0
 
 body: |
diff --git a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
index 6c3563a9c33..ebcdac39274 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
+++ b/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
@@ -2,7 +2,7 @@
 
 
 ; CHECK-LABEL: name: test_f32_inreg
-; CHECK: [[S0:%[0-9]+]](s32) = COPY %sgpr0
+; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
 define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
   call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
@@ -10,7 +10,7 @@ define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {
 }
 
 ; CHECK-LABEL: name: test_f32
-; CHECK: [[V0:%[0-9]+]](s32) = COPY %vgpr0
+; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0
 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]]
 define amdgpu_vs void @test_f32(float %arg0) {
   call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
@@ -18,7 +18,7 @@ define amdgpu_vs void @test_f32(float %arg0) {
 }
 
 ; CHECK-LABEL: name: test_ptr2_byval
-; CHECK: [[S01:%[0-9]+]](p2) = COPY %sgpr0_sgpr1
+; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1
 ; CHECK: G_LOAD [[S01]]
 define amdgpu_vs void @test_ptr2_byval(i32 addrspace(2)* byval %arg0) {
    %tmp0 = load volatile i32, i32 addrspace(2)* %arg0
@@ -26,7 +26,7 @@ define amdgpu_vs void @test_ptr2_byval(i32 addrspace(2)* byval %arg0) {
 }
 
 ; CHECK-LABEL: name: test_ptr2_inreg
-; CHECK: [[S01:%[0-9]+]](p2) = COPY %sgpr0_sgpr1
+; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY %sgpr0_sgpr1
 ; CHECK: G_LOAD [[S01]]
 define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(2)* inreg %arg0) {
   %tmp0 = load volatile i32, i32 addrspace(2)* %arg0
@@ -34,8 +34,8 @@ define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(2)* inreg %arg0) {
 }
 
 ; CHECK-LABEL: name: test_sgpr_alignment0
-; CHECK: [[S0:%[0-9]+]](s32) = COPY %sgpr0
-; CHECK: [[S23:%[0-9]+]](p2) = COPY %sgpr2_sgpr3
+; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
+; CHECK: [[S23:%[0-9]+]]:_(p2) = COPY %sgpr2_sgpr3
 ; CHECK: G_LOAD [[S23]]
 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
 define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(2)* inreg %arg1) {
@@ -45,11 +45,11 @@ define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(2)*
 }
 
 ; CHECK-LABEL: name: test_order
-; CHECK: [[S0:%[0-9]+\(s32\)]] = COPY %sgpr0
-; CHECK: [[S1:%[0-9]+\(s32\)]] = COPY %sgpr1
-; CHECK: [[V0:%[0-9]+\(s32\)]] = COPY %vgpr0
-; CHECK: [[V1:%[0-9]+\(s32\)]] = COPY %vgpr1
-; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]], [[S0]], [[V1]], [[S1]]
+; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY %sgpr0
+; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY %sgpr1
+; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY %vgpr0
+; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY %vgpr1
+; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]](s32), [[S0]](s32), [[V1]](s32), [[S1]](s32)
 define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) {
   call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #0
   ret void
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
index cb97da9893c..60cb6a8244c 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
@@ -16,9 +16,9 @@ body: |
     liveins: %vgpr0, %vgpr1
 
     ; CHECK-LABEL: name: test_add
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
-    ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
     %0(s32) = COPY %vgpr0
     %1(s32) = COPY %vgpr1
     %2(s32) = G_ADD %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index a89543b009c..a0f163d573c 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -16,9 +16,9 @@ body: |
     liveins: %vgpr0, %vgpr1
 
     ; CHECK-LABEL: name: test_and
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
     %0(s32) = COPY %vgpr0
     %1(s32) = COPY %vgpr1
     %2(s32) = G_AND %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
index b052ca069ce..f8b5c99418f 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@@ -16,9 +16,9 @@ body: |
     liveins: %vgpr0
 
     ; CHECK-LABEL: name: test_bitcast
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]](<2 x s16>) = G_BITCAST [[COPY]](s32)
-    ; CHECK: [[BITCAST1:%[0-9]+]](s32) = G_BITCAST [[BITCAST]](<2 x s16>)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s32)
+    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
     %0(s32) = COPY %vgpr0
     %1(<2 x s16>) = G_BITCAST %0
     %2(s32) = G_BITCAST %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
index 99e726ba837..6e2065207f9 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
@@ -27,8 +27,9 @@ body: |
   bb.0.entry:
 
     ; CHECK-LABEL: name: test_constant
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 5
-    ; CHECK: [[C1:%[0-9]+]](s1) = G_CONSTANT i1 false
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C1]](s1), [[C1]](s1)
     %0(s32) = G_CONSTANT i32 5
     %1(s1) = G_CONSTANT i1 0
     G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %0, %0, %0, %0, %0, %1, %1;
@@ -43,8 +44,8 @@ body: |
   bb.0.entry:
 
     ; CHECK-LABEL: name: test_fconstant
-    ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00
-    ; CHECK: [[C1:%[0-9]+]](s32) = G_FCONSTANT float 7.500000e+00
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.500000e+00
     %0(s32) = G_FCONSTANT float 1.0
     %1(s32) = G_FCONSTANT float 7.5
 ...
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
index f84032d05be..7db9c36b750 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
@@ -16,9 +16,9 @@ body: |
     liveins: %vgpr0, %vgpr1
 
     ; CHECK-LABEL: name: test_fmul
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
-    ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
+    ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
     %0(s32) = COPY %vgpr0
     %1(s32) = COPY %vgpr1
     %2(s32) = G_FMUL %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
index 71c3ada29d2..8508f2706fa 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -18,9 +18,9 @@ body: |
   bb.0.entry:
     liveins: %vgpr0
     ; CHECK-LABEL: name: test_icmp
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
     %0(s32) = G_CONSTANT i32 0
     %1(s32) = COPY %vgpr0
     %2(s1) = G_ICMP intpred(ne), %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index 04961e30dc9..879cd47f8c6 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -15,9 +15,9 @@ body: |
     liveins: %vgpr0, %vgpr1
 
     ; CHECK-LABEL: name: test_or
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
-    ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
     %0(s32) = COPY %vgpr0
     %1(s32) = COPY %vgpr1
     %2(s32) = G_OR %0, %1
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index 43f6859e052..09f00936a63 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -18,12 +18,12 @@ body: |
   bb.0:
     liveins: %vgpr0
     ; CHECK-LABEL: name: test_select
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-    ; CHECK: [[SELECT:%[0-9]+]](s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
     %0(s32) = G_CONSTANT i32 0
     %1(s32) = COPY %vgpr0
 
diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
index c2a5af72342..feecb7728cf 100644
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
@@ -12,9 +12,9 @@ body: |
     liveins: %vgpr0, %vgpr1
 
     ; CHECK-LABEL: name: test_shl
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %vgpr1
-    ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %vgpr1
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]]
     %0(s32) = COPY %vgpr0
     %1(s32) = COPY %vgpr1
     %2(s32) = G_SHL %0, %1
diff --git a/test/CodeGen/AMDGPU/clamp-omod-special-case.mir b/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
index 90fba034209..8ab99c6d296 100644
--- a/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
+++ b/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
@@ -1,8 +1,8 @@
 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s
 ---
 # GCN-LABEL: name: v_max_self_clamp_not_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN-NEXT: %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN-NEXT: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
 
 name:            v_max_self_clamp_not_set_f32
 tracksRegLiveness: true
@@ -64,8 +64,8 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: v_clamp_omod_already_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN: %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
 name:            v_clamp_omod_already_set_f32
 tracksRegLiveness: true
 registers:
@@ -127,8 +127,8 @@ body:             |
 # Don't fold a mul that looks like an omod if itself has omod set
 
 # GCN-LABEL: name: v_omod_mul_omod_already_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN-NEXT: %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit %exec
 name:            v_omod_mul_omod_already_set_f32
 tracksRegLiveness: true
 registers:
@@ -191,8 +191,8 @@ body:             |
 # Don't fold a mul that looks like an omod if itself has clamp set
 # This might be OK, but would require folding the clamp at the same time.
 # GCN-LABEL: name: v_omod_mul_clamp_already_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN-NEXT: %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit %exec
 
 name:            v_omod_mul_clamp_already_set_f32
 tracksRegLiveness: true
@@ -269,8 +269,8 @@ body:             |
 # Don't fold a mul that looks like an omod if itself has omod set
 
 # GCN-LABEL: name: v_omod_add_omod_already_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN-NEXT: %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit %exec
 name:            v_omod_add_omod_already_set_f32
 tracksRegLiveness: true
 registers:
@@ -333,8 +333,8 @@ body:             |
 # Don't fold a mul that looks like an omod if itself has clamp set
 # This might be OK, but would require folding the clamp at the same time.
 # GCN-LABEL: name: v_omod_add_clamp_already_set_f32
-# GCN: %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
-# GCN-NEXT: %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit %exec
+# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
+# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit %exec
 
 name:            v_omod_add_clamp_already_set_f32
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
index 0401f7b07e2..d29c6afe7d4 100644
--- a/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ b/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -2,7 +2,7 @@
 ...
 
 # GCN-LABEL: name: s_fold_and_imm_regimm_32{{$}}
-# GCN: %10 = V_MOV_B32_e32 1543, implicit %exec
+# GCN: %10:vgpr_32 = V_MOV_B32_e32 1543, implicit %exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %10,
 name:            s_fold_and_imm_regimm_32
 alignment:       0
@@ -62,19 +62,19 @@ body:             |
 
 # GCN-LABEL: name: v_fold_and_imm_regimm_32{{$}}
 
-# GCN: %9 = V_MOV_B32_e32 646, implicit %exec
+# GCN: %9:vgpr_32 = V_MOV_B32_e32 646, implicit %exec
 # GCN: FLAT_STORE_DWORD %19, %9,
 
-# GCN: %10 = V_MOV_B32_e32 646, implicit %exec
+# GCN: %10:vgpr_32 = V_MOV_B32_e32 646, implicit %exec
 # GCN: FLAT_STORE_DWORD %19, %10
 
-# GCN: %11 = V_MOV_B32_e32 646, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 646, implicit %exec
 # GCN: FLAT_STORE_DWORD %19, %11,
 
-# GCN: %12 = V_MOV_B32_e32 1234567, implicit %exec
+# GCN: %12:vgpr_32 = V_MOV_B32_e32 1234567, implicit %exec
 # GCN: FLAT_STORE_DWORD %19, %12,
 
-# GCN: %13 = V_MOV_B32_e32 63, implicit %exec
+# GCN: %13:vgpr_32 = V_MOV_B32_e32 63, implicit %exec
 # GCN: FLAT_STORE_DWORD %19, %13,
 
 name:            v_fold_and_imm_regimm_32
@@ -226,34 +226,34 @@ body:             |
 ---
 # GCN-LABEL: name: v_fold_shl_imm_regimm_32{{$}}
 
-# GCN: %11 = V_MOV_B32_e32 40955904, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 40955904, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
-# GCN: %12 = V_MOV_B32_e32 24, implicit %exec
+# GCN: %12:vgpr_32 = V_MOV_B32_e32 24, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %12,
 
-# GCN: %13 = V_MOV_B32_e32 4096, implicit %exec
+# GCN: %13:vgpr_32 = V_MOV_B32_e32 4096, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %13,
 
-# GCN: %14 = V_MOV_B32_e32 24, implicit %exec
+# GCN: %14:vgpr_32 = V_MOV_B32_e32 24, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %14,
 
-# GCN: %15 = V_MOV_B32_e32 0, implicit %exec
+# GCN: %15:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %15,
 
-# GCN: %22 = V_MOV_B32_e32 4096, implicit %exec
+# GCN: %22:vgpr_32 = V_MOV_B32_e32 4096, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %22,
 
-# GCN: %23 = V_MOV_B32_e32 1, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 1, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %23,
 
-# GCN: %25 = V_MOV_B32_e32 2, implicit %exec
+# GCN: %25:vgpr_32 = V_MOV_B32_e32 2, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %25,
 
-# GCN: %26 = V_MOV_B32_e32 7927808, implicit %exec
+# GCN: %26:vgpr_32 = V_MOV_B32_e32 7927808, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %26,
 
-# GCN: %28 = V_MOV_B32_e32 -8, implicit %exec
+# GCN: %28:vgpr_32 = V_MOV_B32_e32 -8, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %28,
 
 name:            v_fold_shl_imm_regimm_32
@@ -367,7 +367,7 @@ body:             |
 ---
 
 # GCN-LABEL: name: s_fold_ashr_imm_regimm_32{{$}}
-# GCN: %11 = V_MOV_B32_e32 243, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 243, implicit %exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
 name:            s_fold_ashr_imm_regimm_32
 alignment:       0
@@ -425,34 +425,34 @@ body:             |
 ...
 
 # GCN-LABEL: name: v_fold_ashr_imm_regimm_32{{$}}
-# GCN: %11 = V_MOV_B32_e32 3903258, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
-# GCN: %12 = V_MOV_B32_e32 62452139, implicit %exec
+# GCN: %12:vgpr_32 = V_MOV_B32_e32 62452139, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %12,
 
-# GCN: %13 = V_MOV_B32_e32 1678031, implicit %exec
+# GCN: %13:vgpr_32 = V_MOV_B32_e32 1678031, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %13,
 
-# GCN: %14 = V_MOV_B32_e32 3, implicit %exec
+# GCN: %14:vgpr_32 = V_MOV_B32_e32 3, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %14,
 
-# GCN: %15 = V_MOV_B32_e32 -1, implicit %exec
+# GCN: %15:vgpr_32 = V_MOV_B32_e32 -1, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %15,
 
-# GCN: %22 = V_MOV_B32_e32 62500, implicit %exec
+# GCN: %22:vgpr_32 = V_MOV_B32_e32 62500, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %22,
 
-# GCN: %23 = V_MOV_B32_e32 500000, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 500000, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %23,
 
-# GCN: %25 = V_MOV_B32_e32 1920, implicit %exec
+# GCN: %25:vgpr_32 = V_MOV_B32_e32 1920, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %25,
 
-# GCN: %26 = V_MOV_B32_e32 487907, implicit %exec
+# GCN: %26:vgpr_32 = V_MOV_B32_e32 487907, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %26,
 
-# GCN: %28 = V_MOV_B32_e32 -1, implicit %exec
+# GCN: %28:vgpr_32 = V_MOV_B32_e32 -1, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %28,
 
 name:            v_fold_ashr_imm_regimm_32
@@ -575,7 +575,7 @@ body:             |
 ---
 
 # GCN-LABEL: name: s_fold_lshr_imm_regimm_32{{$}}
-# GCN: %11 = V_MOV_B32_e32 1048332, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 1048332, implicit %exec
 # GCN: BUFFER_STORE_DWORD_OFFSET killed %11, killed %8,
 name:            s_fold_lshr_imm_regimm_32
 alignment:       0
@@ -634,34 +634,34 @@ body:             |
 ---
 
 # GCN-LABEL: name: v_fold_lshr_imm_regimm_32{{$}}
-# GCN: %11 = V_MOV_B32_e32 3903258, implicit %exec
+# GCN: %11:vgpr_32 = V_MOV_B32_e32 3903258, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %11,
 
-# GCN: %12 = V_MOV_B32_e32 62452139, implicit %exec
+# GCN: %12:vgpr_32 = V_MOV_B32_e32 62452139, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %12,
 
-# GCN: %13 = V_MOV_B32_e32 1678031, implicit %exec
+# GCN: %13:vgpr_32 = V_MOV_B32_e32 1678031, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %13,
 
-# GCN: %14 = V_MOV_B32_e32 3, implicit %exec
+# GCN: %14:vgpr_32 = V_MOV_B32_e32 3, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %14,
 
-# GCN: %15 = V_MOV_B32_e32 1, implicit %exec
+# GCN: %15:vgpr_32 = V_MOV_B32_e32 1, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %15,
 
-# GCN: %22 = V_MOV_B32_e32 62500, implicit %exec
+# GCN: %22:vgpr_32 = V_MOV_B32_e32 62500, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %22,
 
-# GCN: %23 = V_MOV_B32_e32 500000, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 500000, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %23,
 
-# GCN: %25 = V_MOV_B32_e32 1920, implicit %exec
+# GCN: %25:vgpr_32 = V_MOV_B32_e32 1920, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %25,
 
-# GCN: %26 = V_MOV_B32_e32 487907, implicit %exec
+# GCN: %26:vgpr_32 = V_MOV_B32_e32 487907, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %26,
 
-# GCN: %28 = V_MOV_B32_e32 1073741823, implicit %exec
+# GCN: %28:vgpr_32 = V_MOV_B32_e32 1073741823, implicit %exec
 # GCN: FLAT_STORE_DWORD %20, %28,
 
 name:            v_fold_lshr_imm_regimm_32
@@ -787,7 +787,7 @@ body:             |
 
 # GCN-LABEL: name: undefined_vreg_operand{{$}}
 # GCN: bb.0
-# GCN-NEXT: FLAT_STORE_DWORD undef %3, undef %1,
+# GCN-NEXT: FLAT_STORE_DWORD undef %3:vreg_64, undef %1:vgpr_32,
 # GCN-NEXT: S_ENDPGM
 name: undefined_vreg_operand
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/test/CodeGen/AMDGPU/detect-dead-lanes.mir
index c265b8e2ad2..b2f5e816b26 100644
--- a/test/CodeGen/AMDGPU/detect-dead-lanes.mir
+++ b/test/CodeGen/AMDGPU/detect-dead-lanes.mir
@@ -6,12 +6,12 @@
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def dead %2
-# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
+# CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %3.sub0
 # CHECK: S_NOP 0, implicit %3.sub1
 # CHECK: S_NOP 0, implicit undef %3.sub2
-# CHECK: %4 = COPY %3.sub0_sub1
-# CHECK: %5 = COPY undef %3.sub2_sub3
+# CHECK: %4:sreg_64 = COPY %3.sub0_sub1
+# CHECK: %5:sreg_64 = COPY undef %3.sub2_sub3
 # CHECK: S_NOP 0, implicit %4.sub0
 # CHECK: S_NOP 0, implicit %4.sub1
 # CHECK: S_NOP 0, implicit undef %5.sub0
@@ -42,9 +42,9 @@ body: |
 # Check defined lanes transfer; Includes checking for some special cases like
 # undef operands or IMPLICIT_DEF definitions.
 # CHECK-LABEL: name: test1
-# CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
-# CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
-# CHECK: %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
+# CHECK: %0:sreg_128 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
+# CHECK: %1:sreg_128 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
+# CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %1.sub0
 # CHECK: S_NOP 0, implicit undef %1.sub1
 # CHECK: S_NOP 0, implicit %1.sub2
@@ -52,25 +52,25 @@ body: |
 # CHECK: S_NOP 0, implicit %2.sub0
 # CHECK: S_NOP 0, implicit undef %2.sub1
 
-# CHECK: %3 = IMPLICIT_DEF
-# CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
+# CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF
+# CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit undef %4.sub0
 # CHECK: S_NOP 0, implicit undef %4.sub1
 # CHECK: S_NOP 0, implicit %4.sub2
 # CHECK: S_NOP 0, implicit undef %4.sub3
 
-# CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
-# CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
-# CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}}
+# CHECK: %5:sreg_64 = EXTRACT_SUBREG %0, {{[0-9]+}}
+# CHECK: %6:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
+# CHECK: %7:sreg_32_xm0 = EXTRACT_SUBREG %5, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %5
 # CHECK: S_NOP 0, implicit %6
 # CHECK: S_NOP 0, implicit undef %7
 
-# CHECK: %8 = IMPLICIT_DEF
-# CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
+# CHECK: %8:sreg_64 = IMPLICIT_DEF
+# CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit undef %9
 
-# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
+# CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit undef %10
 name: test1
 registers:
@@ -125,29 +125,29 @@ body: |
 # CHECK: S_NOP 0, implicit-def dead %0
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def %2
-# CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
+# CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %3.sub1
 # CHECK: S_NOP 0, implicit %3.sub3
 
 # CHECK: S_NOP 0, implicit-def %4
 # CHECK: S_NOP 0, implicit-def dead %5
-# CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
+# CHECK: %6:sreg_64 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %6
 
 # CHECK: S_NOP 0, implicit-def dead %7
 # CHECK: S_NOP 0, implicit-def %8
-# CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
+# CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %9.sub2
 
 # CHECK: S_NOP 0, implicit-def %10
 # CHECK: S_NOP 0, implicit-def dead %11
-# CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
+# CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %12.sub3
 
 # CHECK: S_NOP 0, implicit-def %13
 # CHECK: S_NOP 0, implicit-def dead %14
-# CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
-# CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
+# CHECK: %15:sreg_128 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
+# CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %16.sub1
 
 name: test2
@@ -205,7 +205,7 @@ body: |
 # CHECK-LABEL: name: test3
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %vcc = COPY %0
-# CHECK: %1 = COPY %vcc
+# CHECK: %1:sreg_64 = COPY %vcc
 # CHECK: S_NOP 0, implicit %1
 name: test3
 tracksRegLiveness: true
@@ -225,7 +225,7 @@ body: |
 # CHECK-LABEL: name: test4
 # CHECK: S_NOP 0, implicit-def dead %0
 # CHECK: KILL undef %0
-# CHECK: %1 = IMPLICIT_DEF
+# CHECK: %1:sreg_64 = IMPLICIT_DEF
 # CHECK: S_NOP 0, implicit undef %1
 name: test4
 tracksRegLiveness: true
@@ -245,7 +245,7 @@ body: |
 # used.
 # CHECK-LABEL: name: test5
 # CHECK: S_NOP 0, implicit-def %0
-# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
+# CHECK: %1:sreg_64 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %1.sub1
 name: test5
 tracksRegLiveness: true
@@ -265,10 +265,10 @@ body: |
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: S_NOP 0, implicit-def dead %1
 # CHECK: S_NOP 0, implicit-def dead %2
-# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
+# CHECK: %3:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
 
 # CHECK: bb.1:
-# CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
+# CHECK: %4:sreg_128 = PHI %3, %bb.0, %5, %bb.1
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %4.sub0
@@ -315,12 +315,12 @@ body: |
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def dead %2
 # CHECK: S_NOP 0, implicit-def %3
-# CHECK: %4 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
+# CHECK: %4:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
 
 # CHECK: bb.1:
-# CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
+# CHECK: %5:sreg_128 = PHI %4, %bb.0, %6, %bb.1
 
-# CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
+# CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %6.sub3
@@ -361,12 +361,12 @@ body: |
 # CHECK-LABEL: name: loop2
 # CHECK: bb.0:
 # CHECK: S_NOP 0, implicit-def %0
-# CHECK: %1 = REG_SEQUENCE %0, {{[0-9]+}}
+# CHECK: %1:sreg_128 = REG_SEQUENCE %0, {{[0-9]+}}
 
 # CHECK: bb.1:
-# CHECK: %2 = PHI %1, %bb.0, %3, %bb.1
+# CHECK: %2:sreg_128 = PHI %1, %bb.0, %3, %bb.1
 
-# CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
+# CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
 
 # CHECK: bb.2:
 # CHECK:   S_NOP 0, implicit %2.sub0
diff --git a/test/CodeGen/AMDGPU/endpgm-dce.mir b/test/CodeGen/AMDGPU/endpgm-dce.mir
index 59802ca9792..9833cc10d40 100644
--- a/test/CodeGen/AMDGPU/endpgm-dce.mir
+++ b/test/CodeGen/AMDGPU/endpgm-dce.mir
@@ -25,7 +25,7 @@ body:             |
 ---
 # GCN-LABEL: name: load_without_memoperand
 # GCN:      %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
-# GCN-NEXT: dead %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr
+# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr
 # GCN-NEXT: S_ENDPGM
 name: load_without_memoperand
 tracksRegLiveness: true
@@ -49,7 +49,7 @@ body:             |
 ---
 # GCN-LABEL: name: load_volatile
 # GCN:      %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
-# GCN-NEXT: dead %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile load 4)
+# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile load 4)
 # GCN-NEXT: S_ENDPGM
 name: load_volatile
 tracksRegLiveness: true
@@ -120,7 +120,7 @@ body:             |
 ---
 # GCN-LABEL: name: exp
 # GCN:      %sgpr0_sgpr1 = S_OR_B64 %exec, killed %vcc, implicit-def %scc
-# GCN-NEXT: EXP 32, undef %0, undef %1, %2, undef %3, 0, 0, 15, implicit %exec
+# GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit %exec
 # GCN-NEXT: S_ENDPGM
 name: exp
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/fold-cndmask.mir b/test/CodeGen/AMDGPU/fold-cndmask.mir
index 8dfec916630..1ddb02a59b9 100644
--- a/test/CodeGen/AMDGPU/fold-cndmask.mir
+++ b/test/CodeGen/AMDGPU/fold-cndmask.mir
@@ -1,11 +1,11 @@
 # RUN: llc -march=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s
 
-# CHECK: %1 = V_MOV_B32_e32 0, implicit %exec
-# CHECK: %2 = V_MOV_B32_e32 0, implicit %exec
-# CHECK: %4 = COPY %3
-# CHECK: %5 = V_MOV_B32_e32 0, implicit %exec
-# CHECK: %6 = V_MOV_B32_e32 0, implicit %exec
-# CHECK: %7 = COPY %3
+# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# CHECK: %4:vgpr_32 = COPY %3
+# CHECK: %5:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# CHECK: %6:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# CHECK: %7:vgpr_32 = COPY %3
 
 ---
 name:            fold_cndmask
diff --git a/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir b/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
index 3155b7a8664..9831538aa66 100644
--- a/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
+++ b/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
@@ -1,8 +1,8 @@
 # RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
 ...
 # GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32
-# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
-# GCN-NEXT: %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit %exec
+# GCN-NEXT: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
 
 name:            no_fold_imm_madak_mac_clamp_f32
 tracksRegLiveness: true
@@ -72,8 +72,8 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32
-# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
-# GCN: %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit %exec
+# GCN: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit %exec
 
 name:            no_fold_imm_madak_mac_omod_f32
 tracksRegLiveness: true
@@ -143,8 +143,8 @@ body:             |
 ...
 ---
 # GCN: name: no_fold_imm_madak_mad_clamp_f32
-# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
-# GCN: %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit %exec
+# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit %exec
 
 name:            no_fold_imm_madak_mad_clamp_f32
 tracksRegLiveness: true
@@ -214,8 +214,8 @@ body:             |
 ...
 ---
 # GCN: name: no_fold_imm_madak_mad_omod_f32
-# GCN: %23 = V_MOV_B32_e32 1090519040, implicit %exec
-# GCN: %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit %exec
+# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit %exec
+# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit %exec
 
 name:            no_fold_imm_madak_mad_omod_f32
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/fold-operands-order.mir b/test/CodeGen/AMDGPU/fold-operands-order.mir
index 51bb357fcf6..3f28f39930f 100644
--- a/test/CodeGen/AMDGPU/fold-operands-order.mir
+++ b/test/CodeGen/AMDGPU/fold-operands-order.mir
@@ -6,10 +6,10 @@
 # aren't made in users before the def is seen.
 
 # GCN-LABEL: name: mov_in_use_list_2x{{$}}
-# GCN: %2 = V_MOV_B32_e32 0, implicit %exec
-# GCN-NEXT: %3 = COPY undef %0
+# GCN: %2:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# GCN-NEXT: %3:vgpr_32 = COPY undef %0
 
-# GCN: %1 = V_MOV_B32_e32 0, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
 
 
 name: mov_in_use_list_2x
diff --git a/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir b/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
index dff9024df62..6c6b19a04c6 100644
--- a/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
+++ b/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
@@ -2,8 +2,8 @@
 
 # GCN-LABEL: name: cluster_add_addc
 # GCN: S_NOP 0, implicit-def %vcc
-# GCN: dead %2, %3 = V_ADD_I32_e64 %0, %1, implicit %exec
-# GCN: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
+# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
+# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %3, implicit %exec
 name: cluster_add_addc
 registers:
   - { id: 0, class: vgpr_32 }
@@ -27,10 +27,10 @@ body: |
 ...
 
 # GCN-LABEL: name: interleave_add64s
-# GCN: dead %8, %9 = V_ADD_I32_e64 %0, %1, implicit %exec
-# GCN-NEXT: dead %12, dead %13 = V_ADDC_U32_e64 %4, %5, %9, implicit %exec
-# GCN-NEXT: dead %10, %11 = V_ADD_I32_e64 %2, %3, implicit %exec
-# GCN-NEXT: dead %14, dead %15 = V_ADDC_U32_e64 %6, %7, %11, implicit %exec
+# GCN: dead %8:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
+# GCN-NEXT: dead %12:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %4, %5, %9, implicit %exec
+# GCN-NEXT: dead %10:vgpr_32, %11:sreg_64_xexec = V_ADD_I32_e64 %2, %3, implicit %exec
+# GCN-NEXT: dead %14:vgpr_32, dead %15:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %11, implicit %exec
 name: interleave_add64s
 registers:
   - { id: 0, class: vgpr_32 }
@@ -71,8 +71,8 @@ body: |
 
 # GCN-LABEL: name: cluster_mov_addc
 # GCN: S_NOP 0, implicit-def %vcc
-# GCN-NEXT: %2 = S_MOV_B64 0
-# GCN-NEXT: dead %3, dead %4 = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
+# GCN-NEXT: %2:sreg_64_xexec = S_MOV_B64 0
+# GCN-NEXT: dead %3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 %0, %1, %2, implicit %exec
 name: cluster_mov_addc
 registers:
   - { id: 0, class: vgpr_32 }
@@ -93,12 +93,12 @@ body: |
 ...
 
 # GCN-LABEL: name: no_cluster_add_addc_diff_sgpr
-# GCN: dead %2, dead %3 = V_ADD_I32_e64 %0, %1, implicit %exec
-# GCN-NEXT: %6 = V_MOV_B32_e32 0, implicit %exec
-# GCN-NEXT: %7 = V_MOV_B32_e32 0, implicit %exec
+# GCN: dead %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit %exec
+# GCN-NEXT: %6:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# GCN-NEXT: %7:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
 # GCN-NEXT: S_NOP 0, implicit-def %vcc
-# GCN-NEXT: %8 = S_MOV_B64 0
-# GCN-NEXT: dead %4, dead %5 = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
+# GCN-NEXT: %8:sreg_64_xexec = S_MOV_B64 0
+# GCN-NEXT: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_ADDC_U32_e64 %6, %7, %8, implicit %exec
 name: no_cluster_add_addc_diff_sgpr
 registers:
   - { id: 0, class: vgpr_32 }
@@ -123,8 +123,8 @@ body: |
 ...
 # GCN-LABEL: name: cluster_sub_subb
 # GCN: S_NOP 0, implicit-def %vcc
-# GCN: dead %2, %3 = V_SUB_I32_e64 %0, %1, implicit %exec
-# GCN: dead %4, dead %5 = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
+# GCN: dead %2:vgpr_32, %3:sreg_64_xexec = V_SUB_I32_e64 %0, %1, implicit %exec
+# GCN: dead %4:vgpr_32, dead %5:sreg_64_xexec = V_SUBB_U32_e64 %6, %7, %3, implicit %exec
 name: cluster_sub_subb
 registers:
   - { id: 0, class: vgpr_32 }
@@ -149,8 +149,8 @@ body: |
 
 # GCN-LABEL: name: cluster_cmp_cndmask
 # GCN: S_NOP 0, implicit-def %vcc
-# GCN-NEXT: %3 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
-# GCN-NEXT: dead %4 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
+# GCN-NEXT: %3:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
+# GCN-NEXT: dead %4:vgpr_32 = V_CNDMASK_B32_e64 %0, %1, %3, implicit %exec
 name: cluster_cmp_cndmask
 registers:
   - { id: 0, class: vgpr_32 }
@@ -172,9 +172,9 @@ body: |
 ...
 
 # GCN-LABEL: name: cluster_multi_use_cmp_cndmask
-# GCN: %4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
-# GCN-NEXT: dead %5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
-# GCN-NEXT: dead %6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
+# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
+# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
+# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
 name: cluster_multi_use_cmp_cndmask
 registers:
   - { id: 0, class: vgpr_32 }
@@ -200,10 +200,10 @@ body: |
 ...
 
 # GCN-LABEL: name: cluster_multi_use_cmp_cndmask2
-# GCN: %4 = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
-# GCN-NEXT: dead %5 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
-# GCN-NEXT: %3 = V_MOV_B32_e32 0, implicit %exec
-# GCN-NEXT: dead %6 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
+# GCN: %4:sreg_64_xexec = V_CMP_EQ_I32_e64 %0, %1, implicit %exec
+# GCN-NEXT: dead %5:vgpr_32 = V_CNDMASK_B32_e64 %2, %1, %4, implicit %exec
+# GCN-NEXT: %3:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
+# GCN-NEXT: dead %6:vgpr_32 = V_CNDMASK_B32_e64 %1, %3, %4, implicit %exec
 name: cluster_multi_use_cmp_cndmask2
 registers:
   - { id: 0, class: vgpr_32 }
diff --git a/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir b/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
index 0a6c8a41130..6c6590a154a 100644
--- a/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
+++ b/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
@@ -3,21 +3,21 @@
 # Check that constant is in SGPR registers
 
 # GCN-LABEL: {{^}}name: const_to_sgpr{{$}}
-# GCN:        %[[HI:[0-9]+]] = S_MOV_B32 0
-# GCN-NEXT:   %[[LO:[0-9]+]] = S_MOV_B32 1048576
-# GCN-NEXT:   %[[SGPR_PAIR:[0-9]+]] = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
+# GCN:        %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
+# GCN-NEXT:   %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
+# GCN-NEXT:   %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
 # GCN-NEXT:   V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
 
 
 # GCN-LABEL: {{^}}name: const_to_sgpr_multiple_use{{$}}
-# GCN:        %[[HI:[0-9]+]] = S_MOV_B32 0
-# GCN-NEXT:   %[[LO:[0-9]+]] = S_MOV_B32 1048576
-# GCN-NEXT:   %[[SGPR_PAIR:[0-9]+]] = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
+# GCN:        %[[HI:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
+# GCN-NEXT:   %[[LO:[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
+# GCN-NEXT:   %[[SGPR_PAIR:[0-9]+]]:sreg_64 = REG_SEQUENCE killed %[[LO]], 1, killed %[[HI]], 2
 # GCN-NEXT:   V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
 # GCN-NEXT:   V_CMP_LT_U64_e64 killed %{{[0-9]+}}, %[[SGPR_PAIR]], implicit %exec
 
 # GCN-LABEL: {{^}}name: const_to_sgpr_subreg{{$}}
-# GCN:       %[[OP0:[0-9]+]] = REG_SEQUENCE killed %{{[0-9]+}}, 1, killed %{{[0-9]+}}, 2
+# GCN:       %[[OP0:[0-9]+]]:vreg_64 = REG_SEQUENCE killed %{{[0-9]+}}, 1, killed %{{[0-9]+}}, 2
 # GCN-NEXT:  V_CMP_LT_U32_e64 killed %[[OP0]].sub0, 12, implicit %exec
 
 --- |
diff --git a/test/CodeGen/AMDGPU/regcoal-subrange-join.mir b/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
index bac348aaed7..a03135348ce 100644
--- a/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
+++ b/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
@@ -4,10 +4,10 @@
 # This test will provoke a subrange join (see annotations below) during simple register coalescing
 # Without a fix for PR33524 this causes an unreachable in SubRange Join
 #
-# GCN-DAG: undef %[[REG0:[0-9]+]].sub0 = COPY %sgpr5
-# GCN-DAG: undef %[[REG1:[0-9]+]].sub0 = COPY %sgpr2
-# GCN-DAG: %[[REG0]].sub1 = S_MOV_B32 1
-# GCN-DAG: %[[REG1]].sub1 = S_MOV_B32 1
+# GCN-DAG: undef %[[REG0:[0-9]+]].sub0:sgpr_64 = COPY %sgpr5
+# GCN-DAG: undef %[[REG1:[0-9]+]].sub0:sgpr_64 = COPY %sgpr2
+# GCN-DAG: %[[REG0]].sub1:sgpr_64 = S_MOV_B32 1
+# GCN-DAG: %[[REG1]].sub1:sgpr_64 = S_MOV_B32 1
 
 --- |
   define amdgpu_vs void @regcoal-subrange-join(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 %arg6) local_unnamed_addr #0 {
diff --git a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
index ecf94b5772f..c5a9a0ad01a 100644
--- a/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
+++ b/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
@@ -4,12 +4,12 @@
 # LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have
 # a slot index.
 
-# CHECK: %13.sub2 = S_MOV_B32 0
+# CHECK: %13.sub2:sgpr_128 = S_MOV_B32 0
 # CHECK: DBG_VALUE{{.*}}debug-use %13.sub2
 
 --- |
   define amdgpu_kernel void @test(i32 addrspace(1)* %out) { ret void }
-  
+
   !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
   !1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
   !2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !5)
@@ -25,7 +25,7 @@
 ---
 name:            test
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: sgpr_64 }
   - { id: 1, class: sreg_32_xm0 }
   - { id: 2, class: sgpr_32 }
@@ -47,13 +47,13 @@ registers:
   - { id: 18, class: vgpr_32 }
   - { id: 19, class: vreg_64 }
   - { id: 20, class: vreg_64 }
-liveins:         
+liveins:
   - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
   - { reg: '%vgpr0', virtual-reg: '%3' }
 body:             |
   bb.0:
     liveins: %sgpr0_sgpr1, %vgpr0
-  
+
     %3 = COPY killed %vgpr0
     %0 = COPY killed %sgpr0_sgpr1
     %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
diff --git a/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
index a52b80ba86e..08b3ecf8dba 100644
--- a/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
+++ b/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
@@ -2,7 +2,7 @@
 ---
 
 # GCN-LABEL: name: mac_invalid_operands
-# GCN: undef %18.sub0 = V_MAC_F32_e32 undef %3, undef %9, undef %18.sub0, implicit %exec
+# GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit %exec
 
 name:            mac_invalid_operands
 alignment:       0
@@ -73,13 +73,13 @@ body:             |
 
 # GCN-LABEL: name: vreg_does_not_dominate
 
-# GCN: undef %8.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %8.sub1, implicit %exec
-# GCN: undef %7.sub0 = V_MOV_B32_e32 0, implicit %exec
-# GCN: undef %9.sub2 = COPY %7.sub0
+# GCN: undef %8.sub1:vreg_128 = V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef %8.sub1, implicit %exec
+# GCN: undef %7.sub0:vreg_128 = V_MOV_B32_e32 0, implicit %exec
+# GCN: undef %9.sub2:vreg_128 = COPY %7.sub0
 
-# GCN: undef %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit %exec
-# GCN: undef %7.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit %exec
-# GCN: %8.sub1 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit %exec
+# GCN: undef %6.sub3:vreg_128 = V_ADD_F32_e32 undef %3:vgpr_32, undef %3:vgpr_32, implicit %exec
+# GCN: undef %7.sub0:vreg_128 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit %exec
+# GCN: %8.sub1:vreg_128 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit %exec
 
 # GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,
 # GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0,
@@ -137,8 +137,8 @@ body:             |
 
 # GCN-LABEL: name: inf_loop_tied_operand
 # GCN: bb.0:
-# GCN-NEXT: undef %2.sub0 = V_MAC_F32_e32 1073741824, undef %0, undef %2.sub0, implicit %exec
-# GCN-NEXT: dead undef %3.sub1 = COPY %2.sub0
+# GCN-NEXT: undef %2.sub0:vreg_128 = V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit %exec
+# GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0
 
 name:            inf_loop_tied_operand
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/sdwa-gfx9.mir b/test/CodeGen/AMDGPU/sdwa-gfx9.mir
index 90cb14bf50d..2196e7e65c0 100644
--- a/test/CodeGen/AMDGPU/sdwa-gfx9.mir
+++ b/test/CodeGen/AMDGPU/sdwa-gfx9.mir
@@ -3,20 +3,20 @@
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
 
 # GCN-LABEL: {{^}}name: add_shr_i32
-# GCN: [[SMOV:%[0-9]+]] = S_MOV_B32 123
+# GCN: [[SMOV:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 123
 
-# CI: [[SHIFT:%[0-9]+]] = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
-# CI: %{{[0-9]+}} = V_ADD_I32_e32 [[SMOV]], killed [[SHIFT]], implicit-def %vcc, implicit %exec
+# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
+# CI: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 [[SMOV]], killed [[SHIFT]], implicit-def %vcc, implicit %exec
 
-# VI: [[VMOV:%[0-9]+]] = V_MOV_B32_e32 [[SMOV]], implicit %exec
-# VI: %{{[0-9]+}} = V_ADD_I32_sdwa 0, [[VMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def %vcc, implicit %exec
+# VI: [[VMOV:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[SMOV]], implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_sdwa 0, [[VMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def %vcc, implicit %exec
 
-# GFX9: %{{[0-9]+}} = V_ADD_I32_sdwa 0, [[SMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def %vcc, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_sdwa 0, [[SMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def %vcc, implicit %exec
 
 ---
 name:            add_shr_i32
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -33,7 +33,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
@@ -49,18 +49,18 @@ body:             |
 
 # GCN-LABEL: {{^}}name: trunc_shr_f32
 
-# CI: [[SHIFT:%[0-9]+]] = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
-# CI: %{{[0-9]+}} = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def %vcc, implicit %exec
+# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
+# CI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def %vcc, implicit %exec
 
-# VI: [[SHIFT:%[0-9]+]] = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
-# VI: %{{[0-9]+}} = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def %vcc, implicit %exec
+# VI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def %vcc, implicit %exec
 
-#GFX9: %{{[0-9]+}} = V_TRUNC_F32_sdwa 0, %{{[0-9]+}}, 1, 2, 6, 0, 5, implicit %exec
+#GFX9: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_sdwa 0, %{{[0-9]+}}, 1, 2, 6, 0, 5, implicit %exec
 
 ---
 name:            trunc_shr_f32
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -76,7 +76,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
diff --git a/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir b/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
index ff1b2ad73ef..77c231c584a 100644
--- a/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
+++ b/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
@@ -3,35 +3,35 @@
 
 # GFX89-LABEL: {{^}}name: vop1_instructions
 
-# GFX89: %{{[0-9]+}} = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
-# GFX89: %{{[0-9]+}} = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
 
 
-# GFX89: %{{[0-9]+}} = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
-# GFX89: %{{[0-9]+}} = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
-# GFX89: %{{[0-9]+}} = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit %exec
 
 
-# VI: %{{[0-9]+}} = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
-# VI: %{{[0-9]+}} = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit %exec
-# VI: %{{[0-9]+}} = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
-# VI: %{{[0-9]+}} = V_CVT_F32_I32_e64 %{{[0-9]+}}, 0, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_e64 %{{[0-9]+}}, 0, 1, implicit %exec
 
-# GFX9: %{{[0-9]+}} = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
-# GFX9: %{{[0-9]+}} = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit %exec
-# GFX9: %{{[0-9]+}} = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
-# GFX9: %{{[0-9]+}} = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit %exec
 
 
 ---
 name:            vop1_instructions
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -85,7 +85,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
@@ -148,45 +148,45 @@ body:             |
 # GCN-LABEL: {{^}}name: vop2_instructions
 
 
-# VI: %{{[0-9]+}} = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec
-# VI: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
 
-# GFX9: %{{[0-9]+}} = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec
-# GFX9: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit %exec
 
 
-# VI: %{{[0-9]+}} = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec
-# VI: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit %exec
 
-# GFX9: %{{[0-9]+}} = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec
-# GFX9: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit %exec
 
 
-# VI: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, %{{[0-9]+}}, 1, 0, 6, 0, 6, 1, implicit %exec
-# VI: %{{[0-9]+}} = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, %{{[0-9]+}}, 1, 0, 6, 0, 6, 1, implicit %exec
+# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit %exec
 
-# GFX9: %{{[0-9]+}} = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit %exec
 
 name:            vop2_instructions
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -252,7 +252,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
@@ -324,7 +324,7 @@ body:             |
 
 # GCN-LABEL: {{^}}name: vopc_instructions
 
-# GFX89: %{{[0-9]+}} = V_MOV_B32_e32 123, implicit %exec
+# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 123, implicit %exec
 # GFX89: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec
 # GFX89: %vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec
 # GFX89: %vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec
@@ -332,16 +332,16 @@ body:             |
 
 
 # VI: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec
-# VI: %{{[0-9]+}} = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, implicit-def %exec, implicit %exec
+# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, implicit-def %exec, implicit %exec
 # VI: %vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %3, 0, 6, 4, implicit-def %vcc, implicit %exec
-# VI: %{{[0-9]+}} = V_CMPX_EQ_I32_e64 23, killed %{{[0-9]+}}, implicit-def %exec, implicit %exec
+# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_e64 23, killed %{{[0-9]+}}, implicit-def %exec, implicit %exec
 
 # GFX9: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MOV_B32_e32 23, implicit %exec
-# GFX9: %{{[0-9]+}} = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit %exec
+# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec
 # GFX9: %vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec
-# GFX9: %{{[0-9]+}} = V_MOV_B32_e32 23, implicit %exec
-# GFX9: %{{[0-9]+}} = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec
+# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit %exec
+# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec
 
 
 # VI: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def %vcc, implicit %exec
@@ -364,7 +364,7 @@ body:             |
 
 name:            vopc_instructions
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -397,7 +397,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
diff --git a/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir b/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
index bd222adf6a6..c50601e79f2 100644
--- a/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
+++ b/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
@@ -6,15 +6,15 @@
 
 # GCN-LABEL: {{^}}name: vop2_64bit
 
-# GCN: %{{[0-9]+}} = V_BCNT_U32_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec
-# GCN: %{{[0-9]+}} = V_BFM_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec
-# GCN: %{{[0-9]+}} = V_CVT_PKNORM_I16_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec
-# GCN: %{{[0-9]+}} = V_READLANE_B32 killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec
+# GCN: %{{[0-9]+}}:vgpr_32 = V_BCNT_U32_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec
+# GCN: %{{[0-9]+}}:vgpr_32 = V_BFM_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec
+# GCN: %{{[0-9]+}}:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec
+# GCN: %{{[0-9]+}}:sgpr_32 = V_READLANE_B32 killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec
 
 ---
 name:            vop2_64bit
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: vreg_64 }
   - { id: 1, class: vreg_64 }
   - { id: 2, class: sreg_64 }
@@ -37,7 +37,7 @@ registers:
 body:             |
   bb.0:
     liveins: %vgpr0_vgpr1, %vgpr2_vgpr3, %sgpr30_sgpr31
-  
+
     %2 = COPY %sgpr30_sgpr31
     %1 = COPY %vgpr2_vgpr3
     %0 = COPY %vgpr0_vgpr1
diff --git a/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir b/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
index b1fdc5f8045..0ffee0c4fcf 100644
--- a/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
+++ b/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
@@ -8,8 +8,8 @@
 
 ...
 # GCN-LABEL: name: shrink_add_vop3{{$}}
-# GCN: %29, %9 = V_ADD_I32_e64 %19, %17, implicit %exec
-# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_ADD_I32_e64 %19, %17, implicit %exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
 name:            shrink_add_vop3
 alignment:       0
 exposesReturnsTwice: false
@@ -91,8 +91,8 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: shrink_sub_vop3{{$}}
-# GCN: %29, %9 = V_SUB_I32_e64 %19, %17, implicit %exec
-# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUB_I32_e64 %19, %17, implicit %exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
 
 name:            shrink_sub_vop3
 alignment:       0
@@ -175,8 +175,8 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: shrink_subrev_vop3{{$}}
-# GCN: %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec
-# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
+# GCN: %29:vgpr_32, %9:sreg_64_xexec = V_SUBREV_I32_e64 %19, %17, implicit %exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
 
 name:            shrink_subrev_vop3
 alignment:       0
@@ -259,8 +259,8 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: check_addc_src2_vop3{{$}}
-# GCN: %29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
-# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
+# GCN: %29:vgpr_32, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
 name: check_addc_src2_vop3
 alignment:       0
 exposesReturnsTwice: false
@@ -343,7 +343,7 @@ body:             |
 ...
 ---
 # GCN-LABEL: name: shrink_addc_vop3{{$}}
-# GCN: %29 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit %vcc, implicit %exec
+# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit %vcc, implicit %exec
 # GCN %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
 
 name:            shrink_addc_vop3
@@ -429,8 +429,8 @@ body:             |
 
 ---
 # GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
-# GCN: %29 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit undef %vcc, implicit %exec
-# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
+# GCN: %29:vgpr_32 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit undef %vcc, implicit %exec
+# GCN: %24:vgpr_32 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
 name:            shrink_addc_undef_vcc
 alignment:       0
 exposesReturnsTwice: false
diff --git a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
index 580268deb85..7ae4636a0b5 100644
--- a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
+++ b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
@@ -3,7 +3,7 @@
 ; register operands in the correct order when modifying the opcode of an
 ; instruction to V_ADD_I32_e32.
 
-; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
+; CHECK: %{{[0-9]+}}:vgpr_32 = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec
 
 define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 entry:
diff --git a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
index 6c2e8093c02..aceac34f286 100644
--- a/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
+++ b/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
@@ -7,13 +7,13 @@
 
 # CHECK-LABEL: name: expecting_non_empty_interval
 
-# CHECK: undef %7.sub1 = V_MAC_F32_e32 0, undef %1, undef %7.sub1, implicit %exec
+# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec
 # CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4)
-# CHECK-NEXT: undef %5.sub1 = V_MOV_B32_e32 1786773504, implicit %exec
-# CHECK-NEXT: dead %2 = V_MUL_F32_e32 0, %5.sub1, implicit %exec
+# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec
+# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec
 
 # CHECK: S_NOP 0, implicit %6.sub1
-# CHECK-NEXT: %8 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4)
+# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4)
 # CHECK-NEXT: S_NOP 0, implicit %8.sub1
 # CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
 
@@ -44,12 +44,12 @@ body:             |
 # CHECK-LABEL: name: rematerialize_empty_interval_has_reference
 
 # CHECK-NOT: MOV
-# CHECK: undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
+# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit %exec
 
 # CHECK: bb.1:
 # CHECK-NEXT: S_NOP 0, implicit %3.sub2
 # CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
-# CHECK-NEXT: undef %4.sub2 = V_MOV_B32_e32 0, implicit %exec
+# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit %exec
 # CHECK-NEXT: S_NOP 0, implicit %4.sub2
 name: rematerialize_empty_interval_has_reference
 tracksRegLiveness: true
diff --git a/test/CodeGen/AMDGPU/twoaddr-mad.mir b/test/CodeGen/AMDGPU/twoaddr-mad.mir
index b4e42e83374..707676d8489 100644
--- a/test/CodeGen/AMDGPU/twoaddr-mad.mir
+++ b/test/CodeGen/AMDGPU/twoaddr-mad.mir
@@ -112,8 +112,8 @@ body:             |
 # Make sure constant bus restriction isn't violated if src0 is an SGPR.
 
 # GCN-LABEL: name: test_madak_sgpr_src0_f32
-# GCN: %1 = V_MOV_B32_e32 1078523331, implicit %exec
-# GCN: %2 = V_MAD_F32 0, killed %0, 0, %1, 0, %3, 0, 0, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit %exec
+# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit %exec
 
 ---
 name:            test_madak_sgpr_src0_f32
@@ -134,7 +134,7 @@ body:             |
 # This can still fold if this is an inline immediate.
 
 # GCN-LABEL: name: test_madak_inlineimm_src0_f32
-# GCN: %1 = V_MADMK_F32 1073741824, 1078523331, %2, implicit %exec
+# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit %exec
 
 ---
 name:            test_madak_inlineimm_src0_f32
@@ -152,7 +152,7 @@ body:             |
 # Non-inline immediate uses constant bus already.
 
 # GCN-LABEL: name: test_madak_otherimm_src0_f32
-# GCN: %1 = V_MAC_F32_e32 1120403456, %0, %1, implicit %exec
+# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit %exec
 
 ---
 name:            test_madak_otherimm_src0_f32
@@ -170,7 +170,7 @@ body:             |
 # Non-inline immediate uses constant bus already.
 
 # GCN-LABEL: name: test_madak_other_constantlike_src0_f32
-# GCN: %1 = V_MAC_F32_e32 %stack.0, %0, %1, implicit %exec
+# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit %exec
 ---
 name:            test_madak_other_constantlike_src0_f32
 registers:
diff --git a/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir b/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
index f8a2339626c..1c34789ed60 100644
--- a/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
+++ b/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
@@ -33,9 +33,9 @@
 
 ...
 # GCN-LABEL: name: fold_fi_vgpr{{$}}
-# GCN: %1 = IMPLICIT_DEF
+# GCN: %1:vgpr_32 = IMPLICIT_DEF
 
-# GCN: %2 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
 name: fold_fi_vgpr
 tracksRegLiveness: true
 registers:
@@ -55,8 +55,8 @@ body:             |
 
 ...
 # GCN-LABEL: name: fold_vgpr_fi{{$}}
-# GCN: %1 = IMPLICIT_DEF
-# GCN: %2 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %1:vgpr_32 = IMPLICIT_DEF
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
 name: fold_vgpr_fi
 tracksRegLiveness: true
 registers:
@@ -76,9 +76,9 @@ body:             |
 
 ...
 # GCN-LABEL: name: fold_sgpr_fi{{$}}
-# GCN: %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
-# GCN: %1 = IMPLICIT_DEF
-# GCN: %2 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+# GCN: %1:sgpr_32 = IMPLICIT_DEF
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
 name: fold_sgpr_fi
 tracksRegLiveness: true
 registers:
@@ -98,9 +98,9 @@ body:             |
 
 ...
 # GCN-LABEL: name: fold_fi_sgpr{{$}}
-# GCN: %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
-# GCN: %1 = IMPLICIT_DEF
-# GCN: %2 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+# GCN: %1:sgpr_32 = IMPLICIT_DEF
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %1, %0, implicit-def %vcc, implicit %exec
 name: fold_fi_sgpr
 tracksRegLiveness: true
 registers:
@@ -120,8 +120,8 @@ body:             |
 ...
 # TODO: Should probably prefer folding immediate first
 # GCN-LABEL: name: fold_fi_imm{{$}}
-# GCN: %1 = V_MOV_B32_e32 999, implicit %exec
-# GCN: %2 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 999, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
 name: fold_fi_imm
 tracksRegLiveness: true
 registers:
@@ -141,8 +141,8 @@ body:             |
 
 ...
 # GCN-LABEL: name: fold_imm_fi{{$}}
-# GCN: %0 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
-# GCN: %2 = V_ADD_I32_e32 999, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 %stack.0.alloca, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 999, %0, implicit-def %vcc, implicit %exec
 name: fold_imm_fi
 tracksRegLiveness: true
 registers:
diff --git a/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir b/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
index b4c0c93347c..a190324cdc2 100644
--- a/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
+++ b/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
@@ -1,8 +1,8 @@
 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
 ...
 # GCN-LABEL: name: fold_imm_non_ssa{{$}}
-# GCN: %0 = V_MOV_B32_e32 123, implicit %exec
-# GCN: %2 = V_ADD_I32_e32 456, %0, implicit-def %vcc, implicit %exec
+# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def %vcc, implicit %exec
 
 name: fold_imm_non_ssa
 tracksRegLiveness: true
@@ -21,8 +21,8 @@ body:             |
 
 ...
 # GCN-LABEL: name: fold_partially_defined_superreg{{$}}
-# GCN: %1 = V_MOV_B32_e32 456, implicit %exec
-# GCN: %2 = V_ADD_I32_e32 123, %1, implicit-def %vcc, implicit %exec
+# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit %exec
+# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def %vcc, implicit %exec
 name: fold_partially_defined_superreg
 tracksRegLiveness: true
 registers:
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
index 8f1d4d1d546..e2b6f878e6b 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
@@ -67,12 +67,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_eq_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -97,12 +97,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_ne_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -127,12 +127,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_ugt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -157,12 +157,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_uge_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 2, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -187,12 +187,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_ult_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 3, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -217,12 +217,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_ule_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -247,12 +247,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_sgt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -277,12 +277,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_sge_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -307,12 +307,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_slt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -337,12 +337,12 @@ body:             |
     liveins: %r0, %r1
 
     ; CHECK-LABEL: name: test_icmp_sle_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
@@ -367,8 +367,8 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_true_s32
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -393,8 +393,8 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_false_s32
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -419,13 +419,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_oeq_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -450,13 +450,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ogt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -481,13 +481,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_oge_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -512,13 +512,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_olt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -543,13 +543,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ole_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -574,13 +574,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ord_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -605,13 +605,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ugt_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -636,13 +636,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_uge_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -667,13 +667,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ult_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -698,13 +698,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ule_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -729,13 +729,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_une_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -760,13 +760,13 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_uno_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -791,16 +791,16 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_one_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -825,16 +825,16 @@ body:             |
     liveins: %s0, %s1
 
     ; CHECK-LABEL: name: test_fcmp_ueq_s32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
     ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
@@ -859,8 +859,8 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_true_s64
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -885,8 +885,8 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_false_s64
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -911,13 +911,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_oeq_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -942,13 +942,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ogt_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -973,13 +973,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_oge_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1004,13 +1004,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_olt_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1035,13 +1035,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ole_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1066,13 +1066,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ord_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1097,13 +1097,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ugt_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1128,13 +1128,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_uge_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1159,13 +1159,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ult_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1190,13 +1190,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ule_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1221,13 +1221,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_une_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1252,13 +1252,13 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_uno_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1283,16 +1283,16 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_one_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
@@ -1317,16 +1317,16 @@ body:             |
     liveins: %d0, %d1
 
     ; CHECK-LABEL: name: test_fcmp_ueq_s64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
-    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
     ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
     ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
-    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _
     ; CHECK: %r0 = COPY [[ANDri]]
     ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
index d7f208d4cf5..d96463f00c7 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
@@ -30,13 +30,13 @@ body:             |
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-    ; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+    ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_ADD %3, %2
-    ; CHECK: [[VREGR:%[0-9]+]] = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
@@ -64,13 +64,13 @@ body:             |
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-    ; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+    ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_ADD %3, %2
-    ; CHECK: [[VREGR:%[0-9]+]] = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
@@ -98,13 +98,13 @@ body:             |
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-    ; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
+    ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_SUB %2, %3
-    ; CHECK: [[VREGR:%[0-9]+]] = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
@@ -132,14 +132,14 @@ body:             |
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-    ; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
+    ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
 
     %3(s32) = G_MUL %0, %1
     %4(s32) = G_SUB %2, %3
-    ; CHECK: [[VREGM:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
-    ; CHECK: [[VREGR:%[0-9]+]] = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
+    ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
 
     %r0 = COPY %4(s32)
     ; CHECK: %r0 = COPY [[VREGR]]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index ee077390b53..0d3b10b48e1 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -65,13 +65,13 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ZEXT %1(s1)
-    ; CHECK: [[VREGEXT:%[0-9]+]] = ANDri [[VREGTRUNC]], 1, 14, _, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -95,14 +95,14 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_SEXT %1(s1)
-    ; CHECK: [[VREGAND:%[0-9]+]] = ANDri [[VREGTRUNC]], 1, 14, _, _
-    ; CHECK: [[VREGEXT:%[0-9]+]] = RSBri [[VREGAND]], 0, 14, _, _
+    ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -126,13 +126,13 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s8) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
 
     %2(s32) = G_SEXT %1(s8)
-    ; CHECK: [[VREGEXT:%[0-9]+]] = SXTB [[VREGTRUNC]], 0, 14, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -156,13 +156,13 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s16) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
 
     %2(s32) = G_ZEXT %1(s16)
-    ; CHECK: [[VREGEXT:%[0-9]+]] = UXTH [[VREGTRUNC]], 0, 14, _
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -186,13 +186,13 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s8) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ANYEXT %1(s8)
-    ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGTRUNC]]
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -216,13 +216,13 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREG:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s16) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]] = COPY [[VREG]]
+    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ANYEXT %1(s16)
-    ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGTRUNC]]
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
@@ -249,13 +249,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGSUM]]
@@ -282,13 +282,13 @@ body:             |
     liveins: %s0, %s1
 
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
+    ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
 
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
+    ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
 
     %2(s32) = G_FADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]] = VADDS [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, _
 
     %s0 = COPY %2(s32)
     ; CHECK: %s0 = COPY [[VREGSUM]]
@@ -315,13 +315,13 @@ body:             |
     liveins: %d0, %d1
 
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
+    ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
 
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
+    ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
 
     %2(s64) = G_FADD %0, %1
-    ; CHECK: [[VREGSUM:%[0-9]+]] = VADDD [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, _
 
     %d0 = COPY %2(s64)
     ; CHECK: %d0 = COPY [[VREGSUM]]
@@ -348,13 +348,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SUB %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -381,13 +381,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
 
     %2(s32) = G_MUL %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -414,13 +414,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
 
     %2(s32) = G_MUL %0, %1
-    ; CHECK: early-clobber [[VREGRES:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
+    ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -447,13 +447,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SDIV %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = SDIV [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -480,13 +480,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_UDIV %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = UDIV [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -513,13 +513,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_AND %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = ANDrr [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = ANDrr [[VREGX]], [[VREGY]], 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -546,13 +546,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_OR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = ORRrr [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = ORRrr [[VREGX]], [[VREGY]], 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -579,13 +579,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_XOR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = EORrr [[VREGX]], [[VREGY]], 14, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gpr = EORrr [[VREGX]], [[VREGY]], 14, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -612,13 +612,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_LSHR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -645,13 +645,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_ASHR %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -678,13 +678,13 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = G_SHL %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]] = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGRES]]
@@ -721,22 +721,22 @@ body:             |
     liveins: %r0, %r1, %r2, %r3
 
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
-    ; CHECK: [[FI32VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
+    ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, _, _
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
-    ; CHECK: [[LD32VREG:%[0-9]+]] = LDRi12 [[FI32VREG]], 0, 14, _
+    ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, _
 
     %r0 = COPY %1
     ; CHECK: %r0 = COPY [[LD32VREG]]
 
     %2(p0) = G_FRAME_INDEX %fixed-stack.0
-    ; CHECK: [[FI1VREG:%[0-9]+]] = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
+    ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, _, _
 
     %3(s1) = G_LOAD %2(p0) :: (load 1)
-    ; CHECK: [[LD1VREG:%[0-9]+]] = LDRBi12 [[FI1VREG]], 0, 14, _
+    ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, _
 
     %4(s32) = G_ANYEXT %3(s1)
-    ; CHECK: [[RES:%[0-9]+]] = COPY [[LD1VREG]]
+    ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
 
     %r0 = COPY %4
     ; CHECK: %r0 = COPY [[RES]]
@@ -763,7 +763,7 @@ body:             |
     %0(p0) = COPY %r0
 
     %1(s32) = G_LOAD %0(p0) :: (load 4)
-    ; CHECK: %[[V]] = VLDRS %[[P]], 0, 14, _
+    ; CHECK: %[[V]]:spr = VLDRS %[[P]], 0, 14, _
 
     %s0 = COPY %1
     ; CHECK: %s0 = COPY %[[V]]
@@ -790,7 +790,7 @@ body:             |
     %0(p0) = COPY %r0
 
     %1(s64) = G_LOAD %0(p0) :: (load 8)
-    ; CHECK: %[[V]] = VLDRD %[[P]], 0, 14, _
+    ; CHECK: %[[V]]:dpr = VLDRD %[[P]], 0, 14, _
 
     %d0 = COPY %1
     ; CHECK: %d0 = COPY %[[V]]
@@ -868,7 +868,7 @@ body:             |
     %1(s32) = COPY %r1
 
     %2(p0) = G_GEP %0, %1(s32)
-    ; CHECK: %[[GEP]] = ADDrr %[[PTR]], %[[OFF]], 14, _, _
+    ; CHECK: %[[GEP]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, _, _
 
     %r0 = COPY %2(p0)
     BX_RET 14, _, implicit %r0
@@ -886,7 +886,7 @@ registers:
 body:             |
   bb.0:
     %0(s32) = G_CONSTANT 42
-    ; CHECK: %[[C]] = MOVi 42, 14, _, _
+    ; CHECK: %[[C]]:gpr = MOVi 42, 14, _, _
 
     %r0 = COPY %0(s32)
     BX_RET 14, _, implicit %r0
@@ -906,7 +906,7 @@ body:             |
     ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
     ; We still want to see the same thing in the output though.
     %0(s32) = G_CONSTANT i32 42
-    ; CHECK: %[[C]] = MOVi 42, 14, _, _
+    ; CHECK: %[[C]]:gpr = MOVi 42, 14, _, _
 
     %r0 = COPY %0(s32)
     BX_RET 14, _, implicit %r0
@@ -928,17 +928,17 @@ body:             |
     liveins: %r0, %r1
 
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s1) = G_TRUNC %1(s32)
-    ; CHECK: [[VREGC:%[0-9]+]] = COPY [[VREGY]]
+    ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
 
     %3(s32) = G_SELECT %2(s1),  %0, %1
     ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
-    ; CHECK: [[RES:%[0-9]+]] = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+    ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[RES]]
@@ -963,17 +963,17 @@ body:             |
     liveins: %r0, %r1
 
     %0(p0) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(p0) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
+    ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s1) = G_TRUNC %1(p0)
-    ; CHECK: [[VREGC:%[0-9]+]] = COPY [[VREGY]]
+    ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
 
     %3(p0) = G_SELECT %2(s1),  %0, %1
     ; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr
-    ; CHECK: [[RES:%[0-9]+]] = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
+    ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %3(p0)
     ; CHECK: %r0 = COPY [[RES]]
@@ -998,9 +998,9 @@ body:             |
     liveins: %r0
 
     %0(s32) = COPY %r0
-    ; CHECK: [[COND32:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[COND:%[0-9]+]] = COPY [[COND32]]
+    ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]]
 
     G_BRCOND %1(s1), %bb.1
     ; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr
@@ -1044,16 +1044,16 @@ body:             |
     liveins: %r0, %r1, %r2, %r3
 
     %0(s32) = COPY %r2
-    ; CHECK: [[IN1:%[0-9]+]] = COPY %r2
+    ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY %r2
 
     %1(s32) = COPY %r3
-    ; CHECK: [[IN2:%[0-9]+]] = COPY %r3
+    ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY %r3
 
     %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
-    ; CHECK: %[[DREG]] = VMOVDRR [[IN1]], [[IN2]]
+    ; CHECK: %[[DREG]]:dpr = VMOVDRR [[IN1]], [[IN2]]
 
     %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
-    ; CHECK: [[OUT1:%[0-9]+]], [[OUT2:%[0-9]+]] = VMOVRRD %[[DREG]]
+    ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
 
     %r0 = COPY %3
     ; CHECK: %r0 = COPY [[OUT1]]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index da37f8bfe73..a7a731cf425 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -11,12 +11,12 @@ entry:
 define signext i1 @test_add_i1(i1 %x, i1 %y) {
 ; CHECK-LABEL: name: test_add_i1
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGX:%[0-9]+]](s1) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[VREGY:%[0-9]+]](s1) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]](s1) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[EXT:%[0-9]+]](s32) = G_SEXT [[SUM]]
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
+; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
 ; CHECK: %r0 = COPY [[EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -27,12 +27,12 @@ entry:
 define i8 @test_add_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: name: test_add_i8
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGX:%[0-9]+]](s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[VREGY:%[0-9]+]](s8) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[SUM_EXT:%[0-9]+]](s32) = G_ANYEXT [[SUM]]
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
+; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -43,12 +43,12 @@ entry:
 define i8 @test_sub_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: name: test_sub_i8
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGX:%[0-9]+]](s8) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[VREGY:%[0-9]+]](s8) = G_TRUNC [[VREGR1]]
-; CHECK: [[RES:%[0-9]+]](s8) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: [[RES_EXT:%[0-9]+]](s32) = G_ANYEXT [[RES]]
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
+; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
+; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -59,9 +59,9 @@ entry:
 define signext i8 @test_return_sext_i8(i8 %x) {
 ; CHECK-LABEL: name: test_return_sext_i8
 ; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[VREG:%[0-9]+]](s8) = G_TRUNC [[VREGR0]]
-; CHECK: [[VREGEXT:%[0-9]+]](s32) = G_SEXT [[VREG]]
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
+; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -71,12 +71,12 @@ entry:
 define i16 @test_add_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: name: test_add_i16
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGX:%[0-9]+]](s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[VREGY:%[0-9]+]](s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGX]], [[VREGY]]
-; CHECK: [[SUM_EXT:%[0-9]+]](s32) = G_ANYEXT [[SUM]]
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
+; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -87,12 +87,12 @@ entry:
 define i16 @test_sub_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: name: test_sub_i16
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGX:%[0-9]+]](s16) = G_TRUNC [[VREGR0]]
-; CHECK-DAG: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[VREGY:%[0-9]+]](s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[RES:%[0-9]+]](s16) = G_SUB [[VREGX]], [[VREGY]]
-; CHECK: [[RES_EXT:%[0-9]+]](s32) = G_ANYEXT [[RES]]
+; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
+; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
+; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
+; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
 ; CHECK: %r0 = COPY [[RES_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -103,9 +103,9 @@ entry:
 define zeroext i16 @test_return_zext_i16(i16 %x) {
 ; CHECK-LABEL: name: test_return_zext_i16
 ; CHECK: liveins: %r0
-; CHECK: [[VREGR0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[VREG:%[0-9]+]](s16) = G_TRUNC [[VREGR0]]
-; CHECK: [[VREGEXT:%[0-9]+]](s32) = G_ZEXT [[VREG]]
+; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
+; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
 ; CHECK: %r0 = COPY [[VREGEXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -115,9 +115,9 @@ entry:
 define i32 @test_add_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: name: test_add_i32
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGX]], [[VREGY]]
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
 ; CHECK: %r0 = COPY [[SUM]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -128,9 +128,9 @@ entry:
 define i32 @test_sub_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: name: test_sub_i32
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[VREGX:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGY:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[RES:%[0-9]+]](s32) = G_SUB [[VREGX]], [[VREGY]]
+; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
 ; CHECK: %r0 = COPY [[RES]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -144,10 +144,10 @@ define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5
 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP2:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]]{{.*}}load 4
-; CHECK: [[SUM:%[0-9]+]](s32) = G_ADD [[VREGP2]], [[VREGP5]]
+; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
+; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
+; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
 ; CHECK: %r0 = COPY [[SUM]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -162,13 +162,13 @@ define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[VREGP1:%[0-9]+]](s16) = G_TRUNC [[VREGR1]]
-; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5EXT:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
-; CHECK: [[VREGP5:%[0-9]+]](s16) = G_TRUNC [[VREGP5EXT]]
-; CHECK: [[SUM:%[0-9]+]](s16) = G_ADD [[VREGP1]], [[VREGP5]]
-; CHECK: [[SUM_EXT:%[0-9]+]](s32) = G_ANYEXT [[SUM]]
+; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
+; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
+; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
+; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]]
+; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
+; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -183,13 +183,13 @@ define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[VREGP2:%[0-9]+]](s8) = G_TRUNC [[VREGR2]]
-; CHECK: [[FIP4:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
-; CHECK: [[VREGP4EXT:%[0-9]+]](s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
-; CHECK: [[VREGP4:%[0-9]+]](s8) = G_TRUNC [[VREGP4EXT]]
-; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGP2]], [[VREGP4]]
-; CHECK: [[SUM_EXT:%[0-9]+]](s32) = G_ANYEXT [[SUM]]
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
+; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
+; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
+; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]]
+; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
+; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -204,12 +204,12 @@ define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGR2:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[VREGP2:%[0-9]+]](s8) = G_TRUNC [[VREGR2]]
-; CHECK: [[FIP4:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
-; CHECK: [[VREGP4:%[0-9]+]](s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
-; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[VREGP2]], [[VREGP4]]
-; CHECK: [[SUM_EXT:%[0-9]+]](s32) = G_ANYEXT [[SUM]]
+; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
+; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
+; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
+; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
+; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
 ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -224,10 +224,10 @@ define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2
 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5SEXT:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
-; CHECK: [[VREGP5:%[0-9]+]](s16) = G_TRUNC [[VREGP5SEXT]]
-; CHECK: [[VREGP5ZEXT:%[0-9]+]](s32) = G_ZEXT [[VREGP5]]
+; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
+; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
+; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
+; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
 ; CHECK: %r0 = COPY [[VREGP5ZEXT]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -237,8 +237,8 @@ entry:
 define i16 @test_ptr_arg(i16* %p) {
 ; CHECK-LABEL: name: test_ptr_arg
 ; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]](p0) = COPY %r0
-; CHECK: [[VREGV:%[0-9]+]](s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
 entry:
   %v = load i16, i16* %p
   ret i16 %v
@@ -248,8 +248,8 @@ define i32* @test_ptr_ret(i32** %p) {
 ; Test pointer returns and pointer-to-pointer arguments
 ; CHECK-LABEL: name: test_ptr_ret
 ; CHECK: liveins: %r0
-; CHECK: [[VREGP:%[0-9]+]](p0) = COPY %r0
-; CHECK: [[VREGV:%[0-9]+]](p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
 ; CHECK: %r0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -262,9 +262,9 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
 ; CHECK: fixedStack:
 ; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[FIP:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P]]
-; CHECK: [[VREGP:%[0-9]+]](p0) = G_LOAD [[FIP]](p0){{.*}}load 4
-; CHECK: [[VREGV:%[0-9]+]](s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
+; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
+; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
+; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
 ; CHECK: %r0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -279,10 +279,10 @@ define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
 ; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
 ; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
-; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGP5]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
+; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
+; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
 ; CHECK: %r0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -308,10 +308,10 @@ define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
 ; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15
-; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]](s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
-; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGQ1]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
+; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
+; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %s0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %s0
 entry:
@@ -329,10 +329,10 @@ define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double
 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
 ; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7
-; CHECK: [[VREGP1:%[0-9]+]](s64) = COPY %d1
-; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
-; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGQ1]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d1
+; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
+; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
+; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %d0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %d0
 entry:
@@ -349,15 +349,15 @@ define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p
 ; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 16{{.*}}size: 8
 ; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 24{{.*}}size: 8
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[VREGP1LO:%[0-9]+]](s32) = COPY %r2
-; CHECK-DAG: [[VREGP1HI:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[VREGP1:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
-; BIG: [[VREGP1:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
-; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
-; CHECK: [[VREGP5:%[0-9]+]](s64) = G_LOAD [[FIP5]](p0){{.*}}load 8
-; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGP5]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; CHECK-DAG: [[VREGP1LO:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[VREGP1HI:%[0-9]+]]:_(s32) = COPY %r3
+; LITTLE: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1LO]](s32), [[VREGP1HI]](s32)
+; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
+; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
+; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load 8
+; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
+; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -377,10 +377,10 @@ define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,
 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
 ; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2
-; CHECK: [[VREGP1:%[0-9]+]](s64) = COPY %d2
-; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
-; CHECK: [[VREGQ1:%[0-9]+]](s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
-; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP1]], [[VREGQ1]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d2
+; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
+; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
+; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
 ; CHECK: %d0 = COPY [[VREGV]]
 ; CHECK: BX_RET 14, _, implicit %d0
 entry:
@@ -394,15 +394,15 @@ define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,
 ; CHECK: fixedStack:
 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
 ; CHECK: liveins: %r0, %r2, %r3
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]](s32) = COPY %r2
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
-; BIG: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
-; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
-; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
-; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r3
+; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
+; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
+; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
+; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
+; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -417,15 +417,15 @@ define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,
 ; CHECK: fixedStack:
 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
 ; CHECK: liveins: %r0, %r1, %r2
-; CHECK-DAG: [[VREGP0LO:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[VREGP0HI:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
-; BIG: [[VREGP0:%[0-9]+]](s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
-; CHECK: [[FIP1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
-; CHECK: [[VREGP1:%[0-9]+]](s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
-; CHECK: [[VREGV:%[0-9]+]](s64) = G_FADD [[VREGP0]], [[VREGP1]]
-; LITTLE: [[VREGVLO:%[0-9]+]](s32), [[VREGVHI:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
-; BIG: [[VREGVHI:%[0-9]+]](s32), [[VREGVLO:%[0-9]+]](s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r1
+; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
+; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
+; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
+; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
+; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
+; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
+; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
 ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
 ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -438,7 +438,7 @@ define arm_aapcscc void @test_indirect_call(void() *%fptr) {
 ; CHECK-LABEL: name: test_indirect_call
 ; CHECK: registers:
 ; CHECK-NEXT: id: [[FPTR:[0-9]+]], class: gpr
-; CHECK: %[[FPTR]](p0) = COPY %r0
+; CHECK: %[[FPTR]]:gpr(p0) = COPY %r0
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
@@ -463,13 +463,13 @@ declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
 
 define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
 ; CHECK-LABEL: name: test_call_simple_reg_params
-; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
 ; CHECK-DAG: %r1 = COPY [[AVREG]]
 ; CHECK: BLX @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]](p0) = COPY %r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[RVREG]]
 ; CHECK: BX_RET 14, _, implicit %r0
@@ -482,23 +482,23 @@ declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32,
 
 define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
 ; CHECK-LABEL: name: test_call_simple_stack_params
-; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
-; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
 ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
 ; CHECK-DAG: %r1 = COPY [[AVREG]]
 ; CHECK-DAG: %r2 = COPY [[BVREG]]
 ; CHECK-DAG: %r3 = COPY [[AVREG]]
-; CHECK: [[SP1:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]](p0) = G_GEP [[SP1]], [[OFF1]](s32)
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[FI2:%[0-9]+]](p0) = G_GEP [[SP2]], [[OFF2]](s32)
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
 ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
 ; CHECK: BLX @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[RVREG:%[0-9]+]](p0) = COPY %r0
+; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
 ; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[RVREG]]
 ; CHECK: BX_RET 14, _, implicit %r0
@@ -511,51 +511,51 @@ declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext,
 
 define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
 ; CHECK-LABEL: name: test_call_ext_params
-; CHECK-DAG: [[R0VREG:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[AVREG:%[0-9]+]](s8) = G_TRUNC [[R0VREG]]
-; CHECK-DAG: [[R1VREG:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[BVREG:%[0-9]+]](s16) = G_TRUNC [[R1VREG]]
-; CHECK-DAG: [[R2VREG:%[0-9]+]](s32) = COPY %r2
-; CHECK-DAG: [[CVREG:%[0-9]+]](s1) = G_TRUNC [[R2VREG]]
+; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
+; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
+; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
 ; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[SEXTA:%[0-9]+]](s32) = G_SEXT [[AVREG]](s8)
+; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
 ; CHECK: %r0 = COPY [[SEXTA]]
-; CHECK: [[ZEXTA:%[0-9]+]](s32) = G_ZEXT [[AVREG]](s8)
+; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
 ; CHECK: %r1 = COPY [[ZEXTA]]
-; CHECK: [[SEXTB:%[0-9]+]](s32) = G_SEXT [[BVREG]](s16)
+; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
 ; CHECK: %r2 = COPY [[SEXTB]]
-; CHECK: [[ZEXTB:%[0-9]+]](s32) = G_ZEXT [[BVREG]](s16)
+; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
 ; CHECK: %r3 = COPY [[ZEXTB]]
-; CHECK: [[SP1:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]](p0) = G_GEP [[SP1]], [[OFF1]](s32)
-; CHECK: [[SEXTA2:%[0-9]+]](s32) = G_SEXT [[AVREG]]
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
+; CHECK: [[SEXTA2:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]]
 ; CHECK: G_STORE [[SEXTA2]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[FI2:%[0-9]+]](p0) = G_GEP [[SP2]], [[OFF2]](s32)
-; CHECK: [[ZEXTA2:%[0-9]+]](s32) = G_ZEXT [[AVREG]]
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
+; CHECK: [[ZEXTA2:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]]
 ; CHECK: G_STORE [[ZEXTA2]](s32), [[FI2]](p0){{.*}}store 4
-; CHECK: [[SP3:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF3:%[0-9]+]](s32) = G_CONSTANT i32 8
-; CHECK: [[FI3:%[0-9]+]](p0) = G_GEP [[SP3]], [[OFF3]](s32)
-; CHECK: [[SEXTB2:%[0-9]+]](s32) = G_SEXT [[BVREG]]
+; CHECK: [[SP3:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+; CHECK: [[FI3:%[0-9]+]]:_(p0) = G_GEP [[SP3]], [[OFF3]](s32)
+; CHECK: [[SEXTB2:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]]
 ; CHECK: G_STORE [[SEXTB2]](s32), [[FI3]](p0){{.*}}store 4
-; CHECK: [[SP4:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF4:%[0-9]+]](s32) = G_CONSTANT i32 12
-; CHECK: [[FI4:%[0-9]+]](p0) = G_GEP [[SP4]], [[OFF4]](s32)
-; CHECK: [[ZEXTB2:%[0-9]+]](s32) = G_ZEXT [[BVREG]]
+; CHECK: [[SP4:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+; CHECK: [[FI4:%[0-9]+]]:_(p0) = G_GEP [[SP4]], [[OFF4]](s32)
+; CHECK: [[ZEXTB2:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]]
 ; CHECK: G_STORE [[ZEXTB2]](s32), [[FI4]](p0){{.*}}store 4
-; CHECK: [[SP5:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF5:%[0-9]+]](s32) = G_CONSTANT i32 16
-; CHECK: [[FI5:%[0-9]+]](p0) = G_GEP [[SP5]], [[OFF5]](s32)
-; CHECK: [[ZEXTC:%[0-9]+]](s32) = G_ZEXT [[CVREG]]
+; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32)
+; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
 ; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
 ; CHECK: BLX @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-; CHECK: [[R0VREG:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[RVREG:%[0-9]+]](s16) = G_TRUNC [[R0VREG]]
+; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
 ; CHECK: ADJCALLSTACKUP 20, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[RExtVREG:%[0-9]+]](s32) = G_SEXT [[RVREG]]
+; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
 ; CHECK: %r0 = COPY [[RExtVREG]]
 ; CHECK: BX_RET 14, _, implicit %r0
 entry:
@@ -567,13 +567,13 @@ declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double)
 
 define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
 ; CHECK-LABEL: name: test_call_vfpcc_fp_params
-; CHECK-DAG: [[AVREG:%[0-9]+]](s64) = COPY %d0
-; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %s2
+; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %s0 = COPY [[BVREG]]
 ; CHECK-DAG: %d1 = COPY [[AVREG]]
 ; CHECK: BLX @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
-; CHECK: [[RVREG:%[0-9]+]](s64) = COPY %d0
+; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: %d0 = COPY [[RVREG]]
 ; CHECK: BX_RET 14, _, implicit %d0
@@ -586,33 +586,33 @@ declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double)
 
 define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
 ; CHECK-LABEL: name: test_call_aapcs_fp_params
-; CHECK-DAG: [[A1:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[A2:%[0-9]+]](s32) = COPY %r1
-; LITTLE-DAG: [[AVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
-; BIG-DAG: [[AVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
-; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r2
+; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1
+; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
+; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
+; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
 ; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK-DAG: %r0 = COPY [[BVREG]]
-; CHECK-DAG: [[A1:%[0-9]+]](s32), [[A2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[AVREG]](s64)
+; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
 ; LITTLE-DAG: %r2 = COPY [[A1]]
 ; LITTLE-DAG: %r3 = COPY [[A2]]
 ; BIG-DAG: %r2 = COPY [[A2]]
 ; BIG-DAG: %r3 = COPY [[A1]]
-; CHECK: [[SP1:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF1:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[FI1:%[0-9]+]](p0) = G_GEP [[SP1]], [[OFF1]](s32)
+; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
-; CHECK: [[SP2:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF2:%[0-9]+]](s32) = G_CONSTANT i32 8
-; CHECK: [[FI2:%[0-9]+]](p0) = G_GEP [[SP2]], [[OFF2]](s32)
+; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
 ; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
 ; CHECK: BLX @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[RVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
-; BIG: [[RVREG:%[0-9]+]](s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
+; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
+; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
 ; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RVREG]](s64)
+; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
 ; LITTLE-DAG: %r0 = COPY [[R1]]
 ; LITTLE-DAG: %r1 = COPY [[R2]]
 ; BIG-DAG: %r0 = COPY [[R2]]
@@ -627,11 +627,11 @@ declare arm_aapcscc float @different_call_conv_target(float)
 
 define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
 ; CHECK-LABEL: name: test_call_different_call_conv
-; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
+; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: %r0 = COPY [[X]]
 ; CHECK: BLX @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
-; CHECK: [[R:%[0-9]+]](s32) = COPY %r0
+; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
 ; CHECK: %s0 = COPY [[R]]
 ; CHECK: BX_RET 14, _, implicit %s0
@@ -645,20 +645,20 @@ declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
 define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
 ; CHECK-LABEL: name: test_tiny_int_arrays
 ; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[ARG_ARR:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[RES_ARR:%[0-9]+]](s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
 ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
 ; that composite types larger than 4 bytes should be passed through memory),
 ; but it's what DAGISel does. We should fix it in the common code for both.
@@ -676,15 +676,15 @@ declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
 define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
 ; CHECK-LABEL: name: test_multiple_int_arrays
 ; CHECK: liveins: %r0, %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[R3:%[0-9]+]](s32) = COPY %r3
-; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
-; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
+; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
-; CHECK: [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
+; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: %r2 = COPY [[R2]]
@@ -707,30 +707,30 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
 ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3
-; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[ARG_ARR:%[0-9]+]](s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
 ; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32), [[FIRST_STACK_ELEMENT:%[0-9]+]](s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: %r2 = COPY [[R2]]
 ; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
 ; Match the second-to-last offset, so we can get the correct SP for the last element
 ; CHECK: G_CONSTANT i32 56
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 60
-; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
+; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
 ; CHECK: BLX @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
 ; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp
@@ -747,39 +747,39 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
 ; CHECK: fixedStack:
 ; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK: [[ARR0_0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[ARR0_1:%[0-9]+]](s32) = COPY %r1
-; LITTLE: [[ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
-; BIG: [[ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[ARR1_1:%[0-9]+]](s32) = COPY %r3
-; LITTLE: [[ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
-; BIG: [[ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
-; CHECK: [[ARR2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
-; CHECK: [[ARR2:%[0-9]+]](s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
-; CHECK: [[ARR_MERGED:%[0-9]+]](s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
+; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1
+; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
+; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
+; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3
+; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
+; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
+; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
+; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
+; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
 ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[ARR0:%[0-9]+]](s64), [[ARR1:%[0-9]+]](s64), [[ARR2:%[0-9]+]](s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
-; CHECK: [[ARR0_0:%[0-9]+]](s32), [[ARR0_1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARR0]](s64)
+; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
+; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
 ; LITTLE: %r0 = COPY [[ARR0_0]](s32)
 ; LITTLE: %r1 = COPY [[ARR0_1]](s32)
 ; BIG: %r0 = COPY [[ARR0_1]](s32)
 ; BIG: %r1 = COPY [[ARR0_0]](s32)
-; CHECK: [[ARR1_0:%[0-9]+]](s32), [[ARR1_1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARR1]](s64)
+; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
 ; LITTLE: %r2 = COPY [[ARR1_0]](s32)
 ; LITTLE: %r3 = COPY [[ARR1_1]](s32)
 ; BIG: %r2 = COPY [[ARR1_1]](s32)
 ; BIG: %r3 = COPY [[ARR1_0]](s32)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[ARR2_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[ARR2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
 ; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
 ; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[R_MERGED:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
 ; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -798,57 +798,57 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3
 ; CHECK-DAG: id: [[Z2_ID:[0-9]+]], type: default, offset: 16, size: 8,
 ; CHECK-DAG: id: [[Z3_ID:[0-9]+]], type: default, offset: 24, size: 8,
 ; CHECK: liveins: %d0, %d1, %d2, %s6, %s7, %s8
-; CHECK: [[X0:%[0-9]+]](s64) = COPY %d0
-; CHECK: [[X1:%[0-9]+]](s64) = COPY %d1
-; CHECK: [[X2:%[0-9]+]](s64) = COPY %d2
-; CHECK: [[Y0:%[0-9]+]](s32) = COPY %s6
-; CHECK: [[Y1:%[0-9]+]](s32) = COPY %s7
-; CHECK: [[Y2:%[0-9]+]](s32) = COPY %s8
-; CHECK: [[Z0_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
-; CHECK: [[Z0:%[0-9]+]](s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
-; CHECK: [[Z1_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
-; CHECK: [[Z1:%[0-9]+]](s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
-; CHECK: [[Z2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
-; CHECK: [[Z2:%[0-9]+]](s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
-; CHECK: [[Z3_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
-; CHECK: [[Z3:%[0-9]+]](s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
-; CHECK: [[X_ARR:%[0-9]+]](s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
-; CHECK: [[Y_ARR:%[0-9]+]](s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
-; CHECK: [[Z_ARR:%[0-9]+]](s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
+; CHECK: [[X0:%[0-9]+]]:_(s64) = COPY %d0
+; CHECK: [[X1:%[0-9]+]]:_(s64) = COPY %d1
+; CHECK: [[X2:%[0-9]+]]:_(s64) = COPY %d2
+; CHECK: [[Y0:%[0-9]+]]:_(s32) = COPY %s6
+; CHECK: [[Y1:%[0-9]+]]:_(s32) = COPY %s7
+; CHECK: [[Y2:%[0-9]+]]:_(s32) = COPY %s8
+; CHECK: [[Z0_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z0_ID]]
+; CHECK: [[Z0:%[0-9]+]]:_(s64) = G_LOAD [[Z0_FI]]{{.*}}load 8
+; CHECK: [[Z1_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z1_ID]]
+; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
+; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
+; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
+; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
+; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
+; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
+; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
+; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
 ; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[X0:%[0-9]+]](s64), [[X1:%[0-9]+]](s64), [[X2:%[0-9]+]](s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
-; CHECK: [[Y0:%[0-9]+]](s32), [[Y1:%[0-9]+]](s32), [[Y2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
-; CHECK: [[Z0:%[0-9]+]](s64), [[Z1:%[0-9]+]](s64), [[Z2:%[0-9]+]](s64), [[Z3:%[0-9]+]](s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
+; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
+; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
+; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
 ; CHECK: %d0 = COPY [[X0]](s64)
 ; CHECK: %d1 = COPY [[X1]](s64)
 ; CHECK: %d2 = COPY [[X2]](s64)
 ; CHECK: %s6 = COPY [[Y0]](s32)
 ; CHECK: %s7 = COPY [[Y1]](s32)
 ; CHECK: %s8 = COPY [[Y2]](s32)
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[Z0_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[Z0_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[Z0_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[Z0_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z0_OFFSET]](s32)
 ; CHECK: G_STORE [[Z0]](s64), [[Z0_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[Z1_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 8
-; CHECK: [[Z1_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[Z1_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+; CHECK: [[Z1_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z1_OFFSET]](s32)
 ; CHECK: G_STORE [[Z1]](s64), [[Z1_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[Z2_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 16
-; CHECK: [[Z2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[Z2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+; CHECK: [[Z2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z2_OFFSET]](s32)
 ; CHECK: G_STORE [[Z2]](s64), [[Z2_ADDR]](p0){{.*}}store 8
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[Z3_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 24
-; CHECK: [[Z3_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[Z3_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
 ; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
 ; CHECK: BLX @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %s0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %s1
-; CHECK: [[R2:%[0-9]+]](s32) = COPY %s2
-; CHECK: [[R3:%[0-9]+]](s32) = COPY %s3
-; CHECK: [[R_MERGED:%[0-9]+]](s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1
+; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
+; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
+; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
 ; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
 ; CHECK: %s0 = COPY [[R0]]
 ; CHECK: %s1 = COPY [[R1]]
 ; CHECK: %s2 = COPY [[R2]]
@@ -869,37 +869,37 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
 ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
 ; CHECK: liveins: %r0, %r1, %r2, %r3
-; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[R2:%[0-9]+]](s32) = COPY %r2
-; CHECK-DAG: [[R3:%[0-9]+]](s32) = COPY %r3
-; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
-; CHECK: [[ARG_ARR:%[0-9]+]](s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
+; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
+; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
 ; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32), [[FIRST_STACK_ELEMENT:%[0-9]+]](s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: %r2 = COPY [[R2]]
 ; CHECK: %r3 = COPY [[R3]]
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
 ; Match the second-to-last offset, so we can get the correct SP for the last element
 ; CHECK: G_CONSTANT i32 72
-; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
-; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 76
-; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
+; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
+; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
+; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
 ; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[RES_ARR:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
 ; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
 ; CHECK: %r0 = COPY [[R0]]
 ; CHECK: %r1 = COPY [[R1]]
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -913,19 +913,19 @@ declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
 define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
 ; CHECK-LABEL: test_structs
 ; CHECK: liveins: %r0, %r1
-; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
 ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[X0:%[0-9]+]](s32), [[X1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[X]](s64)
+; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
 ; CHECK-DAG: %r0 = COPY [[X0]](s32)
 ; CHECK-DAG: %r1 = COPY [[X1]](s32)
 ; CHECK: BLX @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[R:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
+; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
 ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
-; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R]](s64)
+; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
 ; CHECK: %r0 = COPY [[R0]](s32)
 ; CHECK: %r1 = COPY [[R1]](s32)
 ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
@@ -935,11 +935,11 @@ define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
 
 define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
-; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0
-; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
   %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
   %shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
@@ -949,15 +949,15 @@ define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
 
 define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
-; CHECK-DAG: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
+; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
+; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
   %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
   %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
@@ -969,15 +969,15 @@ define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
 
 define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32)
-; CHECK-DAG: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<4 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32)
+; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
+; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<4 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>)
   %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
   %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
@@ -988,21 +988,21 @@ define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
 
 define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
 ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
-; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
-; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
-; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %r2
-; CHECK: [[ARG4:%[0-9]+]](s32) = COPY %r3
-; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = G_IMPLICIT_DEF
-; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
-; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK-DAG: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
-; CHECK-DAG: [[V1:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
-; CHECK-DAG: [[V2:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
-; CHECK-DAG: [[V3:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)
-; CHECK-DAG: [[V4:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
+; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %r0
+; CHECK: [[ARG2:%[0-9]+]]:_(s32) = COPY %r1
+; CHECK: [[ARG3:%[0-9]+]]:_(s32) = COPY %r2
+; CHECK: [[ARG4:%[0-9]+]]:_(s32) = COPY %r3
+; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
+; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK-DAG: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
+; CHECK-DAG: [[V1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
+; CHECK-DAG: [[V2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
+; CHECK-DAG: [[V3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)
+; CHECK-DAG: [[V4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
   %v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0
   %v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1
@@ -1017,9 +1017,9 @@ define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32
 
 define i32 @test_constantstruct_v2s32() {
 ; CHECK-LABEL: name: test_constantstruct_v2s32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
 ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
   %vec = extractvalue %struct.v2s32 {<2 x i32><i32 1, i32 2>}, 0
   %elt = extractelement <2 x i32> %vec, i32 0
@@ -1030,16 +1030,16 @@ define i32 @test_constantstruct_v2s32() {
 
 define i32 @test_constantstruct_v2s32_s32_s32() {
 ; CHECK-LABEL: name: test_constantstruct_v2s32_s32_s32
-; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
-; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
-; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
-; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
-; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
-; CHECK: [[C5:%[0-9]+]](s128) = G_IMPLICIT_DEF
-; CHECK: [[C6:%[0-9]+]](s128) = G_INSERT [[C5]], [[VEC]](<2 x s32>), 0
-; CHECK: [[C7:%[0-9]+]](s128) = G_INSERT [[C6]], [[C3]](s32), 64
-; CHECK: [[C8:%[0-9]+]](s128) = G_INSERT [[C7]], [[C4]](s32), 96
-; CHECK: [[EXT:%[0-9]+]](<2 x s32>) = G_EXTRACT [[C8]](s128), 0
+; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
+; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+; CHECK: [[C5:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
+; CHECK: [[C6:%[0-9]+]]:_(s128) = G_INSERT [[C5]], [[VEC]](<2 x s32>), 0
+; CHECK: [[C7:%[0-9]+]]:_(s128) = G_INSERT [[C6]], [[C3]](s32), 64
+; CHECK: [[C8:%[0-9]+]]:_(s128) = G_INSERT [[C7]], [[C4]](s32), 96
+; CHECK: [[EXT:%[0-9]+]]:_(<2 x s32>) = G_EXTRACT [[C8]](s128), 0
 ; CHECK: G_EXTRACT_VECTOR_ELT [[EXT]](<2 x s32>)
   %vec = extractvalue %struct.v2s32.s32.s32 {<2 x i32><i32 1, i32 2>, i32 3, i32 4}, 0
   %elt = extractelement <2 x i32> %vec, i32 0
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
index 337510ccfe2..5fee943423e 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
@@ -37,19 +37,19 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; HWDIV: [[R:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]]
+    ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
     ; SOFT-NOT: G_SDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SDIV
     %2(s32) = G_SDIV %0, %1
@@ -73,19 +73,19 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; HWDIV: [[R:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]]
+    ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
     ; SOFT-NOT: G_UDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UDIV
     %2(s32) = G_UDIV %0, %1
@@ -112,35 +112,35 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s16) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s16) = G_TRUNC %2(s32)
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
     ; SOFT-NOT: G_SDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SDIV
-    ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R16]]
+    ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]]
     ; SOFT-NOT: G_SDIV
     %4(s16) = G_SDIV %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -167,33 +167,33 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s16) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s16) = G_TRUNC %2(s32)
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
     ; SOFT-NOT: G_UDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UDIV
-    ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R16]]
+    ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]]
     ; SOFT-NOT: G_UDIV
     %4(s16) = G_UDIV %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -220,35 +220,35 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s8) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s8) = G_TRUNC %2(s32)
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
     ; SOFT-NOT: G_SDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SDIV
-    ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R8]]
+    ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]]
     ; SOFT-NOT: G_SDIV
     %4(s8) = G_SDIV %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -275,33 +275,33 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s8) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s8) = G_TRUNC %2(s32)
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
     ; SOFT-NOT: G_UDIV
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UDIV
-    ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R8]]
+    ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]]
     ; SOFT-NOT: G_UDIV
     %4(s8) = G_UDIV %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -325,21 +325,21 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; HWDIV: [[Q:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]]
-    ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]]
-    ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]]
+    ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_SDIV [[X]], [[Y]]
+    ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
+    ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
     ; SOFT-NOT: G_SREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-    ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SREM
     %2(s32) = G_SREM %0, %1
@@ -363,21 +363,21 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; HWDIV: [[Q:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]]
-    ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]]
-    ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]]
+    ; HWDIV: [[Q:%[0-9]+]]:_(s32) = G_UDIV [[X]], [[Y]]
+    ; HWDIV: [[P:%[0-9]+]]:_(s32) = G_MUL [[Q]], [[Y]]
+    ; HWDIV: [[R:%[0-9]+]]:_(s32) = G_SUB [[X]], [[P]]
     ; SOFT-NOT: G_UREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
-    ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UREM
     %2(s32) = G_UREM %0, %1
@@ -404,37 +404,37 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 16
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s16) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s16) = G_TRUNC %2(s32)
-    ; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
-    ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
+    ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
+    ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
     ; SOFT-NOT: G_SREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SREM
-    ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R16]]
+    ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]]
     ; SOFT-NOT: G_SREM
     %4(s16) = G_SREM %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -461,35 +461,35 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 65535
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s16) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s16) = G_TRUNC %2(s32)
-    ; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
-    ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
+    ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
+    ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
     ; SOFT-NOT: G_UREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UREM
-    ; CHECK: [[R16:%[0-9]+]](s16) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R16]]
+    ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]]
     ; SOFT-NOT: G_UREM
     %4(s16) = G_UREM %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -516,37 +516,37 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[SHIFTEDX:%[0-9]+]](s32) = G_SHL [[X]], [[BITS]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 24
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[SHIFTEDY:%[0-9]+]](s32) = G_SHL [[Y]], [[BITS]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s8) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s8) = G_TRUNC %2(s32)
-    ; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
-    ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
+    ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_SDIV [[X32]], [[Y32]]
+    ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
     ; SOFT-NOT: G_SREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_SREM
-    ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_SEXT [[R8]]
+    ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]]
     ; SOFT-NOT: G_SREM
     %4(s8) = G_SREM %1, %3
     ; CHECK: %r0 = COPY [[R]]
@@ -573,35 +573,35 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[R0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[R1:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
     ; The G_TRUNC will combine with the extensions introduced by the legalizer,
     ; leading to the following complicated sequences.
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[X:%[0-9]+]](s32) = COPY [[R0]]
-    ; CHECK: [[X32:%[0-9]+]](s32) = G_AND [[X]], [[BITS]]
-    ; CHECK: [[BITS:%[0-9]+]](s32) = G_CONSTANT i32 255
-    ; CHECK: [[Y:%[0-9]+]](s32) = COPY [[R1]]
-    ; CHECK: [[Y32:%[0-9]+]](s32) = G_AND [[Y]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
+    ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
+    ; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
+    ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
     %0(s32) = COPY %r0
     %1(s8) = G_TRUNC %0(s32)
     %2(s32) = COPY %r1
     %3(s8) = G_TRUNC %2(s32)
-    ; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
-    ; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
-    ; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
+    ; HWDIV: [[Q32:%[0-9]+]]:_(s32) = G_UDIV [[X32]], [[Y32]]
+    ; HWDIV: [[P32:%[0-9]+]]:_(s32) = G_MUL [[Q32]], [[Y32]]
+    ; HWDIV: [[R32:%[0-9]+]]:_(s32) = G_SUB [[X32]], [[P32]]
     ; SOFT-NOT: G_UREM
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X32]]
     ; SOFT-DAG: %r1 = COPY [[Y32]]
     ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
+    ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY %r1
     ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
+    ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_UREM
-    ; CHECK: [[R8:%[0-9]+]](s8) = G_TRUNC [[R32]]
-    ; CHECK: [[R:%[0-9]+]](s32) = G_ZEXT [[R8]]
+    ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
+    ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]]
     ; SOFT-NOT: G_UREM
     %4(s8) = G_UREM %1, %3
     ; CHECK: %r0 = COPY [[R]]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 8ef1c065822..d3ee1639033 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -65,8 +65,8 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     ; CHECK-NOT: G_FREM
@@ -77,8 +77,8 @@ body:             |
     ; HARD-DAG: %s1 = COPY [[Y]]
     ; SOFT: BLX $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; HARD: BLX $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
-    ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
-    ; HARD: [[R:%[0-9]+]](s32) = COPY %s0
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+    ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
     ; CHECK: ADJCALLSTACKUP
     ; CHECK-NOT: G_FREM
     %2(s32) = G_FREM %0, %1
@@ -114,16 +114,16 @@ body:             |
     ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
     ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
     ; For hard float, the values need to end up in D0 and D1.
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
     %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
     %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
     ; CHECK-NOT: G_FREM
@@ -160,8 +160,8 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     ; CHECK-NOT: G_FPOW
@@ -172,8 +172,8 @@ body:             |
     ; HARD-DAG: %s1 = COPY [[Y]]
     ; SOFT: BLX $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; HARD: BLX $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
-    ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
-    ; HARD: [[R:%[0-9]+]](s32) = COPY %s0
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+    ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
     ; CHECK: ADJCALLSTACKUP
     ; CHECK-NOT: G_FPOW
     %2(s32) = G_FPOW %0, %1
@@ -209,16 +209,16 @@ body:             |
     ; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
     ; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
     ; For hard float, the values need to end up in D0 and D1.
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
     %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
     %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
     ; CHECK-NOT: G_FPOW
@@ -255,18 +255,18 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; HARD: [[R:%[0-9]+]](s32) = G_FADD [[X]], [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s32) = G_FADD [[X]], [[Y]]
     ; SOFT-NOT: G_FADD
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
     ; SOFT-NOT: G_FADD
     %2(s32) = G_FADD %0, %1
@@ -296,19 +296,19 @@ body:             |
   bb.0:
     liveins: %r0, %r1, %r2, %r3
 
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
     %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
     %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
-    ; HARD: [[R:%[0-9]+]](s64) = G_FADD [[X]], [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s64) = G_FADD [[X]], [[Y]]
     ; SOFT-NOT: G_FADD
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
@@ -345,16 +345,16 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(true), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -378,16 +378,16 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(false), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -411,24 +411,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -452,24 +452,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -493,24 +493,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -534,24 +534,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -575,24 +575,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -616,23 +616,23 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -656,24 +656,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -697,24 +697,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -738,24 +738,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -779,24 +779,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -820,24 +820,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(une), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -861,24 +861,24 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -902,39 +902,39 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(one), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
-    ; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
-    ; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
-    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
-    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
+    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
+    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
+    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -958,39 +958,39 @@ body:             |
 
     %0(s32) = COPY %r0
     %1(s32) = COPY %r1
-    ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
+    ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
     %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X]]
     ; SOFT-DAG: %r1 = COPY [[Y]]
     ; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
-    ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
-    ; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
-    ; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
-    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
-    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
+    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
+    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
+    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
     ; SOFT-NOT: G_FCMP
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1020,22 +1020,22 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(true), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1065,22 +1065,22 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(false), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1110,16 +1110,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1128,14 +1128,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1165,16 +1165,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1183,14 +1183,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1220,16 +1220,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(oge), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1238,14 +1238,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1275,16 +1275,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(olt), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1293,14 +1293,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1330,16 +1330,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ole), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1348,14 +1348,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1385,16 +1385,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ord), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1403,13 +1403,13 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1439,16 +1439,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ugt), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1457,14 +1457,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1494,16 +1494,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(uge), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1512,14 +1512,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1549,16 +1549,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ult), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1567,14 +1567,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1604,16 +1604,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ule), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1622,14 +1622,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1659,16 +1659,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(une), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1677,14 +1677,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+    ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1714,16 +1714,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(uno), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1732,14 +1732,14 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1769,16 +1769,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(one), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1787,10 +1787,10 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1799,19 +1799,19 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
-    ; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
-    ; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
-    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
-    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
+    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
+    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
+    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
@@ -1841,16 +1841,16 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = COPY %r2
     %3(s32) = COPY %r3
-    ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
-    ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
-    ; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
-    ; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
+    ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+    ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+    ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+    ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
     %4(s64) = G_MERGE_VALUES %0(s32), %1
     %5(s64) = G_MERGE_VALUES %2(s32), %3
-    ; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
-    ; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
+    ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
+    ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
     %6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
-    ; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
+    ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1859,10 +1859,10 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET1:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
     ; SOFT-NOT: G_FCMP
     ; SOFT: ADJCALLSTACKDOWN
     ; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1871,19 +1871,19 @@ body:             |
     ; SOFT-DAG: %r3 = COPY [[Y1]]
     ; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
     ; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
-    ; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
+    ; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY %r0
     ; SOFT: ADJCALLSTACKUP
-    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
-    ; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
-    ; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
-    ; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
-    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
-    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
-    ; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
-    ; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
+    ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
+    ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
+    ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
+    ; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
+    ; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
+    ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+    ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
     ; SOFT-NOT: G_FCMP
     %7(s32) = G_ZEXT %6(s1)
-    ; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
+    ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
     %r0 = COPY %7(s32)
     ; CHECK: %r0 = COPY [[REXT]]
     BX_RET 14, _, implicit %r0
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index c54dbc801a5..1d9b1294c0e 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -74,7 +74,7 @@ body:             |
     %0(s8) = G_CONSTANT i8 42
     %1(s32) = G_SEXT %0
     ; G_SEXT with s8 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_SEXT {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
     %r0 = COPY %1(s32)
     BX_RET 14, _, implicit %r0
 ...
@@ -96,7 +96,7 @@ body:             |
     %0(s16) = G_CONSTANT i16 42
     %1(s32) = G_ZEXT %0
     ; G_ZEXT with s16 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_ZEXT {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
     %r0 = COPY %1(s32)
     BX_RET 14, _, implicit %r0
 ...
@@ -121,9 +121,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 30
     %2(s8) = G_ADD %0, %1
     ; G_ADD with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -149,9 +149,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 10
     %2(s16) = G_ADD %0, %1
     ; G_ADD with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -177,7 +177,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_ADD %0, %1
     ; G_ADD with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -203,9 +203,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 6
     %2(s8) = G_SUB %0, %1
     ; G_SUB with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -231,9 +231,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 16
     %2(s16) = G_SUB %0, %1
     ; G_SUB with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -259,7 +259,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_SUB %0, %1
     ; G_SUB with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -285,9 +285,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 6
     %2(s8) = G_MUL %0, %1
     ; G_MUL with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -313,9 +313,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 14
     %2(s16) = G_MUL %0, %1
     ; G_MUL with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -341,7 +341,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_MUL %0, %1
     ; G_MUL with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -367,9 +367,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 58
     %2(s8) = G_AND %0, %1
     ; G_AND with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -395,9 +395,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 106
     %2(s16) = G_AND %0, %1
     ; G_AND with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -423,7 +423,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_AND %0, %1
     ; G_AND with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_AND {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -449,9 +449,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 10
     %2(s8) = G_OR %0, %1
     ; G_OR with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -477,9 +477,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 10
     %2(s16) = G_OR %0, %1
     ; G_OR with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -505,7 +505,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_OR %0, %1
     ; G_OR with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_OR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -531,9 +531,9 @@ body:             |
     %1(s8) = G_CONSTANT i8 32
     %2(s8) = G_XOR %0, %1
     ; G_XOR with s8 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s8)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -559,9 +559,9 @@ body:             |
     %1(s16) = G_CONSTANT i16 2
     %2(s16) = G_XOR %0, %1
     ; G_XOR with s16 should widen
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
-    ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
     %3(s32) = G_SEXT %2(s16)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -587,7 +587,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_XOR %0, %1
     ; G_XOR with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -612,7 +612,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_LSHR %0, %1
     ; G_LSHR with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -637,7 +637,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_ASHR %0, %1
     ; G_ASHR with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -662,7 +662,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_SHL %0, %1
     ; G_SHL with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -690,8 +690,8 @@ body:             |
     liveins: %r0, %r1, %r2, %r3
 
     ; This is legal, so we should find it unchanged in the output
-    ; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
-    ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
+    ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
     %0(p0) = G_FRAME_INDEX %fixed-stack.2
     %1(s32) = G_LOAD %0(p0) :: (load 4)
     BX_RET 14, _
@@ -717,12 +717,12 @@ body:             |
     liveins: %r0, %r1, %r2, %r3
 
     ; These are all legal, so we should find them unchanged in the output
-    ; CHECK-DAG: {{%[0-9]+}}(s64) = G_LOAD %0
-    ; CHECK-DAG: {{%[0-9]+}}(s32) = G_LOAD %0
-    ; CHECK-DAG: {{%[0-9]+}}(s16) = G_LOAD %0
-    ; CHECK-DAG: {{%[0-9]+}}(s8) = G_LOAD %0
-    ; CHECK-DAG: {{%[0-9]+}}(s1) = G_LOAD %0
-    ; CHECK-DAG: {{%[0-9]+}}(p0) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(s64) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0
+    ; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0
     %0(p0) = COPY %r0
     %1(s32) = G_LOAD %0(p0) :: (load 4)
     %2(s16) = G_LOAD %0(p0) :: (load 2)
@@ -793,7 +793,7 @@ body:             |
     %0(p0) = COPY %r0
     %1(s32) = COPY %r1
 
-    ; CHECK: {{%[0-9]+}}(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
     %2(p0) = G_GEP %0, %1(s32)
 
     %r0 = COPY %2(p0)
@@ -815,24 +815,24 @@ registers:
 body:             |
   bb.0:
     %0(s32) = G_CONSTANT 42
-    ; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT 42
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
 
     %1(s16) = G_CONSTANT i16 21
     ; CHECK-NOT: G_CONSTANT i16
-    ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 21
-    ; CHECK: {{%[0-9]+}}(s16) = G_TRUNC [[EXT]](s32)
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+    ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i16
 
     %2(s8) = G_CONSTANT i8 10
     ; CHECK-NOT: G_CONSTANT i8
-    ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 10
-    ; CHECK: {{%[0-9]+}}(s8) = G_TRUNC [[EXT]](s32)
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+    ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i8
 
     %3(s1) = G_CONSTANT i1 1
     ; CHECK-NOT: G_CONSTANT i1
-    ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
-    ; CHECK: {{%[0-9]+}}(s1) = G_TRUNC [[EXT]](s32)
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
     ; CHECK-NOT: G_CONSTANT i1
 
     %r0 = COPY %0(s32)
@@ -859,8 +859,8 @@ body:             |
     %1(s8) = G_CONSTANT i8 43
     %2(s1) = G_ICMP intpred(ne), %0(s8), %1
     ; G_ICMP with s8 should widen
-    ; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -886,8 +886,8 @@ body:             |
     %1(s16) = G_CONSTANT i16 46
     %2(s1) = G_ICMP intpred(slt), %0(s16), %1
     ; G_ICMP with s16 should widen
-    ; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -913,7 +913,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s1) = G_ICMP intpred(eq), %0(s32), %1
     ; G_ICMP with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
@@ -940,7 +940,7 @@ body:             |
     %2(s1) = G_CONSTANT i1 1
     %3(s32) = G_SELECT %2(s1), %0, %1
     ; G_SELECT with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
 ...
@@ -966,7 +966,7 @@ body:             |
     %2(s1) = G_CONSTANT i1 0
     %3(p0) = G_SELECT %2(s1), %0, %1
     ; G_SELECT with p0 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
     %r0 = COPY %3(p0)
     BX_RET 14, _, implicit %r0
 ...
@@ -1024,7 +1024,7 @@ body:             |
     %1(s32) = COPY %r1
     %2(s32) = G_FADD %0, %1
     ; G_FADD with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s32) = G_FADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_FADD {{%[0-9]+, %[0-9]+}}
     %r0 = COPY %2(s32)
     BX_RET 14, _, implicit %r0
 
@@ -1049,7 +1049,7 @@ body:             |
     %1(s64) = COPY %d1
     %2(s64) = G_FADD %0, %1
     ; G_FADD with s64 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(s64) = G_FADD {{%[0-9]+, %[0-9]+}}
+    ; CHECK: {{%[0-9]+}}:_(s64) = G_FADD {{%[0-9]+, %[0-9]+}}
     %d0 = COPY %2(s64)
     BX_RET 14, _, implicit %d0
 
@@ -1072,7 +1072,7 @@ body:             |
     %0(s32) = COPY %r0
     %1(p0) = G_GLOBAL_VALUE @a_global
     ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}(p0) = G_GLOBAL_VALUE @a_global
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global
     %r0 = COPY %1(p0)
     BX_RET 14, _, implicit %r0
 
diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
index dacd227df62..3ef1b61211c 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir
@@ -28,12 +28,12 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel {{.*}}@internal_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel {{.*}}@internal_global
-    ; ELF: [[G:%[0-9]+]] = LDRLIT_ga_pcrel {{.*}}@internal_global
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_global
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
+    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -54,12 +54,12 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_global
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel_ldr {{.*}} @external_global :: (load 4 from got)
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel_ldr {{.*}}@external_global :: (load 4 from got)
-    ; ELF: [[G:%[0-9]+]] = LDRLIT_ga_pcrel_ldr @external_global :: (load 4 from got)
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_global :: (load 4 from got)
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_global :: (load 4 from got)
+    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr @external_global :: (load 4 from got)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -80,12 +80,12 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_constant
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel {{.*}}@internal_constant
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel {{.*}}@internal_constant
-    ; ELF: [[G:%[0-9]+]] = LDRLIT_ga_pcrel {{.*}}@internal_constant
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_constant
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
+    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -106,12 +106,12 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_constant
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel_ldr {{.*}} @external_constant :: (load 4 from got)
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel_ldr {{.*}}@external_constant :: (load 4 from got)
-    ; ELF: [[G:%[0-9]+]] = LDRLIT_ga_pcrel_ldr @external_constant :: (load 4 from got)
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_constant :: (load 4 from got)
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_constant :: (load 4 from got)
+    ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr @external_constant :: (load 4 from got)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
index c31893cf229..e80700317e0 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir
@@ -36,14 +36,14 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]] = MOVi32imm @internal_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI-MOVT: [[OFF:%[0-9]+]] = MOVi32imm {{.*}} @internal_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]] = ADDrr %r9, [[OFF]], 14, _, _
+    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
+    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
+    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -70,14 +70,14 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_global
-    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]] = MOVi32imm @external_global
-    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI-MOVT: [[OFF:%[0-9]+]] = MOVi32imm {{.*}} @external_global
-    ; RWPI-NOMOVT: [[OFF:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; RWPI: [[G:%[0-9]+]] = ADDrr %r9, [[OFF]], 14, _, _
+    ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
+    ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
+    ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -101,13 +101,13 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_constant
-    ; ROPI-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel @internal_constant
-    ; ROPI-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel @internal_constant
-    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]] = MOVi32imm @internal_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
+    ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
+    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
+    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -131,13 +131,13 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_constant
-    ; ROPI-MOVT: [[G:%[0-9]+]] = MOV_ga_pcrel @external_constant
-    ; ROPI-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_pcrel @external_constant
-    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]] = MOVi32imm @external_constant
-    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
+    ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
+    ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
+    ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant)
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
diff --git a/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir b/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
index 9cb402df30a..034b88296dc 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir
@@ -25,13 +25,13 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @internal_global
-    ; ELF-MOVT: [[G:%[0-9]+]] = MOVi32imm @internal_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOVi32imm @internal_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_abs @internal_global
+    ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
+    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
@@ -55,13 +55,13 @@ registers:
 body:             |
   bb.0:
     %0(p0) = G_GLOBAL_VALUE @external_global
-    ; ELF-MOVT: [[G:%[0-9]+]] = MOVi32imm @external_global
-    ; ELF-NOMOVT: [[G:%[0-9]+]] = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
-    ; DARWIN-MOVT: [[G:%[0-9]+]] = MOVi32imm @external_global
-    ; DARWIN-NOMOVT: [[G:%[0-9]+]] = LDRLIT_ga_abs @external_global
+    ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
+    ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
+    ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
+    ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
 
     %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
-    ; CHECK: [[V:%[0-9]+]] = LDRi12 [[G]], 0, 14, _
+    ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _
 
     %r0 = COPY %1(s32)
     ; CHECK: %r0 = COPY [[V]]
diff --git a/test/CodeGen/ARM/imm-peephole-arm.mir b/test/CodeGen/ARM/imm-peephole-arm.mir
index cd30bdb74d5..95ae58ff9bd 100644
--- a/test/CodeGen/ARM/imm-peephole-arm.mir
+++ b/test/CodeGen/ARM/imm-peephole-arm.mir
@@ -1,17 +1,17 @@
 # RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
 
-# CHECK: [[IN:%.*]] = COPY %r0
-# CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133
-# CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600
+# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[SUM1TMP:%.*]]:rgpr = ADDri [[IN]], 133
+# CHECK: [[SUM1:%.*]]:rgpr = ADDri killed [[SUM1TMP]], 25600
 
-# CHECK: [[SUM2TMP:%.*]] = SUBri [[IN]], 133
-# CHECK: [[SUM2:%.*]] = SUBri killed [[SUM2TMP]], 25600
+# CHECK: [[SUM2TMP:%.*]]:rgpr = SUBri [[IN]], 133
+# CHECK: [[SUM2:%.*]]:rgpr = SUBri killed [[SUM2TMP]], 25600
 
-# CHECK: [[SUM3TMP:%.*]] = SUBri [[IN]], 133
-# CHECK: [[SUM3:%.*]] = SUBri killed [[SUM3TMP]], 25600
+# CHECK: [[SUM3TMP:%.*]]:rgpr = SUBri [[IN]], 133
+# CHECK: [[SUM3:%.*]]:rgpr = SUBri killed [[SUM3TMP]], 25600
 
-# CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133
-# CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600
+# CHECK: [[SUM4TMP:%.*]]:rgpr = ADDri killed [[IN]], 133
+# CHECK: [[SUM4:%.*]]:rgpr = ADDri killed [[SUM4TMP]], 25600
 
 
 --- |
@@ -57,4 +57,3 @@ body:             |
     BX_RET 14, _, implicit %r0
 
 ...
-
diff --git a/test/CodeGen/ARM/imm-peephole-thumb.mir b/test/CodeGen/ARM/imm-peephole-thumb.mir
index 3d342902d80..553717ba74a 100644
--- a/test/CodeGen/ARM/imm-peephole-thumb.mir
+++ b/test/CodeGen/ARM/imm-peephole-thumb.mir
@@ -1,17 +1,17 @@
 # RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
 
-# CHECK: [[IN:%.*]] = COPY %r0
-# CHECK: [[SUM1TMP:%.*]] = t2ADDri [[IN]], 25600
-# CHECK: [[SUM1:%.*]] = t2ADDri killed [[SUM1TMP]], 133
+# CHECK: [[IN:%.*]]:gprnopc = COPY %r0
+# CHECK: [[SUM1TMP:%.*]]:rgpr = t2ADDri [[IN]], 25600
+# CHECK: [[SUM1:%.*]]:rgpr = t2ADDri killed [[SUM1TMP]], 133
 
-# CHECK: [[SUM2TMP:%.*]] = t2SUBri [[IN]], 25600
-# CHECK: [[SUM2:%.*]] = t2SUBri killed [[SUM2TMP]], 133
+# CHECK: [[SUM2TMP:%.*]]:rgpr = t2SUBri [[IN]], 25600
+# CHECK: [[SUM2:%.*]]:rgpr = t2SUBri killed [[SUM2TMP]], 133
 
-# CHECK: [[SUM3TMP:%.*]] = t2SUBri [[IN]], 25600
-# CHECK: [[SUM3:%.*]] = t2SUBri killed [[SUM3TMP]], 133
+# CHECK: [[SUM3TMP:%.*]]:rgpr = t2SUBri [[IN]], 25600
+# CHECK: [[SUM3:%.*]]:rgpr = t2SUBri killed [[SUM3TMP]], 133
 
-# CHECK: [[SUM4TMP:%.*]] = t2ADDri killed [[IN]], 25600
-# CHECK: [[SUM4:%.*]] = t2ADDri killed [[SUM4TMP]], 133
+# CHECK: [[SUM4TMP:%.*]]:rgpr = t2ADDri killed [[IN]], 25600
+# CHECK: [[SUM4:%.*]]:rgpr = t2ADDri killed [[SUM4TMP]], 133
 
 
 --- |
@@ -56,4 +56,3 @@ body:             |
     tBX_RET 14, _, implicit %r0
 
 ...
-
diff --git a/test/CodeGen/Hexagon/cext-opt-basic.mir b/test/CodeGen/Hexagon/cext-opt-basic.mir
index 5ad44c1e3ea..63530c88c1e 100644
--- a/test/CodeGen/Hexagon/cext-opt-basic.mir
+++ b/test/CodeGen/Hexagon/cext-opt-basic.mir
@@ -8,7 +8,7 @@
 ...
 
 # CHECK-LABEL: name: test0
-# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address
+# CHECK: [[B:%[0-9]+]]:intregs = A2_tfrsi @global_address
 # CHECK: L2_loadri_io [[B]], 0
 # CHECK: L2_loadri_io [[B]], 4
 # CHECK: L2_loadri_io [[B]], 8
@@ -26,8 +26,8 @@ body: |
 ...
 
 # CHECK-LABEL: name: test1
-# CHECK: [[C:%[0-9]+]] = COPY %r0
-# CHECK: [[B:%[0-9]+]] = A2_addi [[C]], @global_address
+# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[B:%[0-9]+]]:intregs = A2_addi [[C]], @global_address
 # CHECK: L2_loadri_io [[B]], 0
 # CHECK: L2_loadri_io [[B]], 4
 # CHECK: L2_loadri_io [[B]], 8
@@ -48,11 +48,11 @@ body: |
 ...
 
 # CHECK-LABEL: name: test2
-# CHECK: [[C:%[0-9]+]] = COPY %r0
-# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address + 4
-# CHECK: [[T0:%[0-9]+]] = A2_addi [[B]], -4
+# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[B:%[0-9]+]]:intregs = A2_tfrsi @global_address + 4
+# CHECK: [[T0:%[0-9]+]]:intregs = A2_addi [[B]], -4
 # CHECK: %r0 = COPY [[T0]]
-# CHECK: [[T1:%[0-9]+]] = A2_addi [[B]], -2
+# CHECK: [[T1:%[0-9]+]]:intregs = A2_addi [[B]], -2
 # CHECK: %r1 = COPY [[T1]]
 # CHECK: L4_loadri_rr [[B]], [[C]], 0
 ---
@@ -72,4 +72,3 @@ body: |
     %r1 = COPY %2
     %3 = L4_loadri_ur %0, 0, @global_address+4
 ...
-
diff --git a/test/CodeGen/Hexagon/early-if-debug.mir b/test/CodeGen/Hexagon/early-if-debug.mir
index 39b5036f810..7c8fb0aee10 100644
--- a/test/CodeGen/Hexagon/early-if-debug.mir
+++ b/test/CodeGen/Hexagon/early-if-debug.mir
@@ -3,16 +3,16 @@
 # if-converted.
 
 # CHECK-LABEL: bb.0:
-# CHECK: %0 = COPY %r0
-# CHECK: %1 = C2_cmpeqi %0, 0
-# CHECK: %2 = A2_tfrsi 123
+# CHECK: %0:intregs = COPY %r0
+# CHECK: %1:predregs = C2_cmpeqi %0, 0
+# CHECK: %2:intregs = A2_tfrsi 123
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: %3 = A2_tfrsi 321
-# CHECK: %5 = C2_mux %1, %2, %3
+# CHECK: %3:intregs = A2_tfrsi 321
+# CHECK: %5:intregs = C2_mux %1, %2, %3
 
 --- |
   define void @foo() {
diff --git a/test/CodeGen/Hexagon/expand-condsets-def-undef.mir b/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
index 44da969bf29..702099a4453 100644
--- a/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
@@ -32,10 +32,9 @@ body: |
     %1 = COPY %r0
     %2 = COPY %d0
     ; Check that this instruction is unchanged (remains unpredicated)
-    ; CHECK: %3 = A2_addi %2.isub_hi, 1
+    ; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
     %3 = A2_addi %2.isub_hi, 1
     undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
     %2.isub_hi = C2_muxir %0, %3, 0
 
 ...
-
diff --git a/test/CodeGen/Hexagon/expand-condsets-imm.mir b/test/CodeGen/Hexagon/expand-condsets-imm.mir
index 1b0988393b7..141db645329 100644
--- a/test/CodeGen/Hexagon/expand-condsets-imm.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-imm.mir
@@ -1,6 +1,6 @@
 # RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
 # Check that we can expand a mux with a global as an immediate operand.
-# CHECK: C2_cmoveif undef %0, @G
+# CHECK: C2_cmoveif undef %0:predregs, @G
 
 --- |
   @G = global i32 0, align 4
@@ -19,4 +19,3 @@ body: |
     %1 = C2_muxir undef %0, %1, @G
     %r0 = COPY %1
 ...
-
diff --git a/test/CodeGen/Hexagon/expand-condsets-impuse.mir b/test/CodeGen/Hexagon/expand-condsets-impuse.mir
index 08b6798aa2f..725e414f521 100644
--- a/test/CodeGen/Hexagon/expand-condsets-impuse.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-impuse.mir
@@ -53,7 +53,7 @@ body: |
         %7 = L2_loadrb_io %99, 12
         %8 = C2_cmpeqi %7, 9
         %9 = A2_tfrsi -999
-        ; CHECK: %10 = C2_cmoveit killed %8, -999, implicit %10
+        ; CHECK: %10:intregs = C2_cmoveit killed %8, -999, implicit %10
         %10 = C2_mux %8, %9, %1
         J2_jumpr %10, implicit-def %pc
 
diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
index f3d105f75da..e4c54c4b988 100644
--- a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
@@ -39,8 +39,8 @@ body: |
         %1 = COPY %r1
         %2 = COPY %p0
         ; Check that %3 was coalesced into %4.
-        ; CHECK: %4 = A2_abs %1
-        ; CHECK: %4 = A2_tfrt killed %2, killed %0, implicit %4
+        ; CHECK: %4:intregs = A2_abs %1
+        ; CHECK: %4:intregs = A2_tfrt killed %2, killed %0, implicit %4
         %3 = A2_abs %1
         %4 = C2_mux %2, %0, %3
         %r0 = COPY %4
diff --git a/test/CodeGen/Hexagon/hwloop-redef-imm.mir b/test/CodeGen/Hexagon/hwloop-redef-imm.mir
index d1bb1efb651..014908e20a7 100644
--- a/test/CodeGen/Hexagon/hwloop-redef-imm.mir
+++ b/test/CodeGen/Hexagon/hwloop-redef-imm.mir
@@ -7,7 +7,7 @@
 # possible and legal (since the immediate itself will be used in the
 # loop setup in the preheader).
 
-# CHECK:  [[R0:%[0-9]+]] = A2_tfrsi 1920
+# CHECK:  [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920
 # CHECK:  J2_loop0r %bb.1.b1, [[R0]]
 #
 # CHECK: bb.1.b1 (address-taken):
diff --git a/test/CodeGen/Hexagon/regalloc-liveout-undef.mir b/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
index 6a41514b060..a6a398f0cdf 100644
--- a/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
+++ b/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
@@ -6,7 +6,7 @@
 # cover live intervals as well.
 #
 # Make sure that this compiles successfully.
-# CHECK: undef %1.isub_lo = A2_addi %1.isub_lo, 1
+# CHECK: undef %1.isub_lo:doubleregs = A2_addi %1.isub_lo, 1
 
 ---
 name: fred
@@ -32,4 +32,3 @@ body: |
         undef %1.isub_lo = A2_addi %1.isub_lo, 1
         J2_jump %bb.1, implicit-def %pc
 ...
-
diff --git a/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
index 6d6549201ab..a8c342f296c 100644
--- a/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
+++ b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
@@ -17,9 +17,8 @@ body: |
 
   bb.2:
     ; Make sure that the subregister from the PHI operand is preserved.
-    ; CHECK: %[[REG:[0-9]+]] = COPY %0.isub_lo
+    ; CHECK: %[[REG:[0-9]+]]:intregs = COPY %0.isub_lo
     ; CHECK: %r0 = COPY %[[REG]]
     %1 : intregs = PHI %0.isub_lo, %bb.0, %0.isub_hi, %bb.1
     %r0 = COPY %1
 ...
-
diff --git a/test/CodeGen/Lanai/peephole-compare.mir b/test/CodeGen/Lanai/peephole-compare.mir
index 51133b5e58e..a65660cbee4 100644
--- a/test/CodeGen/Lanai/peephole-compare.mir
+++ b/test/CodeGen/Lanai/peephole-compare.mir
@@ -11,23 +11,23 @@
 # been sub.f %r3, 0, %r0 then it would have matched.
 
 # CHECK-LABEL: name: test1a
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
+# CHECK: [[IN1:%.*]]:gpr = COPY %r7
+# CHECK: [[IN2:%.*]]:gpr = COPY %r6
 # CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
 
 # CHECK-LABEL: name: test1b
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
+# CHECK: [[IN1:%.*]]:gpr = COPY %r7
+# CHECK: [[IN2:%.*]]:gpr = COPY %r6
 # CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
 
 # CHECK-LABEL: name: test2a
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
+# CHECK: [[IN1:%.*]]:gpr = COPY %r7
+# CHECK: [[IN2:%.*]]:gpr = COPY %r6
 # CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
 
 # CHECK-LABEL: name: test2b
-# CHECK: [[IN1:%.*]] = COPY %r7
-# CHECK: [[IN2:%.*]] = COPY %r6
+# CHECK: [[IN1:%.*]]:gpr = COPY %r7
+# CHECK: [[IN2:%.*]]:gpr = COPY %r6
 # CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
 
 # CHECK-LABEL: name: test3
@@ -38,10 +38,10 @@
 --- |
   target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
   target triple = "lanai-unknown-unknown"
-  
+
   @a = global i32 -1, align 4
   @b = global i32 0, align 4
-  
+
   define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -49,14 +49,14 @@
     %cond = select i1 %cmp, i32 %c, i32 %sub
     ret i32 %cond
   }
-  
+
   define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %cmp = icmp eq i32 %b, %a
     %cond = select i1 %cmp, i32 %c, i32 %b
     ret i32 %cond
   }
-  
+
   define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -64,7 +64,7 @@
     %cond = select i1 %cmp, i32 %c, i32 %d
     ret i32 %cond
   }
-  
+
   define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -72,7 +72,7 @@
     %cond = select i1 %cmp, i32 %c, i32 %d
     ret i32 %cond
   }
-  
+
   define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -80,7 +80,7 @@
     %cond = select i1 %cmp, i32 %c, i32 %d
     ret i32 %cond
   }
-  
+
   define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -88,7 +88,7 @@
     %cond = select i1 %cmp, i32 %c, i32 %d
     ret i32 %cond
   }
-  
+
   define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %sub = sub i32 %b, %a
@@ -96,38 +96,38 @@
     %cond = select i1 %cmp, i32 %c, i32 %d
     ret i32 %cond
   }
-  
+
   define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
   entry:
     %cmp = icmp ne i32 %a, 0
     %cmp1 = icmp ult i32 %a, %b
     %or.cond = and i1 %cmp, %cmp1
     br i1 %or.cond, label %return, label %if.end
-  
+
   if.end:                                           ; preds = %entry
     %cmp2 = icmp ne i32 %b, 0
     %cmp4 = icmp ult i32 %b, %c
     %or.cond29 = and i1 %cmp2, %cmp4
     br i1 %or.cond29, label %return, label %if.end6
-  
+
   if.end6:                                          ; preds = %if.end
     %cmp7 = icmp ne i32 %c, 0
     %cmp9 = icmp ult i32 %c, %d
     %or.cond30 = and i1 %cmp7, %cmp9
     br i1 %or.cond30, label %return, label %if.end11
-  
+
   if.end11:                                         ; preds = %if.end6
     %cmp12 = icmp ne i32 %d, 0
     %cmp14 = icmp ult i32 %d, %a
     %or.cond31 = and i1 %cmp12, %cmp14
     %b. = select i1 %or.cond31, i32 %b, i32 21
     ret i32 %b.
-  
+
   return:                                           ; preds = %if.end6, %if.end, %entry
     %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
     ret i32 %retval.0
   }
-  
+
   define void @testBB() {
   entry:
     %0 = load i32, i32* @a, align 4, !tbaa !0
@@ -135,36 +135,36 @@
     %sub.i = sub i32 %1, %0
     %tobool = icmp sgt i32 %sub.i, -1
     br i1 %tobool, label %if.end, label %if.then
-  
+
   if.then:                                          ; preds = %entry
     %call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
     br label %while.body
-  
+
   while.body:                                       ; preds = %while.body, %if.then
     br label %while.body
-  
+
   if.end:                                           ; preds = %entry
     %cmp.i = icmp slt i32 %sub.i, 1
     br i1 %cmp.i, label %if.then4, label %if.end7
-  
+
   if.then4:                                         ; preds = %if.end
     %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
     br label %while.body6
-  
+
   while.body6:                                      ; preds = %while.body6, %if.then4
     br label %while.body6
-  
+
   if.end7:                                          ; preds = %if.end
     ret void
   }
-  
+
   declare i32 @g(...)
-  
+
   ; Function Attrs: nounwind
   declare void @llvm.stackprotector(i8*, i8**) #0
-  
+
   attributes #0 = { nounwind }
-  
+
   !0 = !{!1, !1, i64 0}
   !1 = !{!"int", !2, i64 0}
   !2 = !{!"omnipotent char", !3, i64 0}
@@ -176,18 +176,18 @@ name:            test0a
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -204,7 +204,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18
-  
+
     %2 = COPY %r18
     %1 = COPY %r7
     %0 = COPY %r6
@@ -220,17 +220,17 @@ name:            test0b
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -247,7 +247,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18
-  
+
     %2 = COPY %r18
     %1 = COPY %r7
     %0 = COPY %r6
@@ -262,19 +262,19 @@ name:            test1a
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
   - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -291,7 +291,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18, %r19
-  
+
     %3 = COPY %r19
     %2 = COPY %r18
     %1 = COPY %r7
@@ -308,19 +308,19 @@ name:            test1b
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
   - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -337,7 +337,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18, %r19
-  
+
     %3 = COPY %r19
     %2 = COPY %r18
     %1 = COPY %r7
@@ -354,19 +354,19 @@ name:            test2a
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
   - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -383,7 +383,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18, %r19
-  
+
     %3 = COPY %r19
     %2 = COPY %r18
     %1 = COPY %r7
@@ -400,19 +400,19 @@ name:            test2b
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
   - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -429,7 +429,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18, %r19
-  
+
     %3 = COPY %r19
     %2 = COPY %r18
     %1 = COPY %r7
@@ -446,19 +446,19 @@ name:            test3
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%0' }
   - { reg: '%r7', virtual-reg: '%1' }
   - { reg: '%r18', virtual-reg: '%2' }
   - { reg: '%r19', virtual-reg: '%3' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -475,7 +475,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     liveins: %r6, %r7, %r18, %r19
-  
+
     %3 = COPY %r19
     %2 = COPY %r18
     %1 = COPY %r7
@@ -492,7 +492,7 @@ name:            test4
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
@@ -516,12 +516,12 @@ registers:
   - { id: 20, class: gpr }
   - { id: 21, class: gpr }
   - { id: 22, class: gpr }
-liveins:         
+liveins:
   - { reg: '%r6', virtual-reg: '%1' }
   - { reg: '%r7', virtual-reg: '%2' }
   - { reg: '%r18', virtual-reg: '%3' }
   - { reg: '%r19', virtual-reg: '%4' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -539,7 +539,7 @@ body:             |
   bb.0.entry:
     successors: %bb.4.return, %bb.1.if.end
     liveins: %r6, %r7, %r18, %r19
-  
+
     %4 = COPY %r19
     %3 = COPY %r18
     %2 = COPY %r7
@@ -554,10 +554,10 @@ body:             |
     SFSUB_F_RI_LO killed %9, 0, implicit-def %sr
     BRCC %bb.4.return, 6, implicit %sr
     BT %bb.1.if.end
-  
+
   bb.1.if.end:
     successors: %bb.4.return, %bb.2.if.end6
-  
+
     SFSUB_F_RI_LO %2, 0, implicit-def %sr
     %10 = SCC 6, implicit %sr
     SFSUB_F_RR %2, %3, implicit-def %sr
@@ -567,10 +567,10 @@ body:             |
     SFSUB_F_RI_LO killed %14, 0, implicit-def %sr
     BRCC %bb.4.return, 6, implicit %sr
     BT %bb.2.if.end6
-  
+
   bb.2.if.end6:
     successors: %bb.4.return, %bb.3.if.end11
-  
+
     SFSUB_F_RI_LO %3, 0, implicit-def %sr
     %15 = SCC 6, implicit %sr
     SFSUB_F_RR %3, %4, implicit-def %sr
@@ -581,7 +581,7 @@ body:             |
     SFSUB_F_RI_LO killed %19, 0, implicit-def %sr
     BRCC %bb.4.return, 6, implicit %sr
     BT %bb.3.if.end11
-  
+
   bb.3.if.end11:
     %20 = SLI 21
     SFSUB_F_RR %4, %1, implicit-def %sr
@@ -590,7 +590,7 @@ body:             |
     %22 = SELECT killed %21, %20, 6, implicit %sr
     %rv = COPY %22
     RET implicit %rca, implicit %rv
-  
+
   bb.4.return:
     %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6
     %rv = COPY %0
@@ -602,7 +602,7 @@ name:            testBB
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
@@ -612,7 +612,7 @@ registers:
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -629,7 +629,7 @@ frameInfo:
 body:             |
   bb.0.entry:
     successors: %bb.3.if.end, %bb.1.if.then
-  
+
     %1 = MOVHI target-flags(lanai-hi) @a
     %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a
     %3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0)
@@ -640,38 +640,38 @@ body:             |
     SFSUB_F_RI_LO %0, 0, implicit-def %sr
     BRCC %bb.3.if.end, 10, implicit %sr
     BT %bb.1.if.then
-  
+
   bb.1.if.then:
     successors: %bb.2.while.body
-  
+
     ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
     CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
     ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
-  
+
   bb.2.while.body:
     successors: %bb.2.while.body
-  
+
     BT %bb.2.while.body
-  
+
   bb.3.if.end:
     successors: %bb.4.if.then4, %bb.6.if.end7
     liveins: %sr
-  
+
     BRCC %bb.6.if.end7, 14, implicit %sr
     BT %bb.4.if.then4
-  
+
   bb.4.if.then4:
     successors: %bb.5.while.body6
-  
+
     ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
     CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
     ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
-  
+
   bb.5.while.body6:
     successors: %bb.5.while.body6
-  
+
     BT %bb.5.while.body6
-  
+
   bb.6.if.end7:
     RET implicit %rca
 
diff --git a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
index 0b182a7ecc4..2dfb61c53d5 100644
--- a/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
+++ b/test/CodeGen/MIR/AArch64/atomic-memoperands.mir
@@ -14,10 +14,10 @@ body: |
   bb.0:
 
     ; CHECK-LABEL: name: atomic_memoperands
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
-    ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
-    ; CHECK: [[LOAD2:%[0-9]+]](s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load unordered 8)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load monotonic 4)
+    ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
     ; CHECK: G_STORE [[LOAD2]](s16), [[COPY]](p0) :: (store release 2)
     ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store acq_rel 4)
     ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store syncscope("singlethread") seq_cst 8)
diff --git a/test/CodeGen/MIR/AArch64/spill-fold.mir b/test/CodeGen/MIR/AArch64/spill-fold.mir
index 05e7f7521ed..f812bc710aa 100644
--- a/test/CodeGen/MIR/AArch64/spill-fold.mir
+++ b/test/CodeGen/MIR/AArch64/spill-fold.mir
@@ -59,7 +59,7 @@ body:             |
   bb.0:
     %0 = COPY %wzr
     INLINEASM $nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
-    ; CHECK: undef %1.sub_32 = LDRWui %stack.0, 0 :: (load 4 from %stack.0)
+    ; CHECK: undef %1.sub_32:gpr64 = LDRWui %stack.0, 0 :: (load 4 from %stack.0)
     undef %1.sub_32 = COPY %0
     %x0 = COPY %1
     RET_ReallyLR implicit %x0
@@ -75,7 +75,7 @@ body:             |
   bb.0:
     %0 = COPY %wzr
     INLINEASM $nop, 1, 12, implicit-def dead %x0, 12, implicit-def dead %x1, 12, implicit-def dead %x2, 12, implicit-def dead %x3, 12, implicit-def dead %x4, 12, implicit-def dead %x5, 12, implicit-def dead %x6, 12, implicit-def dead %x7, 12, implicit-def dead %x8, 12, implicit-def dead %x9, 12, implicit-def dead %x10, 12, implicit-def dead %x11, 12, implicit-def dead %x12, 12, implicit-def dead %x13, 12, implicit-def dead %x14, 12, implicit-def dead %x15, 12, implicit-def dead %x16, 12, implicit-def dead %x17, 12, implicit-def dead %x18, 12, implicit-def dead %x19, 12, implicit-def dead %x20, 12, implicit-def dead %x21, 12, implicit-def dead %x22, 12, implicit-def dead %x23, 12, implicit-def dead %x24, 12, implicit-def dead %x25, 12, implicit-def dead %x26, 12, implicit-def dead %x27, 12, implicit-def dead %x28, 12, implicit-def dead %fp, 12, implicit-def dead %lr, 12, implicit-def %sp
-    ; CHECK: undef %1.ssub = LDRSui %stack.0, 0 :: (load 4 from %stack.0)
+    ; CHECK: undef %1.ssub:fpr64 = LDRSui %stack.0, 0 :: (load 4 from %stack.0)
     undef %1.ssub = COPY %0
     %d0 = COPY %1
     RET_ReallyLR implicit %d0
diff --git a/test/CodeGen/MIR/AArch64/target-memoperands.mir b/test/CodeGen/MIR/AArch64/target-memoperands.mir
index 0df4443d6a0..a3442f25135 100644
--- a/test/CodeGen/MIR/AArch64/target-memoperands.mir
+++ b/test/CodeGen/MIR/AArch64/target-memoperands.mir
@@ -14,9 +14,9 @@ body: |
   bb.0:
 
     ; CHECK-LABEL: name: target_memoperands
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0
-    ; CHECK: [[LOAD:%[0-9]+]](s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8)
-    ; CHECK: [[LOAD1:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: ("aarch64-suppress-pair" load 8)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load 4)
     ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: ("aarch64-suppress-pair" store 8)
     ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store 4)
     ; CHECK: RET_ReallyLR
diff --git a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
index c0251232fd5..cae8ed80d16 100644
--- a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
+++ b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir
@@ -111,7 +111,7 @@
 #  literal constant.
 
 # CHECK-LABEL: name: add_f32_1.0_one_f16_use
-# CHECK: %13 = V_ADD_F16_e32  1065353216, killed %11, implicit %exec
+# CHECK: %13:vgpr_32 = V_ADD_F16_e32  1065353216, killed %11, implicit %exec
 
 name:            add_f32_1.0_one_f16_use
 alignment:       0
@@ -170,9 +170,9 @@ body:             |
 # operands
 
 # CHECK-LABEL: name: add_f32_1.0_multi_f16_use
-# CHECK: %13 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %14 = V_ADD_F16_e32 killed %11, %13, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 killed %12, killed %13, implicit %exec
+# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit %exec
+# CHECK: %14:vgpr_32 = V_ADD_F16_e32 killed %11, %13, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 killed %12, killed %13, implicit %exec
 
 
 name:            add_f32_1.0_multi_f16_use
@@ -238,8 +238,8 @@ body:             |
 #  immediate, and folded into the single f16 use as a literal constant
 
 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
-# CHECK: %15 = V_ADD_F16_e32 1065353216, %11, implicit %exec
-# CHECK: %16 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit %exec
+# CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
 
 name:            add_f32_1.0_one_f32_use_one_f16_use
 alignment:       0
@@ -306,10 +306,10 @@ body:             |
 #  constant, and not folded as a multi-use literal for the f16 cases
 
 # CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
-# CHECK: %14 = V_MOV_B32_e32 1065353216, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32  %11, %14, implicit %exec
-# CHECK: %16 = V_ADD_F16_e32 %12,  %14, implicit %exec
-# CHECK: %17 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
+# CHECK: %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32  %11, %14, implicit %exec
+# CHECK: %16:vgpr_32 = V_ADD_F16_e32 %12,  %14, implicit %exec
+# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec
 
 name:            add_f32_1.0_one_f32_use_multi_f16_use
 alignment:       0
@@ -375,9 +375,9 @@ body:             |
 ...
 ---
 # CHECK-LABEL: name: add_i32_1_multi_f16_use
-# CHECK: %13 = V_MOV_B32_e32 1, implicit %exec
-# CHECK: %14 = V_ADD_F16_e32 1, killed %11, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 1, killed %12, implicit %exec
+# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit %exec
+# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit %exec
 
 
 name:            add_i32_1_multi_f16_use
@@ -440,10 +440,10 @@ body:             |
 ---
 
 # CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
-# CHECK: %14 = V_MOV_B32_e32 -2, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 -2, %11, implicit %exec
-# CHECK: %16 = V_ADD_F16_e32 -2, %12, implicit %exec
-# CHECK: %17 = V_ADD_F32_e32 -2, killed %13, implicit %exec
+# CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit %exec
+# CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit %exec
+# CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit %exec
 
 name:            add_i32_m2_one_f32_use_multi_f16_use
 alignment:       0
@@ -513,9 +513,9 @@ body:             |
 #  constant, and not folded as a multi-use literal for the f16 cases
 
 # CHECK-LABEL: name: add_f16_1.0_multi_f32_use
-# CHECK: %13 = V_MOV_B32_e32 15360, implicit %exec
-# CHECK: %14 = V_ADD_F32_e32 %11, %13, implicit %exec
-# CHECK: %15 = V_ADD_F32_e32 %12, %13, implicit %exec
+# CHECK: %13:vgpr_32 = V_MOV_B32_e32 15360, implicit %exec
+# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit %exec
 
 name:            add_f16_1.0_multi_f32_use
 alignment:       0
@@ -580,9 +580,9 @@ body:             |
 # FIXME: Should be able to fold this
 
 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
-# CHECK: %13 = V_MOV_B32_e32 80886784, implicit %exec
-# CHECK: %14 = V_ADD_F16_e32 %11, %13, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 %12, %13, implicit %exec
+# CHECK: %13:vgpr_32 = V_MOV_B32_e32 80886784, implicit %exec
+# CHECK: %14:vgpr_32 = V_ADD_F16_e32 %11, %13, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit %exec
 
 name:            add_f16_1.0_other_high_bits_multi_f16_use
 alignment:       0
@@ -647,9 +647,9 @@ body:             |
 # f32 instruction.
 
 # CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
-# CHECK: %13 = V_MOV_B32_e32 305413120, implicit %exec
-# CHECK: %14 = V_ADD_F32_e32 %11, %13, implicit %exec
-# CHECK: %15 = V_ADD_F16_e32 %12, %13, implicit %exec
+# CHECK: %13:vgpr_32 = V_MOV_B32_e32 305413120, implicit %exec
+# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit %exec
+# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit %exec
 name:            add_f16_1.0_other_high_bits_use_f16_f32
 alignment:       0
 exposesReturnsTwice: false
diff --git a/test/CodeGen/MIR/AMDGPU/fold-multiple.mir b/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
index a5da33a997d..b9b6ee6887b 100644
--- a/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
+++ b/test/CodeGen/MIR/AMDGPU/fold-multiple.mir
@@ -14,8 +14,8 @@
 # being processed twice.
 
 # CHECK-LABEL: name: test
-# CHECK: %2 = V_LSHLREV_B32_e32 2, killed %0, implicit %exec
-# CHECK: %4 = V_AND_B32_e32 8, killed %2, implicit %exec
+# CHECK: %2:vgpr_32 = V_LSHLREV_B32_e32 2, killed %0, implicit %exec
+# CHECK: %4:vgpr_32 = V_AND_B32_e32 8, killed %2, implicit %exec
 
 name:            test
 tracksRegLiveness: true
diff --git a/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
index cbe78716ae2..52d3135261a 100644
--- a/test/CodeGen/MIR/AMDGPU/intrinsics.mir
+++ b/test/CodeGen/MIR/AMDGPU/intrinsics.mir
@@ -16,6 +16,6 @@ registers:
 body: |
   bb.0:
     ; CHECK-LABEL: name: use_intrin
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
     %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32)
 ...
diff --git a/test/CodeGen/MIR/AMDGPU/target-flags.mir b/test/CodeGen/MIR/AMDGPU/target-flags.mir
index dff119d573d..e69a94b59ea 100644
--- a/test/CodeGen/MIR/AMDGPU/target-flags.mir
+++ b/test/CodeGen/MIR/AMDGPU/target-flags.mir
@@ -22,8 +22,8 @@ body: |
   bb.0:
     liveins: %sgpr0_sgpr1
     ; CHECK-LABEL: name: flags
-    ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]] = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
-    ; CHECK: [[S_MOV_B64_:%[0-9]+]] = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
+    ; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
+    ; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
     ; CHECK: S_ENDPGM
     %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc
   %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
index 312bf004a9c..71d232b58cf 100644
--- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
+++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
@@ -43,11 +43,11 @@ body: |
     %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
     %1 = CVT_f64_f32 %0, 0
     %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1
-  ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
+  ; CHECK: %3:float64regs = FADD_rnf64ri %1, double 3.250000e+00
     %3 = FADD_rnf64ri %1, double 3.250000e+00
     %4 = CVT_f32_f64 %3, 5
     %5 = CVT_f32_s32 %2, 5
-  ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
+  ; CHECK: %6:float32regs = FADD_rnf32ri %5, float 6.250000e+00
     %6 = FADD_rnf32ri %5, float 6.250000e+00
     %7 = FMUL_rnf32rr %6, %4
     StoreRetvalF32 %7, 0
@@ -69,11 +69,11 @@ body: |
     %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0
     %1 = CVT_f64_f32 %0, 0
     %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1
-  ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+  ; CHECK: %3:float64regs = FADD_rnf64ri %1, double 0x7FF8000000000000
     %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
     %4 = CVT_f32_f64 %3, 5
     %5 = CVT_f32_s32 %2, 5
-  ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+  ; CHECK: %6:float32regs = FADD_rnf32ri %5, float 0x7FF8000000000000
     %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
     %7 = FMUL_rnf32rr %6, %4
     StoreRetvalF32 %7, 0
diff --git a/test/CodeGen/MIR/X86/generic-instr-type.mir b/test/CodeGen/MIR/X86/generic-instr-type.mir
index 78951de70a3..c9835923c44 100644
--- a/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -37,18 +37,18 @@ registers:
 body: |
   bb.0:
     liveins: %edi, %xmm0
-    ; CHECK:      %1(s32) = G_ADD %0
+    ; CHECK:      %1:_(s32) = G_ADD %0
     %0(s32) = COPY %edi
     %6(<2 x s32>) = COPY %xmm0
     %7(s64) = COPY %rdi
 
     %1(s32) = G_ADD %0, %0
-    ; CHECK:      %2(<2 x s32>) = G_ADD %6, %6
+    ; CHECK:      %2:_(<2 x s32>) = G_ADD %6, %6
     %2(<2 x s32>) = G_ADD %6, %6
-    ; CHECK:      %3(s64) = G_ADD %7, %7
+    ; CHECK:      %3:_(s64) = G_ADD %7, %7
     %3(s64) = G_ADD %7, %7
 
-    ; CHECK:      %5(s48) = G_ADD %8, %8
+    ; CHECK:      %5:_(s48) = G_ADD %8, %8
     %8(s48) = G_TRUNC %7
     %5(s48) = G_ADD %8, %8
 ...
diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir
index 758f3031465..501d0c58a63 100644
--- a/test/CodeGen/MIR/X86/metadata-operands.mir
+++ b/test/CodeGen/MIR/X86/metadata-operands.mir
@@ -50,7 +50,7 @@ stack:
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK:      %0 = COPY %edi
+    ; CHECK:      %0:gr32 = COPY %edi
     ; CHECK-NEXT: DBG_VALUE _, 0, !11, !DIExpression()
     %0 = COPY %edi
     DBG_VALUE _, 0, !12, !DIExpression()
diff --git a/test/CodeGen/MIR/X86/roundtrip.mir b/test/CodeGen/MIR/X86/roundtrip.mir
index c697f730604..9679b52f2ba 100644
--- a/test/CodeGen/MIR/X86/roundtrip.mir
+++ b/test/CodeGen/MIR/X86/roundtrip.mir
@@ -6,8 +6,8 @@
 # CHECK:   - { id: 1, class: gr32, preferred-register: '' }
 # CHECK: body: |
 # CHECK:   bb.0:
-# CHECK:     %0 = MOV32r0 implicit-def %eflags
-# CHECK:     dead %1 = COPY %0
+# CHECK:     %0:gr32 = MOV32r0 implicit-def %eflags
+# CHECK:     dead %1:gr32 = COPY %0
 # CHECK:     MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
 # CHECK:     RETQ undef %eax
 name: func0
diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir
index 163d50395a3..262b6dcb399 100644
--- a/test/CodeGen/MIR/X86/stack-object-operands.mir
+++ b/test/CodeGen/MIR/X86/stack-object-operands.mir
@@ -32,10 +32,10 @@ stack:
 body: |
   bb.0.entry:
     ; CHECK-LABEL: name: test
-    ; CHECK: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _
+    ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _
     ; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]]
     ; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2
-    ; CHECK: [[MOV32rm1:%[0-9]+]] = MOV32rm %stack.0.b, 1, _, 0, _
+    ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, _, 0, _
     ; CHECK: %eax = COPY [[MOV32rm1]]
     ; CHECK: RETL %eax
     %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
diff --git a/test/CodeGen/MIR/X86/subregister-index-operands.mir b/test/CodeGen/MIR/X86/subregister-index-operands.mir
index c4f8ee143a0..e3c5b9d17ee 100644
--- a/test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -22,8 +22,8 @@ body: |
     liveins: %edi, %eax
     ; CHECK-LABEL: name: t
     ; CHECK: liveins: %edi, %eax
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]] = INSERT_SUBREG %edi, %al, 1
-    ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]] = EXTRACT_SUBREG %eax, 2
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG %edi, %al, 1
+    ; CHECK: [[EXTRACT_SUBREG:%[0-9]+]]:gr8 = EXTRACT_SUBREG %eax, 2
     ; CHECK: %ax = REG_SEQUENCE [[EXTRACT_SUBREG]], 1, [[EXTRACT_SUBREG]], 2
     ; CHECK: RETQ %ax
     %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir
index 282e0cc7e42..caf342e2671 100644
--- a/test/CodeGen/MIR/X86/subregister-operands.mir
+++ b/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -23,9 +23,9 @@ body: |
     liveins: %edi
     ; CHECK-LABEL: name: t
     ; CHECK: liveins: %edi
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
-    ; CHECK: [[AND8ri:%[0-9]+]] = AND8ri [[COPY1]], 1, implicit-def %eflags
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def %eflags
     ; CHECK: %al = COPY [[AND8ri]]
     ; CHECK: RETQ %al
     %0 = COPY %edi
diff --git a/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir b/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
index d1d7e9d8ad5..52867e57445 100644
--- a/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
+++ b/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir
@@ -31,8 +31,8 @@ body:             |
 
 # CHECK:  bb.1:
 # CHECK:    successors: %bb.2
-# CHECK:    [[TMP1:%[0-9]+]] = COPY undef %{{[0-9]+}}
-# CHECK:    %{{[0-9]+}} = ADD32ri8 killed [[TMP1]], 1
+# CHECK:    [[TMP1:%[0-9]+]]:gr32 = COPY undef %{{[0-9]+}}
+# CHECK:    %{{[0-9]+}}:gr32 = ADD32ri8 killed [[TMP1]], 1
 # CHECK:    JMP_1 %bb.2
 
 # CHECK:  bb.2:
diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir
index 0d181f895aa..6e298910dcb 100644
--- a/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -44,15 +44,15 @@ body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi
-    ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    ; CHECK:      %0:gr32 = COPY %edi
+    ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
     %0 = COPY %edi
     %1 = SUB32ri8 %0, 10, implicit-def %eflags
     JG_1 %bb.2.exit, implicit %eflags
     JMP_1 %bb.1.less
 
   bb.1.less:
-    ; CHECK:      %2 = MOV32r0
+    ; CHECK:      %2:gr32 = MOV32r0
     ; CHECK-NEXT: %eax = COPY %2
     %2 = MOV32r0 implicit-def %eflags
     %eax = COPY %2
@@ -78,15 +78,15 @@ body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi
-    ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = SUB32ri8 %0, 10
+    ; CHECK:      %0:gr32 = COPY %edi
+    ; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
     %2 = COPY %edi
     %0 = SUB32ri8 %2, 10, implicit-def %eflags
     JG_1 %bb.2.exit, implicit %eflags
     JMP_1 %bb.1.less
 
   bb.1.less:
-    ; CHECK:      %2 = MOV32r0
+    ; CHECK:      %2:gr32 = MOV32r0
     ; CHECK-NEXT: %eax = COPY %2
     %10 = MOV32r0 implicit-def %eflags
     %eax = COPY %10
diff --git a/test/CodeGen/PowerPC/debuginfo-split-int.ll b/test/CodeGen/PowerPC/debuginfo-split-int.ll
index e23efa1db72..4bcf43c9dae 100644
--- a/test/CodeGen/PowerPC/debuginfo-split-int.ll
+++ b/test/CodeGen/PowerPC/debuginfo-split-int.ll
@@ -26,9 +26,9 @@ target triple = "ppc32"
 ; CHECK: [[DL:![0-9]+]] = !DILocalVariable(name: "result"
 ;
 ; High 32 bits in R3, low 32 bits in R4
-; CHECK: %0 = COPY %r3
+; CHECK: %0:gprc = COPY %r3
 ; CHECK: DBG_VALUE debug-use %0, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; CHECK: %1 = COPY %r4
+; CHECK: %1:gprc = COPY %r4
 ; CHECK: DBG_VALUE debug-use %1, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
 define void @bar() local_unnamed_addr #0 !dbg !6 {
   %1 = alloca i64, align 8
diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
index bab2ff22a4c..ed6ceec8d40 100644
--- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -3,11 +3,11 @@
 --- |
   target datalayout = "E-m:e-i64:64-n32:64"
   target triple = "powerpc64-unknown-linux-gnu"
-  
+
   @d = global i32 15, align 4
   @b = global i32* @d, align 8
   @a = common global i32 0, align 4
-  
+
   ; Function Attrs: nounwind
   define signext i32 @main() #0 {
   entry:
@@ -31,7 +31,7 @@
     store i32 %or.1, i32* %0, align 4
     ret i32 %or.1
   }
-  
+
   attributes #0 = { nounwind "target-cpu"="ppc64" }
 
 ...
@@ -40,7 +40,7 @@ name:            main
 alignment:       2
 exposesReturnsTwice: false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: g8rc_and_g8rc_nox0 }
   - { id: 1, class: g8rc_and_g8rc_nox0 }
   - { id: 2, class: gprc }
@@ -52,7 +52,7 @@ registers:
   - { id: 8, class: gprc }
   - { id: 9, class: gprc }
   - { id: 10, class: g8rc }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -76,9 +76,9 @@ body:             |
     %3 = LI 0
     %4 = RLWIMI %3, killed %2, 0, 0, 31
     ; CHECK-LABEL: name: main
-    ; CHECK: %[[REG1:[0-9]+]] = LI 0
-    ; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]]
-    ; CHECK: %[[REG2]] = RLWIMI %[[REG2]], killed %2, 0, 0, 31
+    ; CHECK: %[[REG1:[0-9]+]]:gprc = LI 0
+    ; CHECK: %[[REG2:[0-9]+]]:gprc = COPY %[[REG1]]
+    ; CHECK: %[[REG2]]:gprc = RLWIMI %[[REG2]], killed %2, 0, 0, 31
     %8 = RLWIMI %3, %4, 0, 0, 31
     STW %4, 0, %1 :: (store 4 into %ir.0)
     %10 = EXTSW_32_64 %8
diff --git a/test/CodeGen/PowerPC/tls_get_addr_fence1.mir b/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
index fa8e73e321d..d45a83d0723 100644
--- a/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
+++ b/test/CodeGen/PowerPC/tls_get_addr_fence1.mir
@@ -4,9 +4,9 @@
 --- |
   target datalayout = "e-m:e-i64:64-n32:64"
   target triple = "powerpc64le-unknown-linux-gnu"
-  
+
   @tls_var = external thread_local local_unnamed_addr global i32
-  
+
   define i32 @tls_func() local_unnamed_addr {
   entry:
     %0 = load i32, i32* @tls_var
@@ -22,13 +22,13 @@ legalized:       false
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
   - { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
   - { id: 2, class: g8rc, preferred-register: '' }
-liveins:         
+liveins:
   - { reg: '%x2' }
-frameInfo:       
+frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
@@ -45,9 +45,9 @@ frameInfo:
   hasMustTailInVarArgFunc: false
   savePoint:       ''
   restorePoint:    ''
-fixedStack:      
-stack:           
-constants:       
+fixedStack:
+stack:
+constants:
 body:             |
   bb.0.entry:
     liveins: %x2
@@ -57,7 +57,7 @@ body:             |
     %x3 = COPY %2
     BLR8 implicit %lr8, implicit %rm, implicit %x3
     ; CHECK-LABEL: bb.0.entry
-    ; CHECK: %[[reg1:[0-9]+]] = ADDIStlsgdHA %x2, @tls_var
+    ; CHECK: %[[reg1:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDIStlsgdHA %x2, @tls_var
     ; CHECK: ADJCALLSTACKDOWN 0, 0
     ; CHECK: %x3 = ADDItlsgdL %[[reg1]], @tls_var
     ; CHECK: %x3 = GETtlsADDR %x3, @tls_var
diff --git a/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
index 41a52a1384f..4cc2ee566a5 100644
--- a/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
+++ b/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
@@ -18,22 +18,22 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
 ; X64-NEXT: isImmutable: true,
 
 ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
-; X64:      [[ARG1_TMP:%[0-9]+]](s32) = COPY %edi
-; X64:      [[ARG1:%[0-9]+]](s8) = G_TRUNC [[ARG1_TMP]](s32)
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi
-; X64-NEXT: %{{[0-9]+}}(s8) = G_TRUNC %{{[0-9]+}}(s32)
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %edx
-; X64-NEXT: %{{[0-9]+}}(s8) = G_TRUNC %{{[0-9]+}}(s32)
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %ecx
-; X64-NEXT: %{{[0-9]+}}(s8) = G_TRUNC %{{[0-9]+}}(s32)
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r8d
-; X64-NEXT: %{{[0-9]+}}(s8) = G_TRUNC %{{[0-9]+}}(s32)
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r9d
-; X64-NEXT: %{{[0-9]+}}(s8) = G_TRUNC %{{[0-9]+}}(s32)
-; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X64-NEXT: [[ARG7:%[0-9]+]](s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
-; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X64-NEXT: [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
+; X64:      [[ARG1_TMP:%[0-9]+]]:_(s32) = COPY %edi
+; X64:      [[ARG1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1_TMP]](s32)
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %esi
+; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32)
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %edx
+; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32)
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %ecx
+; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32)
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r8d
+; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32)
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r9d
+; X64-NEXT: %{{[0-9]+}}:_(s8) = G_TRUNC %{{[0-9]+}}(s32)
+; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X64-NEXT: [[ARG7:%[0-9]+]]:_(s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
+; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X64-NEXT: [[ARG8:%[0-9]+]]:_(s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
 ; X32:  id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 1, alignment: 4,
@@ -60,26 +60,26 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4,
 ; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1, alignment: 16,
 ; X32-NEXT: isImmutable: true,
 
-; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X32-NEXT:  [[ARG1:%[0-9]+]](s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
-; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
-; X32-NEXT:  [[ARG2:%[0-9]+]](s8) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK4]], align 0)
-; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X32-NEXT:  [[ARG3:%[0-9]+]](s8) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
-; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
-; X32-NEXT:  [[ARG4:%[0-9]+]](s8) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK12]], align 0)
-; X32-NEXT:  [[ARG5_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; X32-NEXT:  [[ARG5:%[0-9]+]](s8) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK16]], align 0)
-; X32-NEXT:  [[ARG6_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
-; X32-NEXT:  [[ARG6:%[0-9]+]](s8) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK20]], align 0)
-; X32-NEXT:  [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
-; X32-NEXT:  [[ARG7:%[0-9]+]](s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK24]], align 0)
-; X32-NEXT:  [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
-; X32-NEXT:  [[ARG8:%[0-9]+]](s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK28]], align 0)
-
-; ALL-NEXT:  [[GADDR_A1:%[0-9]+]](p0) = G_GLOBAL_VALUE @a1_8bit
-; ALL-NEXT:  [[GADDR_A7:%[0-9]+]](p0) = G_GLOBAL_VALUE @a7_8bit
-; ALL-NEXT:  [[GADDR_A8:%[0-9]+]](p0) = G_GLOBAL_VALUE @a8_8bit
+; X32:       [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X32-NEXT:  [[ARG1:%[0-9]+]]:_(s8) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0)
+; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
+; X32-NEXT:  [[ARG2:%[0-9]+]]:_(s8) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK4]], align 0)
+; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X32-NEXT:  [[ARG3:%[0-9]+]]:_(s8) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
+; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
+; X32-NEXT:  [[ARG4:%[0-9]+]]:_(s8) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK12]], align 0)
+; X32-NEXT:  [[ARG5_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
+; X32-NEXT:  [[ARG5:%[0-9]+]]:_(s8) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK16]], align 0)
+; X32-NEXT:  [[ARG6_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
+; X32-NEXT:  [[ARG6:%[0-9]+]]:_(s8) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK20]], align 0)
+; X32-NEXT:  [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
+; X32-NEXT:  [[ARG7:%[0-9]+]]:_(s8) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK24]], align 0)
+; X32-NEXT:  [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
+; X32-NEXT:  [[ARG8:%[0-9]+]]:_(s8) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK28]], align 0)
+
+; ALL-NEXT:  [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_8bit
+; ALL-NEXT:  [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_8bit
+; ALL-NEXT:  [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_8bit
 ; ALL-NEXT:  G_STORE [[ARG1]](s8), [[GADDR_A1]](p0) :: (store 1 into @a1_8bit)
 ; ALL-NEXT:  G_STORE [[ARG7]](s8), [[GADDR_A7]](p0) :: (store 1 into @a7_8bit)
 ; ALL-NEXT:  G_STORE [[ARG8]](s8), [[GADDR_A8]](p0) :: (store 1 into @a8_8bit)
@@ -108,16 +108,16 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
 ; X64:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16,
 ; X64-NEXT: isImmutable: true,
 ; X64: liveins: %ecx, %edi, %edx, %esi, %r8d, %r9d
-; X64:      [[ARG1:%[0-9]+]](s32) = COPY %edi
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %esi
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %edx
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %ecx
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r8d
-; X64-NEXT: %{{[0-9]+}}(s32) = COPY %r9d
-; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X64-NEXT: [[ARG7:%[0-9]+]](s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
-; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X64-NEXT: [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
+; X64:      [[ARG1:%[0-9]+]]:_(s32) = COPY %edi
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %esi
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %edx
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %ecx
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r8d
+; X64-NEXT: %{{[0-9]+}}:_(s32) = COPY %r9d
+; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X64-NEXT: [[ARG7:%[0-9]+]]:_(s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
+; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X64-NEXT: [[ARG8:%[0-9]+]]:_(s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
 ; X32:  id: [[STACK28:[0-9]+]], type: default, offset: 28, size: 4, alignment: 4,
@@ -143,26 +143,26 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
 ; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
 ; X32-NEXT: isImmutable: true,
 
-; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X32-NEXT:  [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
-; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
-; X32-NEXT:  [[ARG2:%[0-9]+]](s32) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
-; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X32-NEXT:  [[ARG3:%[0-9]+]](s32) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
-; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
-; X32-NEXT:  [[ARG4:%[0-9]+]](s32) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0)
-; X32-NEXT:  [[ARG5_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; X32-NEXT:  [[ARG5:%[0-9]+]](s32) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0)
-; X32-NEXT:  [[ARG6_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
-; X32-NEXT:  [[ARG6:%[0-9]+]](s32) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0)
-; X32-NEXT:  [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
-; X32-NEXT:  [[ARG7:%[0-9]+]](s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0)
-; X32-NEXT:  [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
-; X32-NEXT:  [[ARG8:%[0-9]+]](s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0)
-
-; ALL-NEXT:  [[GADDR_A1:%[0-9]+]](p0) = G_GLOBAL_VALUE @a1_32bit
-; ALL-NEXT:  [[GADDR_A7:%[0-9]+]](p0) = G_GLOBAL_VALUE @a7_32bit
-; ALL-NEXT:  [[GADDR_A8:%[0-9]+]](p0) = G_GLOBAL_VALUE @a8_32bit
+; X32:       [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X32-NEXT:  [[ARG1:%[0-9]+]]:_(s32) = G_LOAD [[ARG1_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
+; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
+; X32-NEXT:  [[ARG2:%[0-9]+]]:_(s32) = G_LOAD [[ARG2_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
+; X32-NEXT:  [[ARG3_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X32-NEXT:  [[ARG3:%[0-9]+]]:_(s32) = G_LOAD [[ARG3_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
+; X32-NEXT:  [[ARG4_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
+; X32-NEXT:  [[ARG4:%[0-9]+]]:_(s32) = G_LOAD [[ARG4_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0)
+; X32-NEXT:  [[ARG5_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
+; X32-NEXT:  [[ARG5:%[0-9]+]]:_(s32) = G_LOAD [[ARG5_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0)
+; X32-NEXT:  [[ARG6_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
+; X32-NEXT:  [[ARG6:%[0-9]+]]:_(s32) = G_LOAD [[ARG6_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0)
+; X32-NEXT:  [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
+; X32-NEXT:  [[ARG7:%[0-9]+]]:_(s32) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0)
+; X32-NEXT:  [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
+; X32-NEXT:  [[ARG8:%[0-9]+]]:_(s32) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0)
+
+; ALL-NEXT:  [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_32bit
+; ALL-NEXT:  [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_32bit
+; ALL-NEXT:  [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_32bit
 ; ALL-NEXT:  G_STORE [[ARG1]](s32), [[GADDR_A1]](p0) :: (store 4 into @a1_32bit)
 ; ALL-NEXT:  G_STORE [[ARG7]](s32), [[GADDR_A7]](p0) :: (store 4 into @a7_32bit)
 ; ALL-NEXT:  G_STORE [[ARG8]](s32), [[GADDR_A8]](p0) :: (store 4 into @a8_32bit)
@@ -190,16 +190,16 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
 ; X64:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16,
 ; X64-NEXT: isImmutable: true,
 ; X64: liveins: %rcx, %rdi, %rdx, %rsi, %r8, %r9
-; X64:      [[ARG1:%[0-9]+]](s64) = COPY %rdi
-; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rsi
-; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rdx
-; X64-NEXT: %{{[0-9]+}}(s64) = COPY %rcx
-; X64-NEXT: %{{[0-9]+}}(s64) = COPY %r8
-; X64-NEXT: %{{[0-9]+}}(s64) = COPY %r9
-; X64-NEXT: [[ARG7_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X64-NEXT: [[ARG7:%[0-9]+]](s64) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
-; X64-NEXT: [[ARG8_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X64-NEXT: [[ARG8:%[0-9]+]](s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
+; X64:      [[ARG1:%[0-9]+]]:_(s64) = COPY %rdi
+; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rsi
+; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rdx
+; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %rcx
+; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %r8
+; X64-NEXT: %{{[0-9]+}}:_(s64) = COPY %r9
+; X64-NEXT: [[ARG7_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X64-NEXT: [[ARG7:%[0-9]+]]:_(s64) = G_LOAD [[ARG7_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
+; X64-NEXT: [[ARG8_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X64-NEXT: [[ARG8:%[0-9]+]]:_(s64) = G_LOAD [[ARG8_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0)
 
 ; X32: fixedStack:
 ; X32:  id: [[STACK60:[0-9]+]], type: default, offset: 60, size: 4, alignment: 4,
@@ -235,52 +235,52 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
 ; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
 ; X32-NEXT: isImmutable: true,
 
-; X32:      [[ARG1L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X32-NEXT: [[ARG1L:%[0-9]+]](s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
-; X32-NEXT: [[ARG1H_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
-; X32-NEXT: [[ARG1H:%[0-9]+]](s32) = G_LOAD [[ARG1H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK32]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK32]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK36]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK36]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK40]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK40]], align 0)
-; X32-NEXT: %{{[0-9]+}}(p0) = G_FRAME_INDEX %fixed-stack.[[STACK44]]
-; X32-NEXT: %{{[0-9]+}}(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK44]], align 0)
-; X32-NEXT: [[ARG7L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK48]]
-; X32-NEXT: [[ARG7L:%[0-9]+]](s32) = G_LOAD [[ARG7L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK48]], align 0)
-; X32-NEXT: [[ARG7H_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK52]]
-; X32-NEXT: [[ARG7H:%[0-9]+]](s32) = G_LOAD [[ARG7H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK52]], align 0)
-; X32-NEXT: [[ARG8L_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK56]]
-; X32-NEXT: [[ARG8L:%[0-9]+]](s32) = G_LOAD [[ARG8L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK56]], align 0)
-; X32-NEXT: [[ARG8H_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK60]]
-; X32-NEXT: [[ARG8H:%[0-9]+]](s32) = G_LOAD [[ARG8H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK60]], align 0)
-
-; X32-NEXT: [[ARG1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG1L]](s32), [[ARG1H]](s32)
+; X32:      [[ARG1L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X32-NEXT: [[ARG1L:%[0-9]+]]:_(s32) = G_LOAD [[ARG1L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
+; X32-NEXT: [[ARG1H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
+; X32-NEXT: [[ARG1H:%[0-9]+]]:_(s32) = G_LOAD [[ARG1H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK8]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK12]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK12]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK16]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK20]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK20]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK24]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK24]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK28]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK28]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK32]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK32]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK36]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK36]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK40]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK40]], align 0)
+; X32-NEXT: %{{[0-9]+}}:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK44]]
+; X32-NEXT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (invariant load 4 from %fixed-stack.[[STACK44]], align 0)
+; X32-NEXT: [[ARG7L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK48]]
+; X32-NEXT: [[ARG7L:%[0-9]+]]:_(s32) = G_LOAD [[ARG7L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK48]], align 0)
+; X32-NEXT: [[ARG7H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK52]]
+; X32-NEXT: [[ARG7H:%[0-9]+]]:_(s32) = G_LOAD [[ARG7H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK52]], align 0)
+; X32-NEXT: [[ARG8L_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK56]]
+; X32-NEXT: [[ARG8L:%[0-9]+]]:_(s32) = G_LOAD [[ARG8L_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK56]], align 0)
+; X32-NEXT: [[ARG8H_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK60]]
+; X32-NEXT: [[ARG8H:%[0-9]+]]:_(s32) = G_LOAD [[ARG8H_ADDR]](p0) :: (invariant load 4 from %fixed-stack.[[STACK60]], align 0)
+
+; X32-NEXT: [[ARG1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG1L]](s32), [[ARG1H]](s32)
 ; ... a bunch more that we don't track ...
 ; X32-NEXT: G_MERGE_VALUES
 ; X32-NEXT: G_MERGE_VALUES
 ; X32-NEXT: G_MERGE_VALUES
 ; X32-NEXT: G_MERGE_VALUES
 ; X32-NEXT: G_MERGE_VALUES
-; X32-NEXT: [[ARG7:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG7L]](s32), [[ARG7H]](s32)
-; X32-NEXT: [[ARG8:%[0-9]+]](s64) = G_MERGE_VALUES [[ARG8L]](s32), [[ARG8H]](s32)
+; X32-NEXT: [[ARG7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG7L]](s32), [[ARG7H]](s32)
+; X32-NEXT: [[ARG8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARG8L]](s32), [[ARG8H]](s32)
 
-; ALL-NEXT: [[GADDR_A1:%[0-9]+]](p0) = G_GLOBAL_VALUE @a1_64bit
-; ALL-NEXT: [[GADDR_A7:%[0-9]+]](p0) = G_GLOBAL_VALUE @a7_64bit
-; ALL-NEXT: [[GADDR_A8:%[0-9]+]](p0) = G_GLOBAL_VALUE @a8_64bit
+; ALL-NEXT: [[GADDR_A1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a1_64bit
+; ALL-NEXT: [[GADDR_A7:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a7_64bit
+; ALL-NEXT: [[GADDR_A8:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @a8_64bit
 ; ALL-NEXT: G_STORE [[ARG1]](s64), [[GADDR_A1]](p0) :: (store 8 into @a1_64bit
 ; ALL-NEXT: G_STORE [[ARG7]](s64), [[GADDR_A7]](p0) :: (store 8 into @a7_64bit
 ; ALL-NEXT: G_STORE [[ARG8]](s64), [[GADDR_A8]](p0) :: (store 8 into @a8_64bit
@@ -288,7 +288,7 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4,
 ; X64-NEXT: %rax = COPY [[ARG1]](s64)
 ; X64-NEXT: RET 0, implicit %rax
 
-; X32-NEXT: [[RETL:%[0-9]+]](s32), [[RETH:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](s64)
+; X32-NEXT: [[RETL:%[0-9]+]]:_(s32), [[RETH:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](s64)
 ; X32-NEXT: %eax = COPY [[RETL:%[0-9]+]](s32)
 ; X32-NEXT: %edx = COPY [[RETH:%[0-9]+]](s32)
 ; X32-NEXT: RET 0, implicit %eax, implicit %edx
@@ -304,8 +304,8 @@ define float @test_float_args(float %arg1, float %arg2) {
 ; ALL-LABEL:name:            test_float_args
 
 ; X64: liveins: %xmm0, %xmm1
-; X64:      [[ARG1:%[0-9]+]](s32) = COPY %xmm0
-; X64-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %xmm1
+; X64:      [[ARG1:%[0-9]+]]:_(s32) = COPY %xmm0
+; X64-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %xmm1
 ; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s32)
 ; X64-NEXT: RET 0, implicit %xmm0
 
@@ -314,10 +314,10 @@ define float @test_float_args(float %arg1, float %arg2) {
 ; X32-NEXT: isImmutable: true,
 ; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16
 ; X32-NEXT: isImmutable: true,
-; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X32-NEXT:  [[ARG1:%[0-9]+]](s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
-; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
-; X32-NEXT:  [[ARG2:%[0-9]+]](s32) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
+; X32:       [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X32-NEXT:  [[ARG1:%[0-9]+]]:_(s32) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
+; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
+; X32-NEXT:  [[ARG2:%[0-9]+]]:_(s32) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 4 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  %fp0 = COPY [[ARG2:%[0-9]+]](s32)
 ; X32-NEXT:  RET 0, implicit %fp0
 
@@ -327,8 +327,8 @@ define float @test_float_args(float %arg1, float %arg2) {
 define double @test_double_args(double %arg1, double %arg2) {
 ; ALL-LABEL:name:            test_double_args
 ; X64: liveins: %xmm0, %xmm1
-; X64:     [[ARG1:%[0-9]+]](s64) = COPY %xmm0
-; X64-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %xmm1
+; X64:     [[ARG1:%[0-9]+]]:_(s64) = COPY %xmm0
+; X64-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %xmm1
 ; X64-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](s64)
 ; X64-NEXT: RET 0, implicit %xmm0
 
@@ -339,10 +339,10 @@ define double @test_double_args(double %arg1, double %arg2) {
 ; X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 8, alignment: 16,
 ; X32-NEXT: isImmutable: true,
 
-; X32:       [[ARG1_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-; X32-NEXT:  [[ARG1:%[0-9]+]](s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
-; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
-; X32-NEXT:  [[ARG2:%[0-9]+]](s64) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK4]], align 0)
+; X32:       [[ARG1_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+; X32-NEXT:  [[ARG1:%[0-9]+]]:_(s64) = G_LOAD [[ARG1_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0)
+; X32-NEXT:  [[ARG2_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK4]]
+; X32-NEXT:  [[ARG2:%[0-9]+]]:_(s64) = G_LOAD [[ARG2_ADDR:%[0-9]+]](p0) :: (invariant load 8 from %fixed-stack.[[STACK4]], align 0)
 ; X32-NEXT:  %fp0 = COPY [[ARG2:%[0-9]+]](s64)
 ; X32-NEXT:  RET 0, implicit %fp0
 
@@ -352,8 +352,8 @@ define double @test_double_args(double %arg1, double %arg2) {
 define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) {
 ; ALL: name:            test_v4i32_args
 ; ALL: liveins: %xmm0, %xmm1
-; ALL:      [[ARG1:%[0-9]+]](<4 x s32>) = COPY %xmm0
-; ALL-NEXT: [[ARG2:%[0-9]+]](<4 x s32>) = COPY %xmm1
+; ALL:      [[ARG1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0
+; ALL-NEXT: [[ARG2:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1
 ; ALL-NEXT: %xmm0 = COPY [[ARG2:%[0-9]+]](<4 x s32>)
 ; ALL-NEXT: RET 0, implicit %xmm0
   ret <4 x i32> %arg2
@@ -362,10 +362,10 @@ define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) {
 define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) {
 ; ALL: name:            test_v8i32_args
 ; ALL: liveins: %xmm0, %xmm1
-; ALL:      [[ARG1L:%[0-9]+]](<4 x s32>) = COPY %xmm0
-; ALL-NEXT: [[ARG1H:%[0-9]+]](<4 x s32>) = COPY %xmm1
-; ALL-NEXT: [[ARG1:%[0-9]+]](<8 x s32>) = G_MERGE_VALUES [[ARG1L]](<4 x s32>), [[ARG1H]](<4 x s32>)
-; ALL-NEXT: [[RETL:%[0-9]+]](<4 x s32>), [[RETH:%[0-9]+]](<4 x s32>) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](<8 x s32>)
+; ALL:      [[ARG1L:%[0-9]+]]:_(<4 x s32>) = COPY %xmm0
+; ALL-NEXT: [[ARG1H:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1
+; ALL-NEXT: [[ARG1:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[ARG1L]](<4 x s32>), [[ARG1H]](<4 x s32>)
+; ALL-NEXT: [[RETL:%[0-9]+]]:_(<4 x s32>), [[RETH:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ARG1:%[0-9]+]](<8 x s32>)
 ; ALL-NEXT: %xmm0 = COPY [[RETL:%[0-9]+]](<4 x s32>)
 ; ALL-NEXT: %xmm1 = COPY [[RETH:%[0-9]+]](<4 x s32>)
 ; ALL-NEXT: RET 0, implicit %xmm0, implicit %xmm1
@@ -384,15 +384,15 @@ entry:
 define i32 * @test_memop_i32(i32 * %p1) {
 ; ALL-LABEL:name:            test_memop_i32
 ;X64    liveins: %rdi
-;X64:       %0(p0) = COPY %rdi
+;X64:       %0:_(p0) = COPY %rdi
 ;X64-NEXT:  %rax = COPY %0(p0)
 ;X64-NEXT:  RET 0, implicit %rax
 
 ;X32: fixedStack:
 ;X32:  id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 4, alignment: 16,
 ;X32-NEXT: isImmutable: true,
-;X32:         %1(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
-;X32-NEXT:    %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
+;X32:         %1:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
+;X32-NEXT:    %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.[[STACK0]], align 0)
 ;X32-NEXT:    %eax = COPY %0(p0)
 ;X32-NEXT:    RET 0, implicit %eax
 
@@ -421,32 +421,32 @@ declare void @simple_arg_callee(i32 %in0, i32 %in1)
 define void @test_simple_arg(i32 %in0, i32 %in1) {
 ; ALL-LABEL: name:            test_simple_arg
 
-; X32:      fixedStack:      
+; X32:      fixedStack:
 ; X32:   - { id: 0, type: default, offset: 4, size: 4, alignment: 4,
 ; X32-NEXT:  isImmutable: true,
 ; X32:   - { id: 1, type: default, offset: 0, size: 4, alignment: 16,
 ; X32-NEXT:  isImmutable: true,
 ; X32:      body:             |
 ; X32-NEXT:   bb.1 (%ir-block.0):
-; X32-NEXT:     %2(p0) = G_FRAME_INDEX %fixed-stack.1
-; X32-NEXT:     %0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
-; X32-NEXT:     %3(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:     %1(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32-NEXT:     %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+; X32-NEXT:     %0:_(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+; X32-NEXT:     %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:     %1:_(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
 ; X32-NEXT:     ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:     %4(p0) = COPY %esp
-; X32-NEXT:     %5(s32) = G_CONSTANT i32 0
-; X32-NEXT:     %6(p0) = G_GEP %4, %5(s32)
+; X32-NEXT:     %4:_(p0) = COPY %esp
+; X32-NEXT:     %5:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:     %6:_(p0) = G_GEP %4, %5(s32)
 ; X32-NEXT:     G_STORE %1(s32), %6(p0) :: (store 4 into stack, align 0)
-; X32-NEXT:     %7(p0) = COPY %esp
-; X32-NEXT:     %8(s32) = G_CONSTANT i32 4
-; X32-NEXT:     %9(p0) = G_GEP %7, %8(s32)
+; X32-NEXT:     %7:_(p0) = COPY %esp
+; X32-NEXT:     %8:_(s32) = G_CONSTANT i32 4
+; X32-NEXT:     %9:_(p0) = G_GEP %7, %8(s32)
 ; X32-NEXT:     G_STORE %0(s32), %9(p0) :: (store 4 into stack + 4, align 0)
 ; X32-NEXT:     CALLpcrel32 @simple_arg_callee, csr_32, implicit %esp
 ; X32-NEXT:     ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:     RET 0
 
-; X64:      %0(s32) = COPY %edi
-; X64-NEXT: %1(s32) = COPY %esi
+; X64:      %0:_(s32) = COPY %edi
+; X64-NEXT: %1:_(s32) = COPY %esi
 ; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT: %edi = COPY %1(s32)
 ; X64-NEXT: %esi = COPY %0(s32)
@@ -462,51 +462,51 @@ declare void @simple_arg8_callee(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32
 define void @test_simple_arg8_call(i32 %in0) {
 ; ALL-LABEL: name:            test_simple_arg8_call
 
-; X32:      fixedStack:      
+; X32:      fixedStack:
 ; X32:   - { id: 0, type: default, offset: 0, size: 4, alignment: 16,
-; X32-NEXT:  isImmutable: true,         
+; X32-NEXT:  isImmutable: true,
 ; X32:     body:             |
 ; X32-NEXT:   bb.1 (%ir-block.0):
-; X32-NEXT:     %1(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:     %0(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32-NEXT:     %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:     %0:_(s32) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
 ; X32-NEXT:     ADJCALLSTACKDOWN32 32, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:     %2(p0) = COPY %esp
-; X32-NEXT:     %3(s32) = G_CONSTANT i32 0
-; X32-NEXT:     %4(p0) = G_GEP %2, %3(s32)
+; X32-NEXT:     %2:_(p0) = COPY %esp
+; X32-NEXT:     %3:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:     %4:_(p0) = G_GEP %2, %3(s32)
 ; X32-NEXT:     G_STORE %0(s32), %4(p0) :: (store 4 into stack, align 0)
-; X32-NEXT:     %5(p0) = COPY %esp
-; X32-NEXT:     %6(s32) = G_CONSTANT i32 4
-; X32-NEXT:     %7(p0) = G_GEP %5, %6(s32)
+; X32-NEXT:     %5:_(p0) = COPY %esp
+; X32-NEXT:     %6:_(s32) = G_CONSTANT i32 4
+; X32-NEXT:     %7:_(p0) = G_GEP %5, %6(s32)
 ; X32-NEXT:     G_STORE %0(s32), %7(p0) :: (store 4 into stack + 4, align 0)
-; X32-NEXT:     %8(p0) = COPY %esp
-; X32-NEXT:     %9(s32) = G_CONSTANT i32 8
-; X32-NEXT:     %10(p0) = G_GEP %8, %9(s32)
+; X32-NEXT:     %8:_(p0) = COPY %esp
+; X32-NEXT:     %9:_(s32) = G_CONSTANT i32 8
+; X32-NEXT:     %10:_(p0) = G_GEP %8, %9(s32)
 ; X32-NEXT:     G_STORE %0(s32), %10(p0) :: (store 4 into stack + 8, align 0)
-; X32-NEXT:     %11(p0) = COPY %esp
-; X32-NEXT:     %12(s32) = G_CONSTANT i32 12
-; X32-NEXT:     %13(p0) = G_GEP %11, %12(s32)
+; X32-NEXT:     %11:_(p0) = COPY %esp
+; X32-NEXT:     %12:_(s32) = G_CONSTANT i32 12
+; X32-NEXT:     %13:_(p0) = G_GEP %11, %12(s32)
 ; X32-NEXT:     G_STORE %0(s32), %13(p0) :: (store 4 into stack + 12, align 0)
-; X32-NEXT:     %14(p0) = COPY %esp
-; X32-NEXT:     %15(s32) = G_CONSTANT i32 16
-; X32-NEXT:     %16(p0) = G_GEP %14, %15(s32)
+; X32-NEXT:     %14:_(p0) = COPY %esp
+; X32-NEXT:     %15:_(s32) = G_CONSTANT i32 16
+; X32-NEXT:     %16:_(p0) = G_GEP %14, %15(s32)
 ; X32-NEXT:     G_STORE %0(s32), %16(p0) :: (store 4 into stack + 16, align 0)
-; X32-NEXT:     %17(p0) = COPY %esp
-; X32-NEXT:     %18(s32) = G_CONSTANT i32 20
-; X32-NEXT:     %19(p0) = G_GEP %17, %18(s32)
+; X32-NEXT:     %17:_(p0) = COPY %esp
+; X32-NEXT:     %18:_(s32) = G_CONSTANT i32 20
+; X32-NEXT:     %19:_(p0) = G_GEP %17, %18(s32)
 ; X32-NEXT:     G_STORE %0(s32), %19(p0) :: (store 4 into stack + 20, align 0)
-; X32-NEXT:     %20(p0) = COPY %esp
-; X32-NEXT:     %21(s32) = G_CONSTANT i32 24
-; X32-NEXT:     %22(p0) = G_GEP %20, %21(s32)
+; X32-NEXT:     %20:_(p0) = COPY %esp
+; X32-NEXT:     %21:_(s32) = G_CONSTANT i32 24
+; X32-NEXT:     %22:_(p0) = G_GEP %20, %21(s32)
 ; X32-NEXT:     G_STORE %0(s32), %22(p0) :: (store 4 into stack + 24, align 0)
-; X32-NEXT:     %23(p0) = COPY %esp
-; X32-NEXT:     %24(s32) = G_CONSTANT i32 28
-; X32-NEXT:     %25(p0) = G_GEP %23, %24(s32)
+; X32-NEXT:     %23:_(p0) = COPY %esp
+; X32-NEXT:     %24:_(s32) = G_CONSTANT i32 28
+; X32-NEXT:     %25:_(p0) = G_GEP %23, %24(s32)
 ; X32-NEXT:     G_STORE %0(s32), %25(p0) :: (store 4 into stack + 28, align 0)
 ; X32-NEXT:     CALLpcrel32 @simple_arg8_callee, csr_32, implicit %esp
 ; X32-NEXT:     ADJCALLSTACKUP32 32, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:     RET 0
 
-; X64:          %0(s32) = COPY %edi
+; X64:          %0:_(s32) = COPY %edi
 ; X64-NEXT:     ADJCALLSTACKDOWN64 16, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:     %edi = COPY %0(s32)
 ; X64-NEXT:     %esi = COPY %0(s32)
@@ -514,13 +514,13 @@ define void @test_simple_arg8_call(i32 %in0) {
 ; X64-NEXT:     %ecx = COPY %0(s32)
 ; X64-NEXT:     %r8d = COPY %0(s32)
 ; X64-NEXT:     %r9d = COPY %0(s32)
-; X64-NEXT:     %1(p0) = COPY %rsp
-; X64-NEXT:     %2(s64) = G_CONSTANT i64 0
-; X64-NEXT:     %3(p0) = G_GEP %1, %2(s64)
+; X64-NEXT:     %1:_(p0) = COPY %rsp
+; X64-NEXT:     %2:_(s64) = G_CONSTANT i64 0
+; X64-NEXT:     %3:_(p0) = G_GEP %1, %2(s64)
 ; X64-NEXT:     G_STORE %0(s32), %3(p0) :: (store 4 into stack, align 0)
-; X64-NEXT:     %4(p0) = COPY %rsp
-; X64-NEXT:     %5(s64) = G_CONSTANT i64 8
-; X64-NEXT:     %6(p0) = G_GEP %4, %5(s64)
+; X64-NEXT:     %4:_(p0) = COPY %rsp
+; X64-NEXT:     %5:_(s64) = G_CONSTANT i64 8
+; X64-NEXT:     %6:_(p0) = G_GEP %4, %5(s64)
 ; X64-NEXT:     G_STORE %0(s32), %6(p0) :: (store 4 into stack + 8, align 0)
 ; X64-NEXT:     CALL64pcrel32 @simple_arg8_callee, csr_64, implicit %rsp, implicit %edi, implicit %esi, implicit %edx, implicit %ecx, implicit %r8d, implicit %r9d
 ; X64-NEXT:     ADJCALLSTACKUP64 16, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
@@ -534,29 +534,29 @@ declare i32 @simple_return_callee(i32 %in0)
 define i32 @test_simple_return_callee() {
 ; ALL-LABEL: name:            test_simple_return_callee
 
-; X32:      %1(s32) = G_CONSTANT i32 5
+; X32:      %1:_(s32) = G_CONSTANT i32 5
 ; X32-NEXT: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT: %2(p0) = COPY %esp
-; X32-NEXT: %3(s32) = G_CONSTANT i32 0
-; X32-NEXT: %4(p0) = G_GEP %2, %3(s32)
+; X32-NEXT: %2:_(p0) = COPY %esp
+; X32-NEXT: %3:_(s32) = G_CONSTANT i32 0
+; X32-NEXT: %4:_(p0) = G_GEP %2, %3(s32)
 ; X32-NEXT: G_STORE %1(s32), %4(p0) :: (store 4 into stack, align 0)
 ; X32-NEXT: CALLpcrel32 @simple_return_callee, csr_32, implicit %esp, implicit-def %eax
-; X32-NEXT: %0(s32) = COPY %eax
+; X32-NEXT: %0:_(s32) = COPY %eax
 ; X32-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT: %5(s32) = G_ADD %0, %0
+; X32-NEXT: %5:_(s32) = G_ADD %0, %0
 ; X32-NEXT: %eax = COPY %5(s32)
 ; X32-NEXT: RET 0, implicit %eax
 
-; X64:      %1(s32) = G_CONSTANT i32 5                                                                 
-; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp          
-; X64-NEXT: %edi = COPY %1(s32)                                                                         
+; X64:      %1:_(s32) = G_CONSTANT i32 5
+; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
+; X64-NEXT: %edi = COPY %1(s32)
 ; X64-NEXT: CALL64pcrel32 @simple_return_callee, csr_64, implicit %rsp, implicit %edi, implicit-def %eax
-; X64-NEXT: %0(s32) = COPY %eax                                                                         
-; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp               
-; X64-NEXT: %2(s32) = G_ADD %0, %0                                                                      
-; X64-NEXT: %eax = COPY %2(s32)                                                                         
+; X64-NEXT: %0:_(s32) = COPY %eax
+; X64-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
+; X64-NEXT: %2:_(s32) = G_ADD %0, %0
+; X64-NEXT: %eax = COPY %2(s32)
 ; X64-NEXT: RET 0, implicit %eax
-                    
+
   %call = call i32 @simple_return_callee(i32 5)
   %r = add i32 %call, %call
   ret i32 %r
@@ -566,52 +566,52 @@ declare <8 x i32> @split_return_callee(<8 x i32> %in0)
 define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) {
 ; ALL-LABEL: name: test_split_return_callee
 
-; X32:       fixedStack:                                                                                                                                                                                   
+; X32:       fixedStack:
 ; X32-NEXT:   - { id: 0, type: default, offset: 0, size: 16, alignment: 16,
-; X32-NEXT:       isImmutable: true,                                                                                                            
-; X32:       %2(<4 x s32>) = COPY %xmm0                                                                                                                                                                
-; X32-NEXT:  %3(<4 x s32>) = COPY %xmm1                                                                                                                                                                
-; X32-NEXT:  %4(<4 x s32>) = COPY %xmm2                                                                                                                                                                
-; X32-NEXT:  %6(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:  %5(<4 x s32>) = G_LOAD %6(p0) :: (invariant load 16 from %fixed-stack.0, align 0)
-; X32-NEXT:  %0(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>)
-; X32-NEXT:  %1(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>)
+; X32-NEXT:       isImmutable: true,
+; X32:       %2:_(<4 x s32>) = COPY %xmm0
+; X32-NEXT:  %3:_(<4 x s32>) = COPY %xmm1
+; X32-NEXT:  %4:_(<4 x s32>) = COPY %xmm2
+; X32-NEXT:  %6:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:  %5:_(<4 x s32>) = G_LOAD %6(p0) :: (invariant load 16 from %fixed-stack.0, align 0)
+; X32-NEXT:  %0:_(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>)
+; X32-NEXT:  %1:_(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>)
 ; X32-NEXT:  ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:  %8(<4 x s32>), %9(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
+; X32-NEXT:  %8:_(<4 x s32>), %9:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
 ; X32-NEXT:  %xmm0 = COPY %8(<4 x s32>)
 ; X32-NEXT:  %xmm1 = COPY %9(<4 x s32>)
 ; X32-NEXT:  CALLpcrel32 @split_return_callee, csr_32, implicit %esp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1
-; X32-NEXT:  %10(<4 x s32>) = COPY %xmm0
-; X32-NEXT:  %11(<4 x s32>) = COPY %xmm1
-; X32-NEXT:  %7(<8 x s32>) = G_MERGE_VALUES %10(<4 x s32>), %11(<4 x s32>)
+; X32-NEXT:  %10:_(<4 x s32>) = COPY %xmm0
+; X32-NEXT:  %11:_(<4 x s32>) = COPY %xmm1
+; X32-NEXT:  %7:_(<8 x s32>) = G_MERGE_VALUES %10(<4 x s32>), %11(<4 x s32>)
 ; X32-NEXT:  ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:  %12(<8 x s32>) = G_ADD %0, %7
-; X32-NEXT:  %13(<4 x s32>), %14(<4 x s32>) = G_UNMERGE_VALUES %12(<8 x s32>)
+; X32-NEXT:  %12:_(<8 x s32>) = G_ADD %0, %7
+; X32-NEXT:  %13:_(<4 x s32>), %14:_(<4 x s32>) = G_UNMERGE_VALUES %12(<8 x s32>)
 ; X32-NEXT:  %xmm0 = COPY %13(<4 x s32>)
 ; X32-NEXT:  %xmm1 = COPY %14(<4 x s32>)
-; X32-NEXT:  RET 0, implicit %xmm0, implicit %xmm1    
-
-; X64:       %2(<4 x s32>) = COPY %xmm0
-; X64-NEXT:  %3(<4 x s32>) = COPY %xmm1
-; X64-NEXT:  %4(<4 x s32>) = COPY %xmm2
-; X64-NEXT:  %5(<4 x s32>) = COPY %xmm3
-; X64-NEXT:  %0(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>)
-; X64-NEXT:  %1(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>)
+; X32-NEXT:  RET 0, implicit %xmm0, implicit %xmm1
+
+; X64:       %2:_(<4 x s32>) = COPY %xmm0
+; X64-NEXT:  %3:_(<4 x s32>) = COPY %xmm1
+; X64-NEXT:  %4:_(<4 x s32>) = COPY %xmm2
+; X64-NEXT:  %5:_(<4 x s32>) = COPY %xmm3
+; X64-NEXT:  %0:_(<8 x s32>) = G_MERGE_VALUES %2(<4 x s32>), %3(<4 x s32>)
+; X64-NEXT:  %1:_(<8 x s32>) = G_MERGE_VALUES %4(<4 x s32>), %5(<4 x s32>)
 ; X64-NEXT:  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
-; X64-NEXT:  %7(<4 x s32>), %8(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
+; X64-NEXT:  %7:_(<4 x s32>), %8:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
 ; X64-NEXT:  %xmm0 = COPY %7(<4 x s32>)
 ; X64-NEXT:  %xmm1 = COPY %8(<4 x s32>)
 ; X64-NEXT:  CALL64pcrel32 @split_return_callee, csr_64, implicit %rsp, implicit %xmm0, implicit %xmm1, implicit-def %xmm0, implicit-def %xmm1
-; X64-NEXT:  %9(<4 x s32>) = COPY %xmm0
-; X64-NEXT:  %10(<4 x s32>) = COPY %xmm1
-; X64-NEXT:  %6(<8 x s32>) = G_MERGE_VALUES %9(<4 x s32>), %10(<4 x s32>)
+; X64-NEXT:  %9:_(<4 x s32>) = COPY %xmm0
+; X64-NEXT:  %10:_(<4 x s32>) = COPY %xmm1
+; X64-NEXT:  %6:_(<8 x s32>) = G_MERGE_VALUES %9(<4 x s32>), %10(<4 x s32>)
 ; X64-NEXT:  ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
-; X64-NEXT:  %11(<8 x s32>) = G_ADD %0, %6
-; X64-NEXT:  %12(<4 x s32>), %13(<4 x s32>) = G_UNMERGE_VALUES %11(<8 x s32>)
+; X64-NEXT:  %11:_(<8 x s32>) = G_ADD %0, %6
+; X64-NEXT:  %12:_(<4 x s32>), %13:_(<4 x s32>) = G_UNMERGE_VALUES %11(<8 x s32>)
 ; X64-NEXT:  %xmm0 = COPY %12(<4 x s32>)
 ; X64-NEXT:  %xmm1 = COPY %13(<4 x s32>)
-; X64-NEXT:  RET 0, implicit %xmm0, implicit %xmm1    
-  
+; X64-NEXT:  RET 0, implicit %xmm0, implicit %xmm1
+
   %call = call <8 x i32> @split_return_callee(<8 x i32> %arg2)
   %r = add <8 x i32> %arg1, %call
   ret  <8 x i32> %r
@@ -620,19 +620,19 @@ define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) {
 define void @test_indirect_call(void()* %func) {
 ; ALL-LABEL: name:            test_indirect_call
 
-; X32:       registers:       
+; X32:       registers:
 ; X32-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
 ; X32-NEXT:   - { id: 1, class: _, preferred-register: '' }
-; X32:       %1(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:  %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32:       %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:  %0:gr32(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
 ; X32-NEXT:  ADJCALLSTACKDOWN32 0, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:  CALL32r %0(p0), csr_32, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKUP32 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:  RET 0
 
-; X64:      registers:       
+; X64:      registers:
 ; X64-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
-; X64:       %0(p0) = COPY %rdi
+; X64:       %0:gr64(p0) = COPY %rdi
 ; X64-NEXT:  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:  CALL64r %0(p0), csr_64, implicit %rsp
 ; X64-NEXT:  ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
@@ -647,52 +647,52 @@ declare void @take_char(i8)
 define void @test_abi_exts_call(i8* %addr) {
 ; ALL-LABEL: name:            test_abi_exts_call
 
-; X32:       fixedStack:      
-; X32-NEXT:   - { id: 0, type: default, offset: 0, size: 4, alignment: 16, 
-; X32-NEXT:       isImmutable: true, 
-; X32:       %1(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:  %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
-; X32-NEXT:  %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
+; X32:       fixedStack:
+; X32-NEXT:   - { id: 0, type: default, offset: 0, size: 4, alignment: 16,
+; X32-NEXT:       isImmutable: true,
+; X32:       %1:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:  %0:_(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32-NEXT:  %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
 ; X32-NEXT:  ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:  %3(p0) = COPY %esp
-; X32-NEXT:  %4(s32) = G_CONSTANT i32 0
-; X32-NEXT:  %5(p0) = G_GEP %3, %4(s32)
-; X32-NEXT:  %6(s32) = G_ANYEXT %2(s8)
+; X32-NEXT:  %3:_(p0) = COPY %esp
+; X32-NEXT:  %4:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:  %5:_(p0) = G_GEP %3, %4(s32)
+; X32-NEXT:  %6:_(s32) = G_ANYEXT %2(s8)
 ; X32-NEXT:  G_STORE %6(s32), %5(p0) :: (store 4 into stack, align 0)
 ; X32-NEXT:  CALLpcrel32 @take_char, csr_32, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:  %7(p0) = COPY %esp
-; X32-NEXT:  %8(s32) = G_CONSTANT i32 0
-; X32-NEXT:  %9(p0) = G_GEP %7, %8(s32)
-; X32-NEXT:  %10(s32) = G_SEXT %2(s8)
+; X32-NEXT:  %7:_(p0) = COPY %esp
+; X32-NEXT:  %8:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:  %9:_(p0) = G_GEP %7, %8(s32)
+; X32-NEXT:  %10:_(s32) = G_SEXT %2(s8)
 ; X32-NEXT:  G_STORE %10(s32), %9(p0) :: (store 4 into stack, align 0)
 ; X32-NEXT:  CALLpcrel32 @take_char, csr_32, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKDOWN32 4, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:  %11(p0) = COPY %esp
-; X32-NEXT:  %12(s32) = G_CONSTANT i32 0
-; X32-NEXT:  %13(p0) = G_GEP %11, %12(s32)
-; X32-NEXT:  %14(s32) = G_ZEXT %2(s8)
+; X32-NEXT:  %11:_(p0) = COPY %esp
+; X32-NEXT:  %12:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:  %13:_(p0) = G_GEP %11, %12(s32)
+; X32-NEXT:  %14:_(s32) = G_ZEXT %2(s8)
 ; X32-NEXT:  G_STORE %14(s32), %13(p0) :: (store 4 into stack, align 0)
 ; X32-NEXT:  CALLpcrel32 @take_char, csr_32, implicit %esp
 ; X32-NEXT:  ADJCALLSTACKUP32 4, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:  RET 0
 
-; X64:       %0(p0) = COPY %rdi
-; X64-NEXT:  %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
+; X64:       %0:_(p0) = COPY %rdi
+; X64-NEXT:  %1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
 ; X64-NEXT:  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
-; X64-NEXT:  %2(s32) = G_ANYEXT %1(s8)
+; X64-NEXT:  %2:_(s32) = G_ANYEXT %1(s8)
 ; X64-NEXT:  %edi = COPY %2(s32)
 ; X64-NEXT:  CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %edi
 ; X64-NEXT:  ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
-; X64-NEXT:  %3(s32) = G_SEXT %1(s8)
+; X64-NEXT:  %3:_(s32) = G_SEXT %1(s8)
 ; X64-NEXT:  %edi = COPY %3(s32)
 ; X64-NEXT:  CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %edi
 ; X64-NEXT:  ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
-; X64-NEXT:  %4(s32) = G_ZEXT %1(s8)
+; X64-NEXT:  %4:_(s32) = G_ZEXT %1(s8)
 ; X64-NEXT:  %edi = COPY %4(s32)
 ; X64-NEXT:  CALL64pcrel32 @take_char, csr_64, implicit %rsp, implicit %edi
 ; X64-NEXT:  ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
@@ -709,34 +709,34 @@ declare void @variadic_callee(i8*, ...)
 define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) {
 ; ALL-LABEL: name:            test_variadic_call_1
 
-; X32:      fixedStack:      
-; X32-NEXT:  - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0, 
+; X32:      fixedStack:
+; X32-NEXT:  - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
 ; X32-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
-; X32-NEXT:  - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0, 
+; X32-NEXT:  - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
 ; X32-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
-; X32:         %2(p0) = G_FRAME_INDEX %fixed-stack.1
-; X32-NEXT:    %0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
-; X32-NEXT:    %3(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:    %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
-; X32-NEXT:    %4(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr)
-; X32-NEXT:    %5(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr)
+; X32:         %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+; X32-NEXT:    %0:_(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+; X32-NEXT:    %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:    %1:_(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32-NEXT:    %4:_(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr)
+; X32-NEXT:    %5:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr)
 ; X32-NEXT:    ADJCALLSTACKDOWN32 8, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:    %6(p0) = COPY %esp
-; X32-NEXT:    %7(s32) = G_CONSTANT i32 0
-; X32-NEXT:    %8(p0) = G_GEP %6, %7(s32)
+; X32-NEXT:    %6:_(p0) = COPY %esp
+; X32-NEXT:    %7:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:    %8:_(p0) = G_GEP %6, %7(s32)
 ; X32-NEXT:    G_STORE %4(p0), %8(p0) :: (store 4 into stack, align 0)
-; X32-NEXT:    %9(p0) = COPY %esp
-; X32-NEXT:    %10(s32) = G_CONSTANT i32 4
-; X32-NEXT:    %11(p0) = G_GEP %9, %10(s32)
+; X32-NEXT:    %9:_(p0) = COPY %esp
+; X32-NEXT:    %10:_(s32) = G_CONSTANT i32 4
+; X32-NEXT:    %11:_(p0) = G_GEP %9, %10(s32)
 ; X32-NEXT:    G_STORE %5(s32), %11(p0) :: (store 4 into stack + 4, align 0)
 ; X32-NEXT:    CALLpcrel32 @variadic_callee, csr_32, implicit %esp
 ; X32-NEXT:    ADJCALLSTACKUP32 8, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:    RET 0
-  
-; X64:         %0(p0) = COPY %rdi
-; X64-NEXT:    %1(p0) = COPY %rsi
-; X64-NEXT:    %2(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr)
-; X64-NEXT:    %3(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr)
+
+; X64:         %0:_(p0) = COPY %rdi
+; X64-NEXT:    %1:_(p0) = COPY %rsi
+; X64-NEXT:    %2:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr)
+; X64-NEXT:    %3:_(s32) = G_LOAD %1(p0) :: (load 4 from %ir.val_ptr)
 ; X64-NEXT:    ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:    %rdi = COPY %2(p0)
 ; X64-NEXT:    %esi = COPY %3(s32)
@@ -744,7 +744,7 @@ define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) {
 ; X64-NEXT:    CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %rdi, implicit %esi, implicit %al
 ; X64-NEXT:    ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:    RET 0
-  
+
   %addr = load i8*, i8** %addr_ptr
   %val = load i32, i32* %val_ptr
   call void (i8*, ...) @variadic_callee(i8* %addr, i32 %val)
@@ -754,33 +754,33 @@ define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) {
 define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) {
 ; ALL-LABEL: name:            test_variadic_call_2
 
-; X32:      fixedStack:      
-; X32-NEXT:  - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0, 
+; X32:      fixedStack:
+; X32-NEXT:  - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
 ; X32-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
-; X32-NEXT:  - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0, 
+; X32-NEXT:  - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
 ; X32-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true }
-; X32:         %2(p0) = G_FRAME_INDEX %fixed-stack.1
-; X32-NEXT:    %0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
-; X32-NEXT:    %3(p0) = G_FRAME_INDEX %fixed-stack.0
-; X32-NEXT:    %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
-; X32-NEXT:    %4(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr)
-; X32-NEXT:    %5(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr, align 4)
+; X32:         %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+; X32-NEXT:    %0:_(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+; X32-NEXT:    %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+; X32-NEXT:    %1:_(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+; X32-NEXT:    %4:_(p0) = G_LOAD %0(p0) :: (load 4 from %ir.addr_ptr)
+; X32-NEXT:    %5:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr, align 4)
 ; X32-NEXT:    ADJCALLSTACKDOWN32 12, 0, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
-; X32-NEXT:    %6(p0) = COPY %esp
-; X32-NEXT:    %7(s32) = G_CONSTANT i32 0
-; X32-NEXT:    %8(p0) = G_GEP %6, %7(s32)
+; X32-NEXT:    %6:_(p0) = COPY %esp
+; X32-NEXT:    %7:_(s32) = G_CONSTANT i32 0
+; X32-NEXT:    %8:_(p0) = G_GEP %6, %7(s32)
 ; X32-NEXT:    G_STORE %4(p0), %8(p0) :: (store 4 into stack, align 0)
-; X32-NEXT:    %9(p0) = COPY %esp
-; X32-NEXT:    %10(s32) = G_CONSTANT i32 4
-; X32-NEXT:    %11(p0) = G_GEP %9, %10(s32)
+; X32-NEXT:    %9:_(p0) = COPY %esp
+; X32-NEXT:    %10:_(s32) = G_CONSTANT i32 4
+; X32-NEXT:    %11:_(p0) = G_GEP %9, %10(s32)
 ; X32-NEXT:    G_STORE %5(s64), %11(p0) :: (store 8 into stack + 4, align 0)
 ; X32-NEXT:    CALLpcrel32 @variadic_callee, csr_32, implicit %esp
 ; X32-NEXT:    ADJCALLSTACKUP32 12, 0, implicit-def %esp, implicit-def %eflags, implicit %esp
 ; X32-NEXT:    RET 0
-  
-; X64:         %1(p0) = COPY %rsi
-; X64-NEXT:    %2(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr)
-; X64-NEXT:    %3(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr)
+
+; X64:         %1:_(p0) = COPY %rsi
+; X64-NEXT:    %2:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr_ptr)
+; X64-NEXT:    %3:_(s64) = G_LOAD %1(p0) :: (load 8 from %ir.val_ptr)
 ; X64-NEXT:    ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:    %rdi = COPY %2(p0)
 ; X64-NEXT:    %xmm0 = COPY %3(s64)
@@ -788,7 +788,7 @@ define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) {
 ; X64-NEXT:    CALL64pcrel32 @variadic_callee, csr_64, implicit %rsp, implicit %rdi, implicit %xmm0, implicit %al
 ; X64-NEXT:    ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def %eflags, implicit %rsp
 ; X64-NEXT:    RET 0
-  
+
   %addr = load i8*, i8** %addr_ptr
   %val = load double, double* %val_ptr
   call void (i8*, ...) @variadic_callee(i8* %addr, double %val)
diff --git a/test/CodeGen/X86/GlobalISel/legalize-GV.mir b/test/CodeGen/X86/GlobalISel/legalize-GV.mir
index 7f9971e4c70..60ca303d038 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-GV.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-GV.mir
@@ -19,7 +19,7 @@ regBankSelected: false
 # ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
 registers:
   - { id: 0, class: _, preferred-register: '' }
-# ALL:          %0(p0) = G_GLOBAL_VALUE @g_int
+# ALL:          %0:_(p0) = G_GLOBAL_VALUE @g_int
 # ALL-NEXT:     %rax = COPY %0(p0)
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir b/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
index 8037775176d..4e59331a214 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
@@ -36,9 +36,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_add_v16i8
-    ; ALL: [[DEF:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
-    ; ALL: [[ADD:%[0-9]+]](<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<16 x s8>) = IMPLICIT_DEF
     %1(<16 x s8>) = IMPLICIT_DEF
@@ -60,9 +60,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_add_v8i16
-    ; ALL: [[DEF:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
-    ; ALL: [[ADD:%[0-9]+]](<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<8 x s16>) = IMPLICIT_DEF
     %1(<8 x s16>) = IMPLICIT_DEF
@@ -84,9 +84,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_add_v4i32
-    ; ALL: [[DEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
-    ; ALL: [[ADD:%[0-9]+]](<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<4 x s32>) = IMPLICIT_DEF
     %1(<4 x s32>) = IMPLICIT_DEF
@@ -108,9 +108,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_add_v2i64
-    ; ALL: [[DEF:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
-    ; ALL: [[ADD:%[0-9]+]](<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<2 x s64>) = IMPLICIT_DEF
     %1(<2 x s64>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir b/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
index 9f918c404b1..e6ae67c800d 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
@@ -34,18 +34,18 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# NOT_AVX2:          %0(<32 x s8>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %1(<32 x s8>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %3(<16 x s8>), %4(<16 x s8>) = G_UNMERGE_VALUES %0(<32 x s8>)
-# NOT_AVX2-NEXT:     %5(<16 x s8>), %6(<16 x s8>) = G_UNMERGE_VALUES %1(<32 x s8>)
-# NOT_AVX2-NEXT:     %7(<16 x s8>) = G_ADD %3, %5
-# NOT_AVX2-NEXT:     %8(<16 x s8>) = G_ADD %4, %6
-# NOT_AVX2-NEXT:     %2(<32 x s8>) = G_MERGE_VALUES %7(<16 x s8>), %8(<16 x s8>)
+# NOT_AVX2:          %0:_(<32 x s8>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %1:_(<32 x s8>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %3:_(<16 x s8>), %4:_(<16 x s8>) = G_UNMERGE_VALUES %0(<32 x s8>)
+# NOT_AVX2-NEXT:     %5:_(<16 x s8>), %6:_(<16 x s8>) = G_UNMERGE_VALUES %1(<32 x s8>)
+# NOT_AVX2-NEXT:     %7:_(<16 x s8>) = G_ADD %3, %5
+# NOT_AVX2-NEXT:     %8:_(<16 x s8>) = G_ADD %4, %6
+# NOT_AVX2-NEXT:     %2:_(<32 x s8>) = G_MERGE_VALUES %7(<16 x s8>), %8(<16 x s8>)
 # NOT_AVX2-NEXT:     RET 0
 #
-# AVX2:              %0(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT:         %1(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT:         %2(<32 x s8>) = G_ADD %0, %1
+# AVX2:              %0:_(<32 x s8>) = IMPLICIT_DEF
+# AVX2-NEXT:         %1:_(<32 x s8>) = IMPLICIT_DEF
+# AVX2-NEXT:         %2:_(<32 x s8>) = G_ADD %0, %1
 # AVX2-NEXT:         RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -67,18 +67,18 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# NOT_AVX2:          %0(<16 x s16>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %1(<16 x s16>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %3(<8 x s16>), %4(<8 x s16>) = G_UNMERGE_VALUES %0(<16 x s16>)
-# NOT_AVX2-NEXT:     %5(<8 x s16>), %6(<8 x s16>) = G_UNMERGE_VALUES %1(<16 x s16>)
-# NOT_AVX2-NEXT:     %7(<8 x s16>) = G_ADD %3, %5
-# NOT_AVX2-NEXT:     %8(<8 x s16>) = G_ADD %4, %6
-# NOT_AVX2-NEXT:     %2(<16 x s16>) = G_MERGE_VALUES %7(<8 x s16>), %8(<8 x s16>)
+# NOT_AVX2:          %0:_(<16 x s16>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %1:_(<16 x s16>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %3:_(<8 x s16>), %4:_(<8 x s16>) = G_UNMERGE_VALUES %0(<16 x s16>)
+# NOT_AVX2-NEXT:     %5:_(<8 x s16>), %6:_(<8 x s16>) = G_UNMERGE_VALUES %1(<16 x s16>)
+# NOT_AVX2-NEXT:     %7:_(<8 x s16>) = G_ADD %3, %5
+# NOT_AVX2-NEXT:     %8:_(<8 x s16>) = G_ADD %4, %6
+# NOT_AVX2-NEXT:     %2:_(<16 x s16>) = G_MERGE_VALUES %7(<8 x s16>), %8(<8 x s16>)
 # NOT_AVX2-NEXT:     RET 0
 #
-# AVX2:              %0(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT:         %1(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT:         %2(<16 x s16>) = G_ADD %0, %1
+# AVX2:              %0:_(<16 x s16>) = IMPLICIT_DEF
+# AVX2-NEXT:         %1:_(<16 x s16>) = IMPLICIT_DEF
+# AVX2-NEXT:         %2:_(<16 x s16>) = G_ADD %0, %1
 # AVX2-NEXT:         RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -100,18 +100,18 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# NOT_AVX2:          %0(<8 x s32>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %1(<8 x s32>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %3(<4 x s32>), %4(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
-# NOT_AVX2-NEXT:     %5(<4 x s32>), %6(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
-# NOT_AVX2-NEXT:     %7(<4 x s32>) = G_ADD %3, %5
-# NOT_AVX2-NEXT:     %8(<4 x s32>) = G_ADD %4, %6
-# NOT_AVX2-NEXT:     %2(<8 x s32>) = G_MERGE_VALUES %7(<4 x s32>), %8(<4 x s32>)
+# NOT_AVX2:          %0:_(<8 x s32>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %1:_(<8 x s32>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %3:_(<4 x s32>), %4:_(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
+# NOT_AVX2-NEXT:     %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
+# NOT_AVX2-NEXT:     %7:_(<4 x s32>) = G_ADD %3, %5
+# NOT_AVX2-NEXT:     %8:_(<4 x s32>) = G_ADD %4, %6
+# NOT_AVX2-NEXT:     %2:_(<8 x s32>) = G_MERGE_VALUES %7(<4 x s32>), %8(<4 x s32>)
 # NOT_AVX2-NEXT:     RET 0
 #
-# AVX2:              %0(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT:         %1(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT:         %2(<8 x s32>) = G_ADD %0, %1
+# AVX2:              %0:_(<8 x s32>) = IMPLICIT_DEF
+# AVX2-NEXT:         %1:_(<8 x s32>) = IMPLICIT_DEF
+# AVX2-NEXT:         %2:_(<8 x s32>) = G_ADD %0, %1
 # AVX2-NEXT:         RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -133,18 +133,18 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# NOT_AVX2:          %0(<4 x s64>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %1(<4 x s64>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT:     %3(<2 x s64>), %4(<2 x s64>) = G_UNMERGE_VALUES %0(<4 x s64>)
-# NOT_AVX2-NEXT:     %5(<2 x s64>), %6(<2 x s64>) = G_UNMERGE_VALUES %1(<4 x s64>)
-# NOT_AVX2-NEXT:     %7(<2 x s64>) = G_ADD %3, %5
-# NOT_AVX2-NEXT:     %8(<2 x s64>) = G_ADD %4, %6
-# NOT_AVX2-NEXT:     %2(<4 x s64>) = G_MERGE_VALUES %7(<2 x s64>), %8(<2 x s64>)
+# NOT_AVX2:          %0:_(<4 x s64>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %1:_(<4 x s64>) = IMPLICIT_DEF
+# NOT_AVX2-NEXT:     %3:_(<2 x s64>), %4:_(<2 x s64>) = G_UNMERGE_VALUES %0(<4 x s64>)
+# NOT_AVX2-NEXT:     %5:_(<2 x s64>), %6:_(<2 x s64>) = G_UNMERGE_VALUES %1(<4 x s64>)
+# NOT_AVX2-NEXT:     %7:_(<2 x s64>) = G_ADD %3, %5
+# NOT_AVX2-NEXT:     %8:_(<2 x s64>) = G_ADD %4, %6
+# NOT_AVX2-NEXT:     %2:_(<4 x s64>) = G_MERGE_VALUES %7(<2 x s64>), %8(<2 x s64>)
 # NOT_AVX2-NEXT:     RET 0
 #
-# AVX2:              %0(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT:         %1(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT:         %2(<4 x s64>) = G_ADD %0, %1
+# AVX2:              %0:_(<4 x s64>) = IMPLICIT_DEF
+# AVX2-NEXT:         %1:_(<4 x s64>) = IMPLICIT_DEF
+# AVX2-NEXT:         %2:_(<4 x s64>) = G_ADD %0, %1
 # AVX2-NEXT:         RET 0
 body:             |
   bb.1 (%ir-block.0):
diff --git a/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir b/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
index 5b7532ea5d0..f43d4e1621a 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
@@ -38,29 +38,29 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# AVX1:              %0(<64 x s8>) = IMPLICIT_DEF
-# AVX1-NEXT:         %1(<64 x s8>) = IMPLICIT_DEF
-# AVX1-NEXT:         %3(<16 x s8>), %4(<16 x s8>), %5(<16 x s8>), %6(<16 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
-# AVX1-NEXT:         %7(<16 x s8>), %8(<16 x s8>), %9(<16 x s8>), %10(<16 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
-# AVX1-NEXT:         %11(<16 x s8>) = G_ADD %3, %7
-# AVX1-NEXT:         %12(<16 x s8>) = G_ADD %4, %8
-# AVX1-NEXT:         %13(<16 x s8>) = G_ADD %5, %9
-# AVX1-NEXT:         %14(<16 x s8>) = G_ADD %6, %10
-# AVX1-NEXT:         %2(<64 x s8>) = G_MERGE_VALUES %11(<16 x s8>), %12(<16 x s8>), %13(<16 x s8>), %14(<16 x s8>)
+# AVX1:              %0:_(<64 x s8>) = IMPLICIT_DEF
+# AVX1-NEXT:         %1:_(<64 x s8>) = IMPLICIT_DEF
+# AVX1-NEXT:         %3:_(<16 x s8>), %4:_(<16 x s8>), %5:_(<16 x s8>), %6:_(<16 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
+# AVX1-NEXT:         %7:_(<16 x s8>), %8:_(<16 x s8>), %9:_(<16 x s8>), %10:_(<16 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
+# AVX1-NEXT:         %11:_(<16 x s8>) = G_ADD %3, %7
+# AVX1-NEXT:         %12:_(<16 x s8>) = G_ADD %4, %8
+# AVX1-NEXT:         %13:_(<16 x s8>) = G_ADD %5, %9
+# AVX1-NEXT:         %14:_(<16 x s8>) = G_ADD %6, %10
+# AVX1-NEXT:         %2:_(<64 x s8>) = G_MERGE_VALUES %11(<16 x s8>), %12(<16 x s8>), %13(<16 x s8>), %14(<16 x s8>)
 # AVX1-NEXT:         RET 0
 #
-# AVX512F:           %0(<64 x s8>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %1(<64 x s8>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %3(<32 x s8>), %4(<32 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
-# AVX512F-NEXT:      %5(<32 x s8>), %6(<32 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
-# AVX512F-NEXT:      %7(<32 x s8>) = G_ADD %3, %5
-# AVX512F-NEXT:      %8(<32 x s8>) = G_ADD %4, %6
-# AVX512F-NEXT:      %2(<64 x s8>) = G_MERGE_VALUES %7(<32 x s8>), %8(<32 x s8>)
+# AVX512F:           %0:_(<64 x s8>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %1:_(<64 x s8>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %3:_(<32 x s8>), %4:_(<32 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
+# AVX512F-NEXT:      %5:_(<32 x s8>), %6:_(<32 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
+# AVX512F-NEXT:      %7:_(<32 x s8>) = G_ADD %3, %5
+# AVX512F-NEXT:      %8:_(<32 x s8>) = G_ADD %4, %6
+# AVX512F-NEXT:      %2:_(<64 x s8>) = G_MERGE_VALUES %7(<32 x s8>), %8(<32 x s8>)
 # AVX512F-NEXT:      RET 0
 #
-# AVX512BW:          %0(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %1(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %2(<64 x s8>) = G_ADD %0, %1
+# AVX512BW:          %0:_(<64 x s8>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %1:_(<64 x s8>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %2:_(<64 x s8>) = G_ADD %0, %1
 # AVX512BW-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -82,29 +82,29 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# AVX1:              %0(<32 x s16>) = IMPLICIT_DEF
-# AVX1-NEXT:         %1(<32 x s16>) = IMPLICIT_DEF
-# AVX1-NEXT:         %3(<8 x s16>), %4(<8 x s16>), %5(<8 x s16>), %6(<8 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
-# AVX1-NEXT:         %7(<8 x s16>), %8(<8 x s16>), %9(<8 x s16>), %10(<8 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
-# AVX1-NEXT:         %11(<8 x s16>) = G_ADD %3, %7
-# AVX1-NEXT:         %12(<8 x s16>) = G_ADD %4, %8
-# AVX1-NEXT:         %13(<8 x s16>) = G_ADD %5, %9
-# AVX1-NEXT:         %14(<8 x s16>) = G_ADD %6, %10
-# AVX1-NEXT:         %2(<32 x s16>) = G_MERGE_VALUES %11(<8 x s16>), %12(<8 x s16>), %13(<8 x s16>), %14(<8 x s16>)
+# AVX1:              %0:_(<32 x s16>) = IMPLICIT_DEF
+# AVX1-NEXT:         %1:_(<32 x s16>) = IMPLICIT_DEF
+# AVX1-NEXT:         %3:_(<8 x s16>), %4:_(<8 x s16>), %5:_(<8 x s16>), %6:_(<8 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
+# AVX1-NEXT:         %7:_(<8 x s16>), %8:_(<8 x s16>), %9:_(<8 x s16>), %10:_(<8 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
+# AVX1-NEXT:         %11:_(<8 x s16>) = G_ADD %3, %7
+# AVX1-NEXT:         %12:_(<8 x s16>) = G_ADD %4, %8
+# AVX1-NEXT:         %13:_(<8 x s16>) = G_ADD %5, %9
+# AVX1-NEXT:         %14:_(<8 x s16>) = G_ADD %6, %10
+# AVX1-NEXT:         %2:_(<32 x s16>) = G_MERGE_VALUES %11(<8 x s16>), %12(<8 x s16>), %13(<8 x s16>), %14(<8 x s16>)
 # AVX1-NEXT:         RET 0
 #
-# AVX512F:           %0(<32 x s16>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %1(<32 x s16>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %3(<16 x s16>), %4(<16 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
-# AVX512F-NEXT:      %5(<16 x s16>), %6(<16 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
-# AVX512F-NEXT:      %7(<16 x s16>) = G_ADD %3, %5
-# AVX512F-NEXT:      %8(<16 x s16>) = G_ADD %4, %6
-# AVX512F-NEXT:      %2(<32 x s16>) = G_MERGE_VALUES %7(<16 x s16>), %8(<16 x s16>)
+# AVX512F:           %0:_(<32 x s16>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %1:_(<32 x s16>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %3:_(<16 x s16>), %4:_(<16 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
+# AVX512F-NEXT:      %5:_(<16 x s16>), %6:_(<16 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
+# AVX512F-NEXT:      %7:_(<16 x s16>) = G_ADD %3, %5
+# AVX512F-NEXT:      %8:_(<16 x s16>) = G_ADD %4, %6
+# AVX512F-NEXT:      %2:_(<32 x s16>) = G_MERGE_VALUES %7(<16 x s16>), %8(<16 x s16>)
 # AVX512F-NEXT:      RET 0
 #
-# AVX512BW:          %0(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %1(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %2(<32 x s16>) = G_ADD %0, %1
+# AVX512BW:          %0:_(<32 x s16>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %1:_(<32 x s16>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %2:_(<32 x s16>) = G_ADD %0, %1
 # AVX512BW-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -126,25 +126,25 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# AVX1:              %0(<16 x s32>) = IMPLICIT_DEF
-# AVX1-NEXT:         %1(<16 x s32>) = IMPLICIT_DEF
-# AVX1-NEXT:         %3(<4 x s32>), %4(<4 x s32>), %5(<4 x s32>), %6(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
-# AVX1-NEXT:         %7(<4 x s32>), %8(<4 x s32>), %9(<4 x s32>), %10(<4 x s32>) = G_UNMERGE_VALUES %1(<16 x s32>)
-# AVX1-NEXT:         %11(<4 x s32>) = G_ADD %3, %7
-# AVX1-NEXT:         %12(<4 x s32>) = G_ADD %4, %8
-# AVX1-NEXT:         %13(<4 x s32>) = G_ADD %5, %9
-# AVX1-NEXT:         %14(<4 x s32>) = G_ADD %6, %10
-# AVX1-NEXT:         %2(<16 x s32>) = G_MERGE_VALUES %11(<4 x s32>), %12(<4 x s32>), %13(<4 x s32>), %14(<4 x s32>)
+# AVX1:              %0:_(<16 x s32>) = IMPLICIT_DEF
+# AVX1-NEXT:         %1:_(<16 x s32>) = IMPLICIT_DEF
+# AVX1-NEXT:         %3:_(<4 x s32>), %4:_(<4 x s32>), %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
+# AVX1-NEXT:         %7:_(<4 x s32>), %8:_(<4 x s32>), %9:_(<4 x s32>), %10:_(<4 x s32>) = G_UNMERGE_VALUES %1(<16 x s32>)
+# AVX1-NEXT:         %11:_(<4 x s32>) = G_ADD %3, %7
+# AVX1-NEXT:         %12:_(<4 x s32>) = G_ADD %4, %8
+# AVX1-NEXT:         %13:_(<4 x s32>) = G_ADD %5, %9
+# AVX1-NEXT:         %14:_(<4 x s32>) = G_ADD %6, %10
+# AVX1-NEXT:         %2:_(<16 x s32>) = G_MERGE_VALUES %11(<4 x s32>), %12(<4 x s32>), %13(<4 x s32>), %14(<4 x s32>)
 # AVX1-NEXT:         RET 0
 #
-# AVX512F:           %0(<16 x s32>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %1(<16 x s32>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %2(<16 x s32>) = G_ADD %0, %1
+# AVX512F:           %0:_(<16 x s32>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %1:_(<16 x s32>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %2:_(<16 x s32>) = G_ADD %0, %1
 # AVX512F-NEXT:      RET 0
 #
-# AVX512BW:          %0(<16 x s32>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %1(<16 x s32>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %2(<16 x s32>) = G_ADD %0, %1
+# AVX512BW:          %0:_(<16 x s32>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %1:_(<16 x s32>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %2:_(<16 x s32>) = G_ADD %0, %1
 # AVX512BW-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -166,25 +166,25 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# AVX1:              %0(<8 x s64>) = IMPLICIT_DEF
-# AVX1-NEXT:         %1(<8 x s64>) = IMPLICIT_DEF
-# AVX1-NEXT:         %3(<2 x s64>), %4(<2 x s64>), %5(<2 x s64>), %6(<2 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
-# AVX1-NEXT:         %7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>), %10(<2 x s64>) = G_UNMERGE_VALUES %1(<8 x s64>)
-# AVX1-NEXT:         %11(<2 x s64>) = G_ADD %3, %7
-# AVX1-NEXT:         %12(<2 x s64>) = G_ADD %4, %8
-# AVX1-NEXT:         %13(<2 x s64>) = G_ADD %5, %9
-# AVX1-NEXT:         %14(<2 x s64>) = G_ADD %6, %10
-# AVX1-NEXT:         %2(<8 x s64>) = G_MERGE_VALUES %11(<2 x s64>), %12(<2 x s64>), %13(<2 x s64>), %14(<2 x s64>)
+# AVX1:              %0:_(<8 x s64>) = IMPLICIT_DEF
+# AVX1-NEXT:         %1:_(<8 x s64>) = IMPLICIT_DEF
+# AVX1-NEXT:         %3:_(<2 x s64>), %4:_(<2 x s64>), %5:_(<2 x s64>), %6:_(<2 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
+# AVX1-NEXT:         %7:_(<2 x s64>), %8:_(<2 x s64>), %9:_(<2 x s64>), %10:_(<2 x s64>) = G_UNMERGE_VALUES %1(<8 x s64>)
+# AVX1-NEXT:         %11:_(<2 x s64>) = G_ADD %3, %7
+# AVX1-NEXT:         %12:_(<2 x s64>) = G_ADD %4, %8
+# AVX1-NEXT:         %13:_(<2 x s64>) = G_ADD %5, %9
+# AVX1-NEXT:         %14:_(<2 x s64>) = G_ADD %6, %10
+# AVX1-NEXT:         %2:_(<8 x s64>) = G_MERGE_VALUES %11(<2 x s64>), %12(<2 x s64>), %13(<2 x s64>), %14(<2 x s64>)
 # AVX1-NEXT:         RET 0
 #
-# AVX512F:           %0(<8 x s64>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %1(<8 x s64>) = IMPLICIT_DEF
-# AVX512F-NEXT:      %2(<8 x s64>) = G_ADD %0, %1
+# AVX512F:           %0:_(<8 x s64>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %1:_(<8 x s64>) = IMPLICIT_DEF
+# AVX512F-NEXT:      %2:_(<8 x s64>) = G_ADD %0, %1
 # AVX512F-NEXT:      RET 0
 #
-# AVX512BW:          %0(<8 x s64>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %1(<8 x s64>) = IMPLICIT_DEF
-# AVX512BW-NEXT:     %2(<8 x s64>) = G_ADD %0, %1
+# AVX512BW:          %0:_(<8 x s64>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %1:_(<8 x s64>) = IMPLICIT_DEF
+# AVX512BW-NEXT:     %2:_(<8 x s64>) = G_ADD %0, %1
 # AVX512BW-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -212,42 +212,42 @@ registers:
   - { id: 6, class: _ }
   - { id: 7, class: _ }
   - { id: 8, class: _ }
-# AVX1:              %2(<32 x s8>) = COPY %ymm0
-# AVX1-NEXT:         %3(<32 x s8>) = COPY %ymm1
-# AVX1-NEXT:         %4(<32 x s8>) = COPY %ymm2
-# AVX1-NEXT:         %5(<32 x s8>) = COPY %ymm3
-# AVX1-NEXT:         %9(<16 x s8>), %10(<16 x s8>) = G_UNMERGE_VALUES %2(<32 x s8>)
-# AVX1-NEXT:         %11(<16 x s8>), %12(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
-# AVX1-NEXT:         %13(<16 x s8>), %14(<16 x s8>) = G_UNMERGE_VALUES %4(<32 x s8>)
-# AVX1-NEXT:         %15(<16 x s8>), %16(<16 x s8>) = G_UNMERGE_VALUES %5(<32 x s8>)
-# AVX1-NEXT:         %17(<16 x s8>) = G_ADD %9, %13
-# AVX1-NEXT:         %18(<16 x s8>) = G_ADD %10, %14
-# AVX1-NEXT:         %19(<16 x s8>) = G_ADD %11, %15
-# AVX1-NEXT:         %20(<16 x s8>) = G_ADD %12, %16
-# AVX1-NEXT:         %7(<32 x s8>) = G_MERGE_VALUES %17(<16 x s8>), %18(<16 x s8>)
-# AVX1-NEXT:         %8(<32 x s8>) = G_MERGE_VALUES %19(<16 x s8>), %20(<16 x s8>)
+# AVX1:              %2:_(<32 x s8>) = COPY %ymm0
+# AVX1-NEXT:         %3:_(<32 x s8>) = COPY %ymm1
+# AVX1-NEXT:         %4:_(<32 x s8>) = COPY %ymm2
+# AVX1-NEXT:         %5:_(<32 x s8>) = COPY %ymm3
+# AVX1-NEXT:         %9:_(<16 x s8>), %10:_(<16 x s8>) = G_UNMERGE_VALUES %2(<32 x s8>)
+# AVX1-NEXT:         %11:_(<16 x s8>), %12:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
+# AVX1-NEXT:         %13:_(<16 x s8>), %14:_(<16 x s8>) = G_UNMERGE_VALUES %4(<32 x s8>)
+# AVX1-NEXT:         %15:_(<16 x s8>), %16:_(<16 x s8>) = G_UNMERGE_VALUES %5(<32 x s8>)
+# AVX1-NEXT:         %17:_(<16 x s8>) = G_ADD %9, %13
+# AVX1-NEXT:         %18:_(<16 x s8>) = G_ADD %10, %14
+# AVX1-NEXT:         %19:_(<16 x s8>) = G_ADD %11, %15
+# AVX1-NEXT:         %20:_(<16 x s8>) = G_ADD %12, %16
+# AVX1-NEXT:         %7:_(<32 x s8>) = G_MERGE_VALUES %17(<16 x s8>), %18(<16 x s8>)
+# AVX1-NEXT:         %8:_(<32 x s8>) = G_MERGE_VALUES %19(<16 x s8>), %20(<16 x s8>)
 # AVX1-NEXT:         %ymm0 = COPY %7(<32 x s8>)
 # AVX1-NEXT:         %ymm1 = COPY %8(<32 x s8>)
 # AVX1-NEXT:         RET 0, implicit %ymm0, implicit %ymm1
 #
-# AVX512F:           %2(<32 x s8>) = COPY %ymm0
-# AVX512F-NEXT:      %3(<32 x s8>) = COPY %ymm1
-# AVX512F-NEXT:      %4(<32 x s8>) = COPY %ymm2
-# AVX512F-NEXT:      %5(<32 x s8>) = COPY %ymm3
-# AVX512F-NEXT:      %13(<32 x s8>) = G_ADD %2, %4
-# AVX512F-NEXT:      %14(<32 x s8>) = G_ADD %3, %5
+# AVX512F:           %2:_(<32 x s8>) = COPY %ymm0
+# AVX512F-NEXT:      %3:_(<32 x s8>) = COPY %ymm1
+# AVX512F-NEXT:      %4:_(<32 x s8>) = COPY %ymm2
+# AVX512F-NEXT:      %5:_(<32 x s8>) = COPY %ymm3
+# AVX512F-NEXT:      %13:_(<32 x s8>) = G_ADD %2, %4
+# AVX512F-NEXT:      %14:_(<32 x s8>) = G_ADD %3, %5
 # AVX512F-NEXT:      %ymm0 = COPY %13(<32 x s8>)
 # AVX512F-NEXT:      %ymm1 = COPY %14(<32 x s8>)
 # AVX512F-NEXT:      RET 0, implicit %ymm0, implicit %ymm1
 #
-# AVX512BW:          %2(<32 x s8>) = COPY %ymm0
-# AVX512BW-NEXT:     %3(<32 x s8>) = COPY %ymm1
-# AVX512BW-NEXT:     %4(<32 x s8>) = COPY %ymm2
-# AVX512BW-NEXT:     %5(<32 x s8>) = COPY %ymm3
-# AVX512BW-NEXT:     %0(<64 x s8>) = G_MERGE_VALUES %2(<32 x s8>), %3(<32 x s8>)
-# AVX512BW-NEXT:     %1(<64 x s8>) = G_MERGE_VALUES %4(<32 x s8>), %5(<32 x s8>)
-# AVX512BW-NEXT:     %6(<64 x s8>) = G_ADD %0, %1
-# AVX512BW-NEXT:     %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
+# AVX512BW:          %2:_(<32 x s8>) = COPY %ymm0
+# AVX512BW-NEXT:     %3:_(<32 x s8>) = COPY %ymm1
+# AVX512BW-NEXT:     %4:_(<32 x s8>) = COPY %ymm2
+# AVX512BW-NEXT:     %5:_(<32 x s8>) = COPY %ymm3
+# AVX512BW-NEXT:     %0:_(<64 x s8>) = G_MERGE_VALUES %2(<32 x s8>), %3(<32 x s8>)
+# AVX512BW-NEXT:     %1:_(<64 x s8>) = G_MERGE_VALUES %4(<32 x s8>), %5(<32 x s8>)
+# AVX512BW-NEXT:     %6:_(<64 x s8>) = G_ADD %0, %1
+# AVX512BW-NEXT:     %7:_(<32 x s8>), %8:_(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
 # AVX512BW-NEXT:     %ymm0 = COPY %7(<32 x s8>)
 # AVX512BW-NEXT:     %ymm1 = COPY %8(<32 x s8>)
 # AVX512BW-NEXT:     RET 0, implicit %ymm0, implicit %ymm1
diff --git a/test/CodeGen/X86/GlobalISel/legalize-add.mir b/test/CodeGen/X86/GlobalISel/legalize-add.mir
index 4b4b1a8f31a..cfffcea10e8 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-add.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-add.mir
@@ -41,9 +41,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(s32) = IMPLICIT_DEF
-# ALL-NEXT:     %1(s32) = IMPLICIT_DEF
-# ALL-NEXT:     %2(s32) = G_ADD %0, %1
+# ALL:          %0:_(s32) = IMPLICIT_DEF
+# ALL-NEXT:     %1:_(s32) = IMPLICIT_DEF
+# ALL-NEXT:     %2:_(s32) = G_ADD %0, %1
 # ALL-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -63,20 +63,20 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# X64:          %0(s64) = IMPLICIT_DEF
-# X64-NEXT:     %1(s64) = IMPLICIT_DEF
-# X64-NEXT:     %2(s64) = G_ADD %0, %1
+# X64:          %0:_(s64) = IMPLICIT_DEF
+# X64-NEXT:     %1:_(s64) = IMPLICIT_DEF
+# X64-NEXT:     %2:_(s64) = G_ADD %0, %1
 # X64-NEXT:     RET 0
 #
-# X32:          %0(s64) = IMPLICIT_DEF
-# X32-NEXT:     %1(s64) = IMPLICIT_DEF
-# X32-NEXT:     %3(s32), %4(s32) = G_UNMERGE_VALUES %0(s64)
-# X32-NEXT:     %5(s32), %6(s32) = G_UNMERGE_VALUES %1(s64)
-# X32-NEXT:     %12(s8) = G_CONSTANT i8 0
-# X32-NEXT:     %7(s1) = G_TRUNC %12(s8)
-# X32-NEXT:     %8(s32), %9(s1) = G_UADDE %3, %5, %7
-# X32-NEXT:     %10(s32), %11(s1) = G_UADDE %4, %6, %9
-# X32-NEXT:     %2(s64) = G_MERGE_VALUES %8(s32), %10(s32)
+# X32:          %0:_(s64) = IMPLICIT_DEF
+# X32-NEXT:     %1:_(s64) = IMPLICIT_DEF
+# X32-NEXT:     %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %0(s64)
+# X32-NEXT:     %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %1(s64)
+# X32-NEXT:     %12:_(s8) = G_CONSTANT i8 0
+# X32-NEXT:     %7:_(s1) = G_TRUNC %12(s8)
+# X32-NEXT:     %8:_(s32), %9:_(s1) = G_UADDE %3, %5, %7
+# X32-NEXT:     %10:_(s32), %11:_(s1) = G_UADDE %4, %6, %9
+# X32-NEXT:     %2:_(s64) = G_MERGE_VALUES %8(s32), %10(s32)
 # X32-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
diff --git a/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
index 0280606c718..7930f65ea65 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
@@ -41,11 +41,11 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: test_and_i1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]](s8) = G_AND [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[AND]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[AND]](s8)
     ; CHECK: RET 0
     %0(s32) = COPY %edx
     %1(s1) = G_TRUNC %0(s32)
@@ -67,8 +67,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_and_i8
-    ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
-    ; CHECK: [[AND:%[0-9]+]](s8) = G_AND [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[DEF]], [[DEF]]
     ; CHECK: %al = COPY [[AND]](s8)
     ; CHECK: RET 0, implicit %al
     %0(s8) = IMPLICIT_DEF
@@ -92,8 +92,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_and_i16
-    ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
-    ; CHECK: [[AND:%[0-9]+]](s16) = G_AND [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[DEF]], [[DEF]]
     ; CHECK: %ax = COPY [[AND]](s16)
     ; CHECK: RET 0, implicit %ax
     %0(s16) = IMPLICIT_DEF
@@ -117,8 +117,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_and_i32
-    ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
-    ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF]]
     ; CHECK: %eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s32) = IMPLICIT_DEF
@@ -142,8 +142,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_and_i64
-    ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
-    ; CHECK: [[AND:%[0-9]+]](s64) = G_AND [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
     ; CHECK: %rax = COPY [[AND]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s64) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-brcond.mir b/test/CodeGen/X86/GlobalISel/legalize-brcond.mir
index 9396528c7b0..0346912785e 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-brcond.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-brcond.mir
@@ -26,7 +26,7 @@ registers:
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
   - { id: 3, class: _, preferred-register: '' }
-# ALL:         %1(s1) = G_TRUNC %0(s32)
+# ALL:         %1:_(s1) = G_TRUNC %0(s32)
 # ALL-NEXT:    G_BRCOND %1(s1), %[[TRUE:bb.[0-9]+.if.then]]
 # ALL-NEXT:    G_BR %[[FALSE:bb.[0-9]+.if.else]]
 # ALL:       [[TRUE]]:
diff --git a/test/CodeGen/X86/GlobalISel/legalize-cmp.mir b/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
index 3e7f8bb812e..c3e7b77aa3e 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-cmp.mir
@@ -48,10 +48,10 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_cmp_i8
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[COPY1:%[0-9]+]](s8) = COPY %sil
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY %sil
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
     ; CHECK: %eax = COPY [[ZEXT]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s8) = COPY %dil
@@ -77,10 +77,10 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_cmp_i16
-    ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
-    ; CHECK: [[COPY1:%[0-9]+]](s16) = COPY %si
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY %si
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
     ; CHECK: %eax = COPY [[ZEXT]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s16) = COPY %di
@@ -106,10 +106,10 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_cmp_i32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %esi
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
     ; CHECK: %eax = COPY [[ZEXT]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -135,10 +135,10 @@ body:             |
     liveins: %rdi, %rsi
 
     ; CHECK-LABEL: name: test_cmp_i64
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %rsi
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %rsi
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
     ; CHECK: %eax = COPY [[ZEXT]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s64) = COPY %rdi
@@ -164,10 +164,10 @@ body:             |
     liveins: %rdi, %rsi
 
     ; CHECK-LABEL: name: test_cmp_p0
-    ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]](p0) = COPY %rsi
-    ; CHECK: [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]](s32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY %rsi
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
     ; CHECK: %eax = COPY [[ZEXT]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(p0) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/legalize-constant.mir b/test/CodeGen/X86/GlobalISel/legalize-constant.mir
index fd88fc69ed0..8d6e718e02f 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-constant.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-constant.mir
@@ -1,7 +1,7 @@
 # RUN: llc -mtriple=i386-linux-gnu   -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
 # RUN: llc -mtriple=x86_64-linux-gnu              -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
 
---- | 
+--- |
   define void @test_constant() { ret void }
   define void @test_fconstant() { ret void }
 
@@ -9,7 +9,7 @@
 ---
 name:            test_constant
 # ALL-LABEL: name:            test_constant
-registers:       
+registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
@@ -17,24 +17,24 @@ registers:
   - { id: 4, class: _ }
 body:             |
   bb.1 (%ir-block.0):
-    ; ALL: %5(s8) = G_CONSTANT i8 -1
-    ; ALL: %0(s1) = G_TRUNC %5(s8)
+    ; ALL: %5:_(s8) = G_CONSTANT i8 -1
+    ; ALL: %0:_(s1) = G_TRUNC %5(s8)
     %0(s1) = G_CONSTANT i1 1
 
-    ; ALL: %1(s8) = G_CONSTANT i8 8    
-    %1(s8) = G_CONSTANT i8 8   
+    ; ALL: %1:_(s8) = G_CONSTANT i8 8
+    %1(s8) = G_CONSTANT i8 8
 
-    ; ALL: %2(s16) = G_CONSTANT i16 16
+    ; ALL: %2:_(s16) = G_CONSTANT i16 16
     %2(s16) = G_CONSTANT i16 16
 
-    ; ALL: %3(s32) = G_CONSTANT i32 32
+    ; ALL: %3:_(s32) = G_CONSTANT i32 32
     %3(s32) = G_CONSTANT i32 32
 
-    ; X64: %4(s64) = G_CONSTANT i64 64
-    
-    ; X32: %6(s32) = G_CONSTANT i32 64
-    ; X32: %7(s32) = G_CONSTANT i32 0
-    ; X32: %4(s64) = G_MERGE_VALUES %6(s32), %7(s32) 
+    ; X64: %4:_(s64) = G_CONSTANT i64 64
+
+    ; X32: %6:_(s32) = G_CONSTANT i32 64
+    ; X32: %7:_(s32) = G_CONSTANT i32 0
+    ; X32: %4:_(s64) = G_MERGE_VALUES %6(s32), %7(s32)
     %4(s64) = G_CONSTANT i64 64
 
     RET 0
@@ -47,8 +47,8 @@ registers:
   - { id: 1, class: _ }
 body: |
   bb.0:
-    ; ALL: %0(s32) = G_FCONSTANT  float 1.000000e+00
-    ; ALL: %1(s64) = G_FCONSTANT  double 2.000000e+00
+    ; ALL: %0:_(s32) = G_FCONSTANT  float 1.000000e+00
+    ; ALL: %1:_(s64) = G_FCONSTANT  double 2.000000e+00
 
     %0(s32) = G_FCONSTANT float 1.0
     %1(s64) = G_FCONSTANT double 2.0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
index 9631ab119f8..8eae4d31ae7 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
@@ -76,9 +76,9 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_sext_i1
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
-    ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[TRUNC]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s8)
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s1)
     ; CHECK: %rax = COPY [[SEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -101,8 +101,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_sext_i8
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
     ; CHECK: %rax = COPY [[SEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -124,8 +124,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_sext_i16
-    ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
-    ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s16)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
     ; CHECK: %rax = COPY [[SEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s16) = COPY %di
@@ -147,8 +147,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_sext_i32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
-    ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
     ; CHECK: %rax = COPY [[SEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s32) = COPY %edi
@@ -171,9 +171,9 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_zext_i1
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
-    ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[TRUNC]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s8)
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1)
     ; CHECK: %rax = COPY [[ZEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -196,8 +196,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_zext_i8
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s8)
     ; CHECK: %rax = COPY [[ZEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -219,8 +219,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_zext_i16
-    ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
-    ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s16)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
     ; CHECK: %rax = COPY [[ZEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s16) = COPY %di
@@ -242,8 +242,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_zext_i32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
-    ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
     ; CHECK: %rax = COPY [[ZEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s32) = COPY %edi
@@ -266,9 +266,9 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_anyext_i1
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[COPY]](s8)
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[TRUNC]](s1)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s8)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s1)
     ; CHECK: %rax = COPY [[ANYEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -291,8 +291,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_anyext_i8
-    ; CHECK: [[COPY:%[0-9]+]](s8) = COPY %dil
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
     ; CHECK: %rax = COPY [[ANYEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -314,8 +314,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_anyext_i16
-    ; CHECK: [[COPY:%[0-9]+]](s16) = COPY %di
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s16)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
     ; CHECK: %rax = COPY [[ANYEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s16) = COPY %di
@@ -337,8 +337,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_anyext_i32
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
-    ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
     ; CHECK: %rax = COPY [[ANYEXT]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s32) = COPY %edi
diff --git a/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/test/CodeGen/X86/GlobalISel/legalize-ext.mir
index 55433d6d9c8..66b6b03d8eb 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-ext.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-ext.mir
@@ -98,8 +98,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s8) = G_ZEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s8) = G_ZEXT %0(s1)
 # ALL-NEXT:     %al = COPY %1(s8)
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -121,8 +121,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s16) = G_ZEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s16) = G_ZEXT %0(s1)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -145,9 +145,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s1) = G_TRUNC %0(s8)
-# ALL-NEXT:     %2(s32) = G_ZEXT %1(s1)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s1) = G_TRUNC %0(s8)
+# ALL-NEXT:     %2:_(s32) = G_ZEXT %1(s1)
 # ALL-NEXT:     %eax = COPY %2(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -170,8 +170,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s16) = G_ZEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s16) = G_ZEXT %0(s8)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -193,8 +193,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s32) = G_ZEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s32) = G_ZEXT %0(s8)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -216,8 +216,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s16) = COPY %di
-# ALL-NEXT:     %1(s32) = G_ZEXT %0(s16)
+# ALL:          %0:_(s16) = COPY %di
+# ALL-NEXT:     %1:_(s32) = G_ZEXT %0(s16)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -239,8 +239,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s8) = G_SEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s8) = G_SEXT %0(s1)
 # ALL-NEXT:     %al = COPY %1(s8)
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -262,8 +262,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s16) = G_SEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s16) = G_SEXT %0(s1)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -286,9 +286,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s1) = G_TRUNC %0(s8)
-# ALL-NEXT:     %2(s32) = G_SEXT %1(s1)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s1) = G_TRUNC %0(s8)
+# ALL-NEXT:     %2:_(s32) = G_SEXT %1(s1)
 # ALL-NEXT:     %eax = COPY %2(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -311,8 +311,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s16) = G_SEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s16) = G_SEXT %0(s8)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -334,8 +334,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s32) = G_SEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s32) = G_SEXT %0(s8)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -357,8 +357,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s16) = COPY %di
-# ALL-NEXT:     %1(s32) = G_SEXT %0(s16)
+# ALL:          %0:_(s16) = COPY %di
+# ALL-NEXT:     %1:_(s32) = G_SEXT %0(s16)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -380,8 +380,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s8) = G_ANYEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s8) = G_ANYEXT %0(s1)
 # ALL-NEXT:     %al = COPY %1(s8)
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -403,8 +403,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s1) = COPY %edi
-# ALL-NEXT:     %1(s16) = G_ANYEXT %0(s1)
+# ALL:          %0:_(s1) = COPY %edi
+# ALL-NEXT:     %1:_(s16) = G_ANYEXT %0(s1)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -427,9 +427,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s1) = G_TRUNC %0(s8)
-# ALL-NEXT:     %2(s32) = G_ANYEXT %1(s1)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s1) = G_TRUNC %0(s8)
+# ALL-NEXT:     %2:_(s32) = G_ANYEXT %1(s1)
 # ALL-NEXT:     %eax = COPY %2(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -452,8 +452,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s16) = G_ANYEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s16) = G_ANYEXT %0(s8)
 # ALL-NEXT:     %ax = COPY %1(s16)
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -475,8 +475,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s8) = COPY %dil
-# ALL-NEXT:     %1(s32) = G_ANYEXT %0(s8)
+# ALL:          %0:_(s8) = COPY %dil
+# ALL-NEXT:     %1:_(s32) = G_ANYEXT %0(s8)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -498,8 +498,8 @@ regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
-# ALL:          %0(s16) = COPY %di
-# ALL-NEXT:     %1(s32) = G_ANYEXT %0(s16)
+# ALL:          %0:_(s16) = COPY %di
+# ALL-NEXT:     %1:_(s32) = G_ANYEXT %0(s16)
 # ALL-NEXT:     %eax = COPY %1(s32)
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir
index eeb6c49f459..407c42567ac 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir
@@ -31,9 +31,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fadd_float
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
-    ; CHECK: [[FADD:%[0-9]+]](s32) = G_FADD [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1
+    ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FADD]](s32)
     ; CHECK: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
@@ -61,9 +61,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fadd_double
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
-    ; CHECK: [[FADD:%[0-9]+]](s64) = G_FADD [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1
+    ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FADD]](s64)
     ; CHECK: RET 0, implicit %xmm0
     %0(s64) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir
index 23d6a6c49ce..128ab9b0ee8 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir
@@ -31,9 +31,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fdiv_float
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
-    ; CHECK: [[FDIV:%[0-9]+]](s32) = G_FDIV [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1
+    ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FDIV]](s32)
     ; CHECK: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
@@ -61,9 +61,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fdiv_double
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
-    ; CHECK: [[FDIV:%[0-9]+]](s64) = G_FDIV [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1
+    ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FDIV]](s64)
     ; CHECK: RET 0, implicit %xmm0
     %0(s64) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir
index 7dd6119142f..73e04d0fcf8 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir
@@ -31,9 +31,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fmul_float
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
-    ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1
+    ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FMUL]](s32)
     ; CHECK: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
@@ -61,9 +61,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fmul_double
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
-    ; CHECK: [[FMUL:%[0-9]+]](s64) = G_FMUL [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1
+    ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FMUL]](s64)
     ; CHECK: RET 0, implicit %xmm0
     %0(s64) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir
index 1829a8d7170..25d1fbc564e 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir
@@ -22,8 +22,8 @@ body:             |
     liveins: %xmm0
 
     ; ALL-LABEL: name: test
-    ; ALL: [[COPY:%[0-9]+]](s32) = COPY %xmm0
-    ; ALL: [[FPEXT:%[0-9]+]](s64) = G_FPEXT [[COPY]](s32)
+    ; ALL: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0
+    ; ALL: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
     ; ALL: %xmm0 = COPY [[FPEXT]](s64)
     ; ALL: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
index 3d76fb7829d..253d1fb49a3 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir
@@ -31,9 +31,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fsub_float
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %xmm1
-    ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm1
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FSUB]](s32)
     ; CHECK: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
@@ -61,9 +61,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_fsub_double
-    ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]](s64) = COPY %xmm1
-    ; CHECK: [[FSUB:%[0-9]+]](s64) = G_FSUB [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm1
+    ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[FSUB]](s64)
     ; CHECK: RET 0, implicit %xmm0
     %0(s64) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-gep.mir b/test/CodeGen/X86/GlobalISel/legalize-gep.mir
index 402fcdc4822..7958cecafa0 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-gep.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-gep.mir
@@ -32,10 +32,10 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i8
-    ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]](s8) = G_CONSTANT i8 20
-    ; CHECK: [[SEXT:%[0-9]+]](s32) = G_SEXT [[C]](s8)
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[SEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 20
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s8)
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
     ; CHECK: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s8) = G_CONSTANT i8 20
@@ -52,10 +52,10 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i16
-    ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]](s16) = G_CONSTANT i16 20
-    ; CHECK: [[SEXT:%[0-9]+]](s32) = G_SEXT [[C]](s16)
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[SEXT]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 20
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
     ; CHECK: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s16) = G_CONSTANT i16 20
@@ -72,9 +72,9 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i32
-    ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT i32 20
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[C]](s32)
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
     ; CHECK: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
@@ -91,9 +91,9 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_gep_i64
-    ; CHECK: [[DEF:%[0-9]+]](p0) = IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]](s64) = G_CONSTANT i64 20
-    ; CHECK: [[GEP:%[0-9]+]](p0) = G_GEP [[DEF]], [[C]](s64)
+    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
+    ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s64)
     ; CHECK: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s64) = G_CONSTANT i64 20
diff --git a/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir b/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir
index 8989fb69b41..613f2a794b0 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir
@@ -15,9 +15,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:               %0(<8 x s32>) = COPY %ymm0
-# ALL-NEXT:          %1(<4 x s32>) = COPY %xmm1
-# ALL-NEXT:          %2(<8 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
+# ALL:               %0:_(<8 x s32>) = COPY %ymm0
+# ALL-NEXT:          %1:_(<4 x s32>) = COPY %xmm1
+# ALL-NEXT:          %2:_(<8 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
 # ALL-NEXT:          %ymm0 = COPY %2(<8 x s32>)
 # ALL-NEXT:          RET 0, implicit %ymm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir b/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
index 8e01a672351..d9fb35e44dc 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir
@@ -24,9 +24,9 @@ body:             |
     liveins: %zmm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_128
-    ; ALL: [[COPY:%[0-9]+]](<16 x s32>) = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]](<4 x s32>) = COPY %xmm1
-    ; ALL: [[INSERT:%[0-9]+]](<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0
+    ; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1
+    ; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0
     ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>)
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
@@ -50,9 +50,9 @@ body:             |
     liveins: %zmm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_256
-    ; ALL: [[COPY:%[0-9]+]](<16 x s32>) = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]](<8 x s32>) = COPY %ymm1
-    ; ALL: [[INSERT:%[0-9]+]](<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0
+    ; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY %ymm1
+    ; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0
     ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>)
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
diff --git a/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
index 60d9fc63c14..1840ec75fb8 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
@@ -28,23 +28,23 @@ registers:
   - { id: 8, class: _, preferred-register: '' }
   - { id: 9, class: _, preferred-register: '' }
   - { id: 10, class: _, preferred-register: '' }
-# ALL:          %0(p0) = IMPLICIT_DEF
-# ALL-NEXT:     %11(s8) = G_LOAD %0(p0) :: (load 1)
-# ALL-NEXT:     %9(s1) = G_TRUNC %11(s8)
-# ALL-NEXT:     %1(s8) = G_LOAD %0(p0) :: (load 1)
-# ALL-NEXT:     %2(s16) = G_LOAD %0(p0) :: (load 2)
-# ALL-NEXT:     %3(s32) = G_LOAD %0(p0) :: (load 4)
-# ALL-NEXT:     %4(p0) = G_LOAD %0(p0) :: (load 8)
-# ALL-NEXT:     %10(s1) = IMPLICIT_DEF
-# ALL-NEXT:     %12(s8) = G_ZEXT %10(s1)
+# ALL:          %0:_(p0) = IMPLICIT_DEF
+# ALL-NEXT:     %11:_(s8) = G_LOAD %0(p0) :: (load 1)
+# ALL-NEXT:     %9:_(s1) = G_TRUNC %11(s8)
+# ALL-NEXT:     %1:_(s8) = G_LOAD %0(p0) :: (load 1)
+# ALL-NEXT:     %2:_(s16) = G_LOAD %0(p0) :: (load 2)
+# ALL-NEXT:     %3:_(s32) = G_LOAD %0(p0) :: (load 4)
+# ALL-NEXT:     %4:_(p0) = G_LOAD %0(p0) :: (load 8)
+# ALL-NEXT:     %10:_(s1) = IMPLICIT_DEF
+# ALL-NEXT:     %12:_(s8) = G_ZEXT %10(s1)
 # ALL-NEXT:     G_STORE %12(s8), %0(p0) :: (store 1)
-# ALL-NEXT:     %5(s8) = IMPLICIT_DEF
+# ALL-NEXT:     %5:_(s8) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %5(s8), %0(p0) :: (store 1)
-# ALL-NEXT:     %6(s16) = IMPLICIT_DEF
+# ALL-NEXT:     %6:_(s16) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %6(s16), %0(p0) :: (store 2)
-# ALL-NEXT:     %7(s32) = IMPLICIT_DEF
+# ALL-NEXT:     %7:_(s32) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %7(s32), %0(p0) :: (store 4)
-# ALL-NEXT:     %8(p0) = IMPLICIT_DEF
+# ALL-NEXT:     %8:_(p0) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %8(p0), %0(p0) :: (store 8)
 body:             |
   bb.1 (%ir-block.0):
@@ -79,22 +79,22 @@ registers:
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
 liveins:
-# X64:          %0(p0) = IMPLICIT_DEF
-# X64-NEXT:     %1(s64) = G_LOAD %0(p0) :: (load 8)
-# X64-NEXT:     %2(s64) = IMPLICIT_DEF
+# X64:          %0:_(p0) = IMPLICIT_DEF
+# X64-NEXT:     %1:_(s64) = G_LOAD %0(p0) :: (load 8)
+# X64-NEXT:     %2:_(s64) = IMPLICIT_DEF
 # X64-NEXT:     G_STORE %2(s64), %0(p0) :: (store 8)
 #
-# X32:          %0(p0) = IMPLICIT_DEF
-# X32-NEXT:     %3(s32) = G_LOAD %0(p0) :: (load 8)
-# X32-NEXT:     %6(s32) = G_CONSTANT i32 4
-# X32-NEXT:     %5(p0) = G_GEP %0, %6(s32)
-# X32-NEXT:     %4(s32) = G_LOAD %5(p0) :: (load 8)
-# X32-NEXT:     %1(s64) = G_MERGE_VALUES %3(s32), %4(s32)
-# X32-NEXT:     %2(s64) = IMPLICIT_DEF
-# X32-NEXT:     %7(s32), %8(s32) = G_UNMERGE_VALUES %2(s64)
+# X32:          %0:_(p0) = IMPLICIT_DEF
+# X32-NEXT:     %3:_(s32) = G_LOAD %0(p0) :: (load 8)
+# X32-NEXT:     %6:_(s32) = G_CONSTANT i32 4
+# X32-NEXT:     %5:_(p0) = G_GEP %0, %6(s32)
+# X32-NEXT:     %4:_(s32) = G_LOAD %5(p0) :: (load 8)
+# X32-NEXT:     %1:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
+# X32-NEXT:     %2:_(s64) = IMPLICIT_DEF
+# X32-NEXT:     %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %2(s64)
 # X32-NEXT:     G_STORE %7(s32), %0(p0) :: (store 8)
-# X32-NEXT:     %10(s32) = G_CONSTANT i32 4
-# X32-NEXT:     %9(p0) = G_GEP %0, %10(s32)
+# X32-NEXT:     %10:_(s32) = G_CONSTANT i32 4
+# X32-NEXT:     %9:_(p0) = G_GEP %0, %10(s32)
 # X32-NEXT:     G_STORE %8(s32), %9(p0) :: (store 8)
 body:             |
   bb.1 (%ir-block.0):
@@ -107,4 +107,3 @@ body:             |
     G_STORE %2, %0 :: (store 8)
 
 ...
-
diff --git a/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
index 49a317e4f76..40012ae5792 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
@@ -2,7 +2,7 @@
 
 --- |
   define void @test_mul_i1() { ret void}
-  
+
   define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
     %ret = mul i16 %arg1, %arg2
     ret i16 %ret
@@ -29,11 +29,11 @@ registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
-# CHECK:          %0(s32) = COPY %edx
-# CHECK-NEXT:     %3(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT:     %4(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT:     %5(s8) = G_MUL %3, %4
-# CHECK-NEXT:     %2(s1) = G_TRUNC %5(s8)
+# CHECK:          %0:_(s32) = COPY %edx
+# CHECK-NEXT:     %3:_(s8) = G_TRUNC %0(s32)
+# CHECK-NEXT:     %4:_(s8) = G_TRUNC %0(s32)
+# CHECK-NEXT:     %5:_(s8) = G_MUL %3, %4
+# CHECK-NEXT:     %2:_(s1) = G_TRUNC %5(s8)
 # CHECK-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
@@ -59,9 +59,9 @@ registers:
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
-# CHECK-NEXT:     %0(s16) = COPY %di
-# CHECK-NEXT:     %1(s16) = COPY %si
-# CHECK-NEXT:     %2(s16) = G_MUL %0, %1
+# CHECK-NEXT:     %0:_(s16) = COPY %di
+# CHECK-NEXT:     %1:_(s16) = COPY %si
+# CHECK-NEXT:     %2:_(s16) = G_MUL %0, %1
 # CHECK-NEXT:     %ax = COPY %2(s16)
 # CHECK-NEXT:     RET 0, implicit %ax
 body:             |
@@ -91,9 +91,9 @@ registers:
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
-# CHECK-NEXT:     %0(s32) = COPY %edi
-# CHECK-NEXT:     %1(s32) = COPY %esi
-# CHECK-NEXT:     %2(s32) = G_MUL %0, %1
+# CHECK-NEXT:     %0:_(s32) = COPY %edi
+# CHECK-NEXT:     %1:_(s32) = COPY %esi
+# CHECK-NEXT:     %2:_(s32) = G_MUL %0, %1
 # CHECK-NEXT:     %eax = COPY %2(s32)
 # CHECK-NEXT:     RET 0, implicit %eax
 body:             |
@@ -123,9 +123,9 @@ registers:
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
-# CHECK-NEXT:     %0(s64) = COPY %rdi
-# CHECK-NEXT:     %1(s64) = COPY %rsi
-# CHECK-NEXT:     %2(s64) = G_MUL %0, %1
+# CHECK-NEXT:     %0:_(s64) = COPY %rdi
+# CHECK-NEXT:     %1:_(s64) = COPY %rsi
+# CHECK-NEXT:     %2:_(s64) = G_MUL %0, %1
 # CHECK-NEXT:     %rax = COPY %2(s64)
 # CHECK-NEXT:     RET 0, implicit %rax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
index effd26e9866..f14b6eb2ebb 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
@@ -33,9 +33,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<8 x s16>) = COPY %xmm0
-# ALL-NEXT:     %1(<8 x s16>) = COPY %xmm1
-# ALL-NEXT:     %2(<8 x s16>) = G_MUL %0, %1
+# ALL:          %0:_(<8 x s16>) = COPY %xmm0
+# ALL-NEXT:     %1:_(<8 x s16>) = COPY %xmm1
+# ALL-NEXT:     %2:_(<8 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<8 x s16>)
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -63,9 +63,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<4 x s32>) = COPY %xmm0
-# ALL-NEXT:     %1(<4 x s32>) = COPY %xmm1
-# ALL-NEXT:     %2(<4 x s32>) = G_MUL %0, %1
+# ALL:          %0:_(<4 x s32>) = COPY %xmm0
+# ALL-NEXT:     %1:_(<4 x s32>) = COPY %xmm1
+# ALL-NEXT:     %2:_(<4 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<4 x s32>)
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -93,9 +93,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<2 x s64>) = COPY %xmm0
-# ALL-NEXT:     %1(<2 x s64>) = COPY %xmm1
-# ALL-NEXT:     %2(<2 x s64>) = G_MUL %0, %1
+# ALL:          %0:_(<2 x s64>) = COPY %xmm0
+# ALL-NEXT:     %1:_(<2 x s64>) = COPY %xmm1
+# ALL-NEXT:     %2:_(<2 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<2 x s64>)
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
index 5ae8132156d..b0921a9b074 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
@@ -33,9 +33,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<16 x s16>) = COPY %ymm0
-# ALL-NEXT:     %1(<16 x s16>) = COPY %ymm1
-# ALL-NEXT:     %2(<16 x s16>) = G_MUL %0, %1
+# ALL:          %0:_(<16 x s16>) = COPY %ymm0
+# ALL-NEXT:     %1:_(<16 x s16>) = COPY %ymm1
+# ALL-NEXT:     %2:_(<16 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<16 x s16>)
 # ALL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -63,9 +63,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<8 x s32>) = COPY %ymm0
-# ALL-NEXT:     %1(<8 x s32>) = COPY %ymm1
-# ALL-NEXT:     %2(<8 x s32>) = G_MUL %0, %1
+# ALL:          %0:_(<8 x s32>) = COPY %ymm0
+# ALL-NEXT:     %1:_(<8 x s32>) = COPY %ymm1
+# ALL-NEXT:     %2:_(<8 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<8 x s32>)
 # ALL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -93,9 +93,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<4 x s64>) = COPY %ymm0
-# ALL-NEXT:     %1(<4 x s64>) = COPY %ymm1
-# ALL-NEXT:     %2(<4 x s64>) = G_MUL %0, %1
+# ALL:          %0:_(<4 x s64>) = COPY %ymm0
+# ALL-NEXT:     %1:_(<4 x s64>) = COPY %ymm1
+# ALL-NEXT:     %2:_(<4 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<4 x s64>)
 # ALL-NEXT:     RET 0, implicit %ymm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
index 71ea313c4c7..79d65f2fe7d 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
@@ -35,9 +35,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<32 x s16>) = COPY %zmm0
-# ALL-NEXT:     %1(<32 x s16>) = COPY %zmm1
-# ALL-NEXT:     %2(<32 x s16>) = G_MUL %0, %1
+# ALL:          %0:_(<32 x s16>) = COPY %zmm0
+# ALL-NEXT:     %1:_(<32 x s16>) = COPY %zmm1
+# ALL-NEXT:     %2:_(<32 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<32 x s16>)
 # ALL-NEXT:     RET 0, implicit %zmm0
 body:             |
@@ -65,9 +65,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<16 x s32>) = COPY %zmm0
-# ALL-NEXT:     %1(<16 x s32>) = COPY %zmm1
-# ALL-NEXT:     %2(<16 x s32>) = G_MUL %0, %1
+# ALL:          %0:_(<16 x s32>) = COPY %zmm0
+# ALL-NEXT:     %1:_(<16 x s32>) = COPY %zmm1
+# ALL-NEXT:     %2:_(<16 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<16 x s32>)
 # ALL-NEXT:     RET 0, implicit %zmm0
 body:             |
@@ -95,9 +95,9 @@ registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
-# ALL:          %0(<8 x s64>) = COPY %zmm0
-# ALL-NEXT:     %1(<8 x s64>) = COPY %zmm1
-# ALL-NEXT:     %2(<8 x s64>) = G_MUL %0, %1
+# ALL:          %0:_(<8 x s64>) = COPY %zmm0
+# ALL-NEXT:     %1:_(<8 x s64>) = COPY %zmm1
+# ALL-NEXT:     %2:_(<8 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<8 x s64>)
 # ALL-NEXT:     RET 0, implicit %zmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
index 248ba9d650a..86e31a2192c 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
@@ -41,11 +41,11 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: test_or_i1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[OR:%[0-9]+]](s8) = G_OR [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[OR]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[OR]](s8)
     ; CHECK: RET 0
     %0(s32) = COPY %edx
     %1(s1) = G_TRUNC %0(s32)
@@ -67,8 +67,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_or_i8
-    ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
-    ; CHECK: [[OR:%[0-9]+]](s8) = G_OR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
     ; CHECK: %al = COPY [[OR]](s8)
     ; CHECK: RET 0, implicit %al
     %0(s8) = IMPLICIT_DEF
@@ -92,8 +92,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_or_i16
-    ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
-    ; CHECK: [[OR:%[0-9]+]](s16) = G_OR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
     ; CHECK: %ax = COPY [[OR]](s16)
     ; CHECK: RET 0, implicit %ax
     %0(s16) = IMPLICIT_DEF
@@ -117,8 +117,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_or_i32
-    ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
-    ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
     ; CHECK: %eax = COPY [[OR]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s32) = IMPLICIT_DEF
@@ -142,8 +142,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_or_i64
-    ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
-    ; CHECK: [[OR:%[0-9]+]](s64) = G_OR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
     ; CHECK: %rax = COPY [[OR]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s64) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-phi.mir b/test/CodeGen/X86/GlobalISel/legalize-phi.mir
index a26c2846e39..1e532633216 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-phi.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-phi.mir
@@ -143,24 +143,24 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %edx, %esi
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s1) = COPY %esi
-  ; ALL:   [[COPY2:%[0-9]+]](s1) = COPY %edx
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s1) = COPY %esi
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s1) = COPY %edx
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
-  ; ALL:   [[ANYEXT:%[0-9]+]](s8) = G_ANYEXT [[COPY1]](s1)
+  ; ALL:   [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY1]](s1)
   ; ALL:   G_BR %bb.3.cond.end
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
-  ; ALL:   [[ANYEXT1:%[0-9]+]](s8) = G_ANYEXT [[COPY2]](s1)
+  ; ALL:   [[ANYEXT1:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY2]](s1)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s8) = G_PHI [[ANYEXT]](s8), %bb.1.cond.true, [[ANYEXT1]](s8), %bb.2.cond.false
-  ; ALL:   [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[PHI]](s8)
-  ; ALL:   [[ZEXT:%[0-9]+]](s8) = G_ZEXT [[TRUNC]](s1)
+  ; ALL:   [[PHI:%[0-9]+]]:_(s8) = G_PHI [[ANYEXT]](s8), %bb.1.cond.true, [[ANYEXT1]](s8), %bb.2.cond.false
+  ; ALL:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI]](s8)
+  ; ALL:   [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
   ; ALL:   %al = COPY [[ZEXT]](s8)
   ; ALL:   RET 0, implicit %al
   bb.1.entry:
@@ -216,11 +216,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %edx, %esi
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s8) = COPY %sil
-  ; ALL:   [[COPY2:%[0-9]+]](s8) = COPY %edx
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s8) = COPY %sil
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s8) = COPY %edx
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -229,7 +229,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s8) = G_PHI [[COPY1]](s8), %bb.1.cond.true, [[COPY2]](s8), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s8) = G_PHI [[COPY1]](s8), %bb.1.cond.true, [[COPY2]](s8), %bb.2.cond.false
   ; ALL:   %al = COPY [[PHI]](s8)
   ; ALL:   RET 0, implicit %al
   bb.1.entry:
@@ -284,11 +284,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %edx, %esi
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s16) = COPY %si
-  ; ALL:   [[COPY2:%[0-9]+]](s16) = COPY %edx
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s16) = COPY %si
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s16) = COPY %edx
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -297,7 +297,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s16) = G_PHI [[COPY1]](s16), %bb.1.cond.true, [[COPY2]](s16), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[COPY1]](s16), %bb.1.cond.true, [[COPY2]](s16), %bb.2.cond.false
   ; ALL:   %ax = COPY [[PHI]](s16)
   ; ALL:   RET 0, implicit %ax
   bb.1.entry:
@@ -352,11 +352,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %edx, %esi
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s32) = COPY %esi
-  ; ALL:   [[COPY2:%[0-9]+]](s32) = COPY %edx
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY %esi
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY %edx
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -365,7 +365,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
   ; ALL:   %eax = COPY [[PHI]](s32)
   ; ALL:   RET 0, implicit %eax
   bb.1.entry:
@@ -420,11 +420,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %rdx, %rsi
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s64) = COPY %rsi
-  ; ALL:   [[COPY2:%[0-9]+]](s64) = COPY %rdx
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s64) = COPY %rsi
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s64) = COPY %rdx
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -433,7 +433,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
   ; ALL:   %rax = COPY [[PHI]](s64)
   ; ALL:   RET 0, implicit %rax
   bb.1.entry:
@@ -488,11 +488,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %xmm0, %xmm1
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s32) = COPY %xmm0
-  ; ALL:   [[COPY2:%[0-9]+]](s32) = COPY %xmm1
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY %xmm0
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY %xmm1
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -501,7 +501,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1.cond.true, [[COPY2]](s32), %bb.2.cond.false
   ; ALL:   %xmm0 = COPY [[PHI]](s32)
   ; ALL:   RET 0, implicit %xmm0
   bb.1.entry:
@@ -556,11 +556,11 @@ body:             |
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1.cond.true(0x40000000), %bb.2.cond.false(0x40000000)
   ; ALL:   liveins: %edi, %xmm0, %xmm1
-  ; ALL:   [[COPY:%[0-9]+]](s32) = COPY %edi
-  ; ALL:   [[COPY1:%[0-9]+]](s64) = COPY %xmm0
-  ; ALL:   [[COPY2:%[0-9]+]](s64) = COPY %xmm1
-  ; ALL:   [[C:%[0-9]+]](s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+  ; ALL:   [[COPY1:%[0-9]+]]:_(s64) = COPY %xmm0
+  ; ALL:   [[COPY2:%[0-9]+]]:_(s64) = COPY %xmm1
+  ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
   ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1.cond.true
   ; ALL:   G_BR %bb.2.cond.false
   ; ALL: bb.1.cond.true:
@@ -569,7 +569,7 @@ body:             |
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3.cond.end(0x80000000)
   ; ALL: bb.3.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]](s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
+  ; ALL:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY1]](s64), %bb.1.cond.true, [[COPY2]](s64), %bb.2.cond.false
   ; ALL:   %xmm0 = COPY [[PHI]](s64)
   ; ALL:   RET 0, implicit %xmm0
   bb.1.entry:
diff --git a/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir b/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
index cb7b9e98c07..081dd4f802e 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
@@ -36,9 +36,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_sub_v16i8
-    ; ALL: [[DEF:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<16 x s8>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<16 x s8>) = IMPLICIT_DEF
     %1(<16 x s8>) = IMPLICIT_DEF
@@ -60,9 +60,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_sub_v8i16
-    ; ALL: [[DEF:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<8 x s16>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<8 x s16>) = IMPLICIT_DEF
     %1(<8 x s16>) = IMPLICIT_DEF
@@ -84,9 +84,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_sub_v4i32
-    ; ALL: [[DEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<4 x s32>) = IMPLICIT_DEF
     %1(<4 x s32>) = IMPLICIT_DEF
@@ -108,9 +108,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; ALL-LABEL: name: test_sub_v2i64
-    ; ALL: [[DEF:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<2 x s64>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<2 x s64>) = IMPLICIT_DEF
     %1(<2 x s64>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir b/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
index afdfe1f4e3a..fc770eb5c58 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
@@ -37,9 +37,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_sub_v32i8
-    ; ALL: [[DEF:%[0-9]+]](<32 x s8>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<32 x s8>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<32 x s8>) = IMPLICIT_DEF
     %1(<32 x s8>) = IMPLICIT_DEF
@@ -61,9 +61,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_sub_v16i16
-    ; ALL: [[DEF:%[0-9]+]](<16 x s16>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<16 x s16>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<16 x s16>) = IMPLICIT_DEF
     %1(<16 x s16>) = IMPLICIT_DEF
@@ -85,9 +85,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_sub_v8i32
-    ; ALL: [[DEF:%[0-9]+]](<8 x s32>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<8 x s32>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = IMPLICIT_DEF
@@ -109,9 +109,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_sub_v4i64
-    ; ALL: [[DEF:%[0-9]+]](<4 x s64>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<4 x s64>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<4 x s64>) = IMPLICIT_DEF
     %1(<4 x s64>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir b/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
index 1566a7c8819..1ac2625b8de 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
@@ -37,9 +37,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v64i8
-    ; ALL: [[DEF:%[0-9]+]](<64 x s8>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<64 x s8>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<64 x s8>) = IMPLICIT_DEF
     %1(<64 x s8>) = IMPLICIT_DEF
@@ -61,9 +61,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v32i16
-    ; ALL: [[DEF:%[0-9]+]](<32 x s16>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<32 x s16>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<32 x s16>) = IMPLICIT_DEF
     %1(<32 x s16>) = IMPLICIT_DEF
@@ -85,9 +85,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v16i32
-    ; ALL: [[DEF:%[0-9]+]](<16 x s32>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<16 x s32>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = IMPLICIT_DEF
@@ -109,9 +109,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v8i64
-    ; ALL: [[DEF:%[0-9]+]](<8 x s64>) = IMPLICIT_DEF
-    ; ALL: [[DEF1:%[0-9]+]](<8 x s64>) = IMPLICIT_DEF
-    ; ALL: [[SUB:%[0-9]+]](<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
+    ; ALL: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+    ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+    ; ALL: [[SUB:%[0-9]+]]:_(<8 x s64>) = G_SUB [[DEF]], [[DEF1]]
     ; ALL: RET 0
     %0(<8 x s64>) = IMPLICIT_DEF
     %1(<8 x s64>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/test/CodeGen/X86/GlobalISel/legalize-sub.mir
index 79ac0e2fa97..577cfbc3b32 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-sub.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-sub.mir
@@ -24,11 +24,11 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: test_sub_i1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[SUB:%[0-9]+]](s8) = G_SUB [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[SUB]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[SUB]](s8)
     ; CHECK: RET 0
     %0(s32) = COPY %edx
     %1(s1) = G_TRUNC %0(s32)
@@ -51,9 +51,9 @@ body:             |
 
     ; CHECK-LABEL: name: test_sub_i32
     ; CHECK: liveins: %edi, %esi
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %esi
-    ; CHECK: [[SUB:%[0-9]+]](s32) = G_SUB [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
     ; CHECK: %eax = COPY [[SUB]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
diff --git a/test/CodeGen/X86/GlobalISel/legalize-trunc.mir b/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
index 6b390d990ec..00827d331a4 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
@@ -17,15 +17,14 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = IMPLICIT_DEF
-    ; ALL: %1(s1)  = G_TRUNC %0(s32)
+    ; ALL: %1:_(s1)  = G_TRUNC %0(s32)
     %1(s1)  = G_TRUNC %0(s32)
 
-    ; ALL: %2(s8)  = G_TRUNC %0(s32)
+    ; ALL: %2:_(s8)  = G_TRUNC %0(s32)
     %2(s8)  = G_TRUNC %0(s32)
 
-    ; ALL: %3(s16) = G_TRUNC %0(s32)
+    ; ALL: %3:_(s16) = G_TRUNC %0(s32)
     %3(s16) = G_TRUNC %0(s32)
     RET 0
 
 ...
-
diff --git a/test/CodeGen/X86/GlobalISel/legalize-undef.mir b/test/CodeGen/X86/GlobalISel/legalize-undef.mir
index 83c92dfd2c7..2f4372fa4a3 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-undef.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-undef.mir
@@ -5,19 +5,19 @@
 name:            test_implicit_def
 # ALL-LABEL: name:  test_implicit_def
 registers:
-# X64:          %0(s1) = G_IMPLICIT_DEF
-# X64-NEXT:     %1(s8) = G_IMPLICIT_DEF
-# X64-NEXT:     %2(s16) = G_IMPLICIT_DEF
-# X64-NEXT:     %3(s32) = G_IMPLICIT_DEF
-# X64-NEXT:     %4(s64) = G_IMPLICIT_DEF
+# X64:          %0:_(s1) = G_IMPLICIT_DEF
+# X64-NEXT:     %1:_(s8) = G_IMPLICIT_DEF
+# X64-NEXT:     %2:_(s16) = G_IMPLICIT_DEF
+# X64-NEXT:     %3:_(s32) = G_IMPLICIT_DEF
+# X64-NEXT:     %4:_(s64) = G_IMPLICIT_DEF
 #
-# X32:          %0(s1) = G_IMPLICIT_DEF
-# X32-NEXT:     %1(s8) = G_IMPLICIT_DEF
-# X32-NEXT:     %2(s16) = G_IMPLICIT_DEF
-# X32-NEXT:     %3(s32) = G_IMPLICIT_DEF
-# X32-NEXT:     %5(s32) = G_IMPLICIT_DEF
-# X32-NEXT:     %6(s32) = G_IMPLICIT_DEF
-# X32-NEXT:     %4(s64) = G_MERGE_VALUES %5(s32), %6(s32)
+# X32:          %0:_(s1) = G_IMPLICIT_DEF
+# X32-NEXT:     %1:_(s8) = G_IMPLICIT_DEF
+# X32-NEXT:     %2:_(s16) = G_IMPLICIT_DEF
+# X32-NEXT:     %3:_(s32) = G_IMPLICIT_DEF
+# X32-NEXT:     %5:_(s32) = G_IMPLICIT_DEF
+# X32-NEXT:     %6:_(s32) = G_IMPLICIT_DEF
+# X32-NEXT:     %4:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
 body: |
   bb.0.entry:
     liveins:
diff --git a/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir b/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
index 373f4839734..1e6b27ef3ba 100644
--- a/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
@@ -41,11 +41,11 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; CHECK-LABEL: name: test_xor_i1
-    ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %edx
-    ; CHECK: [[TRUNC:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]](s8) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[XOR:%[0-9]+]](s8) = G_XOR [[TRUNC]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]](s1) = G_TRUNC [[XOR]](s8)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[XOR]](s8)
     ; CHECK: RET 0
     %0(s32) = COPY %edx
     %1(s1) = G_TRUNC %0(s32)
@@ -67,8 +67,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_xor_i8
-    ; CHECK: [[DEF:%[0-9]+]](s8) = IMPLICIT_DEF
-    ; CHECK: [[XOR:%[0-9]+]](s8) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
+    ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
     ; CHECK: %al = COPY [[XOR]](s8)
     ; CHECK: RET 0, implicit %al
     %0(s8) = IMPLICIT_DEF
@@ -92,8 +92,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_xor_i16
-    ; CHECK: [[DEF:%[0-9]+]](s16) = IMPLICIT_DEF
-    ; CHECK: [[XOR:%[0-9]+]](s16) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
+    ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
     ; CHECK: %ax = COPY [[XOR]](s16)
     ; CHECK: RET 0, implicit %ax
     %0(s16) = IMPLICIT_DEF
@@ -117,8 +117,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_xor_i32
-    ; CHECK: [[DEF:%[0-9]+]](s32) = IMPLICIT_DEF
-    ; CHECK: [[XOR:%[0-9]+]](s32) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
     ; CHECK: %eax = COPY [[XOR]](s32)
     ; CHECK: RET 0, implicit %eax
     %0(s32) = IMPLICIT_DEF
@@ -142,8 +142,8 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: test_xor_i64
-    ; CHECK: [[DEF:%[0-9]+]](s64) = IMPLICIT_DEF
-    ; CHECK: [[XOR:%[0-9]+]](s64) = G_XOR [[DEF]], [[DEF]]
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
     ; CHECK: %rax = COPY [[XOR]](s64)
     ; CHECK: RET 0, implicit %rax
     %0(s64) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
index e0e61c4ac81..ad72d301ea3 100644
--- a/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
+++ b/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir
@@ -35,7 +35,7 @@
     %ret = fadd double %arg1, %arg2
     ret double %ret
   }
-  
+
   define void @test_fsub_float() {
     %ret1 = fsub float undef, undef
     %ret2 = fsub double undef, undef
@@ -53,7 +53,7 @@
     %ret2 = fdiv double undef, undef
     ret void
   }
-  
+
 
   define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
     %ret = add <4 x i32> %arg1, %arg2
@@ -180,7 +180,7 @@
   entry:
     ret i32* @g_int
   }
-  
+
   define i8 @test_undef() {
     ret i8 undef
   }
@@ -198,7 +198,7 @@
     %r = fadd float %a, undef
     ret float %r
   }
-  
+
   define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
   entry:
     %cmp = icmp sgt i32 %a, 0
@@ -236,9 +236,9 @@
     %conv = fpext float %a to double
     ret double %conv
   }
-  
-  define void @test_fconstant() { 
-    ret void 
+
+  define void @test_fconstant() {
+    ret void
   }
 
 ...
@@ -375,10 +375,10 @@ registers:
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }
-  - { id: 7, class: _ }  
+  - { id: 7, class: _ }
 body:             |
   bb.1 (%ir-block.0):
-    
+
     %0(s64) = IMPLICIT_DEF
     %1(s32) = IMPLICIT_DEF
     %2(s16) = IMPLICIT_DEF
@@ -831,9 +831,9 @@ body:             |
 
     %0(s32) = COPY %xmm0
     %1(p0) = COPY %rdi
-    ; CHECK:      %1(p0) = COPY %rdi
+    ; CHECK:      %1:gpr(p0) = COPY %rdi
 
-    ; FAST-NEXT:  %2(s32) = COPY %0(s32)
+    ; FAST-NEXT:  %2:gpr(s32) = COPY %0(s32)
     ; FAST-NEXT:  G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
 
     ; GREEDY-NEXT:  G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
@@ -869,9 +869,9 @@ body:             |
     %0(s64) = COPY %xmm0
     %1(p0) = COPY %rdi
 
-    ; CHECK:       %1(p0) = COPY %rdi
+    ; CHECK:       %1:gpr(p0) = COPY %rdi
 
-    ; FAST-NEXT:   %2(s64) = COPY %0(s64)
+    ; FAST-NEXT:   %2:gpr(s64) = COPY %0(s64)
     ; FAST-NEXT:   G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1)
 
     ; GREEDY-NEXT: G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
@@ -1161,7 +1161,7 @@ regBankSelected: false
 # CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _, preferred-register: '' }
-# CHECK:           %0(p0) = G_GLOBAL_VALUE @g_int
+# CHECK:           %0:gpr(p0) = G_GLOBAL_VALUE @g_int
 # CHECK-NEXT:      %rax = COPY %0(p0)
 # CHECK-NEXT:      RET 0, implicit %rax
 body:             |
@@ -1185,7 +1185,7 @@ liveins:
 fixedStack:
 stack:
 constants:
-# CHECK:           %0(s8) = G_IMPLICIT_DEF
+# CHECK:           %0:gpr(s8) = G_IMPLICIT_DEF
 # CHECK-NEXT:      %al = COPY %0(s8)
 # CHECK-NEXT:      RET 0, implicit %al
 body:             |
@@ -1213,9 +1213,9 @@ liveins:
 fixedStack:
 stack:
 constants:
-# CHECK:           %0(s8) = COPY %dil
-# CHECK-NEXT:      %1(s8) = G_IMPLICIT_DEF
-# CHECK-NEXT:      %2(s8) = G_ADD %0, %1
+# CHECK:           %0:gpr(s8) = COPY %dil
+# CHECK-NEXT:      %1:gpr(s8) = G_IMPLICIT_DEF
+# CHECK-NEXT:      %2:gpr(s8) = G_ADD %0, %1
 # CHECK-NEXT:      %al = COPY %2(s8)
 # CHECK-NEXT:      RET 0, implicit %al
 body:             |
@@ -1243,7 +1243,7 @@ liveins:
 fixedStack:
 stack:
 constants:
-# CHECK:           %0(s32) = G_IMPLICIT_DEF
+# CHECK:           %0:gpr(s32) = G_IMPLICIT_DEF
 # CHECK-NEXT:      %xmm0 = COPY %0(s32)
 # CHECK-NEXT:      RET 0, implicit %xmm0
 body:             |
@@ -1272,10 +1272,10 @@ liveins:
 fixedStack:
 stack:
 constants:
-# CHECK:           %0(s32) = COPY %xmm0
-# CHECK-NEXT:      %1(s32) = G_IMPLICIT_DEF
-# CHECK-NEXT:      %3(s32) = COPY %1(s32)
-# CHECK-NEXT:      %2(s32) = G_FADD %0, %3
+# CHECK:           %0:vecr(s32) = COPY %xmm0
+# CHECK-NEXT:      %1:gpr(s32) = G_IMPLICIT_DEF
+# CHECK-NEXT:      %3:vecr(s32) = COPY %1(s32)
+# CHECK-NEXT:      %2:vecr(s32) = G_FADD %0, %3
 # CHECK-NEXT:      %xmm0 = COPY %2(s32)
 # CHECK-NEXT:      RET 0, implicit %xmm0
 body:             |
@@ -1311,7 +1311,7 @@ registers:
   - { id: 4, class: _, preferred-register: '' }
   - { id: 5, class: _, preferred-register: '' }
 # CHECK:       bb.3.cond.end:
-# CHECK-NEXT:      %5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
+# CHECK-NEXT:      %5:gpr(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
 # CHECK-NEXT:      %eax = COPY %5(s32)
 # CHECK-NEXT:      RET 0, implicit %eax
 body:             |
@@ -1363,7 +1363,7 @@ registers:
   - { id: 4, class: _, preferred-register: '' }
   - { id: 5, class: _, preferred-register: '' }
 # CHECK:         bb.3.cond.end:
-# CHECK-NEXT:      %5(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
+# CHECK-NEXT:      %5:vecr(s32) = G_PHI %1(s32), %bb.1.cond.true, %2(s32), %bb.2.cond.false
 # CHECK-NEXT:      %xmm0 = COPY %5(s32)
 # CHECK-NEXT:      RET 0, implicit %xmm0
 body:             |
@@ -1430,4 +1430,3 @@ body: |
     %0(s32) = G_FCONSTANT float 1.0
     %1(s64) = G_FCONSTANT double 2.0
 ...
-
diff --git a/test/CodeGen/X86/GlobalISel/select-GV.mir b/test/CodeGen/X86/GlobalISel/select-GV.mir
index 7e8d61f002e..7de74269ce7 100644
--- a/test/CodeGen/X86/GlobalISel/select-GV.mir
+++ b/test/CodeGen/X86/GlobalISel/select-GV.mir
@@ -40,23 +40,23 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# X64:                     %0 = IMPLICIT_DEF
-# X64-NEXT:                %1 = LEA64r _, 1, _, @g_int, _
+# X64:                     %0:gr64 = IMPLICIT_DEF
+# X64-NEXT:                %1:gr64 = LEA64r _, 1, _, @g_int, _
 # X64-NEXT:                MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`)
 # X64-NEXT:                RET 0
 #
-# X64_DARWIN_PIC:          %0 = IMPLICIT_DEF
-# X64_DARWIN_PIC-NEXT:     %1 = LEA64r %rip, 1, _, @g_int, _
+# X64_DARWIN_PIC:          %0:gr64 = IMPLICIT_DEF
+# X64_DARWIN_PIC-NEXT:     %1:gr64 = LEA64r %rip, 1, _, @g_int, _
 # X64_DARWIN_PIC-NEXT:     MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`)
 # X64_DARWIN_PIC-NEXT:     RET 0
 #
-# X32:                     %0 = IMPLICIT_DEF
-# X32-NEXT:                %1 = LEA32r _, 1, _, @g_int, _
+# X32:                     %0:gr32 = IMPLICIT_DEF
+# X32-NEXT:                %1:gr32 = LEA32r _, 1, _, @g_int, _
 # X32-NEXT:                MOV32mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`)
 # X32-NEXT:                RET 0
 #
-# X32ABI:                  %0 = IMPLICIT_DEF
-# X32ABI-NEXT:             %1 = LEA64_32r _, 1, _, @g_int, _
+# X32ABI:                  %0:low32_addr_access = IMPLICIT_DEF
+# X32ABI-NEXT:             %1:gr32 = LEA64_32r _, 1, _, @g_int, _
 # X32ABI-NEXT:             MOV32mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`)
 # X32ABI-NEXT:             RET 0
 body:             |
@@ -85,23 +85,23 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# X64:                     %1 = LEA64r _, 1, _, @g_int, _
-# X64-NEXT:                %0 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
+# X64:                     %1:gr64 = LEA64r _, 1, _, @g_int, _
+# X64-NEXT:                %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
 # X64-NEXT:                %eax = COPY %0
 # X64-NEXT:                RET 0, implicit %eax
 #
-# X64_DARWIN_PIC:          %1 = LEA64r %rip, 1, _, @g_int, _
-# X64_DARWIN_PIC-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
+# X64_DARWIN_PIC:          %1:gr64 = LEA64r %rip, 1, _, @g_int, _
+# X64_DARWIN_PIC-NEXT:     %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
 # X64_DARWIN_PIC-NEXT:     %eax = COPY %0
 # X64_DARWIN_PIC-NEXT:     RET 0, implicit %eax
 #
-# X32:                     %1 = LEA32r _, 1, _, @g_int, _
-# X32-NEXT:                %0 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
+# X32:                     %1:gr32 = LEA32r _, 1, _, @g_int, _
+# X32-NEXT:                %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
 # X32-NEXT:                %eax = COPY %0
 # X32-NEXT:                RET 0, implicit %eax
 #
-# X32ABI:                  %1 = LEA64_32r _, 1, _, @g_int, _
-# X32ABI-NEXT:             %0 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
+# X32ABI:                  %1:gr32 = LEA64_32r _, 1, _, @g_int, _
+# X32ABI-NEXT:             %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int)
 # X32ABI-NEXT:             %eax = COPY %0
 # X32ABI-NEXT:             RET 0, implicit %eax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/test/CodeGen/X86/GlobalISel/select-add-v128.mir
index 4f7b6ec72d5..7a2f606a45a 100644
--- a/test/CodeGen/X86/GlobalISel/select-add-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/select-add-v128.mir
@@ -49,13 +49,13 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PADDBrr %0, %1
+# SSE2:                %2:vr128 = PADDBrr %0, %1
 #
-# AVX1:                %2 = VPADDBrr %0, %1
+# AVX1:                %2:vr128 = VPADDBrr %0, %1
 #
-# AVX512VL:            %2 = VPADDBrr %0, %1
+# AVX512VL:            %2:vr128 = VPADDBrr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDBZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPADDBZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -91,13 +91,13 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PADDWrr %0, %1
+# SSE2:                %2:vr128 = PADDWrr %0, %1
 #
-# AVX1:                %2 = VPADDWrr %0, %1
+# AVX1:                %2:vr128 = VPADDWrr %0, %1
 #
-# AVX512VL:            %2 = VPADDWrr %0, %1
+# AVX512VL:            %2:vr128 = VPADDWrr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDWZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPADDWZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -133,13 +133,13 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PADDDrr %0, %1
+# SSE2:                %2:vr128 = PADDDrr %0, %1
 #
-# AVX1:                %2 = VPADDDrr %0, %1
+# AVX1:                %2:vr128 = VPADDDrr %0, %1
 #
-# AVX512VL:            %2 = VPADDDZ128rr %0, %1
+# AVX512VL:            %2:vr128x = VPADDDZ128rr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDDZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPADDDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -175,13 +175,13 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PADDQrr %0, %1
+# SSE2:                %2:vr128 = PADDQrr %0, %1
 #
-# AVX1:                %2 = VPADDQrr %0, %1
+# AVX1:                %2:vr128 = VPADDQrr %0, %1
 #
-# AVX512VL:            %2 = VPADDQZ128rr %0, %1
+# AVX512VL:            %2:vr128x = VPADDQZ128rr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDQZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPADDQZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
diff --git a/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/test/CodeGen/X86/GlobalISel/select-add-v256.mir
index 143fd942297..8a98a6d8764 100644
--- a/test/CodeGen/X86/GlobalISel/select-add-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-add-v256.mir
@@ -47,11 +47,11 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPADDBYrr %0, %1
+# AVX2:                %2:vr256 = VPADDBYrr %0, %1
 #
-# AVX512VL:            %2 = VPADDBYrr %0, %1
+# AVX512VL:            %2:vr256 = VPADDBYrr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDBZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPADDBZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -87,11 +87,11 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPADDWYrr %0, %1
+# AVX2:                %2:vr256 = VPADDWYrr %0, %1
 #
-# AVX512VL:            %2 = VPADDWYrr %0, %1
+# AVX512VL:            %2:vr256 = VPADDWYrr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDWZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPADDWZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -127,11 +127,11 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPADDDYrr %0, %1
+# AVX2:                %2:vr256 = VPADDDYrr %0, %1
 #
-# AVX512VL:            %2 = VPADDDZ256rr %0, %1
+# AVX512VL:            %2:vr256x = VPADDDZ256rr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDDZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPADDDZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -167,11 +167,11 @@ registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPADDQYrr %0, %1
+# AVX2:                %2:vr256 = VPADDQYrr %0, %1
 #
-# AVX512VL:            %2 = VPADDQZ256rr %0, %1
+# AVX512VL:            %2:vr256x = VPADDQZ256rr %0, %1
 #
-# AVX512BWVL:          %2 = VPADDQZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPADDQZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
diff --git a/test/CodeGen/X86/GlobalISel/select-add-v512.mir b/test/CodeGen/X86/GlobalISel/select-add-v512.mir
index 8814e26d7b4..392d22c0900 100644
--- a/test/CodeGen/X86/GlobalISel/select-add-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-add-v512.mir
@@ -39,13 +39,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_add_v64i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPADDBZrr:%[0-9]+]] = VPADDBZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPADDBZrr:%[0-9]+]]:vr512 = VPADDBZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPADDBZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<64 x s8>) = COPY %zmm0
@@ -69,13 +65,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_add_v32i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPADDWZrr:%[0-9]+]] = VPADDWZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPADDWZrr:%[0-9]+]]:vr512 = VPADDWZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPADDWZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<32 x s16>) = COPY %zmm0
@@ -99,13 +91,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_add_v16i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPADDDZrr:%[0-9]+]] = VPADDDZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPADDDZrr:%[0-9]+]]:vr512 = VPADDDZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPADDDZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<16 x s32>) = COPY %zmm0
@@ -129,13 +117,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_add_v8i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPADDQZrr:%[0-9]+]] = VPADDQZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPADDQZrr:%[0-9]+]]:vr512 = VPADDQZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPADDQZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<8 x s64>) = COPY %zmm0
diff --git a/test/CodeGen/X86/GlobalISel/select-add-x32.mir b/test/CodeGen/X86/GlobalISel/select-add-x32.mir
index a945b4060e0..4f04bc58ae6 100644
--- a/test/CodeGen/X86/GlobalISel/select-add-x32.mir
+++ b/test/CodeGen/X86/GlobalISel/select-add-x32.mir
@@ -26,26 +26,15 @@ registers:
 body:             |
   bb.0 (%ir-block.0):
     ; X32-LABEL: name: test_add_i64
-    ; X32: registers:
-    ; X32-NEXT: id: 0, class: gr32
-    ; X32-NEXT: id: 1, class: gr32
-    ; X32-NEXT: id: 2, class: gr32
-    ; X32-NEXT: id: 3, class: gr32
-    ; X32-NEXT: id: 4, class: gpr
-    ; X32-NEXT: id: 5, class: gr32
-    ; X32-NEXT: id: 6, class: gr32
-    ; X32-NEXT: id: 7, class: gr32
-    ; X32-NEXT: id: 8, class: gr32
-    ; X32-NEXT: id: 9, class: gpr
-    ; X32: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; X32: [[DEF1:%[0-9]+]] = IMPLICIT_DEF
-    ; X32: [[DEF2:%[0-9]+]] = IMPLICIT_DEF
-    ; X32: [[DEF3:%[0-9]+]] = IMPLICIT_DEF
-    ; X32: [[ADD32rr:%[0-9]+]] = ADD32rr [[DEF]], [[DEF2]], implicit-def %eflags
-    ; X32: [[COPY:%[0-9]+]] = COPY %eflags
+    ; X32: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; X32: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; X32: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; X32: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
+    ; X32: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def %eflags
+    ; X32: [[COPY:%[0-9]+]]:gr32 = COPY %eflags
     ; X32: %eflags = COPY [[COPY]]
-    ; X32: [[ADC32rr:%[0-9]+]] = ADC32rr [[DEF1]], [[DEF3]], implicit-def %eflags, implicit %eflags
-    ; X32: [[COPY1:%[0-9]+]] = COPY %eflags
+    ; X32: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def %eflags, implicit %eflags
+    ; X32: [[COPY1:%[0-9]+]]:gr32 = COPY %eflags
     ; X32: %eax = COPY [[ADD32rr]]
     ; X32: %edx = COPY [[ADC32rr]]
     ; X32: RET 0, implicit %eax, implicit %edx
diff --git a/test/CodeGen/X86/GlobalISel/select-add.mir b/test/CodeGen/X86/GlobalISel/select-add.mir
index 8962e7ff502..1f42fd4fc85 100644
--- a/test/CodeGen/X86/GlobalISel/select-add.mir
+++ b/test/CodeGen/X86/GlobalISel/select-add.mir
@@ -40,17 +40,13 @@ name:            test_add_i64
 # ALL-LABEL: name:            test_add_i64
 legalized:       true
 regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:      %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %rsi
-# ALL-NEXT: %2 = ADD64rr %0, %1
+# ALL:      %0:gr64 = COPY %rdi
+# ALL-NEXT: %1:gr64 = COPY %rsi
+# ALL-NEXT: %2:gr64 = ADD64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -67,17 +63,13 @@ name:            test_add_i32
 # ALL-LABEL: name:            test_add_i32
 legalized:       true
 regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:      %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = ADD32rr %0, %1
+# ALL:      %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr32 = COPY %esi
+# ALL-NEXT: %2:gr32 = ADD32rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -95,17 +87,13 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr16, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL: %0 = COPY %di
-# ALL: %1 = COPY %si
-# ALL: %2 = ADD16rr %0, %1, implicit-def %eflags
+# ALL: %0:gr16 = COPY %di
+# ALL: %1:gr16 = COPY %si
+# ALL: %2:gr16 = ADD16rr %0, %1, implicit-def %eflags
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -124,17 +112,13 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL: %0 = COPY %dil
-# ALL: %1 = COPY %sil
-# ALL: %2 = ADD8rr %0, %1, implicit-def %eflags
+# ALL: %0:gr8 = COPY %dil
+# ALL: %1:gr8 = COPY %sil
+# ALL: %2:gr8 = ADD8rr %0, %1, implicit-def %eflags
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -154,23 +138,18 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = PADDDrr %0, %1
-# AVX-NEXT:      %2 = VPADDDrr %0, %1
-# AVX512F-NEXT:  %2 = VPADDDrr %0, %1
-# AVX512VL-NEXT: %2 = VPADDDZ128rr %0, %1
+# NO_AVX512VL:   %0:vr128 = COPY %xmm0
+# NO_AVX512VL:   %1:vr128 = COPY %xmm1
+# SSE-NEXT:      %2:vr128 = PADDDrr %0, %1
+# AVX-NEXT:      %2:vr128 = VPADDDrr %0, %1
+# AVX512F-NEXT:  %2:vr128 = VPADDDrr %0, %1
+# AVX512VL:      %0:vr128x = COPY %xmm0
+# AVX512VL:      %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr128x = VPADDDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -190,23 +169,22 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = ADDPSrr %0, %1
-# AVX-NEXT:      %2 = VADDPSrr %0, %1
-# AVX512F-NEXT:  %2 = VADDPSrr %0, %1
-# AVX512VL-NEXT: %2 = VADDPSZ128rr %0, %1
+# SSE:           %0:vr128 = COPY %xmm0
+# SSE-NEXT:      %1:vr128 = COPY %xmm1
+# SSE-NEXT:      %2:vr128 = ADDPSrr %0, %1
+# AVX:           %0:vr128 = COPY %xmm0
+# AVX-NEXT:      %1:vr128 = COPY %xmm1
+# AVX-NEXT:      %2:vr128 = VADDPSrr %0, %1
+# AVX512F:       %0:vr128 = COPY %xmm0
+# AVX512F-NEXT:  1:vr128 = COPY %xmm1
+# AVX512F-NEXT:  %2:vr128 = VADDPSrr %0, %1
+# AVX512VL:      %0:vr128x = COPY %xmm0
+# AVX512VL-NEXT: %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr128x = VADDPSZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
diff --git a/test/CodeGen/X86/GlobalISel/select-and-scalar.mir b/test/CodeGen/X86/GlobalISel/select-and-scalar.mir
index 4085eea2ab0..0ecb8816d79 100644
--- a/test/CodeGen/X86/GlobalISel/select-and-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-and-scalar.mir
@@ -41,13 +41,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_and_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr8
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %sil
-    ; ALL: [[AND8rr:%[0-9]+]] = AND8rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
+    ; ALL: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %al = COPY [[AND8rr]]
     ; ALL: RET 0, implicit %al
     %0(s8) = COPY %dil
@@ -75,13 +71,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_and_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr16
-    ; ALL-NEXT: id: 2, class: gr16
-    ; ALL: [[COPY:%[0-9]+]] = COPY %di
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %si
-    ; ALL: [[AND16rr:%[0-9]+]] = AND16rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+    ; ALL: [[AND16rr:%[0-9]+]]:gr16 = AND16rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %ax = COPY [[AND16rr]]
     ; ALL: RET 0, implicit %ax
     %0(s16) = COPY %di
@@ -109,13 +101,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_and_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[COPY:%[0-9]+]] = COPY %edi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
-    ; ALL: [[AND32rr:%[0-9]+]] = AND32rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+    ; ALL: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %eax = COPY [[AND32rr]]
     ; ALL: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -143,13 +131,9 @@ body:             |
     liveins: %rdi, %rsi
 
     ; ALL-LABEL: name: test_and_i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
-    ; ALL: [[AND64rr:%[0-9]+]] = AND64rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+    ; ALL: [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %rax = COPY [[AND64rr]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-blsi.mir b/test/CodeGen/X86/GlobalISel/select-blsi.mir
index 6545678ccb2..02478837134 100644
--- a/test/CodeGen/X86/GlobalISel/select-blsi.mir
+++ b/test/CodeGen/X86/GlobalISel/select-blsi.mir
@@ -24,13 +24,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_blsi32rr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[BLSI32rr:%[0-9]+]] = BLSI32rr [[COPY]], implicit-def %eflags
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[BLSI32rr:%[0-9]+]]:gr32 = BLSI32rr [[COPY]], implicit-def %eflags
     ; CHECK: %edi = COPY [[BLSI32rr]]
     %0(s32) = COPY %edi
     %1(s32) = G_CONSTANT i32 0
@@ -55,15 +50,10 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_blsi32rr_nomatch
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr32
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[MOV32r0_:%[0-9]+]] = MOV32r0 implicit-def %eflags
-    ; CHECK: [[SUB32ri:%[0-9]+]] = SUB32ri [[MOV32r0_]], 0, implicit-def %eflags
-    ; CHECK: [[AND32rr:%[0-9]+]] = AND32rr [[SUB32ri]], [[COPY]], implicit-def %eflags
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags
+    ; CHECK: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri [[MOV32r0_]], 0, implicit-def %eflags
+    ; CHECK: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32ri]], [[COPY]], implicit-def %eflags
     ; CHECK: %edi = COPY [[AND32rr]]
     %0(s32) = COPY %edi
     %1(s32) = G_CONSTANT i32 0
diff --git a/test/CodeGen/X86/GlobalISel/select-blsr.mir b/test/CodeGen/X86/GlobalISel/select-blsr.mir
index 737502ff1e9..95c6cfdef80 100644
--- a/test/CodeGen/X86/GlobalISel/select-blsr.mir
+++ b/test/CodeGen/X86/GlobalISel/select-blsr.mir
@@ -21,13 +21,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_blsr32rr
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gpr
-    ; CHECK-NEXT: id: 2, class: gpr
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[BLSR32rr:%[0-9]+]] = BLSR32rr [[COPY]], implicit-def %eflags
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[BLSR32rr:%[0-9]+]]:gr32 = BLSR32rr [[COPY]], implicit-def %eflags
     ; CHECK: %edi = COPY [[BLSR32rr]]
     %0(s32) = COPY %edi
     %1(s32) = G_CONSTANT i32 -1
@@ -52,15 +47,10 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: test_blsr32rr_nomatch
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr32
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 4294967295
-    ; CHECK: [[DEC32r:%[0-9]+]] = DEC32r [[MOV32ri]], implicit-def %eflags
-    ; CHECK: [[AND32rr:%[0-9]+]] = AND32rr [[DEC32r]], [[COPY]], implicit-def %eflags
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4294967295
+    ; CHECK: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def %eflags
+    ; CHECK: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def %eflags
     ; CHECK: %edi = COPY [[AND32rr]]
     %0(s32) = COPY %edi
     %1(s32) = G_CONSTANT i32 -1
diff --git a/test/CodeGen/X86/GlobalISel/select-brcond.mir b/test/CodeGen/X86/GlobalISel/select-brcond.mir
index d36338b9711..3d099a99df4 100644
--- a/test/CodeGen/X86/GlobalISel/select-brcond.mir
+++ b/test/CodeGen/X86/GlobalISel/select-brcond.mir
@@ -22,29 +22,19 @@ name:            test
 alignment:       4
 legalized:       true
 regBankSelected: true
-# X64:        registers:
-# X64-NEXT:     - { id: 0, class: gr32, preferred-register: '' }
-# X64-NEXT:     - { id: 1, class: gr8, preferred-register: '' }
-# X64-NEXT:     - { id: 2, class: gr32, preferred-register: '' }
-# X64-NEXT:     - { id: 3, class: gr32, preferred-register: '' }
-#
-# X32:        registers:
-# X32-NEXT:     - { id: 0, class: gr32_abcd, preferred-register: '' }
-# X32-NEXT:     - { id: 1, class: gr8, preferred-register: '' }
-# X32-NEXT:     - { id: 2, class: gr32, preferred-register: '' }
-# X32-NEXT:     - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
   - { id: 3, class: gpr, preferred-register: '' }
-# CHECK:         %0 = COPY %edi
-# CHECK-NEXT:    %2 = MOV32r0 implicit-def %eflags
-# CHECK-NEXT:    %3 = MOV32ri 1
-# CHECK-NEXT:    %1 = COPY %0.sub_8bit
+# X64:           %0:gr32 = COPY %edi
+# X32:           %0:gr32_abcd = COPY %edi
+# CHECK-NEXT:    %2:gr32 = MOV32r0 implicit-def %eflags
+# CHECK-NEXT:    %3:gr32 = MOV32ri 1
+# CHECK-NEXT:    %1:gr8 = COPY %0.sub_8bit
 # CHECK-NEXT:    TEST8ri %1, 1, implicit-def %eflags
 # CHECK-NEXT:    JNE_1 %[[TRUE:bb.[0-9].true]], implicit %eflags
-# CHECK-NEXT:    JMP_1 %[[FALSE:bb.[0-9].false]] 
+# CHECK-NEXT:    JMP_1 %[[FALSE:bb.[0-9].false]]
 # CHECK:      [[TRUE]]:
 # CHECK-NEXT:    %eax = COPY %2
 # CHECK-NEXT:    RET 0, implicit %eax
diff --git a/test/CodeGen/X86/GlobalISel/select-cmp.mir b/test/CodeGen/X86/GlobalISel/select-cmp.mir
index 4403053fc51..9058f010f76 100644
--- a/test/CodeGen/X86/GlobalISel/select-cmp.mir
+++ b/test/CodeGen/X86/GlobalISel/select-cmp.mir
@@ -96,18 +96,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr8
-    ; CHECK-NEXT: id: 1, class: gr8
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %dil
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %sil
+    ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
     ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s8) = COPY %dil
@@ -133,18 +127,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr16
-    ; CHECK-NEXT: id: 1, class: gr16
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %di
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %si
+    ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY %si
     ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s16) = COPY %di
@@ -170,18 +158,12 @@ body:             |
     liveins: %rdi, %rsi
 
     ; CHECK-LABEL: name: test_icmp_eq_i64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK-NEXT: id: 1, class: gr64
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %rsi
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
     ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s64) = COPY %rdi
@@ -207,18 +189,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETEr:%[0-9]+]] = SETEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETEr:%[0-9]+]]:gr8 = SETEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -244,18 +220,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_ne_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETNEr:%[0-9]+]] = SETNEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETNEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETNEr:%[0-9]+]]:gr8 = SETNEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETNEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -281,18 +251,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_ugt_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETAr:%[0-9]+]] = SETAr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETAr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETAr:%[0-9]+]]:gr8 = SETAr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -318,18 +282,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_uge_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETAEr:%[0-9]+]] = SETAEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETAEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETAEr:%[0-9]+]]:gr8 = SETAEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETAEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -355,18 +313,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_ult_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETBr:%[0-9]+]] = SETBr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETBr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETBr:%[0-9]+]]:gr8 = SETBr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -392,18 +344,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_ule_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETBEr:%[0-9]+]] = SETBEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETBEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETBEr:%[0-9]+]]:gr8 = SETBEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETBEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -429,18 +375,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_sgt_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETGr:%[0-9]+]] = SETGr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETGr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETGr:%[0-9]+]]:gr8 = SETGr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -466,18 +406,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_sge_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETGEr:%[0-9]+]] = SETGEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETGEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETGEr:%[0-9]+]]:gr8 = SETGEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETGEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -503,18 +437,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_slt_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETLr:%[0-9]+]] = SETLr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETLr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETLr:%[0-9]+]]:gr8 = SETLr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -540,18 +468,12 @@ body:             |
     liveins: %edi, %esi
 
     ; CHECK-LABEL: name: test_icmp_sle_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK-NEXT: id: 2, class: gr8
-    ; CHECK-NEXT: id: 3, class: gr32
-    ; CHECK-NEXT: id: 4, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %esi
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def %eflags
-    ; CHECK: [[SETLEr:%[0-9]+]] = SETLEr implicit %eflags
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[SETLEr]], 1
-    ; CHECK: [[AND32ri8_:%[0-9]+]] = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; CHECK: [[SETLEr:%[0-9]+]]:gr8 = SETLEr implicit %eflags
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[SETLEr]], 1
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; CHECK: %eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = COPY %edi
diff --git a/test/CodeGen/X86/GlobalISel/select-constant.mir b/test/CodeGen/X86/GlobalISel/select-constant.mir
index db6c8c984a8..5dffc33e9dd 100644
--- a/test/CodeGen/X86/GlobalISel/select-constant.mir
+++ b/test/CodeGen/X86/GlobalISel/select-constant.mir
@@ -46,9 +46,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr8
-    ; CHECK: [[MOV8ri:%[0-9]+]] = MOV8ri 2
+    ; CHECK: [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 2
     ; CHECK: %al = COPY [[MOV8ri]]
     ; CHECK: RET 0, implicit %al
     %0(s8) = G_CONSTANT i8 2
@@ -66,9 +64,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr16
-    ; CHECK: [[MOV16ri:%[0-9]+]] = MOV16ri 3
+    ; CHECK: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 3
     ; CHECK: %ax = COPY [[MOV16ri]]
     ; CHECK: RET 0, implicit %ax
     %0(s16) = G_CONSTANT i16 3
@@ -86,9 +82,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 4
+    ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 4
     ; CHECK: %eax = COPY [[MOV32ri]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 4
@@ -105,9 +99,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_0
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32r0_:%[0-9]+]] = MOV32r0 implicit-def %eflags
+    ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def %eflags
     ; CHECK: %eax = COPY [[MOV32r0_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 0
@@ -125,9 +117,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK: [[MOV64ri:%[0-9]+]] = MOV64ri 68719476720
+    ; CHECK: [[MOV64ri:%[0-9]+]]:gr64 = MOV64ri 68719476720
     ; CHECK: %rax = COPY [[MOV64ri]]
     ; CHECK: RET 0, implicit %rax
     %0(s64) = G_CONSTANT i64 68719476720
@@ -146,9 +136,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64_u32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 1879048192
+    ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 1879048192
     ; CHECK: %rax = COPY [[MOV64ri32_]]
     ; CHECK: RET 0, implicit %rax
     %0(s64) = G_CONSTANT i64 1879048192
@@ -166,9 +154,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i64_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 -1
+    ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 -1
     ; CHECK: %rax = COPY [[MOV64ri32_]]
     ; CHECK: RET 0, implicit %rax
     %0(s64) = G_CONSTANT i64 -1
@@ -189,11 +175,8 @@ body:             |
     liveins: %rdi
 
     ; CHECK-LABEL: name: main
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK-NEXT: id: 1, class: gr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 0
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0
     ; CHECK: MOV64mr [[COPY]], 1, _, 0, _, [[MOV64ri32_]] :: (store 8 into %ir.data)
     ; CHECK: RET 0
     %0(p0) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-copy.mir b/test/CodeGen/X86/GlobalISel/select-copy.mir
index 2b5126e9363..a72f42782c0 100644
--- a/test/CodeGen/X86/GlobalISel/select-copy.mir
+++ b/test/CodeGen/X86/GlobalISel/select-copy.mir
@@ -41,9 +41,9 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %al
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT:     %1 = AND32ri8 %2, 1, implicit-def %eflags
+# ALL:          %0:gr8 = COPY %al
+# ALL-NEXT:     %2:gr32 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT:     %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -68,8 +68,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %al
-# ALL-NEXT:     %1 = MOVZX32rr8 %0
+# ALL:          %0:gr8 = COPY %al
+# ALL-NEXT:     %1:gr32 = MOVZX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -94,8 +94,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %al
-# ALL-NEXT:     %1 = MOVZX32rr8 %0
+# ALL:          %0:gr8 = COPY %al
+# ALL-NEXT:     %1:gr32 = MOVZX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -120,8 +120,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %ax
-# ALL-NEXT:     %1 = MOVZX32rr16 %0
+# ALL:          %0:gr16 = COPY %ax
+# ALL-NEXT:     %1:gr32 = MOVZX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -145,8 +145,8 @@ regBankSelected: true
 # ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %dl
-# ALL-NEXT:     %1 = SUBREG_TO_REG 0, %0, 1
+# ALL:          %0:gr8 = COPY %dl
+# ALL-NEXT:     %1:gr32 = SUBREG_TO_REG 0, %0, 1
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -169,8 +169,8 @@ regBankSelected: true
 # ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %dx
-# ALL-NEXT:     %1 = SUBREG_TO_REG 0, %0, 3
+# ALL:          %0:gr16 = COPY %dx
+# ALL-NEXT:     %1:gr32 = SUBREG_TO_REG 0, %0, 3
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
index df9265e45fe..51088e126e5 100644
--- a/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
+++ b/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
@@ -37,15 +37,10 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: test_zext_i1
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL-NEXT: id: 3, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]]
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
-    ; ALL: [[AND64ri8_:%[0-9]+]] = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]]
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
+    ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; ALL: %rax = COPY [[AND64ri8_]]
     ; ALL: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -68,11 +63,8 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: test_sext_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[MOVSX64rr8_:%[0-9]+]] = MOVSX64rr8 [[COPY]]
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]]
     ; ALL: %rax = COPY [[MOVSX64rr8_]]
     ; ALL: RET 0, implicit %rax
     %0(s8) = COPY %dil
@@ -94,11 +86,8 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: test_sext_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %di
-    ; ALL: [[MOVSX64rr16_:%[0-9]+]] = MOVSX64rr16 [[COPY]]
+    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]]
     ; ALL: %rax = COPY [[MOVSX64rr16_]]
     ; ALL: RET 0, implicit %rax
     %0(s16) = COPY %di
@@ -121,13 +110,9 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: anyext_s64_from_s1
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
+    ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
     ; ALL: %rax = COPY [[SUBREG_TO_REG]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
@@ -150,13 +135,9 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: anyext_s64_from_s8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64_with_sub_8bit
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 1
+    ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 1
     ; ALL: %rax = COPY [[SUBREG_TO_REG]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
@@ -179,13 +160,9 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: anyext_s64_from_s16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr16
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 3
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 3
     ; ALL: %rax = COPY [[SUBREG_TO_REG]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
@@ -208,13 +185,9 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: anyext_s64_from_s32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY1]], 4
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], 4
     ; ALL: %rax = COPY [[SUBREG_TO_REG]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-ext.mir b/test/CodeGen/X86/GlobalISel/select-ext.mir
index 49d1e798662..5167ee987a5 100644
--- a/test/CodeGen/X86/GlobalISel/select-ext.mir
+++ b/test/CodeGen/X86/GlobalISel/select-ext.mir
@@ -57,8 +57,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %dil
-# ALL-NEXT:     %1 = AND8ri %0, 1, implicit-def %eflags
+# ALL:          %0:gr8 = COPY %dil
+# ALL-NEXT:     %1:gr8 = AND8ri %0, 1, implicit-def %eflags
 # ALL-NEXT:     %al = COPY %1
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -84,9 +84,9 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
-# ALL:          %0 = COPY %dil
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT:     %1 = AND16ri8 %2, 1, implicit-def %eflags
+# ALL:          %0:gr8 = COPY %dil
+# ALL-NEXT:     %2:gr16 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT:     %1:gr16 = AND16ri8 %2, 1, implicit-def %eflags
 # ALL-NEXT:     %ax = COPY %1
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -112,9 +112,9 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:          %0 = COPY %dil
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %0, 1
-# ALL-NEXT:     %1 = AND32ri8 %2, 1, implicit-def %eflags
+# ALL:          %0:gr8 = COPY %dil
+# ALL-NEXT:     %2:gr32 = SUBREG_TO_REG 0, %0, 1
+# ALL-NEXT:     %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -139,8 +139,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:          %0 = COPY %dil
-# ALL-NEXT:     %1 = MOVZX32rr8 %0
+# ALL:          %0:gr8 = COPY %dil
+# ALL-NEXT:     %1:gr32 = MOVZX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -165,8 +165,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:          %0 = COPY %di
-# ALL-NEXT:     %1 = MOVZX32rr16 %0
+# ALL:          %0:gr16 = COPY %di
+# ALL-NEXT:     %1:gr32 = MOVZX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -191,8 +191,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:          %0 = COPY %dil
-# ALL-NEXT:     %1 = MOVSX32rr8 %0
+# ALL:          %0:gr8 = COPY %dil
+# ALL-NEXT:     %1:gr32 = MOVSX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -217,8 +217,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:          %0 = COPY %di
-# ALL-NEXT:     %1 = MOVSX32rr16 %0
+# ALL:          %0:gr16 = COPY %di
+# ALL-NEXT:     %1:gr32 = MOVSX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -250,9 +250,10 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_8bit
-# ALL-NEXT:     %2 = COPY %1
+# X32:          %0:gr32_abcd = COPY %edi
+# X64:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr8 = COPY %1
 # ALL-NEXT:     %al = COPY %2
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -284,9 +285,10 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_8bit
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# X32:          %0:gr32_abcd = COPY %edi
+# X64:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr16 = SUBREG_TO_REG 0, %1, 1
 # ALL-NEXT:     %ax = COPY %2
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -318,9 +320,10 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_8bit
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# X32:          %0:gr32_abcd = COPY %edi
+# X64:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr32 = SUBREG_TO_REG 0, %1, 1
 # ALL-NEXT:     %eax = COPY %2
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -352,9 +355,10 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_8bit
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# X32:          %0:gr32_abcd = COPY %edi
+# X64:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr16 = SUBREG_TO_REG 0, %1, 1
 # ALL-NEXT:     %ax = COPY %2
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -386,9 +390,10 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_8bit
-# ALL-NEXT:     %2 = MOVZX32rr8 %1
+# X32:          %0:gr32_abcd = COPY %edi
+# X64:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr32 = MOVZX32rr8 %1
 # ALL-NEXT:     %eax = COPY %2
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -415,9 +420,9 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:          %0 = COPY %edi
-# ALL-NEXT:     %1 = COPY %0.sub_16bit
-# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 3
+# ALL:          %0:gr32 = COPY %edi
+# ALL-NEXT:     %1:gr16 = COPY %0.sub_16bit
+# ALL-NEXT:     %2:gr32 = SUBREG_TO_REG 0, %1, 3
 # ALL-NEXT:     %eax = COPY %2
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
index 89bb84932cc..01f43be153b 100644
--- a/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
@@ -27,8 +27,10 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# ALL:               %0 = COPY %ymm1
-# ALL-NEXT:          %1 = COPY %0.sub_xmm
+# AVX:               %0:vr256 = COPY %ymm1
+# AVX-NEXT:          %1:vr128 = COPY %0.sub_xmm
+# AVX512VL:          %0:vr256x = COPY %ymm1
+# AVX512VL-NEXT:     %1:vr128x = COPY %0.sub_xmm
 # ALL-NEXT:          %xmm0 = COPY %1
 # ALL-NEXT:          RET 0, implicit %xmm0
 body:             |
@@ -57,13 +59,13 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# AVX:               %0 = COPY %ymm1
-# AVX-NEXT:          %1 = VEXTRACTF128rr %0, 1
+# AVX:               %0:vr256 = COPY %ymm1
+# AVX-NEXT:          %1:vr128 = VEXTRACTF128rr %0, 1
 # AVX-NEXT:          %xmm0 = COPY %1
 # AVX-NEXT:          RET 0, implicit %xmm0
 #
-# AVX512VL:          %0 = COPY %ymm1
-# AVX512VL-NEXT:     %1 = VEXTRACTF32x4Z256rr %0, 1
+# AVX512VL:          %0:vr256x = COPY %ymm1
+# AVX512VL-NEXT:     %1:vr128x = VEXTRACTF32x4Z256rr %0, 1
 # AVX512VL-NEXT:     %xmm0 = COPY %1
 # AVX512VL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -76,5 +78,3 @@ body:             |
     RET 0, implicit %xmm0
 
 ...
-
-
diff --git a/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
index a0f0d6f39d4..b17b9793d10 100644
--- a/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
@@ -32,8 +32,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# ALL:          %0 = COPY %zmm1
-# ALL-NEXT:     %1 = COPY %0.sub_xmm
+# ALL:          %0:vr512 = COPY %zmm1
+# ALL-NEXT:     %1:vr128x = COPY %0.sub_xmm
 # ALL-NEXT:     %xmm0 = COPY %1
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -58,8 +58,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# ALL:          %0 = COPY %zmm1
-# ALL-NEXT:     %1 = VEXTRACTF32x4Zrr %0, 1
+# ALL:          %0:vr512 = COPY %zmm1
+# ALL-NEXT:     %1:vr128x = VEXTRACTF32x4Zrr %0, 1
 # ALL-NEXT:     %xmm0 = COPY %1
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -84,8 +84,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# ALL:          %0 = COPY %zmm1
-# ALL-NEXT:     %1 = COPY %0.sub_ymm
+# ALL:          %0:vr512 = COPY %zmm1
+# ALL-NEXT:     %1:vr256x = COPY %0.sub_ymm
 # ALL-NEXT:     %ymm0 = COPY %1
 # ALL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -110,8 +110,8 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
-# ALL:          %0 = COPY %zmm1
-# ALL-NEXT:     %1 = VEXTRACTF64x4Zrr %0, 1
+# ALL:          %0:vr512 = COPY %zmm1
+# ALL-NEXT:     %1:vr256x = VEXTRACTF64x4Zrr %0, 1
 # ALL-NEXT:     %ymm0 = COPY %1
 # ALL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -124,4 +124,3 @@ body:             |
     RET 0, implicit %ymm0
 
 ...
-
diff --git a/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
index fa4c529982c..da8262bc38f 100644
--- a/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir
@@ -38,21 +38,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = ADDSSrr %0, %1
+# SSE:                  %0:fr32 = COPY %xmm0
+# SSE-NEXT:             %1:fr32 = COPY %xmm1
+# SSE-NEXT:             %2:fr32 = ADDSSrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VADDSSrr %0, %1
+# AVX:                  %0:fr32 = COPY %xmm0
+# AVX-NEXT:             %1:fr32 = COPY %xmm1
+# AVX-NEXT:             %2:fr32 = VADDSSrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VADDSSZrr %0, %1
+# AVX512ALL:            %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr32x = VADDSSZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
@@ -89,21 +89,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = ADDSDrr %0, %1
+# SSE:                  %0:fr64 = COPY %xmm0
+# SSE-NEXT:             %1:fr64 = COPY %xmm1
+# SSE-NEXT:             %2:fr64 = ADDSDrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VADDSDrr %0, %1
+# AVX:                  %0:fr64 = COPY %xmm0
+# AVX-NEXT:             %1:fr64 = COPY %xmm1
+# AVX-NEXT:             %2:fr64 = VADDSDrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VADDSDZrr %0, %1
+# AVX512ALL:            %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr64x = VADDSDZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-fconstant.mir b/test/CodeGen/X86/GlobalISel/select-fconstant.mir
index 44e37765f69..4e8f3daad2e 100644
--- a/test/CodeGen/X86/GlobalISel/select-fconstant.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fconstant.mir
@@ -23,27 +23,18 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
-# CHECK_SMALL64:        registers:
-# CHECK_SMALL64-NEXT:   - { id: 0, class: fr32, preferred-register: '' }
-#
-# CHECK_LARGE64:      registers:
-# CHECK_LARGE64-NEXT:   - { id: 0, class: fr32, preferred-register: '' }
-# CHECK_LARGE64-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
-#
-# CHECK32:            registers:
-# CHECK32-NEXT:         - { id: 0, class: fr32, preferred-register: '' }
 registers:
   - { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64:          %0 = MOVSSrm %rip, 1, _, %const.0, _
+# CHECK_SMALL64:          %0:fr32 = MOVSSrm %rip, 1, _, %const.0, _
 # CHECK_SMALL64-NEXT:     %xmm0 = COPY %0
 # CHECK_SMALL64-NEXT:     RET 0, implicit %xmm0
 #
-# CHECK_LARGE64:          %1 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT:     %0 = MOVSSrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 32)
+# CHECK_LARGE64:          %1:gr64 = MOV64ri %const.0
+# CHECK_LARGE64-NEXT:     %0:fr32 = MOVSSrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 32)
 # CHECK_LARGE64-NEXT:     %xmm0 = COPY %0
 # CHECK_LARGE64-NEXT:     RET 0, implicit %xmm0
 #
-# CHECK32:                %0 = MOVSSrm _, 1, _, %const.0, _
+# CHECK32:                %0:fr32 = MOVSSrm _, 1, _, %const.0, _
 # CHECK32-NEXT:           %xmm0 = COPY %0
 # CHECK32-NEXT:           RET 0, implicit %xmm0
 body:             |
@@ -73,16 +64,16 @@ tracksRegLiveness: true
 # CHECK32-NEXT:         - { id: 0, class: fr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr, preferred-register: '' }
-# CHECK_SMALL64:          %0 = MOVSDrm %rip, 1, _, %const.0, _
+# CHECK_SMALL64:          %0:fr64 = MOVSDrm %rip, 1, _, %const.0, _
 # CHECK_SMALL64-NEXT:     %xmm0 = COPY %0
 # CHECK_SMALL64-NEXT:     RET 0, implicit %xmm0
 #
-# CHECK_LARGE64:          %1 = MOV64ri %const.0
-# CHECK_LARGE64-NEXT:     %0 = MOVSDrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 64)
+# CHECK_LARGE64:          %1:gr64 = MOV64ri %const.0
+# CHECK_LARGE64-NEXT:     %0:fr64 = MOVSDrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 64)
 # CHECK_LARGE64-NEXT:     %xmm0 = COPY %0
 # CHECK_LARGE64-NEXT:     RET 0, implicit %xmm0
 #
-# CHECK32:                %0 = MOVSDrm _, 1, _, %const.0, _
+# CHECK32:                %0:fr64 = MOVSDrm _, 1, _, %const.0, _
 # CHECK32-NEXT:           %xmm0 = COPY %0
 # CHECK32-NEXT:           RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
index d2c1d152865..7dec4c5dffd 100644
--- a/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir
@@ -38,21 +38,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = DIVSSrr %0, %1
+# SSE:                  %0:fr32 = COPY %xmm0
+# SSE-NEXT:             %1:fr32 = COPY %xmm1
+# SSE-NEXT:             %2:fr32 = DIVSSrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VDIVSSrr %0, %1
+# AVX:                  %0:fr32 = COPY %xmm0
+# AVX-NEXT:             %1:fr32 = COPY %xmm1
+# AVX-NEXT:             %2:fr32 = VDIVSSrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VDIVSSZrr %0, %1
+# AVX512ALL:            %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr32x = VDIVSSZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
@@ -89,21 +89,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = DIVSDrr %0, %1
+# SSE:                  %0:fr64 = COPY %xmm0
+# SSE-NEXT:             %1:fr64 = COPY %xmm1
+# SSE-NEXT:             %2:fr64 = DIVSDrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VDIVSDrr %0, %1
+# AVX:                  %0:fr64 = COPY %xmm0
+# AVX-NEXT:             %1:fr64 = COPY %xmm1
+# AVX-NEXT:             %2:fr64 = VDIVSDrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VDIVSDZrr %0, %1
+# AVX512ALL:            %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr64x = VDIVSDZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
index 98e5d303d7b..ef4195d5d74 100644
--- a/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir
@@ -38,21 +38,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = MULSSrr %0, %1
+# SSE:                  %0:fr32 = COPY %xmm0
+# SSE-NEXT:             %1:fr32 = COPY %xmm1
+# SSE-NEXT:             %2:fr32 = MULSSrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VMULSSrr %0, %1
+# AVX:                  %0:fr32 = COPY %xmm0
+# AVX-NEXT:             %1:fr32 = COPY %xmm1
+# AVX-NEXT:             %2:fr32 = VMULSSrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VMULSSZrr %0, %1
+# AVX512ALL:            %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr32x = VMULSSZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
@@ -89,21 +89,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = MULSDrr %0, %1
+# SSE:                  %0:fr64 = COPY %xmm0
+# SSE-NEXT:             %1:fr64 = COPY %xmm1
+# SSE-NEXT:             %2:fr64 = MULSDrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VMULSDrr %0, %1
+# AVX:                  %0:fr64 = COPY %xmm0
+# AVX-NEXT:             %1:fr64 = COPY %xmm1
+# AVX-NEXT:             %2:fr64 = VMULSDrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VMULSDZrr %0, %1
+# AVX512ALL:            %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr64x = VMULSDZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
index 1cc9dda4877..00dfa6ae726 100644
--- a/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir
@@ -26,11 +26,8 @@ body:             |
     liveins: %xmm0
 
     ; ALL-LABEL: name: test
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: fr32
-    ; ALL-NEXT: id: 1, class: fr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; ALL: [[CVTSS2SDrr:%[0-9]+]] = CVTSS2SDrr [[COPY]]
+    ; ALL: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
+    ; ALL: [[CVTSS2SDrr:%[0-9]+]]:fr64 = CVTSS2SDrr [[COPY]]
     ; ALL: %xmm0 = COPY [[CVTSS2SDrr]]
     ; ALL: RET 0, implicit %xmm0
     %0(s32) = COPY %xmm0
diff --git a/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir b/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
index 9f58327d9bb..e72bf4bac19 100644
--- a/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir
@@ -38,21 +38,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = SUBSSrr %0, %1
+# SSE:                  %0:fr32 = COPY %xmm0
+# SSE-NEXT:             %1:fr32 = COPY %xmm1
+# SSE-NEXT:             %2:fr32 = SUBSSrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VSUBSSrr %0, %1
+# AVX:                  %0:fr32 = COPY %xmm0
+# AVX-NEXT:             %1:fr32 = COPY %xmm1
+# AVX-NEXT:             %2:fr32 = VSUBSSrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VSUBSSZrr %0, %1
+# AVX512ALL:            %0:fr32x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr32x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr32x = VSUBSSZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
@@ -89,21 +89,21 @@ liveins:
 fixedStack:
 stack:
 constants:
-# SSE:                  %0 = COPY %xmm0
-# SSE-NEXT:             %1 = COPY %xmm1
-# SSE-NEXT:             %2 = SUBSDrr %0, %1
+# SSE:                  %0:fr64 = COPY %xmm0
+# SSE-NEXT:             %1:fr64 = COPY %xmm1
+# SSE-NEXT:             %2:fr64 = SUBSDrr %0, %1
 # SSE-NEXT:             %xmm0 = COPY %2
 # SSE-NEXT:             RET 0, implicit %xmm0
 #
-# AVX:                  %0 = COPY %xmm0
-# AVX-NEXT:             %1 = COPY %xmm1
-# AVX-NEXT:             %2 = VSUBSDrr %0, %1
+# AVX:                  %0:fr64 = COPY %xmm0
+# AVX-NEXT:             %1:fr64 = COPY %xmm1
+# AVX-NEXT:             %2:fr64 = VSUBSDrr %0, %1
 # AVX-NEXT:             %xmm0 = COPY %2
 # AVX-NEXT:             RET 0, implicit %xmm0
 #
-# AVX512ALL:            %0 = COPY %xmm0
-# AVX512ALL-NEXT:       %1 = COPY %xmm1
-# AVX512ALL-NEXT:       %2 = VSUBSDZrr %0, %1
+# AVX512ALL:            %0:fr64x = COPY %xmm0
+# AVX512ALL-NEXT:       %1:fr64x = COPY %xmm1
+# AVX512ALL-NEXT:       %2:fr64x = VSUBSDZrr %0, %1
 # AVX512ALL-NEXT:       %xmm0 = COPY %2
 # AVX512ALL-NEXT:       RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-gep.mir b/test/CodeGen/X86/GlobalISel/select-gep.mir
index 440817b4e1c..e66b25afc14 100644
--- a/test/CodeGen/X86/GlobalISel/select-gep.mir
+++ b/test/CodeGen/X86/GlobalISel/select-gep.mir
@@ -22,13 +22,9 @@ body:             |
     liveins: %rdi
 
     ; CHECK-LABEL: name: test_gep_i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK-NEXT: id: 1, class: gr64_nosp
-    ; CHECK-NEXT: id: 2, class: gr64
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[MOV64ri32_:%[0-9]+]] = MOV64ri32 20
-    ; CHECK: [[LEA64r:%[0-9]+]] = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64_nosp = MOV64ri32 20
+    ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _
     ; CHECK: %rax = COPY [[LEA64r]]
     ; CHECK: RET 0, implicit %rax
     %0(p0) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-inc.mir b/test/CodeGen/X86/GlobalISel/select-inc.mir
index dc489335d6f..b2cfa4724b2 100644
--- a/test/CodeGen/X86/GlobalISel/select-inc.mir
+++ b/test/CodeGen/X86/GlobalISel/select-inc.mir
@@ -21,9 +21,9 @@ registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:      %0 = COPY %al
-# INC-NEXT: %2 = INC8r %0
-# ADD-NEXT: %2 = ADD8ri %0, 1
+# ALL:      %0:gr8 = COPY %al
+# INC-NEXT: %2:gr8 = INC8r %0
+# ADD-NEXT: %2:gr8 = ADD8ri %0, 1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %al
diff --git a/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir b/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
index 923dc22678f..744dfd6c820 100644
--- a/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
@@ -24,28 +24,19 @@ name:            test_insert_128_idx0
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX:           registers:
-# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:      registers:
-# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX:               %0 = COPY %ymm0
-# AVX-NEXT:          %1 = COPY %xmm1
-# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 0
+# AVX:               %0:vr256 = COPY %ymm0
+# AVX-NEXT:          %1:vr128 = COPY %xmm1
+# AVX-NEXT:          %2:vr256 = VINSERTF128rr %0, %1, 0
 # AVX-NEXT:          %ymm0 = COPY %2
 # AVX-NEXT:          RET 0, implicit %ymm0
 #
-# AVX512VL:          %0 = COPY %ymm0
-# AVX512VL-NEXT:     %1 = COPY %xmm1
-# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 0
+# AVX512VL:          %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT:     %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT:     %2:vr256x = VINSERTF32x4Z256rr %0, %1, 0
 # AVX512VL-NEXT:     %ymm0 = COPY %2
 # AVX512VL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -65,23 +56,19 @@ name:            test_insert_128_idx0_undef
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX:           registers:
-# AVX-NEXT:        - { id: 0, class: vecr, preferred-register: '' }
-# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:      registers:
-# AVX512VL-NEXT:   - { id: 0, class: vecr, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# ALL:               %1 = COPY %xmm1
-# ALL-NEXT:          undef %2.sub_xmm = COPY %1
-# ALL-NEXT:          %ymm0 = COPY %2
-# ALL-NEXT:          RET 0, implicit %ymm0
+# AVX:               %1:vr128 = COPY %xmm1
+# AVX-NEXT:          undef %2.sub_xmm:vr256 = COPY %1
+# AVX-NEXT:          %ymm0 = COPY %2
+# AVX-NEXT:          RET 0, implicit %ymm0
+#
+# AVX512VL:          %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT:     undef %2.sub_xmm:vr256x = COPY %1
+# AVX512VL-NEXT:     %ymm0 = COPY %2
+# AVX512VL-NEXT:     RET 0, implicit %ymm0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -99,28 +86,19 @@ name:            test_insert_128_idx1
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX:           registers:
-# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:      registers:
-# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX:               %0 = COPY %ymm0
-# AVX-NEXT:          %1 = COPY %xmm1
-# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 1
+# AVX:               %0:vr256 = COPY %ymm0
+# AVX-NEXT:          %1:vr128 = COPY %xmm1
+# AVX-NEXT:          %2:vr256 = VINSERTF128rr %0, %1, 1
 # AVX-NEXT:          %ymm0 = COPY %2
 # AVX-NEXT:          RET 0, implicit %ymm0
 #
-# AVX512VL:          %0 = COPY %ymm0
-# AVX512VL-NEXT:     %1 = COPY %xmm1
-# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL:          %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT:     %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT:     %2:vr256x = VINSERTF32x4Z256rr %0, %1, 1
 # AVX512VL-NEXT:     %ymm0 = COPY %2
 # AVX512VL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -139,28 +117,19 @@ name:            test_insert_128_idx1_undef
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX:           registers:
-# AVX-NEXT:        - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT:        - { id: 1, class: vr128, preferred-register: '' }
-# AVX-NEXT:        - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:      registers:
-# AVX512VL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX:               %0 = IMPLICIT_DEF
-# AVX-NEXT:          %1 = COPY %xmm1
-# AVX-NEXT:          %2 = VINSERTF128rr %0, %1, 1
+# AVX:               %0:vr256 = IMPLICIT_DEF
+# AVX-NEXT:          %1:vr128 = COPY %xmm1
+# AVX-NEXT:          %2:vr256 = VINSERTF128rr %0, %1, 1
 # AVX-NEXT:          %ymm0 = COPY %2
 # AVX-NEXT:          RET 0, implicit %ymm0
 #
-# AVX512VL:          %0 = IMPLICIT_DEF
-# AVX512VL-NEXT:     %1 = COPY %xmm1
-# AVX512VL-NEXT:     %2 = VINSERTF32x4Z256rr %0, %1, 1
+# AVX512VL:          %0:vr256x = IMPLICIT_DEF
+# AVX512VL-NEXT:     %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT:     %2:vr256x = VINSERTF32x4Z256rr %0, %1, 1
 # AVX512VL-NEXT:     %ymm0 = COPY %2
 # AVX512VL-NEXT:     RET 0, implicit %ymm0
 body:             |
@@ -173,4 +142,3 @@ body:             |
     %ymm0 = COPY %2(<8 x s32>)
     RET 0, implicit %ymm0
 ...
-
diff --git a/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir b/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
index aae03113ad2..45ed7289494 100644
--- a/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
@@ -49,13 +49,9 @@ body:             |
     liveins: %zmm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_128_idx0
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr128x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0
     ; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
@@ -79,12 +75,8 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_128_idx0_undef
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vecr
-    ; ALL-NEXT: id: 1, class: vr128x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
-    ; ALL: undef %2.sub_xmm = COPY [[COPY]]
+    ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm1
+    ; ALL: undef %2.sub_xmm:vr512 = COPY [[COPY]]
     ; ALL: %zmm0 = COPY %2
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = IMPLICIT_DEF
@@ -108,13 +100,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_128_idx1
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr128x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1
     ; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
@@ -137,13 +125,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_128_idx1_undef
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr128x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: [[COPY:%[0-9]+]] = COPY %xmm1
-    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
+    ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+    ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY %xmm1
+    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1
     ; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = IMPLICIT_DEF
@@ -166,13 +150,9 @@ body:             |
     liveins: %zmm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_256_idx0
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr256x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0
     ; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
@@ -196,12 +176,8 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_256_idx0_undef
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vecr
-    ; ALL-NEXT: id: 1, class: vr256x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
-    ; ALL: undef %2.sub_ymm = COPY [[COPY]]
+    ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY %ymm1
+    ; ALL: undef %2.sub_ymm:vr512 = COPY [[COPY]]
     ; ALL: %zmm0 = COPY %2
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = IMPLICIT_DEF
@@ -225,13 +201,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_256_idx1
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr256x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1
     ; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = COPY %zmm0
@@ -254,13 +226,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; ALL-LABEL: name: test_insert_256_idx1_undef
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr256x
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: [[COPY:%[0-9]+]] = COPY %ymm1
-    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
+    ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+    ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY %ymm1
+    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1
     ; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir b/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
index 77c11b12e23..596c48b4922 100644
--- a/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
+++ b/test/CodeGen/X86/GlobalISel/select-intrinsic-x86-flags-read-u32.mir
@@ -19,11 +19,8 @@ registers:
 body:             |
   bb.0:
     ; CHECK-LABEL: name: read_flags
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr64
-    ; CHECK: [[RDFLAGS32_:%[0-9]+]] = RDFLAGS32 implicit-def %esp, implicit %esp
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
+    ; CHECK: [[RDFLAGS32_:%[0-9]+]]:gr32 = RDFLAGS32 implicit-def %esp, implicit %esp
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[RDFLAGS32_]], 4
     ; CHECK: %rax = COPY [[SUBREG_TO_REG]]
     %0(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.x86.flags.read.u32)
     %rax = COPY %0(s32)
diff --git a/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir b/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
index f38b3b80f70..897f9a56a20 100644
--- a/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
+++ b/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir
@@ -33,9 +33,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
+    ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
     ; CHECK: %eax = COPY [[MOV32ri]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 1
@@ -52,9 +50,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1_optsize
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
+    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def %eflags
     ; CHECK: %eax = COPY [[MOV32r1_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 1
@@ -71,9 +67,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1b
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32ri:%[0-9]+]] = MOV32ri 1
+    ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
     ; CHECK: %eax = COPY [[MOV32ri]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 1
@@ -90,9 +84,7 @@ registers:
 body:             |
   bb.1 (%ir-block.0):
     ; CHECK-LABEL: name: const_i32_1_optsizeb
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK: [[MOV32r1_:%[0-9]+]] = MOV32r1 implicit-def %eflags
+    ; CHECK: [[MOV32r1_:%[0-9]+]]:gr32 = MOV32r1 implicit-def %eflags
     ; CHECK: %eax = COPY [[MOV32r1_]]
     ; CHECK: RET 0, implicit %eax
     %0(s32) = G_CONSTANT i32 1
diff --git a/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir b/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
index ce4e769d86a..0b7160d2bd9 100644
--- a/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
@@ -57,12 +57,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_load_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gpr
-    ; ALL-NEXT: id: 2, class: gr8
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1)
     ; ALL: %al = COPY [[MOV8rm]]
     ; ALL: RET 0, implicit %al
     %1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -86,12 +82,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_load_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gpr
-    ; ALL-NEXT: id: 2, class: gr16
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1)
     ; ALL: %ax = COPY [[MOV16rm]]
     ; ALL: RET 0, implicit %ax
     %1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -115,12 +107,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_load_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gpr
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1)
     ; ALL: %eax = COPY [[MOV32rm1]]
     ; ALL: RET 0, implicit %eax
     %1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -146,13 +134,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_store_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gpr
-    ; ALL-NEXT: id: 3, class: gpr
-    ; ALL: [[MOV8rm:%[0-9]+]] = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+    ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
     ; ALL: MOV8mr [[MOV32rm]], 1, _, 0, _, [[MOV8rm]] :: (store 1 into %ir.p1)
     ; ALL: %eax = COPY [[MOV32rm]]
     ; ALL: RET 0, implicit %eax
@@ -181,13 +164,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_store_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gpr
-    ; ALL-NEXT: id: 3, class: gpr
-    ; ALL: [[MOV16rm:%[0-9]+]] = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+    ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
     ; ALL: MOV16mr [[MOV32rm]], 1, _, 0, _, [[MOV16rm]] :: (store 2 into %ir.p1)
     ; ALL: %eax = COPY [[MOV32rm]]
     ; ALL: RET 0, implicit %eax
@@ -216,13 +194,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_store_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gpr
-    ; ALL-NEXT: id: 3, class: gpr
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
     ; ALL: MOV32mr [[MOV32rm1]], 1, _, 0, _, [[MOV32rm]] :: (store 4 into %ir.p1)
     ; ALL: %eax = COPY [[MOV32rm1]]
     ; ALL: RET 0, implicit %eax
@@ -249,12 +222,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_load_ptr
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gpr
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1)
     ; ALL: %eax = COPY [[MOV32rm1]]
     ; ALL: RET 0, implicit %eax
     %1(p0) = G_FRAME_INDEX %fixed-stack.0
@@ -280,13 +249,8 @@ fixedStack:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test_store_ptr
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gpr
-    ; ALL-NEXT: id: 3, class: gpr
-    ; ALL: [[MOV32rm:%[0-9]+]] = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-    ; ALL: [[MOV32rm1:%[0-9]+]] = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
+    ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
+    ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
     ; ALL: MOV32mr [[MOV32rm]], 1, _, 0, _, [[MOV32rm1]] :: (store 4 into %ir.ptr1)
     ; ALL: RET 0
     %2(p0) = G_FRAME_INDEX %fixed-stack.1
diff --git a/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
index de79aac9f30..6e85fb9ed9b 100644
--- a/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
@@ -109,8 +109,8 @@ registers:
 # ALL:   - { id: 1, class: gr8, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr8 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
 # ALL:     %al = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -133,8 +133,8 @@ registers:
 # ALL:   - { id: 1, class: gr16, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr16 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
 # ALL:     %ax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -157,8 +157,8 @@ registers:
 # ALL:   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %eax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -181,8 +181,8 @@ registers:
 # ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -205,8 +205,8 @@ registers:
 # ALL:   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -225,15 +225,12 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: fr32, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: fr32x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# ALL:       %0 = COPY %rdi
-# SSE:       %1 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX:       %1 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX512ALL: %1 = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# ALL:       %0:gr64 = COPY %rdi
+# SSE:       %1:fr32 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# AVX:       %1:fr32 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
+# AVX512ALL: %1:fr32x = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -256,8 +253,8 @@ registers:
 # ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -276,15 +273,12 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: fr64, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: fr64x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# ALL:       %0 = COPY %rdi
-# SSE:       %1 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX:       %1 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX512ALL: %1 = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# ALL:       %0:gr64 = COPY %rdi
+# SSE:       %1:fr64 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# AVX:       %1:fr64 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
+# AVX512ALL: %1:fr64x = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -307,8 +301,8 @@ registers:
 # ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %edi
-# ALL:     %1 = COPY %rsi
+# ALL:     %0:gr32 = COPY %edi
+# ALL:     %1:gr64 = COPY %rsi
 # ALL:     MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
@@ -333,8 +327,8 @@ registers:
 # ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL:     %0 = COPY %rdi
-# ALL:     %1 = COPY %rsi
+# ALL:     %0:gr64 = COPY %rdi
+# ALL:     %1:gr64 = COPY %rsi
 # ALL:     MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
@@ -354,22 +348,14 @@ name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 2, class: gr32, preferred-register: '' }
-#
-# AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:     %0 = COPY %xmm0
-# ALL:     %1 = COPY %rdi
-# ALL:     %2 = COPY %0
+# NO_AVX512F: %0:fr32 = COPY %xmm0
+# AVX512ALL:  %0:fr32x = COPY %xmm0
+# ALL:     %1:gr64 = COPY %rdi
+# ALL:     %2:gr32 = COPY %0
 # ALL:     MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
@@ -391,13 +377,11 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr32, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: fr32x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# ALL:       %0 = COPY %xmm0
-# ALL:       %1 = COPY %rdi
+# NO_AVX512F: %0:fr32 = COPY %xmm0
+# AVX512ALL:  %0:fr32x = COPY %xmm0
+# ALL:       %1:gr64 = COPY %rdi
 # SSE:       MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX:       VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
@@ -419,22 +403,14 @@ name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 2, class: gr64, preferred-register: '' }
-#
-# AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:     %0 = COPY %xmm0
-# ALL:     %1 = COPY %rdi
-# ALL:     %2 = COPY %0
+# NO_AVX512X: %0:fr64 = COPY %xmm0
+# AVX512ALL:  %0:fr64x = COPY %xmm0
+# ALL:     %1:gr64 = COPY %rdi
+# ALL:     %2:gr64 = COPY %0
 # ALL:     MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
@@ -456,13 +432,11 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr64, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: fr64x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# ALL:       %0 = COPY %xmm0
-# ALL:       %1 = COPY %rdi
+# NO_AVX512F: %0:fr64 = COPY %xmm0
+# AVX512ALL:  %0:fr64x = COPY %xmm0
+# ALL:       %1:gr64 = COPY %rdi
 # SSE:       MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX:       VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
@@ -490,7 +464,7 @@ registers:
 # ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
+# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
@@ -542,10 +516,10 @@ registers:
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
-# ALL:                  %0 = COPY %rdi
-# ALL-NEXT:             %1 = COPY %esi
+# ALL:                  %0:gr64 = COPY %rdi
+# ALL-NEXT:             %1:gr32 = COPY %esi
 # ALL-NEXT:             MOV32mr %0, 1, _, 20, _, %1 :: (store 4 into %ir.arrayidx)
-# ALL-NEXT:             %4 = MOV32rm %0, 1, _, 20, _ :: (load 4 from %ir.arrayidx)
+# ALL-NEXT:             %4:gr32 = MOV32rm %0, 1, _, 20, _ :: (load 4 from %ir.arrayidx)
 # ALL-NEXT:             %eax = COPY %4
 # ALL-NEXT:             RET 0, implicit %eax
 body:             |
@@ -580,12 +554,12 @@ registers:
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
-# ALL:                  %0 = COPY %rdi
-# ALL-NEXT:             %1 = COPY %esi
-# ALL-NEXT:             %2 = MOV64ri 228719476720
-# ALL-NEXT:             %3 = LEA64r %0, 1, %2, 0, _
+# ALL:                  %0:gr64 = COPY %rdi
+# ALL-NEXT:             %1:gr32 = COPY %esi
+# ALL-NEXT:             %2:gr64_nosp = MOV64ri 228719476720
+# ALL-NEXT:             %3:gr64 = LEA64r %0, 1, %2, 0, _
 # ALL-NEXT:             MOV32mr %3, 1, _, 0, _, %1 :: (store 4 into %ir.arrayidx)
-# ALL-NEXT:             %4 = MOV32rm %3, 1, _, 0, _ :: (load 4 from %ir.arrayidx)
+# ALL-NEXT:             %4:gr32 = MOV32rm %3, 1, _, 0, _ :: (load 4 from %ir.arrayidx)
 # ALL-NEXT:             %eax = COPY %4
 # ALL-NEXT:             RET 0, implicit %eax
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-memop-v128.mir b/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
index 08844657e2a..4edab36b57c 100644
--- a/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
@@ -32,16 +32,13 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# ALL:      %0 = COPY %rdi
-# SSE:      %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX:      %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512F:  %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# ALL:      %0:gr64 = COPY %rdi
+# SSE:      %1:vr128 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX:      %1:vr128 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512F:  %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -60,16 +57,13 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# ALL:      %0 = COPY %rdi
-# SSE:      %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX:      %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512F:  %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# ALL:      %0:gr64 = COPY %rdi
+# SSE:      %1:vr128 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX:      %1:vr128 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512F:  %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
@@ -88,13 +82,11 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# ALL:       %0 = COPY %xmm0
-# ALL:       %1 = COPY %rdi
+# NO_AVX512F: %0:vr128 = COPY %xmm0
+# AVX512ALL:  %0:vr128x = COPY %xmm0
+# ALL:       %1:gr64 = COPY %rdi
 # SSE:       MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX:       VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX512F:   VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
@@ -118,13 +110,11 @@ alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# ALL:       %0 = COPY %xmm0
-# ALL:       %1 = COPY %rdi
+# NO_AVX512F: %0:vr128 = COPY %xmm0
+# AVX512ALL:  %0:vr128x = COPY %xmm0
+# ALL:       %1:gr64 = COPY %rdi
 # SSE:       MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX:       VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX512F:   VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
diff --git a/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
index ff371ad9989..86310d25760 100644
--- a/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
@@ -42,18 +42,18 @@ regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# NO_AVX512F:           %0 = COPY %rdi
-# NO_AVX512F-NEXT:      %1 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# NO_AVX512F:           %0:gr64 = COPY %rdi
+# NO_AVX512F-NEXT:      %1:vr256 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #
-# AVX512F:              %0 = COPY %rdi
-# AVX512F-NEXT:         %1 = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# AVX512F:              %0:gr64 = COPY %rdi
+# AVX512F-NEXT:         %1:vr256x = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
 # AVX512F-NEXT:         %ymm0 = COPY %1
 # AVX512F-NEXT:         RET 0, implicit %ymm0
 #
-# AVX512VL:             %0 = COPY %rdi
-# AVX512VL-NEXT:        %1 = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
+# AVX512VL:             %0:gr64 = COPY %rdi
+# AVX512VL-NEXT:        %1:vr256x = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
 # AVX512VL-NEXT:        %ymm0 = COPY %1
 # AVX512VL-NEXT:        RET 0, implicit %ymm0
 body:             |
@@ -72,28 +72,21 @@ name:            test_load_v8i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: '' }
-#
-# AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
-# NO_AVX512F:           %0 = COPY %rdi
-# NO_AVX512F-NEXT:      %1 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# NO_AVX512F:           %0:gr64 = COPY %rdi
+# NO_AVX512F-NEXT:      %1:vr256 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #
-# AVX512F:              %0 = COPY %rdi
-# AVX512F-NEXT:         %1 = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# AVX512F:              %0:gr64 = COPY %rdi
+# AVX512F-NEXT:         %1:vr256x = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1)
 # AVX512F-NEXT:         %ymm0 = COPY %1
 # AVX512F-NEXT:         RET 0, implicit %ymm0
 #
-# AVX512VL:             %0 = COPY %rdi
-# AVX512VL-NEXT:        %1 = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
+# AVX512VL:             %0:gr64 = COPY %rdi
+# AVX512VL-NEXT:        %1:vr256x = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
 # AVX512VL-NEXT:        %ymm0 = COPY %1
 # AVX512VL-NEXT:        RET 0, implicit %ymm0
 body:             |
@@ -122,18 +115,18 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# NO_AVX512F:           %0 = COPY %ymm0
-# NO_AVX512F-NEXT:      %1 = COPY %rdi
+# NO_AVX512F:           %0:vr256 = COPY %ymm0
+# NO_AVX512F-NEXT:      %1:gr64 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
 # NO_AVX512F-NEXT:      RET 0
 #
-# AVX512F:              %0 = COPY %ymm0
-# AVX512F-NEXT:         %1 = COPY %rdi
+# AVX512F:              %0:vr256x = COPY %ymm0
+# AVX512F-NEXT:         %1:gr64 = COPY %rdi
 # AVX512F-NEXT:         VMOVUPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
 # AVX512F-NEXT:         RET 0
 #
-# AVX512VL:             %0 = COPY %ymm0
-# AVX512VL-NEXT:        %1 = COPY %rdi
+# AVX512VL:             %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT:        %1:gr64 = COPY %rdi
 # AVX512VL-NEXT:        VMOVUPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
 # AVX512VL-NEXT:        RET 0
 body:             |
@@ -162,18 +155,18 @@ regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
-# NO_AVX512F:           %0 = COPY %ymm0
-# NO_AVX512F-NEXT:      %1 = COPY %rdi
+# NO_AVX512F:           %0:vr256 = COPY %ymm0
+# NO_AVX512F-NEXT:      %1:gr64 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
 # NO_AVX512F-NEXT:      RET 0
 #
-# AVX512F:              %0 = COPY %ymm0
-# AVX512F-NEXT:         %1 = COPY %rdi
+# AVX512F:              %0:vr256x = COPY %ymm0
+# AVX512F-NEXT:         %1:gr64 = COPY %rdi
 # AVX512F-NEXT:         VMOVAPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
 # AVX512F-NEXT:         RET 0
 #
-# AVX512VL:             %0 = COPY %ymm0
-# AVX512VL-NEXT:        %1 = COPY %rdi
+# AVX512VL:             %0:vr256x = COPY %ymm0
+# AVX512VL-NEXT:        %1:gr64 = COPY %rdi
 # AVX512VL-NEXT:        VMOVAPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
 # AVX512VL-NEXT:        RET 0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-memop-v512.mir b/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
index 8d216418c9c..e1b25903f06 100644
--- a/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-memop-v512.mir
@@ -35,11 +35,8 @@ body:             |
     liveins: %rdi
 
     ; AVX512F-LABEL: name: test_load_v16i32_noalign
-    ; AVX512F: registers:
-    ; AVX512F-NEXT: id: 0, class: gr64
-    ; AVX512F-NEXT: id: 1, class: vr512
-    ; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
-    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
+    ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
     ; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
     ; AVX512F: RET 0, implicit %zmm0
     %0(p0) = COPY %rdi
@@ -61,11 +58,8 @@ body:             |
     liveins: %rdi
 
     ; AVX512F-LABEL: name: test_load_v16i32_align
-    ; AVX512F: registers:
-    ; AVX512F-NEXT: id: 0, class: gr64
-    ; AVX512F-NEXT: id: 1, class: vr512
-    ; AVX512F: [[COPY:%[0-9]+]] = COPY %rdi
-    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]] = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
+    ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
     ; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
     ; AVX512F: RET 0, implicit %zmm0
     %0(p0) = COPY %rdi
@@ -87,11 +81,8 @@ body:             |
     liveins: %rdi, %zmm0
 
     ; AVX512F-LABEL: name: test_store_v16i32_noalign
-    ; AVX512F: registers:
-    ; AVX512F-NEXT: id: 0, class: vr512
-    ; AVX512F-NEXT: id: 1, class: gr64
-    ; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
+    ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
     ; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 1)
     ; AVX512F: RET 0
     %0(<16 x s32>) = COPY %zmm0
@@ -113,11 +104,8 @@ body:             |
     liveins: %rdi, %zmm0
 
     ; AVX512F-LABEL: name: test_store_v16i32_align
-    ; AVX512F: registers:
-    ; AVX512F-NEXT: id: 0, class: vr512
-    ; AVX512F-NEXT: id: 1, class: gr64
-    ; AVX512F: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; AVX512F: [[COPY1:%[0-9]+]] = COPY %rdi
+    ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
     ; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 32)
     ; AVX512F: RET 0
     %0(<16 x s32>) = COPY %zmm0
diff --git a/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir b/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
index 87ea38dd16f..0dfb678479f 100644
--- a/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
@@ -21,27 +21,17 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; AVX-LABEL: name: test_merge
-    ; AVX: registers:
-    ; AVX-NEXT: id: 0, class: vr128
-    ; AVX-NEXT: id: 1, class: vr256
-    ; AVX-NEXT: id: 2, class: vr256
-    ; AVX-NEXT: id: 3, class: vr256
-    ; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; AVX: undef %2.sub_xmm = COPY [[DEF]]
-    ; AVX: [[VINSERTF128rr:%[0-9]+]] = VINSERTF128rr %2, [[DEF]], 1
-    ; AVX: [[COPY:%[0-9]+]] = COPY [[VINSERTF128rr]]
+    ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
+    ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
+    ; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
+    ; AVX: [[COPY:%[0-9]+]]:vr256 = COPY [[VINSERTF128rr]]
     ; AVX: %ymm0 = COPY [[COPY]]
     ; AVX: RET 0, implicit %ymm0
     ; AVX512VL-LABEL: name: test_merge
-    ; AVX512VL: registers:
-    ; AVX512VL-NEXT: id: 0, class: vr128x
-    ; AVX512VL-NEXT: id: 1, class: vr256x
-    ; AVX512VL-NEXT: id: 2, class: vr256x
-    ; AVX512VL-NEXT: id: 3, class: vr256x
-    ; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; AVX512VL: undef %2.sub_xmm = COPY [[DEF]]
-    ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]] = VINSERTF32x4Z256rr %2, [[DEF]], 1
-    ; AVX512VL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Z256rr]]
+    ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
+    ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
+    ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
+    ; AVX512VL: [[COPY:%[0-9]+]]:vr256x = COPY [[VINSERTF32x4Z256rr]]
     ; AVX512VL: %ymm0 = COPY [[COPY]]
     ; AVX512VL: RET 0, implicit %ymm0
     %0(<4 x s32>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir b/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
index 0cddb35ca40..5de38e4ce1f 100644
--- a/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
@@ -22,19 +22,12 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_merge_v128
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr128x
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL-NEXT: id: 3, class: vr512
-    ; ALL-NEXT: id: 4, class: vr512
-    ; ALL-NEXT: id: 5, class: vr512
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: undef %2.sub_xmm = COPY [[DEF]]
-    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]] = VINSERTF32x4Zrr %2, [[DEF]], 1
-    ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
-    ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]] = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
-    ; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF32x4Zrr2]]
+    ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
+    ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
+    ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
+    ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
+    ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF32x4Zrr2]]
     ; ALL: %zmm0 = COPY [[COPY]]
     ; ALL: RET 0, implicit %zmm0
     %0(<4 x s32>) = IMPLICIT_DEF
@@ -55,15 +48,10 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_merge_v256
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr256x
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL-NEXT: id: 3, class: vr512
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: undef %2.sub_ymm = COPY [[DEF]]
-    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]] = VINSERTF64x4Zrr %2, [[DEF]], 1
-    ; ALL: [[COPY:%[0-9]+]] = COPY [[VINSERTF64x4Zrr]]
+    ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
+    ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
+    ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF64x4Zrr]]
     ; ALL: %zmm0 = COPY [[COPY]]
     ; ALL: RET 0, implicit %zmm0
     %0(<8 x s32>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir b/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
index 58f830be960..f0766ff7eb5 100644
--- a/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
@@ -32,13 +32,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_mul_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr16
-    ; ALL-NEXT: id: 2, class: gr16
-    ; ALL: [[COPY:%[0-9]+]] = COPY %di
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %si
-    ; ALL: [[IMUL16rr:%[0-9]+]] = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+    ; ALL: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %ax = COPY [[IMUL16rr]]
     ; ALL: RET 0, implicit %ax
     %0(s16) = COPY %di
@@ -62,13 +58,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_mul_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[COPY:%[0-9]+]] = COPY %edi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
-    ; ALL: [[IMUL32rr:%[0-9]+]] = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+    ; ALL: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %eax = COPY [[IMUL32rr]]
     ; ALL: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -92,13 +84,9 @@ body:             |
     liveins: %rdi, %rsi
 
     ; ALL-LABEL: name: test_mul_i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
-    ; ALL: [[IMUL64rr:%[0-9]+]] = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+    ; ALL: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %rax = COPY [[IMUL64rr]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-mul-vec.mir b/test/CodeGen/X86/GlobalISel/select-mul-vec.mir
index d00aa015152..afc40815af0 100644
--- a/test/CodeGen/X86/GlobalISel/select-mul-vec.mir
+++ b/test/CodeGen/X86/GlobalISel/select-mul-vec.mir
@@ -103,13 +103,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v8i16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128
-    ; CHECK-NEXT: id: 1, class: vr128
-    ; CHECK-NEXT: id: 2, class: vr128
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[PMULLWrr:%[0-9]+]] = PMULLWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+    ; CHECK: [[PMULLWrr:%[0-9]+]]:vr128 = PMULLWrr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[PMULLWrr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<8 x s16>) = COPY %xmm0
@@ -133,13 +129,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v8i16_avx
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128
-    ; CHECK-NEXT: id: 1, class: vr128
-    ; CHECK-NEXT: id: 2, class: vr128
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[VPMULLWrr:%[0-9]+]] = VPMULLWrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+    ; CHECK: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[VPMULLWrr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<8 x s16>) = COPY %xmm0
@@ -163,13 +155,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v8i16_avx512bwvl
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128x
-    ; CHECK-NEXT: id: 1, class: vr128x
-    ; CHECK-NEXT: id: 2, class: vr128x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[VPMULLWZ128rr:%[0-9]+]] = VPMULLWZ128rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+    ; CHECK: [[VPMULLWZ128rr:%[0-9]+]]:vr128x = VPMULLWZ128rr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[VPMULLWZ128rr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<8 x s16>) = COPY %xmm0
@@ -193,13 +181,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v4i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128
-    ; CHECK-NEXT: id: 1, class: vr128
-    ; CHECK-NEXT: id: 2, class: vr128
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[PMULLDrr:%[0-9]+]] = PMULLDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+    ; CHECK: [[PMULLDrr:%[0-9]+]]:vr128 = PMULLDrr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[PMULLDrr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<4 x s32>) = COPY %xmm0
@@ -223,13 +207,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v4i32_avx
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128
-    ; CHECK-NEXT: id: 1, class: vr128
-    ; CHECK-NEXT: id: 2, class: vr128
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[VPMULLDrr:%[0-9]+]] = VPMULLDrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY %xmm1
+    ; CHECK: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[VPMULLDrr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<4 x s32>) = COPY %xmm0
@@ -253,13 +233,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v4i32_avx512vl
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128x
-    ; CHECK-NEXT: id: 1, class: vr128x
-    ; CHECK-NEXT: id: 2, class: vr128x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[VPMULLDZ128rr:%[0-9]+]] = VPMULLDZ128rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+    ; CHECK: [[VPMULLDZ128rr:%[0-9]+]]:vr128x = VPMULLDZ128rr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[VPMULLDZ128rr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<4 x s32>) = COPY %xmm0
@@ -283,13 +259,9 @@ body:             |
     liveins: %xmm0, %xmm1
 
     ; CHECK-LABEL: name: test_mul_v2i64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr128x
-    ; CHECK-NEXT: id: 1, class: vr128x
-    ; CHECK-NEXT: id: 2, class: vr128x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %xmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %xmm1
-    ; CHECK: [[VPMULLQZ128rr:%[0-9]+]] = VPMULLQZ128rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY %xmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY %xmm1
+    ; CHECK: [[VPMULLQZ128rr:%[0-9]+]]:vr128x = VPMULLQZ128rr [[COPY]], [[COPY1]]
     ; CHECK: %xmm0 = COPY [[VPMULLQZ128rr]]
     ; CHECK: RET 0, implicit %xmm0
     %0(<2 x s64>) = COPY %xmm0
@@ -313,13 +285,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; CHECK-LABEL: name: test_mul_v16i16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr256
-    ; CHECK-NEXT: id: 1, class: vr256
-    ; CHECK-NEXT: id: 2, class: vr256
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; CHECK: [[VPMULLWYrr:%[0-9]+]] = VPMULLWYrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY %ymm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY %ymm1
+    ; CHECK: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY]], [[COPY1]]
     ; CHECK: %ymm0 = COPY [[VPMULLWYrr]]
     ; CHECK: RET 0, implicit %ymm0
     %0(<16 x s16>) = COPY %ymm0
@@ -343,13 +311,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; CHECK-LABEL: name: test_mul_v16i16_avx512bwvl
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr256x
-    ; CHECK-NEXT: id: 1, class: vr256x
-    ; CHECK-NEXT: id: 2, class: vr256x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; CHECK: [[VPMULLWZ256rr:%[0-9]+]] = VPMULLWZ256rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+    ; CHECK: [[VPMULLWZ256rr:%[0-9]+]]:vr256x = VPMULLWZ256rr [[COPY]], [[COPY1]]
     ; CHECK: %ymm0 = COPY [[VPMULLWZ256rr]]
     ; CHECK: RET 0, implicit %ymm0
     %0(<16 x s16>) = COPY %ymm0
@@ -373,13 +337,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; CHECK-LABEL: name: test_mul_v8i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr256
-    ; CHECK-NEXT: id: 1, class: vr256
-    ; CHECK-NEXT: id: 2, class: vr256
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; CHECK: [[VPMULLDYrr:%[0-9]+]] = VPMULLDYrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY %ymm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY %ymm1
+    ; CHECK: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY]], [[COPY1]]
     ; CHECK: %ymm0 = COPY [[VPMULLDYrr]]
     ; CHECK: RET 0, implicit %ymm0
     %0(<8 x s32>) = COPY %ymm0
@@ -403,13 +363,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; CHECK-LABEL: name: test_mul_v8i32_avx512vl
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr256x
-    ; CHECK-NEXT: id: 1, class: vr256x
-    ; CHECK-NEXT: id: 2, class: vr256x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; CHECK: [[VPMULLDZ256rr:%[0-9]+]] = VPMULLDZ256rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+    ; CHECK: [[VPMULLDZ256rr:%[0-9]+]]:vr256x = VPMULLDZ256rr [[COPY]], [[COPY1]]
     ; CHECK: %ymm0 = COPY [[VPMULLDZ256rr]]
     ; CHECK: RET 0, implicit %ymm0
     %0(<8 x s32>) = COPY %ymm0
@@ -433,13 +389,9 @@ body:             |
     liveins: %ymm0, %ymm1
 
     ; CHECK-LABEL: name: test_mul_v4i64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr256x
-    ; CHECK-NEXT: id: 1, class: vr256x
-    ; CHECK-NEXT: id: 2, class: vr256x
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %ymm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %ymm1
-    ; CHECK: [[VPMULLQZ256rr:%[0-9]+]] = VPMULLQZ256rr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY %ymm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY %ymm1
+    ; CHECK: [[VPMULLQZ256rr:%[0-9]+]]:vr256x = VPMULLQZ256rr [[COPY]], [[COPY1]]
     ; CHECK: %ymm0 = COPY [[VPMULLQZ256rr]]
     ; CHECK: RET 0, implicit %ymm0
     %0(<4 x s64>) = COPY %ymm0
@@ -463,13 +415,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; CHECK-LABEL: name: test_mul_v32i16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr512
-    ; CHECK-NEXT: id: 1, class: vr512
-    ; CHECK-NEXT: id: 2, class: vr512
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; CHECK: [[VPMULLWZrr:%[0-9]+]] = VPMULLWZrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; CHECK: [[VPMULLWZrr:%[0-9]+]]:vr512 = VPMULLWZrr [[COPY]], [[COPY1]]
     ; CHECK: %zmm0 = COPY [[VPMULLWZrr]]
     ; CHECK: RET 0, implicit %zmm0
     %0(<32 x s16>) = COPY %zmm0
@@ -493,13 +441,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; CHECK-LABEL: name: test_mul_v16i32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr512
-    ; CHECK-NEXT: id: 1, class: vr512
-    ; CHECK-NEXT: id: 2, class: vr512
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; CHECK: [[VPMULLDZrr:%[0-9]+]] = VPMULLDZrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; CHECK: [[VPMULLDZrr:%[0-9]+]]:vr512 = VPMULLDZrr [[COPY]], [[COPY1]]
     ; CHECK: %zmm0 = COPY [[VPMULLDZrr]]
     ; CHECK: RET 0, implicit %zmm0
     %0(<16 x s32>) = COPY %zmm0
@@ -523,13 +467,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; CHECK-LABEL: name: test_mul_v8i64
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: vr512
-    ; CHECK-NEXT: id: 1, class: vr512
-    ; CHECK-NEXT: id: 2, class: vr512
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; CHECK: [[VPMULLQZrr:%[0-9]+]] = VPMULLQZrr [[COPY]], [[COPY1]]
+    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; CHECK: [[VPMULLQZrr:%[0-9]+]]:vr512 = VPMULLQZrr [[COPY]], [[COPY1]]
     ; CHECK: %zmm0 = COPY [[VPMULLQZrr]]
     ; CHECK: RET 0, implicit %zmm0
     %0(<8 x s64>) = COPY %zmm0
diff --git a/test/CodeGen/X86/GlobalISel/select-or-scalar.mir b/test/CodeGen/X86/GlobalISel/select-or-scalar.mir
index bbd877d21fb..21c6ed50d3b 100644
--- a/test/CodeGen/X86/GlobalISel/select-or-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-or-scalar.mir
@@ -41,13 +41,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_or_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr8
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %sil
-    ; ALL: [[OR8rr:%[0-9]+]] = OR8rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
+    ; ALL: [[OR8rr:%[0-9]+]]:gr8 = OR8rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %al = COPY [[OR8rr]]
     ; ALL: RET 0, implicit %al
     %0(s8) = COPY %dil
@@ -75,13 +71,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_or_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr16
-    ; ALL-NEXT: id: 2, class: gr16
-    ; ALL: [[COPY:%[0-9]+]] = COPY %di
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %si
-    ; ALL: [[OR16rr:%[0-9]+]] = OR16rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+    ; ALL: [[OR16rr:%[0-9]+]]:gr16 = OR16rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %ax = COPY [[OR16rr]]
     ; ALL: RET 0, implicit %ax
     %0(s16) = COPY %di
@@ -109,13 +101,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_or_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[COPY:%[0-9]+]] = COPY %edi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
-    ; ALL: [[OR32rr:%[0-9]+]] = OR32rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+    ; ALL: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %eax = COPY [[OR32rr]]
     ; ALL: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -143,13 +131,9 @@ body:             |
     liveins: %rdi, %rsi
 
     ; ALL-LABEL: name: test_or_i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
-    ; ALL: [[OR64rr:%[0-9]+]] = OR64rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+    ; ALL: [[OR64rr:%[0-9]+]]:gr64 = OR64rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %rax = COPY [[OR64rr]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-phi.mir b/test/CodeGen/X86/GlobalISel/select-phi.mir
index 4715c29b6f6..f92ba0d71c2 100644
--- a/test/CodeGen/X86/GlobalISel/select-phi.mir
+++ b/test/CodeGen/X86/GlobalISel/select-phi.mir
@@ -121,7 +121,7 @@ registers:
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:gr8 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %al = COPY %5
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
@@ -174,7 +174,7 @@ registers:
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:gr16 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %ax = COPY %5
 # ALL-NEXT:     RET 0, implicit %ax
 body:             |
@@ -227,7 +227,7 @@ registers:
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:gr32 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %eax = COPY %5
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
@@ -280,7 +280,7 @@ registers:
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:gr64 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %rax = COPY %5
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |
@@ -337,7 +337,7 @@ fixedStack:
 stack:
 constants:
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:fr32 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %xmm0 = COPY %5
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
@@ -390,7 +390,7 @@ registers:
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: vecr, preferred-register: '' }
 # ALL-LABEL: bb.3.cond.end:
-# ALL:          %5 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
+# ALL:          %5:fr64 = PHI %1, %bb.1.cond.true, %2, %bb.2.cond.false
 # ALL-NEXT:     %xmm0 = COPY %5
 # ALL-NEXT:     RET 0, implicit %xmm0
 body:             |
diff --git a/test/CodeGen/X86/GlobalISel/select-sub-v128.mir b/test/CodeGen/X86/GlobalISel/select-sub-v128.mir
index f77879d9300..bb050075194 100644
--- a/test/CodeGen/X86/GlobalISel/select-sub-v128.mir
+++ b/test/CodeGen/X86/GlobalISel/select-sub-v128.mir
@@ -31,31 +31,17 @@ name:            test_sub_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PSUBBrr %0, %1
+# SSE2:                %2:vr128 = PSUBBrr %0, %1
 #
-# AVX1:                %2 = VPSUBBrr %0, %1
+# AVX1:                %2:vr128 = VPSUBBrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBBrr %0, %1
+# AVX512VL:            %2:vr128 = VPSUBBrr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBBZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPSUBBZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -73,31 +59,17 @@ name:            test_sub_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PSUBWrr %0, %1
+# SSE2:                %2:vr128 = PSUBWrr %0, %1
 #
-# AVX1:                %2 = VPSUBWrr %0, %1
+# AVX1:                %2:vr128 = VPSUBWrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBWrr %0, %1
+# AVX512VL:            %2:vr128 = VPSUBWrr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBWZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPSUBWZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -115,31 +87,17 @@ name:            test_sub_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PSUBDrr %0, %1
+# SSE2:                %2:vr128 = PSUBDrr %0, %1
 #
-# AVX1:                %2 = VPSUBDrr %0, %1
+# AVX1:                %2:vr128 = VPSUBDrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBDZ128rr %0, %1
+# AVX512VL:            %2:vr128x = VPSUBDZ128rr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBDZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPSUBDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -157,31 +115,17 @@ name:            test_sub_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
-# NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# SSE2:                %2 = PSUBQrr %0, %1
+# SSE2:                %2:vr128 = PSUBQrr %0, %1
 #
-# AVX1:                %2 = VPSUBQrr %0, %1
+# AVX1:                %2:vr128 = VPSUBQrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBQZ128rr %0, %1
+# AVX512VL:            %2:vr128x = VPSUBQZ128rr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBQZ128rr %0, %1
+# AVX512BWVL:          %2:vr128x = VPSUBQZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
diff --git a/test/CodeGen/X86/GlobalISel/select-sub-v256.mir b/test/CodeGen/X86/GlobalISel/select-sub-v256.mir
index d6bde7fbb69..614d13169f3 100644
--- a/test/CodeGen/X86/GlobalISel/select-sub-v256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-sub-v256.mir
@@ -29,29 +29,15 @@ name:            test_sub_v32i8
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPSUBBYrr %0, %1
+# AVX2:                %2:vr256 = VPSUBBYrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBBYrr %0, %1
+# AVX512VL:            %2:vr256 = VPSUBBYrr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBBZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPSUBBZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -69,29 +55,15 @@ name:            test_sub_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPSUBWYrr %0, %1
+# AVX2:                %2:vr256 = VPSUBWYrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBWYrr %0, %1
+# AVX512VL:            %2:vr256 = VPSUBWYrr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBWZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPSUBWZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -109,29 +81,15 @@ name:            test_sub_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPSUBDYrr %0, %1
+# AVX2:                %2:vr256 = VPSUBDYrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBDZ256rr %0, %1
+# AVX512VL:            %2:vr256x = VPSUBDZ256rr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBDZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPSUBDZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
@@ -149,29 +107,15 @@ name:            test_sub_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
-# AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
-#
-# AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
-#
-# AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# AVX2:                %2 = VPSUBQYrr %0, %1
+# AVX2:                %2:vr256 = VPSUBQYrr %0, %1
 #
-# AVX512VL:            %2 = VPSUBQZ256rr %0, %1
+# AVX512VL:            %2:vr256x = VPSUBQZ256rr %0, %1
 #
-# AVX512BWVL:          %2 = VPSUBQZ256rr %0, %1
+# AVX512BWVL:          %2:vr256x = VPSUBQZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
diff --git a/test/CodeGen/X86/GlobalISel/select-sub-v512.mir b/test/CodeGen/X86/GlobalISel/select-sub-v512.mir
index b32910ce725..67949219ba4 100644
--- a/test/CodeGen/X86/GlobalISel/select-sub-v512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-sub-v512.mir
@@ -39,13 +39,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v64i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPSUBBZrr:%[0-9]+]] = VPSUBBZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPSUBBZrr:%[0-9]+]]:vr512 = VPSUBBZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPSUBBZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<64 x s8>) = COPY %zmm0
@@ -69,13 +65,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v32i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPSUBWZrr:%[0-9]+]] = VPSUBWZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPSUBWZrr:%[0-9]+]]:vr512 = VPSUBWZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPSUBWZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<32 x s16>) = COPY %zmm0
@@ -99,13 +91,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v16i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPSUBDZrr:%[0-9]+]] = VPSUBDZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPSUBDZrr:%[0-9]+]]:vr512 = VPSUBDZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPSUBDZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<16 x s32>) = COPY %zmm0
@@ -129,13 +117,9 @@ body:             |
     liveins: %zmm0, %zmm1
 
     ; ALL-LABEL: name: test_sub_v8i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr512
-    ; ALL-NEXT: id: 2, class: vr512
-    ; ALL: [[COPY:%[0-9]+]] = COPY %zmm0
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %zmm1
-    ; ALL: [[VPSUBQZrr:%[0-9]+]] = VPSUBQZrr [[COPY]], [[COPY1]]
+    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
+    ; ALL: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm1
+    ; ALL: [[VPSUBQZrr:%[0-9]+]]:vr512 = VPSUBQZrr [[COPY]], [[COPY1]]
     ; ALL: %zmm0 = COPY [[VPSUBQZrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<8 x s64>) = COPY %zmm0
diff --git a/test/CodeGen/X86/GlobalISel/select-sub.mir b/test/CodeGen/X86/GlobalISel/select-sub.mir
index 971b5468079..d2f99d12ae5 100644
--- a/test/CodeGen/X86/GlobalISel/select-sub.mir
+++ b/test/CodeGen/X86/GlobalISel/select-sub.mir
@@ -29,17 +29,13 @@
 name:            test_sub_i64
 legalized:       true
 regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:      %0 = COPY %rdi
-# ALL-NEXT: %1 = COPY %rsi
-# ALL-NEXT: %2 = SUB64rr %0, %1
+# ALL:      %0:gr64 = COPY %rdi
+# ALL-NEXT: %1:gr64 = COPY %rsi
+# ALL-NEXT: %2:gr64 = SUB64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -55,17 +51,13 @@ body:             |
 name:            test_sub_i32
 legalized:       true
 regBankSelected: true
-# ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
-# ALL:      %0 = COPY %edi
-# ALL-NEXT: %1 = COPY %esi
-# ALL-NEXT: %2 = SUB32rr %0, %1
+# ALL:      %0:gr32 = COPY %edi
+# ALL-NEXT: %1:gr32 = COPY %esi
+# ALL-NEXT: %2:gr32 = SUB32rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
@@ -83,23 +75,18 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = PSUBDrr %0, %1
-# AVX-NEXT:      %2 = VPSUBDrr %0, %1
-# AVX512F-NEXT:  %2 = VPSUBDrr %0, %1
-# AVX512VL-NEXT: %2 = VPSUBDZ128rr %0, %1
+# NO_AVX512VL:   %0:vr128 = COPY %xmm0
+# AVX512VL:      %0:vr128x = COPY %xmm0
+# NO_AVX512VL:   %1:vr128 = COPY %xmm1
+# AVX512VL:      %1:vr128x = COPY %xmm1
+# SSE-NEXT:      %2:vr128 = PSUBDrr %0, %1
+# AVX-NEXT:      %2:vr128 = VPSUBDrr %0, %1
+# AVX512F-NEXT:  %2:vr128 = VPSUBDrr %0, %1
+# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
@@ -118,23 +105,19 @@ legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
-# ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
-# ALL:           %0 = COPY %xmm0
-# ALL-NEXT:      %1 = COPY %xmm1
-# SSE-NEXT:      %2 = SUBPSrr %0, %1
-# AVX-NEXT:      %2 = VSUBPSrr %0, %1
-# AVX512F-NEXT:  %2 = VSUBPSrr %0, %1
-# AVX512VL-NEXT: %2 = VSUBPSZ128rr %0, %1
+# NO_AVX512VL:   %0:vr128 = COPY %xmm0
+# NO_AVX512VL:   %1:vr128 = COPY %xmm1
+# SSE-NEXT:      %2:vr128 = SUBPSrr %0, %1
+# AVX-NEXT:      %2:vr128 = VSUBPSrr %0, %1
+# AVX512F-NEXT:  %2:vr128 = VSUBPSrr %0, %1
+#
+# AVX512VL:      %0:vr128x = COPY %xmm0
+# AVX512VL:      %1:vr128x = COPY %xmm1
+# AVX512VL-NEXT: %2:vr128x = VSUBPSZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
diff --git a/test/CodeGen/X86/GlobalISel/select-trunc.mir b/test/CodeGen/X86/GlobalISel/select-trunc.mir
index ebb28e71782..3ebecafc05d 100644
--- a/test/CodeGen/X86/GlobalISel/select-trunc.mir
+++ b/test/CodeGen/X86/GlobalISel/select-trunc.mir
@@ -45,11 +45,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: trunc_i32toi1
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr8
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
     ; CHECK: %al = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %al
     %0(s32) = COPY %edi
@@ -71,11 +68,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: trunc_i32toi8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr8
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
     ; CHECK: %al = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %al
     %0(s32) = COPY %edi
@@ -97,11 +91,8 @@ body:             |
     liveins: %edi
 
     ; CHECK-LABEL: name: trunc_i32toi16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr32
-    ; CHECK-NEXT: id: 1, class: gr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %edi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; CHECK: %ax = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %ax
     %0(s32) = COPY %edi
@@ -123,11 +114,8 @@ body:             |
     liveins: %rdi
 
     ; CHECK-LABEL: name: trunc_i64toi8
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64_with_sub_8bit
-    ; CHECK-NEXT: id: 1, class: gr8
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_8bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
     ; CHECK: %al = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %al
     %0(s64) = COPY %rdi
@@ -149,11 +137,8 @@ body:             |
     liveins: %rdi
 
     ; CHECK-LABEL: name: trunc_i64toi16
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK-NEXT: id: 1, class: gr16
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_16bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
     ; CHECK: %ax = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %ax
     %0(s64) = COPY %rdi
@@ -175,11 +160,8 @@ body:             |
     liveins: %rdi
 
     ; CHECK-LABEL: name: trunc_i64toi32
-    ; CHECK: registers:
-    ; CHECK-NEXT: id: 0, class: gr64
-    ; CHECK-NEXT: id: 1, class: gr32
-    ; CHECK: [[COPY:%[0-9]+]] = COPY %rdi
-    ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32bit
+    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit
     ; CHECK: %eax = COPY [[COPY1]]
     ; CHECK: RET 0, implicit %eax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/GlobalISel/select-undef.mir b/test/CodeGen/X86/GlobalISel/select-undef.mir
index 2099c2ccff0..897ed8550e1 100644
--- a/test/CodeGen/X86/GlobalISel/select-undef.mir
+++ b/test/CodeGen/X86/GlobalISel/select-undef.mir
@@ -26,9 +26,7 @@ constants:
 body:             |
   bb.1 (%ir-block.0):
     ; ALL-LABEL: name: test
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
+    ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
     ; ALL: %al = COPY [[DEF]]
     ; ALL: RET 0, implicit %al
     %0(s8) = G_IMPLICIT_DEF
@@ -54,13 +52,9 @@ body:             |
     liveins: %edi
 
     ; ALL-LABEL: name: test2
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr8
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: [[ADD8rr:%[0-9]+]] = ADD8rr [[COPY]], [[DEF]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[DEF:%[0-9]+]]:gr8 = IMPLICIT_DEF
+    ; ALL: [[ADD8rr:%[0-9]+]]:gr8 = ADD8rr [[COPY]], [[DEF]], implicit-def %eflags
     ; ALL: %al = COPY [[ADD8rr]]
     ; ALL: RET 0, implicit %al
     %0(s8) = COPY %dil
diff --git a/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir b/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
index c0aafdd45cf..55a3428c055 100644
--- a/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
+++ b/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir
@@ -23,24 +23,16 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; AVX-LABEL: name: test_unmerge
-    ; AVX: registers:
-    ; AVX-NEXT: id: 0, class: vr256
-    ; AVX-NEXT: id: 1, class: vr128
-    ; AVX-NEXT: id: 2, class: vr128
-    ; AVX: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; AVX: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
-    ; AVX: [[VEXTRACTF128rr:%[0-9]+]] = VEXTRACTF128rr [[DEF]], 1
+    ; AVX: [[DEF:%[0-9]+]]:vr256 = IMPLICIT_DEF
+    ; AVX: [[COPY:%[0-9]+]]:vr128 = COPY [[DEF]].sub_xmm
+    ; AVX: [[VEXTRACTF128rr:%[0-9]+]]:vr128 = VEXTRACTF128rr [[DEF]], 1
     ; AVX: %xmm0 = COPY [[COPY]]
     ; AVX: %xmm1 = COPY [[VEXTRACTF128rr]]
     ; AVX: RET 0, implicit %xmm0, implicit %xmm1
     ; AVX512VL-LABEL: name: test_unmerge
-    ; AVX512VL: registers:
-    ; AVX512VL-NEXT: id: 0, class: vr256x
-    ; AVX512VL-NEXT: id: 1, class: vr128x
-    ; AVX512VL-NEXT: id: 2, class: vr128x
-    ; AVX512VL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; AVX512VL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
-    ; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]] = VEXTRACTF32x4Z256rr [[DEF]], 1
+    ; AVX512VL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
+    ; AVX512VL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
+    ; AVX512VL: [[VEXTRACTF32x4Z256rr:%[0-9]+]]:vr128x = VEXTRACTF32x4Z256rr [[DEF]], 1
     ; AVX512VL: %xmm0 = COPY [[COPY]]
     ; AVX512VL: %xmm1 = COPY [[VEXTRACTF32x4Z256rr]]
     ; AVX512VL: RET 0, implicit %xmm0, implicit %xmm1
diff --git a/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir b/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
index 451c3dfd76f..4446ab5de99 100644
--- a/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
+++ b/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir
@@ -25,17 +25,11 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_unmerge_v128
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr128x
-    ; ALL-NEXT: id: 2, class: vr128x
-    ; ALL-NEXT: id: 3, class: vr128x
-    ; ALL-NEXT: id: 4, class: vr128x
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_xmm
-    ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 1
-    ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 2
-    ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]] = VEXTRACTF32x4Zrr [[DEF]], 3
+    ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+    ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY [[DEF]].sub_xmm
+    ; ALL: [[VEXTRACTF32x4Zrr:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 1
+    ; ALL: [[VEXTRACTF32x4Zrr1:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 2
+    ; ALL: [[VEXTRACTF32x4Zrr2:%[0-9]+]]:vr128x = VEXTRACTF32x4Zrr [[DEF]], 3
     ; ALL: %xmm0 = COPY [[COPY]]
     ; ALL: RET 0, implicit %xmm0
     %0(<16 x s32>) = IMPLICIT_DEF
@@ -57,13 +51,9 @@ body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_unmerge_v256
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: vr512
-    ; ALL-NEXT: id: 1, class: vr256x
-    ; ALL-NEXT: id: 2, class: vr256x
-    ; ALL: [[DEF:%[0-9]+]] = IMPLICIT_DEF
-    ; ALL: [[COPY:%[0-9]+]] = COPY [[DEF]].sub_ymm
-    ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]] = VEXTRACTF64x4Zrr [[DEF]], 1
+    ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF
+    ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY [[DEF]].sub_ymm
+    ; ALL: [[VEXTRACTF64x4Zrr:%[0-9]+]]:vr256x = VEXTRACTF64x4Zrr [[DEF]], 1
     ; ALL: %ymm0 = COPY [[COPY]]
     ; ALL: RET 0, implicit %ymm0
     %0(<16 x s32>) = IMPLICIT_DEF
diff --git a/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir b/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
index 07079eb001c..26b07db83c3 100644
--- a/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
+++ b/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir
@@ -41,13 +41,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_xor_i8
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr8
-    ; ALL-NEXT: id: 1, class: gr8
-    ; ALL-NEXT: id: 2, class: gr8
-    ; ALL: [[COPY:%[0-9]+]] = COPY %dil
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %sil
-    ; ALL: [[XOR8rr:%[0-9]+]] = XOR8rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
+    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
+    ; ALL: [[XOR8rr:%[0-9]+]]:gr8 = XOR8rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %al = COPY [[XOR8rr]]
     ; ALL: RET 0, implicit %al
     %0(s8) = COPY %dil
@@ -75,13 +71,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_xor_i16
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr16
-    ; ALL-NEXT: id: 1, class: gr16
-    ; ALL-NEXT: id: 2, class: gr16
-    ; ALL: [[COPY:%[0-9]+]] = COPY %di
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %si
-    ; ALL: [[XOR16rr:%[0-9]+]] = XOR16rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
+    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
+    ; ALL: [[XOR16rr:%[0-9]+]]:gr16 = XOR16rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %ax = COPY [[XOR16rr]]
     ; ALL: RET 0, implicit %ax
     %0(s16) = COPY %di
@@ -109,13 +101,9 @@ body:             |
     liveins: %edi, %esi
 
     ; ALL-LABEL: name: test_xor_i32
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr32
-    ; ALL-NEXT: id: 1, class: gr32
-    ; ALL-NEXT: id: 2, class: gr32
-    ; ALL: [[COPY:%[0-9]+]] = COPY %edi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %esi
-    ; ALL: [[XOR32rr:%[0-9]+]] = XOR32rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
+    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
+    ; ALL: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %eax = COPY [[XOR32rr]]
     ; ALL: RET 0, implicit %eax
     %0(s32) = COPY %edi
@@ -143,13 +131,9 @@ body:             |
     liveins: %rdi, %rsi
 
     ; ALL-LABEL: name: test_xor_i64
-    ; ALL: registers:
-    ; ALL-NEXT: id: 0, class: gr64
-    ; ALL-NEXT: id: 1, class: gr64
-    ; ALL-NEXT: id: 2, class: gr64
-    ; ALL: [[COPY:%[0-9]+]] = COPY %rdi
-    ; ALL: [[COPY1:%[0-9]+]] = COPY %rsi
-    ; ALL: [[XOR64rr:%[0-9]+]] = XOR64rr [[COPY]], [[COPY1]], implicit-def %eflags
+    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
+    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
+    ; ALL: [[XOR64rr:%[0-9]+]]:gr64 = XOR64rr [[COPY]], [[COPY1]], implicit-def %eflags
     ; ALL: %rax = COPY [[XOR64rr]]
     ; ALL: RET 0, implicit %rax
     %0(s64) = COPY %rdi
diff --git a/test/CodeGen/X86/debugloc-no-line-0.ll b/test/CodeGen/X86/debugloc-no-line-0.ll
index 04fe623a1bd..65dfe577d2f 100644
--- a/test/CodeGen/X86/debugloc-no-line-0.ll
+++ b/test/CodeGen/X86/debugloc-no-line-0.ll
@@ -7,9 +7,7 @@
 ; CHECK: JMP{{.*}}%bb.4.entry, debug-location ![[JUMPLOC:[0-9]+]]
 ; CHECK: bb.4.entry:
 ; CHECK: successors:
-; CHECK-NOT: :
 ; CHECK: JE{{.*}}debug-location ![[JUMPLOC]]
-; CHECK-NOT: :
 ; CHECK: JMP{{.*}}debug-location ![[JUMPLOC]]
 
 define i32 @main() !dbg !12 {
diff --git a/test/CodeGen/X86/domain-reassignment.mir b/test/CodeGen/X86/domain-reassignment.mir
index b0185f8c9c9..cd678d2b952 100644
--- a/test/CodeGen/X86/domain-reassignment.mir
+++ b/test/CodeGen/X86/domain-reassignment.mir
@@ -56,9 +56,6 @@ regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 registers:       
-  # CHECK: - { id: 0, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 1, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 2, class: vk8, preferred-register: '' }
   - { id: 0, class: gr8, preferred-register: '' }
   - { id: 1, class: gr8, preferred-register: '' }
   - { id: 2, class: gr8, preferred-register: '' }
@@ -72,12 +69,8 @@ registers:
   - { id: 10, class: fr32x, preferred-register: '' }
   - { id: 11, class: gr8, preferred-register: '' }
   - { id: 12, class: vk1, preferred-register: '' }
-  # CHECK: - { id: 13, class: vk32, preferred-register: '' }
   - { id: 13, class: gr32, preferred-register: '' }
   - { id: 14, class: vk1, preferred-register: '' }
-  # CHECK: - { id: 15, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 16, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 17, class: vk32, preferred-register: '' }
   - { id: 15, class: gr32, preferred-register: '' }
   - { id: 16, class: gr32, preferred-register: '' }
   - { id: 17, class: gr32, preferred-register: '' }
@@ -139,8 +132,8 @@ body:             |
     %14 = VCMPSSZrr %7, %8, 0
 
     ; check that cross domain copies are replaced with same domain copies.
-    ; CHECK: %15 = COPY %14
-    ; CHECK: %0 = COPY %15
+    ; CHECK: %15:vk32 = COPY %14
+    ; CHECK: %0:vk8 = COPY %15
     
     %15 = COPY %14
     %0 = COPY %15.sub_8bit
@@ -151,8 +144,8 @@ body:             |
     %12 = VCMPSSZrr %9, %10, 0
 
     ; check that cross domain copies are replaced with same domain copies.
-    ; CHECK: %13 = COPY %12
-    ; CHECK: %1 = COPY %13
+    ; CHECK: %13:vk32 = COPY %12
+    ; CHECK: %1:vk8 = COPY %13
 
     %13 = COPY %12
     %1 = COPY %13.sub_8bit
@@ -160,9 +153,9 @@ body:             |
   bb.3.exit:
 
     ; check PHI, IMPLICIT_DEF, and INSERT_SUBREG replacers.
-    ; CHECK: %2 = PHI %1, %bb.2.else, %0, %bb.1.if
-    ; CHECK: %16 = COPY %2
-    ; CHECK: %18 = COPY %16
+    ; CHECK: %2:vk8 = PHI %1, %bb.2.else, %0, %bb.1.if
+    ; CHECK: %16:vk32 = COPY %2
+    ; CHECK: %18:vk1wm = COPY %16
   
     %2 = PHI %1, %bb.2.else, %0, %bb.1.if
     %17 = IMPLICIT_DEF
@@ -192,23 +185,12 @@ registers:
   - { id: 3, class: vr512, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
   - { id: 5, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk32, preferred-register: '' }
   - { id: 6, class: gr32, preferred-register: '' }
   - { id: 7, class: gr8, preferred-register: '' }
   - { id: 8, class: gr32, preferred-register: '' }
   - { id: 9, class: gr32, preferred-register: '' }
   - { id: 10, class: vk8wm, preferred-register: '' }
   - { id: 11, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 12, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 13, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 14, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 15, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 16, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 17, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 18, class: vk8, preferred-register: '' }
   - { id: 12, class: gr8, preferred-register: '' }
   - { id: 13, class: gr8, preferred-register: '' }
   - { id: 14, class: gr8, preferred-register: '' }
@@ -253,18 +235,18 @@ body:             |
     %4 = COPY %zmm3
   
     %5 = VCMPPDZrri %3, %4, 0
-    ; CHECK: %6 = COPY %5
-    ; CHECK: %7 = COPY %6
+    ; CHECK: %6:vk32 = COPY %5
+    ; CHECK: %7:vk8 = COPY %6
     %6 = COPY %5
     %7 = COPY %6.sub_8bit
 
-    ; CHECK: %12 = KSHIFTRBri %7, 2
-    ; CHECK: %13 = KSHIFTLBri %12, 1
-    ; CHECK: %14 = KNOTBrr %13
-    ; CHECK: %15 = KORBrr %14, %12
-    ; CHECK: %16 = KANDBrr %15, %13
-    ; CHECK: %17 = KXORBrr %16, %12
-    ; CHECK: %18 = KADDBrr %17, %14
+    ; CHECK: %12:vk8 = KSHIFTRBri %7, 2
+    ; CHECK: %13:vk8 = KSHIFTLBri %12, 1
+    ; CHECK: %14:vk8 = KNOTBrr %13
+    ; CHECK: %15:vk8 = KORBrr %14, %12
+    ; CHECK: %16:vk8 = KANDBrr %15, %13
+    ; CHECK: %17:vk8 = KXORBrr %16, %12
+    ; CHECK: %18:vk8 = KADDBrr %17, %14
     %12 = SHR8ri %7, 2, implicit-def dead %eflags
     %13 = SHL8ri %12, 1, implicit-def dead %eflags
     %14 = NOT8r %13
@@ -273,8 +255,8 @@ body:             |
     %17 = XOR8rr %16, %12, implicit-def dead %eflags
     %18 = ADD8rr %17, %14, implicit-def dead %eflags
   
-    ; CHECK: %9 = COPY %18
-    ; CHECK: %10 = COPY %9
+    ; CHECK: %9:vk32 = COPY %18
+    ; CHECK: %10:vk8wm = COPY %9
     %8 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %8, %18, 1
     %10 = COPY %9
@@ -308,22 +290,12 @@ registers:
   - { id: 3, class: vr512, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
   - { id: 5, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk32, preferred-register: '' }
   - { id: 6, class: gr32, preferred-register: '' }
   - { id: 7, class: gr16, preferred-register: '' }
   - { id: 8, class: gr32, preferred-register: '' }
   - { id: 9, class: gr32, preferred-register: '' }
   - { id: 10, class: vk16wm, preferred-register: '' }
   - { id: 11, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 12, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 13, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 14, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 15, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 16, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 17, class: vk16, preferred-register: '' }
   - { id: 12, class: gr16, preferred-register: '' }
   - { id: 13, class: gr16, preferred-register: '' }
   - { id: 14, class: gr16, preferred-register: '' }
@@ -367,17 +339,17 @@ body:             |
     %4 = COPY %zmm3
   
     %5 = VCMPPSZrri %3, %4, 0
-    ; CHECK: %6 = COPY %5
-    ; CHECK: %7 = COPY %6
+    ; CHECK: %6:vk32 = COPY %5
+    ; CHECK: %7:vk16 = COPY %6
     %6 = COPY %5
     %7 = COPY %6.sub_16bit
 
-    ; CHECK: %12 = KSHIFTRWri %7, 2
-    ; CHECK: %13 = KSHIFTLWri %12, 1
-    ; CHECK: %14 = KNOTWrr %13
-    ; CHECK: %15 = KORWrr %14, %12
-    ; CHECK: %16 = KANDWrr %15, %13
-    ; CHECK: %17 = KXORWrr %16, %12
+    ; CHECK: %12:vk16 = KSHIFTRWri %7, 2
+    ; CHECK: %13:vk16 = KSHIFTLWri %12, 1
+    ; CHECK: %14:vk16 = KNOTWrr %13
+    ; CHECK: %15:vk16 = KORWrr %14, %12
+    ; CHECK: %16:vk16 = KANDWrr %15, %13
+    ; CHECK: %17:vk16 = KXORWrr %16, %12
     %12 = SHR16ri %7, 2, implicit-def dead %eflags
     %13 = SHL16ri %12, 1, implicit-def dead %eflags
     %14 = NOT16r %13
@@ -385,8 +357,8 @@ body:             |
     %16 = AND16rr %15, %13, implicit-def dead %eflags
     %17 = XOR16rr %16, %12, implicit-def dead %eflags
   
-    ; CHECK: %9 = COPY %17
-    ; CHECK: %10 = COPY %9
+    ; CHECK: %9:vk32 = COPY %17
+    ; CHECK: %10:vk16wm = COPY %9
     %8 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %8, %17, 3
     %10 = COPY %9
@@ -419,15 +391,6 @@ registers:
   - { id: 2, class: vr512, preferred-register: '' }
   - { id: 3, class: vk32wm, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 5, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 10, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 11, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 12, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 13, class: vk32, preferred-register: '' }
   - { id: 5, class: gr32, preferred-register: '' }
   - { id: 6, class: gr32, preferred-register: '' }
   - { id: 7, class: gr32, preferred-register: '' }
@@ -469,15 +432,15 @@ body:             |
     %1 = COPY %zmm0
     %2 = COPY %zmm1
   
-    ; CHECK: %5 = KMOVDkm %0, 1, _, 0, _
-    ; CHECK: %6 = KSHIFTRDri %5, 2
-    ; CHECK: %7 = KSHIFTLDri %6, 1
-    ; CHECK: %8 = KNOTDrr %7
-    ; CHECK: %9 = KORDrr %8, %6
-    ; CHECK: %10 = KANDDrr %9, %7
-    ; CHECK: %11 = KXORDrr %10, %6
-    ; CHECK: %12 = KANDNDrr %11, %9
-    ; CHECK: %13 = KADDDrr %12, %11
+    ; CHECK: %5:vk32 = KMOVDkm %0, 1, _, 0, _
+    ; CHECK: %6:vk32 = KSHIFTRDri %5, 2
+    ; CHECK: %7:vk32 = KSHIFTLDri %6, 1
+    ; CHECK: %8:vk32 = KNOTDrr %7
+    ; CHECK: %9:vk32 = KORDrr %8, %6
+    ; CHECK: %10:vk32 = KANDDrr %9, %7
+    ; CHECK: %11:vk32 = KXORDrr %10, %6
+    ; CHECK: %12:vk32 = KANDNDrr %11, %9
+    ; CHECK: %13:vk32 = KADDDrr %12, %11
     %5 = MOV32rm %0, 1, _, 0, _
     %6 = SHR32ri %5, 2, implicit-def dead %eflags
     %7 = SHL32ri %6, 1, implicit-def dead %eflags
@@ -488,7 +451,7 @@ body:             |
     %12 = ANDN32rr %11, %9, implicit-def dead %eflags
     %13 = ADD32rr %12, %11, implicit-def dead %eflags
   
-    ; CHECK: %3 = COPY %13
+    ; CHECK: %3:vk32wm = COPY %13
     %3 = COPY %13
     %4 = VMOVDQU16Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -519,15 +482,6 @@ registers:
   - { id: 2, class: vr512, preferred-register: '' }
   - { id: 3, class: vk64wm, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 5, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 10, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 11, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 12, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 13, class: vk64, preferred-register: '' }
   - { id: 5, class: gr64, preferred-register: '' }
   - { id: 6, class: gr64, preferred-register: '' }
   - { id: 7, class: gr64, preferred-register: '' }
@@ -569,15 +523,15 @@ body:             |
     %1 = COPY %zmm0
     %2 = COPY %zmm1
   
-    ; CHECK: %5 = KMOVQkm %0, 1, _, 0, _
-    ; CHECK: %6 = KSHIFTRQri %5, 2
-    ; CHECK: %7 = KSHIFTLQri %6, 1
-    ; CHECK: %8 = KNOTQrr %7
-    ; CHECK: %9 = KORQrr %8, %6
-    ; CHECK: %10 = KANDQrr %9, %7
-    ; CHECK: %11 = KXORQrr %10, %6
-    ; CHECK: %12 = KANDNQrr %11, %9
-    ; CHECK: %13 = KADDQrr %12, %11
+    ; CHECK: %5:vk64 = KMOVQkm %0, 1, _, 0, _
+    ; CHECK: %6:vk64 = KSHIFTRQri %5, 2
+    ; CHECK: %7:vk64 = KSHIFTLQri %6, 1
+    ; CHECK: %8:vk64 = KNOTQrr %7
+    ; CHECK: %9:vk64 = KORQrr %8, %6
+    ; CHECK: %10:vk64 = KANDQrr %9, %7
+    ; CHECK: %11:vk64 = KXORQrr %10, %6
+    ; CHECK: %12:vk64 = KANDNQrr %11, %9
+    ; CHECK: %13:vk64 = KADDQrr %12, %11
     %5 = MOV64rm %0, 1, _, 0, _
     %6 = SHR64ri %5, 2, implicit-def dead %eflags
     %7 = SHL64ri %6, 1, implicit-def dead %eflags
@@ -588,7 +542,7 @@ body:             |
     %12 = ANDN64rr %11, %9, implicit-def dead %eflags
     %13 = ADD64rr %12, %11, implicit-def dead %eflags
   
-    ; CHECK: %3 = COPY %13
+    ; CHECK: %3:vk64wm = COPY %13
     %3 = COPY %13
     %4 = VMOVDQU8Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -619,11 +573,8 @@ registers:
   - { id: 2, class: vr512, preferred-register: '' }
   - { id: 3, class: vk16wm, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 5, class: vk16, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk16, preferred-register: '' }
   - { id: 5, class: gr16, preferred-register: '' }
   - { id: 6, class: gr16, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk8, preferred-register: '' }
 liveins:         
   - { reg: '%rdi', virtual-reg: '%0' }
   - { reg: '%zmm0', virtual-reg: '%1' }
@@ -656,13 +607,13 @@ body:             |
     %1 = COPY %zmm0
     %2 = COPY %zmm1
   
-    ; CHECK: %7 = KMOVBkm %0, 1, _, 0, _
-    ; CHECK: %5 = COPY %7
-    ; CHECK: %6 = KNOTWrr %5
+    ; CHECK: %7:vk8 = KMOVBkm %0, 1, _, 0, _
+    ; CHECK: %5:vk16 = COPY %7
+    ; CHECK: %6:vk16 = KNOTWrr %5
     %5 = MOVZX16rm8 %0, 1, _, 0, _
     %6 = NOT16r %5
 
-    ; CHECK: %3 = COPY %6
+    ; CHECK: %3:vk16wm = COPY %6
     %3 = COPY %6
     %4 = VMOVAPSZrrk %2, killed %3, %1
     VMOVAPSZmr %0, 1, _, 0, _, killed %4
@@ -684,14 +635,9 @@ registers:
   - { id: 2, class: vr512, preferred-register: '' }
   - { id: 3, class: vk64wm, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 5, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk32, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk32, preferred-register: '' }
   - { id: 5, class: gr32, preferred-register: '' }
   - { id: 6, class: gr32, preferred-register: '' }
   - { id: 7, class: gr32, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk16, preferred-register: '' }
 liveins:         
   - { reg: '%rdi', virtual-reg: '%0' }
   - { reg: '%zmm0', virtual-reg: '%1' }
@@ -724,16 +670,16 @@ body:             |
     %1 = COPY %zmm0
     %2 = COPY %zmm1
   
-    ; CHECK: %8 = KMOVBkm %0, 1, _, 0, _
-    ; CHECK: %5 = COPY %8
-    ; CHECK: %9 = KMOVWkm %0, 1, _, 0, _
-    ; CHECK: %6 = COPY %9
-    ; CHECK: %7 = KADDDrr %5, %6
+    ; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _
+    ; CHECK: %5:vk32 = COPY %8
+    ; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _
+    ; CHECK: %6:vk32 = COPY %9
+    ; CHECK: %7:vk32 = KADDDrr %5, %6
     %5 = MOVZX32rm8 %0, 1, _, 0, _
     %6 = MOVZX32rm16 %0, 1, _, 0, _
     %7 = ADD32rr %5, %6, implicit-def dead %eflags
 
-    ; CHECK: %3 = COPY %7
+    ; CHECK: %3:vk64wm = COPY %7
     %3 = COPY %7
     %4 = VMOVDQU16Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
@@ -755,14 +701,9 @@ registers:
   - { id: 2, class: vr512, preferred-register: '' }
   - { id: 3, class: vk64wm, preferred-register: '' }
   - { id: 4, class: vr512, preferred-register: '' }
-  # CHECK: - { id: 5, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 6, class: vk64, preferred-register: '' }
-  # CHECK: - { id: 7, class: vk64, preferred-register: '' }
   - { id: 5, class: gr64, preferred-register: '' }
   - { id: 6, class: gr64, preferred-register: '' }
   - { id: 7, class: gr64, preferred-register: '' }
-  # CHECK: - { id: 8, class: vk8, preferred-register: '' }
-  # CHECK: - { id: 9, class: vk16, preferred-register: '' }
 liveins:         
   - { reg: '%rdi', virtual-reg: '%0' }
   - { reg: '%zmm0', virtual-reg: '%1' }
@@ -795,16 +736,16 @@ body:             |
     %1 = COPY %zmm0
     %2 = COPY %zmm1
   
-    ; CHECK: %8 = KMOVBkm %0, 1, _, 0, _
-    ; CHECK: %5 = COPY %8
-    ; CHECK: %9 = KMOVWkm %0, 1, _, 0, _
-    ; CHECK: %6 = COPY %9
-    ; CHECK: %7 = KADDQrr %5, %6
+    ; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _
+    ; CHECK: %5:vk64 = COPY %8
+    ; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _
+    ; CHECK: %6:vk64 = COPY %9
+    ; CHECK: %7:vk64 = KADDQrr %5, %6
     %5 = MOVZX64rm8 %0, 1, _, 0, _
     %6 = MOVZX64rm16 %0, 1, _, 0, _
     %7 = ADD64rr %5, %6, implicit-def dead %eflags
 
-    ; CHECK: %3 = COPY %7
+    ; CHECK: %3:vk64wm = COPY %7
     %3 = COPY %7
     %4 = VMOVDQU8Zrrk %2, killed %3, %1
     VMOVDQA32Zmr %0, 1, _, 0, _, killed %4
diff --git a/test/CodeGen/X86/implicit-use-spill.mir b/test/CodeGen/X86/implicit-use-spill.mir
index 94bdd47b447..9d8b04564e5 100644
--- a/test/CodeGen/X86/implicit-use-spill.mir
+++ b/test/CodeGen/X86/implicit-use-spill.mir
@@ -14,7 +14,7 @@ body: |
   ; CHECK-NEXT: MOV64mr [[SLOT:%stack.[0-9]+]], 1, _, 0, _, [[VAL]]
   ; CHECK-NEXT: NOOP csr_noregs
   ; We need to reload before the (implicit) use.
-  ; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]] = MOV64rm [[SLOT]], 1, _, 0, _
+  ; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]]:gr64 = MOV64rm [[SLOT]], 1, _, 0, _
   ; CHECK-NEXT: NOOP implicit [[RELOADED_VAL]]
   NOOP implicit-def %0
   NOOP csr_noregs
diff --git a/test/CodeGen/X86/lea-opt-with-debug.mir b/test/CodeGen/X86/lea-opt-with-debug.mir
index 5a32d7e0815..dfa9eed479a 100644
--- a/test/CodeGen/X86/lea-opt-with-debug.mir
+++ b/test/CodeGen/X86/lea-opt-with-debug.mir
@@ -95,9 +95,9 @@ body:             |
   bb.0 (%ir-block.0):
     successors: %bb.1(0x80000000)
 
-    ; CHECK: %3 = LEA64r %2, 2, %2, 0, _, debug-location !13
-    ; CHECK-NEXT: %4 = LEA64r %1, 4, %3, 0, _, debug-location !13
-    ; CHECK-NOT: %0 = LEA64r %1, 4, %3, 8, _, debug-location !14
+    ; CHECK: %3:gr64_nosp = LEA64r %2, 2, %2, 0, _, debug-location !13
+    ; CHECK-NEXT: %4:gr64 = LEA64r %1, 4, %3, 0, _, debug-location !13
+    ; CHECK-NOT: %0:gr64 = LEA64r %1, 4, %3, 8, _, debug-location !14
     ; CHECK: DBG_VALUE debug-use %4, debug-use _, !11, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_stack_value), debug-location !15
 
     %1 = MOV64rm %rip, 1, _, @c, _, debug-location !13 :: (dereferenceable load 8 from @c)
@@ -110,7 +110,7 @@ body:             |
     DBG_VALUE debug-use %0, debug-use _, !11, !DIExpression(), debug-location !15
 
     ; CHECK-LABEL: bb.1 (%ir-block.8):
-    ; CHECK: %6 = MOV32rm %4, 1, _, 8, _, debug-location !17 :: (load 4 from %ir.7)
+    ; CHECK: %6:gr32 = MOV32rm %4, 1, _, 8, _, debug-location !17 :: (load 4 from %ir.7)
 
   bb.1 (%ir-block.8):
     successors: %bb.1(0x80000000)
diff --git a/test/CodeGen/X86/movtopush.mir b/test/CodeGen/X86/movtopush.mir
index 42856ea1690..4b8fac8d411 100644
--- a/test/CodeGen/X86/movtopush.mir
+++ b/test/CodeGen/X86/movtopush.mir
@@ -41,10 +41,10 @@
 # CHECK-NEXT: CALLpcrel32 @good, csr_32, implicit %esp, implicit-def %esp
 # CHECK-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit %esp
 # CHECK-NEXT: ADJCALLSTACKDOWN32 20, 0, 20, implicit-def dead %esp, implicit-def dead %eflags, implicit %esp
-# CHECK-NEXT: %1 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8)
-# CHECK-NEXT: %2 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4)
-# CHECK-NEXT: %4 = LEA32r %stack.0.p, 1, _, 0, _
-# CHECK-NEXT: %5 = LEA32r %stack.1.q, 1, _, 0, _
+# CHECK-NEXT: %1:gr32 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8)
+# CHECK-NEXT: %2:gr32 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4)
+# CHECK-NEXT: %4:gr32 = LEA32r %stack.0.p, 1, _, 0, _
+# CHECK-NEXT: %5:gr32 = LEA32r %stack.1.q, 1, _, 0, _
 # CHECK-NEXT: PUSH32r %4, implicit-def %esp, implicit %esp
 # CHECK-NEXT: PUSH32r %5, implicit-def %esp, implicit %esp
 # CHECK-NEXT: PUSH32i8 6, implicit-def %esp, implicit %esp
diff --git a/test/CodeGen/X86/peephole-recurrence.mir b/test/CodeGen/X86/peephole-recurrence.mir
index af57a4fd526..07ce876d99e 100644
--- a/test/CodeGen/X86/peephole-recurrence.mir
+++ b/test/CodeGen/X86/peephole-recurrence.mir
@@ -4,54 +4,54 @@
   define i32 @foo(i32 %a) {
   bb0:
     br label %bb1
-  
+
   bb1:                                              ; preds = %bb7, %bb0
     %vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
     %cond0 = icmp eq i32 %a, 0
     br i1 %cond0, label %bb4, label %bb3
-  
+
   bb3:                                              ; preds = %bb1
     br label %bb4
-  
+
   bb4:                                              ; preds = %bb1, %bb3
     %vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
     %cond1 = icmp eq i32 %vreg5, 0
     br i1 %cond1, label %bb7, label %bb6
-  
+
   bb6:                                              ; preds = %bb4
     br label %bb7
-  
+
   bb7:                                              ; preds = %bb4, %bb6
     %vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
     %vreg2 = add i32 %vreg5, %vreg0
     %vreg3 = add i32 %vreg1, %vreg2
     %cond2 = icmp slt i32 %vreg3, 10
     br i1 %cond2, label %bb1, label %bb8
-  
+
   bb8:                                              ; preds = %bb7
     ret i32 0
   }
-  
+
   define i32 @bar(i32 %a, i32* %p) {
   bb0:
     br label %bb1
-  
+
   bb1:                                              ; preds = %bb7, %bb0
     %vreg0 = phi i32 [ 0, %bb0 ], [ %vreg3, %bb7 ]
     %cond0 = icmp eq i32 %a, 0
     br i1 %cond0, label %bb4, label %bb3
-  
+
   bb3:                                              ; preds = %bb1
     br label %bb4
-  
+
   bb4:                                              ; preds = %bb1, %bb3
     %vreg5 = phi i32 [ 2, %bb3 ], [ 1, %bb1 ]
     %cond1 = icmp eq i32 %vreg5, 0
     br i1 %cond1, label %bb7, label %bb6
-  
+
   bb6:                                              ; preds = %bb4
     br label %bb7
-  
+
   bb7:                                              ; preds = %bb4, %bb6
     %vreg1 = phi i32 [ 2, %bb6 ], [ 1, %bb4 ]
     %vreg2 = add i32 %vreg5, %vreg0
@@ -59,7 +59,7 @@
     %vreg3 = add i32 %vreg1, %vreg2
     %cond2 = icmp slt i32 %vreg3, 10
     br i1 %cond2, label %bb1, label %bb8
-  
+
   bb8:                                              ; preds = %bb7
     ret i32 0
   }
@@ -71,7 +71,7 @@
 # the recurrence are tied. This will remove redundant copy instruction.
 name:            foo
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gr32, preferred-register: '' }
   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 2, class: gr32, preferred-register: '' }
@@ -85,60 +85,60 @@ registers:
   - { id: 10, class: gr32, preferred-register: '' }
   - { id: 11, class: gr32, preferred-register: '' }
   - { id: 12, class: gr32, preferred-register: '' }
-liveins:         
+liveins:
   - { reg: '%edi', virtual-reg: '%4' }
 body:             |
   bb.0.bb0:
     successors: %bb.1.bb1(0x80000000)
     liveins: %edi
-  
+
     %4 = COPY %edi
     %5 = MOV32r0 implicit-def dead %eflags
-  
+
   bb.1.bb1:
     successors: %bb.3.bb4(0x30000000), %bb.2.bb3(0x50000000)
-  
-    ; CHECK: %0 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
+
+    ; CHECK: %0:gr32 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
     %0 = PHI %5, %bb.0.bb0, %3, %bb.5.bb7
     %6 = MOV32ri 1
     TEST32rr %4, %4, implicit-def %eflags
     JE_1 %bb.3.bb4, implicit %eflags
     JMP_1 %bb.2.bb3
-  
+
   bb.2.bb3:
     successors: %bb.3.bb4(0x80000000)
-  
+
     %7 = MOV32ri 2
-  
+
   bb.3.bb4:
     successors: %bb.5.bb7(0x30000000), %bb.4.bb6(0x50000000)
-  
+
     %1 = PHI %6, %bb.1.bb1, %7, %bb.2.bb3
     TEST32rr %1, %1, implicit-def %eflags
     JE_1 %bb.5.bb7, implicit %eflags
     JMP_1 %bb.4.bb6
-  
+
   bb.4.bb6:
     successors: %bb.5.bb7(0x80000000)
-  
+
     %9 = MOV32ri 2
-  
+
   bb.5.bb7:
     successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000)
-  
+
     %2 = PHI %6, %bb.3.bb4, %9, %bb.4.bb6
     %10 = ADD32rr %1, %0, implicit-def dead %eflags
-    ; CHECK: %10 = ADD32rr
+    ; CHECK: %10:gr32 = ADD32rr
     ; CHECK-SAME: %0,
     ; CHECK-SAME: %1,
     %3 = ADD32rr %2, killed %10, implicit-def dead %eflags
-    ; CHECK: %3 = ADD32rr
+    ; CHECK: %3:gr32 = ADD32rr
     ; CHECK-SAME: %10,
     ; CHECK-SAME: %2,
     %11 = SUB32ri8 %3, 10, implicit-def %eflags
     JL_1 %bb.1.bb1, implicit %eflags
     JMP_1 %bb.6.bb8
-  
+
   bb.6.bb8:
     %12 = MOV32r0 implicit-def dead %eflags
     %eax = COPY %12
@@ -149,10 +149,10 @@ body:             |
 # Here a recurrence is formulated around %0, %11, and %3, but operands should
 # not be commuted because %0 has a use outside of recurrence. This is to
 # prevent the case of commuting operands ties the values with overlapping live
-# ranges. 
+# ranges.
 name:            bar
 tracksRegLiveness: true
-registers:       
+registers:
   - { id: 0, class: gr32, preferred-register: '' }
   - { id: 1, class: gr32, preferred-register: '' }
   - { id: 2, class: gr32, preferred-register: '' }
@@ -167,63 +167,63 @@ registers:
   - { id: 11, class: gr32, preferred-register: '' }
   - { id: 12, class: gr32, preferred-register: '' }
   - { id: 13, class: gr32, preferred-register: '' }
-liveins:         
+liveins:
   - { reg: '%edi', virtual-reg: '%4' }
   - { reg: '%rsi', virtual-reg: '%5' }
 body:             |
   bb.0.bb0:
     successors: %bb.1.bb1(0x80000000)
     liveins: %edi, %rsi
-  
+
     %5 = COPY %rsi
     %4 = COPY %edi
     %6 = MOV32r0 implicit-def dead %eflags
-  
+
   bb.1.bb1:
     successors: %bb.3.bb4(0x30000000), %bb.2.bb3(0x50000000)
-  
+
     %0 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
-    ; CHECK: %0 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
+    ; CHECK: %0:gr32 = PHI %6, %bb.0.bb0, %3, %bb.5.bb7
     %7 = MOV32ri 1
     TEST32rr %4, %4, implicit-def %eflags
     JE_1 %bb.3.bb4, implicit %eflags
     JMP_1 %bb.2.bb3
-  
+
   bb.2.bb3:
     successors: %bb.3.bb4(0x80000000)
-  
+
     %8 = MOV32ri 2
-  
+
   bb.3.bb4:
     successors: %bb.5.bb7(0x30000000), %bb.4.bb6(0x50000000)
-  
+
     %1 = PHI %7, %bb.1.bb1, %8, %bb.2.bb3
     TEST32rr %1, %1, implicit-def %eflags
     JE_1 %bb.5.bb7, implicit %eflags
     JMP_1 %bb.4.bb6
-  
+
   bb.4.bb6:
     successors: %bb.5.bb7(0x80000000)
-  
+
     %10 = MOV32ri 2
-  
+
   bb.5.bb7:
     successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000)
-  
+
     %2 = PHI %7, %bb.3.bb4, %10, %bb.4.bb6
     %11 = ADD32rr %1, %0, implicit-def dead %eflags
-    ; CHECK: %11 = ADD32rr
+    ; CHECK: %11:gr32 = ADD32rr
     ; CHECK-SAME: %1,
     ; CHECK-SAME: %0,
     MOV32mr %5, 1, _, 0, _, %0 :: (store 4 into %ir.p)
     %3 = ADD32rr %2, killed %11, implicit-def dead %eflags
-    ; CHECK: %3 = ADD32rr
+    ; CHECK: %3:gr32 = ADD32rr
     ; CHECK-SAME: %2,
     ; CHECK-SAME: %11,
     %12 = SUB32ri8 %3, 10, implicit-def %eflags
     JL_1 %bb.1.bb1, implicit %eflags
     JMP_1 %bb.6.bb8
-  
+
   bb.6.bb8:
     %13 = MOV32r0 implicit-def dead %eflags
     %eax = COPY %13
diff --git a/test/CodeGen/X86/peephole.mir b/test/CodeGen/X86/peephole.mir
index 6391836e9ca..28ce9f1f0e8 100644
--- a/test/CodeGen/X86/peephole.mir
+++ b/test/CodeGen/X86/peephole.mir
@@ -19,18 +19,18 @@ registers:
 
 body: |
   bb.0:
-    ; CHECK: %1 = VMOVDI2SSrr %0
-    ; CHECK: %7 = COPY %0
+    ; CHECK: %1:fr32 = VMOVDI2SSrr %0
+    ; CHECK: %7:gr32 = COPY %0
     ; CHECK: NOOP implicit %7
     %0 = MOV32ri 42
     %1 = VMOVDI2SSrr %0
     %2 = MOVSS2DIrr %1
     NOOP implicit %2
 
-    ; CHECK: %4 = VMOVDI2SSrr %3
+    ; CHECK: %4:fr32 = VMOVDI2SSrr %3
     ; CHECK-NOT: COPY
-    ; CHECK: %5 = MOVSS2DIrr %4
-    ; CHECK: %6 = SUBREG_TO_REG %5, 0
+    ; CHECK: %5:gr32 = MOVSS2DIrr %4
+    ; CHECK: %6:gr64 = SUBREG_TO_REG %5, 0
     ; CHECK: NOOP implicit %6
     %3 = MOV32ri 42
     %4 = VMOVDI2SSrr %3
diff --git a/test/CodeGen/X86/sqrt-fastmath-mir.ll b/test/CodeGen/X86/sqrt-fastmath-mir.ll
index c613ef8ee38..3e4600bfd5d 100644
--- a/test/CodeGen/X86/sqrt-fastmath-mir.ll
+++ b/test/CodeGen/X86/sqrt-fastmath-mir.ll
@@ -5,21 +5,21 @@ declare float @llvm.sqrt.f32(float) #0
 define float @foo(float %f) #0 {
 ; CHECK: {{name: *foo}}
 ; CHECK: body:
-; CHECK:     %0 = COPY %xmm0
-; CHECK:     %1 = VRSQRTSSr killed %2, %0
-; CHECK:     %3 = VMULSSrr %0, %1
-; CHECK:     %4 = VMOVSSrm
-; CHECK:     %5 = VFMADD213SSr %1, killed %3, %4
-; CHECK:     %6 = VMOVSSrm
-; CHECK:     %7 = VMULSSrr %1, %6
-; CHECK:     %8 = VMULSSrr killed %7, killed %5
-; CHECK:     %9 = VMULSSrr %0, %8
-; CHECK:     %10 = VFMADD213SSr %8, %9, %4
-; CHECK:     %11 = VMULSSrr %9, %6
-; CHECK:     %12 = VMULSSrr killed %11, killed %10
-; CHECK:     %14 = FsFLD0SS
-; CHECK:     %15 = VCMPSSrr %0, killed %14, 0
-; CHECK:     %17 = VANDNPSrr killed %16, killed %13
+; CHECK:     %0:fr32 = COPY %xmm0
+; CHECK:     %1:fr32 = VRSQRTSSr killed %2, %0
+; CHECK:     %3:fr32 = VMULSSrr %0, %1
+; CHECK:     %4:fr32 = VMOVSSrm
+; CHECK:     %5:fr32 = VFMADD213SSr %1, killed %3, %4
+; CHECK:     %6:fr32 = VMOVSSrm
+; CHECK:     %7:fr32 = VMULSSrr %1, %6
+; CHECK:     %8:fr32 = VMULSSrr killed %7, killed %5
+; CHECK:     %9:fr32 = VMULSSrr %0, %8
+; CHECK:     %10:fr32 = VFMADD213SSr %8, %9, %4
+; CHECK:     %11:fr32 = VMULSSrr %9, %6
+; CHECK:     %12:fr32 = VMULSSrr killed %11, killed %10
+; CHECK:     %14:fr32 = FsFLD0SS
+; CHECK:     %15:fr32 = VCMPSSrr %0, killed %14, 0
+; CHECK:     %17:vr128 = VANDNPSrr killed %16, killed %13
 ; CHECK:     %xmm0 = COPY %18
 ; CHECK:     RET 0, %xmm0
   %call = tail call float @llvm.sqrt.f32(float %f) #1
@@ -29,18 +29,18 @@ define float @foo(float %f) #0 {
 define float @rfoo(float %f) #0 {
 ; CHECK: {{name: *rfoo}}
 ; CHECK: body:             |
-; CHECK:     %0 = COPY %xmm0
-; CHECK:     %1 = VRSQRTSSr killed %2, %0
-; CHECK:     %3 = VMULSSrr %0, %1
-; CHECK:     %4 = VMOVSSrm
-; CHECK:     %5 = VFMADD213SSr %1, killed %3, %4
-; CHECK:     %6 = VMOVSSrm
-; CHECK:     %7 = VMULSSrr %1, %6
-; CHECK:     %8 = VMULSSrr killed %7, killed %5
-; CHECK:     %9 = VMULSSrr %0, %8
-; CHECK:     %10 = VFMADD213SSr %8, killed %9, %4
-; CHECK:     %11 = VMULSSrr %8, %6
-; CHECK:     %12 = VMULSSrr killed %11, killed %10
+; CHECK:     %0:fr32 = COPY %xmm0
+; CHECK:     %1:fr32 = VRSQRTSSr killed %2, %0
+; CHECK:     %3:fr32 = VMULSSrr %0, %1
+; CHECK:     %4:fr32 = VMOVSSrm
+; CHECK:     %5:fr32 = VFMADD213SSr %1, killed %3, %4
+; CHECK:     %6:fr32 = VMOVSSrm
+; CHECK:     %7:fr32 = VMULSSrr %1, %6
+; CHECK:     %8:fr32 = VMULSSrr killed %7, killed %5
+; CHECK:     %9:fr32 = VMULSSrr %0, %8
+; CHECK:     %10:fr32 = VFMADD213SSr %8, killed %9, %4
+; CHECK:     %11:fr32 = VMULSSrr %8, %6
+; CHECK:     %12:fr32 = VMULSSrr killed %11, killed %10
 ; CHECK:     %xmm0 = COPY %12
 ; CHECK:     RET 0, %xmm0
   %sqrt = tail call float @llvm.sqrt.f32(float %f)
diff --git a/test/CodeGen/X86/tail-dup-debugloc.ll b/test/CodeGen/X86/tail-dup-debugloc.ll
index 5e0e8a229a5..4907e5244b6 100644
--- a/test/CodeGen/X86/tail-dup-debugloc.ll
+++ b/test/CodeGen/X86/tail-dup-debugloc.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -stop-after=tailduplication < %s | FileCheck %s
 ;
-; Check that DebugLoc attached to the branch instruction of 
+; Check that DebugLoc attached to the branch instruction of
 ; 'while.cond1.preheader.lr.ph' survives after tailduplication pass.
 ;
 ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 9, column: 5, scope: !{{[0-9]+}})
-; CHECK: [[VREG:%[^ ]+]] = COPY %rdi
+; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY %rdi
 ; CHECK: TEST64rr [[VREG]], [[VREG]]
 ; CHECK-NEXT: JE_1 {{.+}}, debug-location [[DLOC]]
 ; CHECK-NEXT: JMP_1 {{.+}}, debug-location [[DLOC]]
diff --git a/test/CodeGen/X86/update-terminator-debugloc.ll b/test/CodeGen/X86/update-terminator-debugloc.ll
index 2e1010f6f7a..17b98c3ee62 100644
--- a/test/CodeGen/X86/update-terminator-debugloc.ll
+++ b/test/CodeGen/X86/update-terminator-debugloc.ll
@@ -15,18 +15,18 @@
 ; 12   }
 ; 13   return ret;
 ; 14 }
-; 
-; With the test code, LLVM-IR below shows that loop-control branches have a 
+;
+; With the test code, LLVM-IR below shows that loop-control branches have a
 ; debug location of line 6 (branches in entry and for.body block). Make sure that
 ; these debug locations are propaged correctly to lowered instructions.
 ;
 ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 6
-; CHECK-DAG: [[VREG1:%[^ ]+]] = COPY %rsi
-; CHECK-DAG: [[VREG2:%[^ ]+]] = COPY %rdi
+; CHECK-DAG: [[VREG1:%[^ ]+]]:gr64 = COPY %rsi
+; CHECK-DAG: [[VREG2:%[^ ]+]]:gr64 = COPY %rdi
 ; CHECK: SUB64rr [[VREG2]], [[VREG1]]
 ; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
-; CHECK: [[VREG3:%[^ ]+]] = PHI [[VREG2]]
-; CHECK: [[VREG4:%[^ ]+]] = ADD64ri8 [[VREG3]], 4
+; CHECK: [[VREG3:%[^ ]+]]:gr64 = PHI [[VREG2]]
+; CHECK: [[VREG4:%[^ ]+]]:gr64 = ADD64ri8 [[VREG3]], 4
 ; CHECK: SUB64rr [[VREG1]], [[VREG4]]
 ; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
 ; CHECK-NEXT: JMP_1 {{.*}}, debug-location [[DLOC]]{{$}}
diff --git a/test/CodeGen/X86/xor-combine-debugloc.ll b/test/CodeGen/X86/xor-combine-debugloc.ll
index 21777c1c572..4491d1434e2 100644
--- a/test/CodeGen/X86/xor-combine-debugloc.ll
+++ b/test/CodeGen/X86/xor-combine-debugloc.ll
@@ -4,11 +4,11 @@
 ; that implictly defines %eflags has a same debug location with the icmp
 ; instruction, and the branch instructions have a same debug location with the
 ; br instruction.
-; 
+;
 ; CHECK:      [[DLOC1:![0-9]+]] = !DILocation(line: 5, column: 9, scope: !{{[0-9]+}})
 ; CHECK:      [[DLOC2:![0-9]+]] = !DILocation(line: 5, column: 7, scope: !{{[0-9]+}})
-; CHECK-DAG:  [[VREG1:%[^ ]+]] = COPY %esi
-; CHECK-DAG:  [[VREG2:%[^ ]+]] = COPY %edi
+; CHECK-DAG:  [[VREG1:%[^ ]+]]:gr32 = COPY %esi
+; CHECK-DAG:  [[VREG2:%[^ ]+]]:gr32 = COPY %edi
 ; CHECK:      SUB32rr [[VREG2]], [[VREG1]], implicit-def %eflags, debug-location [[DLOC1]]
 ; CHECK-NEXT: JE_1{{.*}} implicit %eflags, debug-location [[DLOC2]]
 ; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]]
@@ -36,8 +36,8 @@ return:                                           ; preds = %if.else, %if.then
   ret i32 %retval.0, !dbg !21
 }
 
-declare i32 @bar(...) 
-declare i32 @baz(...) 
+declare i32 @bar(...)
+declare i32 @baz(...)
 
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
author	Justin Bogner <mail@justinbogner.com>	2017-10-24 18:04:54 +0000
committer	Justin Bogner <mail@justinbogner.com>	2017-10-24 18:04:54 +0000
commit	edab7579664b13faad3680c676c6b8a49d2ea00b (patch)
tree	dee3b97d46f3325ed2ceb0ddedb5e54e151a3676 /test/CodeGen
parent	7c330fabaedaba3d02c58bc3cc1198896c895f34 (diff)